JP5416478B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device including elements constituting an ESD (ElectroStatic Discharge) protection circuit.

  In a semiconductor device, an internal circuit may be damaged by external static electricity. For this reason, a protective element is provided in the semiconductor device, and the internal circuit is protected by releasing static electricity input by the protective element (see, for example, FIG. 13).

  According to FIG. 13, the protection circuit PE1 is provided between the power supply voltage Vcc and the ground line GND in the previous stage of the internal circuit Z, and the protection element PE2 is provided between the input Vin and the ground line GND. As a result, when static electricity is input, current flows out to the ground line via the protective element PE1 or PE2, so that the internal circuit Z is protected.

  As the protective elements PE1 and PE2, thyristors and lateral (lateral) transistors are used. For example, according to Patent Document 1 below, a PNPN structure is formed on a substrate with an element isolation region interposed therebetween. FIG. 14 is a schematic cross-sectional view of a protective element having this thyristor structure. FIG. 15 is a circuit diagram equivalently showing the protection element of FIG. 14, and the corresponding equivalent resistance and circuit symbols of the equivalent transistor are also shown in FIG.

  The structure of FIG. 14 will be described. A P-type well 2 and an N-type well 3 are formed on the N-type substrate 1. In the P-type well 2, a P-type impurity diffusion region 4 and an N-type impurity diffusion region 5 are formed that are separated from each other by an element isolation region 10 in a direction parallel to the substrate surface. In the N-type well 3, a P-type impurity diffusion region 7 and an N-type impurity diffusion region 8 are formed that are separated from each other by an element isolation region 10 in a direction parallel to the substrate surface. Further, an N-type impurity diffusion region 6 is formed so as to straddle the P-type well 2 and the N-type well 3.

  Hereinafter, the P-type impurity diffusion region and the N-type impurity diffusion region are abbreviated as “P-type region” and “N-type region”, respectively.

  The P-type regions 4 and 7 are impurity diffusion regions having a higher concentration than the P-type well 2. Similarly, the N-type regions 5, 6, and 8 are impurity diffusion regions having a concentration higher than that of the N-type well 3. As a result, a PNP transistor having the P-type region 7 as an emitter, the N-type well 3 and the N-type substrate 1 as a base, the P-type well 2 and the P-type region 4 as a collector, and the N-type region 8 and the N-type well 3 are formed. An NPN transistor having a collector, a P-type well 2 and a P-type region 4 as a base and an N-type region 5 as an emitter is formed, thereby realizing a PNPN thyristor.

  FIG. 15 shows an equivalent circuit in the state where the power supply voltage Vcc or the input voltage Vin is applied to the terminals d and e and the terminals a and b are grounded with respect to the thyristor having the structure of FIG.

  In this case, when a trigger current starts to flow from the terminal c, a current flows between the base and emitter of the PNP transistor located in the upper stage, and a collector current having a current amplification factor hFE times determined by the characteristics of the PNP transistor flows. The collector current of this PNP transistor becomes the base current of the lower NPN transistor, and a collector current having a current amplification factor hFE times determined by the characteristics of this NPN transistor flows. Since the collector current of this NPN transistor becomes the base current of the upper PNP transistor, a collector current of hFE times flows again. Further, the emitter current of the NPN transistor escapes to the ground line.

  Hereinafter, the current continues to flow in the thyristor based on the same principle. By using such a thyristor as the protection elements PE1 and PE2 in FIG. 13, the internal circuit Z is protected.

  In Patent Document 1, an NMOS transistor is used as a trigger element, and the operation of the thyristor is started by a trigger from the NMOS transistor. This document also describes a device that triggers at a low voltage.

JP-A-9-213811

  However, in Patent Document 1, the operation of the thyristor remains the same as before. For this reason, if the thyristor starts to operate earlier with respect to the same trigger and allows more electrostatic current to flow, the internal circuit Z can be effectively protected. An object of this invention is to provide the semiconductor device containing the protection element which improved the protection capability further compared with the past.

  In order to achieve the above object, a semiconductor device of the present invention has the following configuration.

That is,
A semiconductor device provided with a protection element,
The protective element is
A P-type well and an N-type well formed adjacent to each other in a first direction parallel to the substrate surface;
In the P-type well, a first P-type region and a first N-type region formed by being separated by an element isolation region in the first direction;
A second P-type region and a second N-type region formed in the N-type well and separated from each other by an element isolation region in the first direction;
A third N-type region formed across a part of the P-type well and a part of the N-type well;
The first to third N-type regions have a higher impurity concentration than the N-type well,
The first and second P-type regions have a higher impurity concentration than the P-type well,
The first P-type region is formed at a position facing the N-type well via the first N-type region,
The second N-type region is formed at a position facing the P-type well via the second P-type region,
The third N-type region is formed at the position sandwiched between the first N-type region and the second P-type region and separated by the two regions and the element isolation region,
The upper layer of at least one of the first N-type region and the second P-type region is in contact with the region, and is doped polysilicon having the same conductivity type as the lower layer region and having a higher impurity concentration than the same region A film is formed ,
Trigger having a trigger gate electrode so as to overlap the first N-type region and the third N-type region in the P-type well, and using the first N-type region and the third N-type region as source / drain, respectively A MOS transistor is formed in the P-type well;
An N-type doped polysilicon film doped at a higher concentration than the third N-type region is formed in contact with the upper layer of the third N-type region .

  According to the above configuration, a thyristor structure including an NPN transistor having the first N-type region as an emitter and a PNP transistor having the second P-type region as an emitter is formed. Then, at least one of the emitters of both transistors is formed with a highly doped polysilicon film of the same conductivity type in contact with the impurity diffusion region. As a result, the hFE of the transistor in which the heavily doped polysilicon is formed increases.

  Therefore, when an external voltage such as static electricity is applied to generate a trigger, the collector current of at least one of the transistors greatly increases. In other words, the increasing speed of the collector current can be increased.

  The collector current of the PNP transistor becomes the base current of the NPN transistor, and the collector current of the NPN transistor becomes the base current of the PNP transistor. For this reason, when the rising speed of the collector current of at least one of the transistors increases, the rising speed of the current flowing inside the thyristor increases. Accordingly, since the rise rate of the emitter current of the NPN transistor can be increased, the emitter current is made to flow outside, so that even when charges such as static electricity are inputted from the outside, the emitter current is inputted. In the initial stage, the emitter current of the NPN transistor can be released early.

Therefore, by providing such a semiconductor device of the present invention in the previous stage of the internal circuit,
Even when static electricity or the like is input, voltage (charge) derived from the static electricity can be released from the semiconductor device at an early stage, and the internal circuit can be protected.

  According to the configuration of the present invention, since it can be realized only by forming a doped polysilicon film on the upper layer of at least one of the first N-type region and the second P-type region, an increase in the occupied area of the element can be achieved. There is no invitation. In other words, the protection capability can be increased with the same element occupation area, and the element occupation area can be reduced with the same protection capability.

  Furthermore, the semiconductor device of the present invention can be realized only by forming a doped polysilicon film above the impurity diffusion region, so that no additional complicated process is required. For this reason, the affinity with the conventional manufacturing method is high, and the additional cost can be suppressed to a minimum.

In particular, an impurity diffusion region located under the doped polysilicon film is formed simultaneously with the LDD region forming step in the peripheral MOS transistor, and a high concentration impurity ion is formed on the polysilicon film in order to form a doped polysilicon film. By forming the step of implanting simultaneously with the source / drain formation step in the peripheral MOS transistor, it can be manufactured in parallel with the peripheral MOS transistor manufacturing step. In addition, this configuration increases the breakdown voltage of the trigger gate electrode, particularly when the trigger gate electrode is formed so as to overlap the first N-type region and the third N-type region. it can. For this reason, it is useful when the withstand voltage of the internal circuit to be protected is high, or when the power supply voltage or input voltage input to the internal circuit is high.

In addition to the above features, the semiconductor device of the present invention has
The first P-type region and the first N-type region are electrically connected;
Another feature is that the second P-type region and the second N-type region are electrically connected.

  For example, the first P-type region and the first N-type region can be connected to the ground line, and the second P-type region and the second N-type region can be connected to the power supply voltage line or the input voltage line. At this time, when an external voltage such as static electricity is applied, the voltage can be quickly released to the ground line, and the internal circuit is protected.

In addition to the above features, the semiconductor device of the present invention has
A P-type doped polysilicon film doped in a higher concentration than the second P-type region is formed in contact with the upper layer of the second P-type region,
An N-type doped polysilicon film doped at a higher concentration than the first N-type region is formed on the upper layer of the first N-type region in contact with the same region;
The impurity concentration of the first P-type region is higher than that of the second P-type region and is similar to that of the P-type doped polysilicon film,
The impurity concentration of the second N-type region is higher than that of the first N-type region and is approximately the same as that of the N-type doped polysilicon film.

  Thus, by forming the doped polysilicon film on both the first N-type region and the second P-type region, the hFE values of both the PNP transistor and the NPN transistor constituting the thyristor can be increased. . As a result, the rising speed of the current flowing in the thyristor is further increased, and external voltage such as static electricity inputted earlier can be released.

  The semiconductor device of the present invention is characterized by having the following configuration.

That is,
A semiconductor device provided with a protection element,
The protective element is
A P-type well formed on the substrate;
In the P-type well, a P-type region, a first N-type region, and a second N-type region that are formed apart from each other in a first direction parallel to the substrate surface,
The P-type region has a higher impurity concentration than the P-type well,
The first N-type region is formed at a position sandwiched between the P-type region and the second N-type region, and an N-type doped polysilicon film having an impurity concentration higher than that of the first N-type region is formed on the upper layer. It is formed in contact with,
A trigger reverse junction diode is formed by the second N-type region and the P-type well,
An N-type doped polysilicon film having an impurity concentration higher than that of the second N-type region is formed in contact with the second N-type region .

  According to the above configuration, a lateral NPN transistor having a P-type well as a base and a first N-type region and a second N-type region as an emitter / collector is formed. In this case, since the high-concentration N-type doped polysilicon film is formed on the second N-type region, the hFE value of the transistor increases. For this reason, when an external voltage such as static electricity is applied to cause a trigger, a larger collector current flows, thereby increasing the rate of increase of the emitter current. Therefore, by setting the emitter current to flow to the outside, even when a charge such as static electricity is input from the outside, it can be released as an emitter current of the NPN transistor at an early stage of input. .

  The second N-type region and the P-type well form a reverse-connected diode, which constitutes a trigger element. By forming a high-concentration N-type doped polysilicon film on the upper layer of the second N-type region, the breakdown voltage of the trigger element can be increased. For this reason, it is useful when the withstand voltage of the internal circuit to be protected is high, or when the power supply voltage or input voltage input to the internal circuit is high.

  According to the semiconductor device of the present invention, the protection capability can be further enhanced as compared with the conventional protection element while suppressing an increase in the occupied area.

Schematic plan view of the semiconductor device of the present invention Schematic sectional view of the semiconductor device of the present invention Graph comparing hFE of the present invention and a conventional PNP transistor Graph comparing hFE of the present invention and the conventional NPN transistor Process sectional view of the semiconductor device of the present invention Process sectional view of the semiconductor device of the present invention Another schematic plan view of the semiconductor device of the present invention Another schematic sectional view of the semiconductor device of the present invention Schematic plan view of the second embodiment of the semiconductor device of the present invention. Schematic sectional view of a second embodiment of the semiconductor device of the present invention. Equivalent circuit diagram when using lateral transistors as protection elements Another typical sectional view of a 2nd embodiment of a semiconductor device of the present invention. Circuit example for protecting the internal circuit with a protection element Conventional schematic cross-sectional view when using a thyristor as a protective element Equivalent circuit diagram when using a thyristor as a protection element

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In addition, the same code | symbol is attached | subjected about the same component as FIGS. 13-B3, and the description is abbreviate | omitted or simplified.

[First Embodiment]
FIG. 1 shows a schematic plan view of a first embodiment of the semiconductor device of the present invention, and FIG. 2 shows a schematic cross-sectional view thereof. 2A shows a cross section taken along the line L1-L1 ′ in FIG. 1, and FIG. 2B shows a cross section taken along the line L2-L2 ′.

  On the N-type substrate 1, a P-type well 2 and an N-type well 3 are formed adjacent to a direction parallel to the substrate surface (first direction). The P-type well 2 includes a P-type region 4 and an N-type region. 5a, a P-type region 7a and an N-type region 8 are formed in the N-type well 3, respectively. An N-type region 6 is formed across the P-type well 2 and the N-type well 3.

  The P-type region 4 corresponds to a “first P-type region”, the N-type region 5 a corresponds to a “first N-type region”, the P-type region 7 a corresponds to a “second P-type region”, and the N-type region 8 The N-type region 6 corresponds to a “second N-type region”, and the N-type region 6 corresponds to a “third N-type region”.

  The N-type region 5a is an impurity diffusion region having a higher concentration than the N-type well 3, and the N-type regions 6 and 8 have a higher impurity concentration. The P-type region 7a is a higher concentration impurity diffusion region than the P-type well 2, and the P-type region 4 has a higher impurity concentration.

  Over the N-type region 5a, an N-type doped polysilicon film 11 doped with N-type impurity ions is formed in contact with the N-type region 5a. The impurity concentration of the N-type doped polysilicon film 11 is higher than that of the N-type region 5a and is about the same as that of the N-type regions 6 and 8.

  A P-type doped polysilicon film 12 doped with P-type impurity ions is formed on the P-type region 7a in contact with the P-type region 7a. The impurity concentration of the P-type doped polysilicon film 12 is higher than that of the P-type region 7 a and is about the same as that of the P-type region 4.

  The N-type region 5a and the N-type region 6 are partially spaced from each other, and the gate electrode 13 is formed through the gate oxide film 14 so as to straddle both the regions 5a and 6 at that portion. . In this region, an NMOS transistor having the P-type well 2 positioned below the gate electrode 13 as a channel and the N-type region 5a and the N-type region as a source / drain is formed. The NMOS transistor constitutes a trigger element, and the gate electrode 13 constitutes a trigger electrode.

  Note that the lower limit value of the input voltage functioning as a trigger can be appropriately adjusted according to the thickness of the gate oxide film 14 and the gate length of the gate electrode 13. The gate electrode 13 is normally set to the ground potential, and the N-type region 5a and the N-type region 6 are not conductive.

  Compared with the conventional configuration shown in FIG. 14, the semiconductor device of the present invention has an N-type doped polysilicon film 11 on the N-type region 5 a in the P-type well 2 and a P-type region 7 a in the N-type well 3. The difference is that a P-type doped polysilicon film 12 is provided thereon, and the equivalent circuit is the same as that of FIG.

  It is assumed that the trigger gate electrode 13 is broken by applying an external voltage such as static electricity under such a configuration. At this time, the N-type region 5a and the N-type region 6 forming the source / drain of the NMOS transistor serving as the trigger element are brought into conduction. As a result, electrons from the N-type region 5a flow into the base of the upper PNP transistor formed by the N-type region 6, thereby causing a base current to flow.

  At this time, a collector current that is hFE times the base current flows through the PNP transistor. However, in the case of the semiconductor device of the present invention, unlike the prior art, the high-concentration P-type doped polysilicon film 12 is formed in the upper layer of the P-type region 7a.

  FIG. 3 is a graph showing the relationship between the hFE and the collector current Ic of the PNP transistor of the present invention configuration and the conventional configuration. Referring to FIG. 3, it can be seen that the hFE value is significantly increased by forming the heavily doped polysilicon as in the present invention.

  Therefore, according to the configuration of the present invention, since the hFE value is larger than that of the conventional configuration shown in FIG. 13, even if the base current value is the same, a collector current larger than that of the conventional configuration flows through the PNP transistor.

  Since the collector current larger than the conventional one becomes the base current of the NPN transistor, the base current of the NPN transistor also shows a large value.

  As shown in FIGS. 1 and 2, in the semiconductor device of the present invention, the high-concentration N-type doped polysilicon film 11 is also formed on the N-type region 5a. For this reason, the hFE value is larger than the conventional value for the same reason as the PNP type. FIG. 4 is a graph showing the relationship between the hFE and collector current Ic of the NPN transistor of the present invention and the conventional structure. As in the case of the PNP transistor, the semiconductor device of the present invention has a larger hFE value than the conventional one. You can see that.

  Since the base current of the NPN transistor is large in the first place and the value of hFE is also large, the collector current of the NPN transistor shows a significantly larger value than before. This collector current contributes as the base current of the PNP transistor.

  According to the configuration of the present invention, since the value of hFE can be increased in both the NPN transistor and the PNP transistor, the speed at which the current flowing in the thyristor can be increased as compared with the conventional configuration. As a result, a larger amount of current can be released in a shorter time than before, and the function as a protective element can be improved. Further, according to the configuration of the present invention, it can be realized only by forming a doped polysilicon film on the N-type region 5a and the P-type region 7a, so that the occupied area of the element is not increased. In other words, the protection capability can be increased with the same element occupation area, and the element occupation area can be reduced with the same protection capability.

  Hereinafter, with reference to FIGS. 5 to 6, a method for manufacturing a semiconductor device of the present invention will be described. 5 and 6 are schematic process cross-sectional views of the semiconductor device of the present invention, which are divided into two drawings for the sake of space.

  First, as shown in FIG. 5A, a P-type well 2, an N-type well 3, and an element isolation region 10 are formed on an N-type substrate 1 using a known technique.

The well is formed by implanting impurities using an ion implanter and annealing in a diffusion furnace. When forming the N-type well 3, the formation (planned) region of the P-type well 2 is masked with a resist, and the implantation energy ranges from 120 keV to 2 MeV, and the dose amount is 1 × 10 ¹² to 2 × 10 ¹³ cm ⁻² . In the range, phosphorus (P) ions are implanted in two or three stages. When forming the P-type well 2, the formation (planned) region of the N-type well 3 is masked with a resist, and the implantation energy ranges from 20 keV to 1 MeV, and the dose amount is 1 × 10 ¹² to 2 × 10 ¹³ cm ⁻² . In a range, boron (B) ions are implanted in two or three stages.

  The element isolation region 10 is formed using a known LOCOS (LOCal Oxidation of Silicon) method or STI (Shallow Trench Isolation) method.

Next, after forming a gate oxide film, forming and processing a gate electrode, as shown in FIG. 5B, the regions to be formed of the N-type regions 5a, 7a, and 8 are masked with a resist 21. Then, BF ₂ ions are implanted in an implantation energy range of 10 to 20 keV and a dose amount of 5 × 10 ^{12 to} 3 × 10 ¹⁴ cm ⁻² . Alternatively, boron (B) ions are implanted in an implantation energy range of 20 to 60 keV and a dose amount in the range of 5 × 10 ^{12 to} 3 × 10 ¹⁴ cm ⁻² . By this ion implantation, a P-type region 4 a is formed in the P-type well 2 and a P-type region 7 a is formed in the N-type well 3. This ion implantation can also be used for LDD (Lightly Doped Drain) formation of a PMOS transistor formed in the periphery or drift implantation.

  The gate oxide film 14 and the gate electrode 13 of the trigger MOS transistor shown in FIG. 2B are formed by forming and processing the gate oxide film and the gate electrode.

Next, as shown in FIG. 5C, the upper portions of the P-type regions 4a and 7a are masked with a resist so that the implantation energy is in the range of 15 to 120 keV and the dose is 5 × 10 ¹² to 1 × 10 ¹⁴ cm ^−2. P ions are implanted in the range of By this ion implantation, an N-type region 5 a is formed in the P-type well 2, an N-type region 8 a is formed in the N-type well 3, and an N-type region 6 a is formed so as to extend over the P-type well 2 and the N-type well 3. Is done. This ion implantation can also be used for LDD formation of NMOS transistors formed in the periphery or drift implantation.

Next, as shown in FIG. 5D, after the insulating film 18 is deposited by the CVD (Chemical Vapor Deposition) method, the processing is performed. As an example, SiO ₂ is deposited with a film thickness of 80 to 120 nm. Thereafter, the N-type region 5a and the P-type region 7a are opened by a known photolithography technique and etching technique. This opening is formed to bring a polysilicon film to be formed later into contact with a diffusion region on the substrate.

  Next, as shown in FIG. 6A, after a polysilicon film is formed, the polysilicon film is selectively formed above the N-type region 5a and the P-type region 7a by a known photolithography technique and etching technique. (Polysilicon films 11a and 12a).

Next, as shown in FIG. 6B, the portions other than the upper part of the P-type region 4a and the polysilicon film 12a are masked with a resist, for example, in the range of implantation energy of ¹⁵ to 30 keV, and the dose amount 2 × 10 ¹⁵ to 4 ×. BF ₂ ions are selectively implanted into the P-type region 4a and the polysilicon film 12a within a range of 10 ¹⁵ cm ⁻² . By this ion implantation, the P-type region 4a becomes a P-type region 4 having a high impurity concentration, and the polysilicon film 12a becomes a doped polysilicon film 12 doped to a high concentration P-type. This ion implantation can also be used as a source / drain formation step of a PMOS transistor formed in the periphery.

Next, as shown in FIG. 6C, the portions other than the N-type regions 6a and 8a and the polysilicon film 11a are masked with a resist so that, for example, the implantation energy is in the range of 20 to 30 keV, and the dose is 2 × 10 ^15. Arsenic (As) ions are selectively implanted into the N-type regions 6a and 8a and the polysilicon film 11a within a range of ˜4 × 10 ¹⁵ cm ⁻² . By this ion implantation, the N-type regions 6a and 8a become high-concentration N-type regions 6 and 8, respectively, and the polysilicon film 11a becomes a high-concentration N-type doped polysilicon film 11. . This ion implantation can also be used as a source / drain formation step of the NMOS transistor formed in the periphery.

  Thereafter, a known wiring process is performed, and the N-type region 4, the doped polysilicon film 11, and the gate electrode 13 are set to the GND line, and the doped polysilicon film 12 and the P-type region 8 are set to the power supply voltage (Vcc) line or Connect to the input voltage (Vin) line. Thereby, the semiconductor device of the present invention shown in FIG. 2 is formed. Note that the order of ion implantation into the P-type well 2 region and ion implantation into the N-type well 3 region may be reversed as appropriate.

  Thus, the semiconductor device of the present invention can be manufactured in parallel with the peripheral MOS transistor manufacturing process. Therefore, there is an effect that the electrostatic protection capability can be enhanced without adding a new dedicated process.

  In the above embodiment, the doped polysilicon film is not formed above the N-type region 6. However, the N-type doped polysilicon film 16 may be formed above the N-type region 6. . FIG. 7 shows a schematic plan view thereof, and FIG. 8 shows a schematic sectional view thereof. 8A shows a cross section taken along line L1-L1 'in FIG. 7, and FIG. 8B shows a cross section taken along line L2-L2'.

  In the configuration of FIG. 7, the doped polysilicon film 16 (and 11) is formed above the source / drain of the trigger NMOS. With this configuration, the active region formed on the substrate 1 (on the wells 2 and 3) is only a drift region having a low impurity concentration. Since the high-concentration impurity diffusion region is formed on the doped polysilicon side (11, 12, 16), the distance of the depletion layer extending in the drift region is extended, thereby increasing the breakdown voltage of the trigger MOS transistor. it can. Therefore, such a configuration is suitable when the breakdown voltage of the internal circuit Z is high, or when the power supply voltage Vcc and the input voltage Vin are high.

  7 and 8 differ only in the patterning shape of the formed film, and can be realized by the same manufacturing method as the configuration in FIGS. 1 and 2, so description of the manufacturing method is omitted.

  In FIG. 7, the case where the doped polysilicon film is formed above the source / drain of the trigger NMOS is taken up. However, the case where the N-type doped polysilicon film 16 is also formed above the N-type region 6. Even so, a configuration in which the doped polysilicon film is not formed above the source / drain of the trigger NMOS as shown in FIG. 1 can be employed.

  Further, in the above embodiment, the doped polysilicon film is formed on the upper layer of both the P-type region 7a and the N-type region 5a, but the doped polysilicon film is formed only on the upper layer of one of the regions. Even in this case, since the hFE of one of the PNP transistor and the NPN transistor in FIG. 15 can be increased, the protection capability can be improved as compared with the conventional configuration. However, it is more preferable that the doped polysilicon film is provided in the upper layer of both regions as in the above embodiment because the protection capability can be further enhanced.

[Second Embodiment]
FIG. 9 shows a schematic plan view of a second embodiment of the semiconductor device of the present invention, and FIG. 10 shows a schematic cross-sectional view thereof. FIG. 10 shows a cross section taken along line L3-L3 ′ in FIG. In addition, about the component same as 1st Embodiment, the same code | symbol is attached | subjected and the description is abbreviate | omitted. In addition, since the semiconductor device of this embodiment can be manufactured by using the same method as that of the first embodiment, description of the manufacturing method is omitted.

  Unlike the first embodiment using a thyristor as a protection element, this embodiment uses a lateral transistor as a protection element. In FIG. 10, a lateral NPN transistor having an N-type region 8 as a collector, a P-type well 2 as a base, and an N-type region 5a as an emitter is formed.

  In FIG. 10, a doped polysilicon film 11 doped in a high concentration N-type in contact with the N-type region 5 a is formed above the N-type region 5 a. This doped polysilicon film 11 constitutes the emitter of a lateral NPN transistor together with the N-type region 5a. Therefore, as in the first embodiment, this NPN transistor has a larger hFE value than the case without the doped polysilicon film 11.

  The N-type region 8 constitutes a diode connected in the reverse direction with the P-type well 2.

  Under such a configuration, when an external voltage such as static electricity is applied to the N-type region 8, the diode in reverse connection is broken down. The current flowing at this time is given as the base current of the lateral NPN transistor (see the equivalent circuit in FIG. 11).

  At this time, a collector current that is hFE times the base current flows from the N-type region 8 toward the P-type well 2 in the lateral NPN transistor. Then, the emitter current of the transistor escapes to the ground line. Until the voltage across the reverse-connected diode that is the trigger falls below the breakdown voltage, current flows continuously from the N-type region 8 toward the ground line through the transistor.

  Then, as shown in FIG. 10, the doped polysilicon film 11 is formed in the upper layer of the N-type region 5a, so that the value of hFE is increased, and the value of the collector current is compared with the case where the doped polysilicon film 11 is not provided. Becomes larger. As a result, it is possible to secure a current path through which the emitter current starts to flow earlier and to the ground line, and the protection function of the internal circuit Z can be enhanced.

  Also in this embodiment, the N-type doped polysilicon film 17 may be formed on the upper layer of the N-type region 8 so as to be in contact with the region 8 (see FIG. 12). By doing in this way, the withstand voltage of the reverse junction diode which becomes a trigger can be raised like the case of FIG. 7 of 1st Embodiment. Such a configuration is suitable when the breakdown voltage of the internal circuit Z is high, or when the power supply voltage Vcc and the input voltage Vin are high.

  As described above, according to the present invention, when a thyristor is used as a protection element and a lateral transistor is used, when the hFE value of a bipolar transistor as a constituent element is increased, a trigger is given. A large amount of collector current can flow. Thereby, at the initial stage when static electricity is applied from the outside, a greatly amplified emitter current can flow toward the ground line. In other words, the input charge (voltage) can be released early, and the protection function of the internal circuit can be enhanced.

[Another embodiment]
Another embodiment will be described below.

  <1> In each of the above embodiments, an N-type substrate is used as the substrate 1, but the conductivity type of the substrate may be N-type or P-type.

  <2> In the first embodiment, a MOS transistor is used as a trigger element for causing a trigger current to flow out. In the second embodiment, a reverse-connected diode is used as a trigger element for causing a trigger current to flow in. Using. These trigger elements are those that can break when an input voltage exceeding a certain threshold is applied and can start the operation of protection elements (thyristors, lateral transistors) formed inside. For example, other elements can be used.

  <3> The above embodiments have been described on the assumption that the input static electricity flows out to the ground line. That is, the description has been made on the assumption that the P-type region 4 and the N-type doped polysilicon film 11 are connected to the ground line. However, if the P-type region 4 and the N-type doped polysilicon film 11 are connected to a voltage line lower than at least the power supply voltage Vcc or the input voltage Vin. good.

  <4> In each of the above embodiments, a doped polysilicon film is formed by performing ion implantation on the polysilicon film at the same time as the ion implantation for forming the high concentration region after forming the polysilicon film. However, a pre-doped polysilicon film may be formed at the time of film formation.

1: Semiconductor substrate 2: P-type well 3: N-type well 4, 4a: P-type impurity diffusion region 5, 5a: N-type impurity diffusion region 6, 6a: N-type impurity diffusion region 7, 7a: P-type impurity diffusion region 8, 8a: N-type impurity diffusion region 10: Element isolation region 11: N-type doped polysilicon film 11a: Polysilicon film 12: P-type doped polysilicon film 12a: Polysilicon film 13: Gate electrode 14: Gate oxidation Film 16: N-type doped polysilicon film 17: N-type doped polysilicon film 18: Insulating film 21: Resist 22: Resist 23: Resist 24: Resist

Claims (3)

A semiconductor device provided with a protection element,
The protective element is
A P-type well and an N-type well formed adjacent to each other in a first direction parallel to the substrate surface;
In the P-type well, a first P-type region and a first N-type region formed by being separated by an element isolation region in the first direction;
A second P-type region and a second N-type region formed in the N-type well and separated from each other by an element isolation region in the first direction;
A third N-type region formed across a part of the P-type well and a part of the N-type well;
The first to third N-type regions have a higher impurity concentration than the N-type well,
The first and second P-type regions have a higher impurity concentration than the P-type well,
The first P-type region is formed at a position facing the N-type well via the first N-type region,
The second N-type region is formed at a position facing the P-type well via the second P-type region,
The third N-type region is formed at the position sandwiched between the first N-type region and the second P-type region and separated by the two regions and the element isolation region,
The upper layer of at least one of the first N-type region and the second P-type region is in contact with the region, and is doped polysilicon having the same conductivity type as the lower layer region and having a higher impurity concentration than the same region A film is formed,
Trigger having a trigger gate electrode so as to overlap the first N-type region and the third N-type region in the P-type well, and using the first N-type region and the third N-type region as source / drain, respectively A MOS transistor is formed in the P-type well,
A semiconductor device, wherein an N-type doped polysilicon film doped at a higher concentration than the third N-type region is formed on and in contact with the third N-type region. The first P-type region and the first N-type region are electrically connected;
The semiconductor device according to claim 1, wherein the second P-type region and the second N-type region are electrically connected. A P-type doped polysilicon film doped in a higher concentration than the second P-type region is formed in contact with the upper layer of the second P-type region,
An N-type doped polysilicon film doped at a higher concentration than the first N-type region is formed on the upper layer of the first N-type region in contact with the same region;
The impurity concentration of the first P-type region is higher than that of the second P-type region and is similar to that of the P-type doped polysilicon film,
3. The semiconductor device according to claim 1, wherein an impurity concentration of the second N-type region is higher than that of the first N-type region and is approximately the same as that of the N-type doped polysilicon film.

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