JP2011171662A - Protective transistor, and semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a protective transistor having a small occupation area and balancing desired withstand voltage with prevention of thermal destruction. <P>SOLUTION: A region REgd between a gate and a drain that is adjacent to a region immediately under the gate on one side in a gate length direction includes a first region REgd1 and a second region REgd2 as regions adjacent to each other in a gate width direction. In the first region, drain withstand voltage is relatively large, and in the second region, a distance from a drain electrode (a silicide layer 10D formed in a drain contact part) is large relative to that in the first region in a plan view, and drain withstand voltage is relatively small. Thereby, a drain contact part is distant from a heating part A of a region REgd2 between the gate and the drain that is low in withstand voltage and is formed into a structure having a small area (or without expanding). <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention turns on when an excessive voltage such as static electricity is applied to the drain to protect the circuit connected to the drain from the voltage, and connects the protection transistor to a terminal of the internal circuit. And a semiconductor integrated circuit.

  In general, a semiconductor integrated circuit includes a protective element that performs electrostatic discharge (ESD) in order to protect an internal circuit from static electricity entering from an external terminal.

The protection element is connected for ESD protection between wirings where static electricity easily overlaps, such as between a power supply line and a GND line of an internal circuit.
As the ESD protection element, a GGMOS (Gate-Grounded MOSFET) using a MOSFET constituting an internal circuit or a thyristor is usually used. Among these, the thyristor has a low on-resistance, but its trigger voltage is higher than the breakdown voltage of the MOS transistor made by the same process. In addition, since thyristors have the disadvantages that they are easy to latch up and the operation speed is slower than that of GGMOS, it is necessary to use GGMOS and thyristor properly depending on the application.

  For example, Patent Documents 1 and 2 disclose protection transistors such as GGMOS.

  In Patent Document 2, it is pointed out that formation of a silicide layer causes a decrease in resistance to electrostatic breakdown in a GGMOS used for an ESD protection circuit. The reason for this is that, according to Patent Document 2, since the resistance value of the silicide layer is lower than that of the high concentration drain region, most of the current is concentrated in the silicide layer when the protection circuit is operated, This is because thermal destruction easily occurs.

  Therefore, in the transistor structures disclosed in Patent Documents 1 and 2, a drain region where a silicide layer is not formed or a part of an LDD region, which is called a non-silicide region, is connected to a sidewall spacer on the gate sidewall and a drain electrode connected to the drain electrode. It is provided between the silicide layer on the region. The silicide layer is separated from the gate electrode in the gate length direction in which the drain current flows by the amount corresponding to the non-silicide region. As a result, in Patent Document 1, thermal breakdown of the junction of the ESD protection transistor is prevented.

Japanese Patent Laid-Open No. 07-106567 JP 2002-009281 A

As in Patent Documents 1 and 2, just by taking the distance from the gate electrode to the silicide layer by forming a non-silicide region in the gate length direction, the transistor size increases and the occupied area increases accordingly.
Patent Document 2 proposes a technique for shortening the distance as much as possible by devising the structure of the impurity diffusion layer with respect to Patent Document 1 in which the distance is simply increased.
However, even in Patent Document 2, an increase in the transistor size in the gate length direction is inevitable, and the effect of suppressing the increase in the occupied area is limited.
Further, the size of the non-silicide region has an appropriate value for increasing the resistance Ron after snapback of the ESD protection element, and in general, the size cannot be freely changed.

  The present invention provides a protection transistor that occupies a small area because there is no need to increase the transistor size in the gate length direction, and that achieves both desired breakdown voltage and prevention of thermal breakdown. The present invention also provides a semiconductor integrated circuit having this protection transistor as a protection element for an internal circuit.

The protection transistor according to the present invention includes a gate electrode, a second conductivity type gate-drain region, a second conductivity type drain region and a source region, and a source electrode and a drain electrode.
The gate electrode is stacked on a channel formation region of a semiconductor substrate via a gate insulating film.
The gate-drain region is adjacent to the channel formation region on one side in the first direction defining the gate length of the gate electrode.
The drain region is adjacent to the gate-drain region on the side opposite to the channel formation region in the first direction.
The source region is located on the other side of the channel formation region in the first direction.
The source electrode and the drain electrode are provided in contact with each of the source region and the source region.

The gate-drain region includes a first region and a second region as regions adjacent to each other in a second direction orthogonal to the first direction in plan view.
The first region is a region having a relatively large breakdown voltage with respect to a drain voltage applied to the drain electrode with reference to the potential of the source electrode.
The second region is a region whose distance from the drain electrode is farther than the first region in a plan view and whose breakdown voltage is relatively small.

In the protection transistor having such a structure, an external voltage is applied to the drain electrode. At this time, the source electrode and the gate electrode are held at a constant voltage that turns off the protection transistor when no external voltage is applied, for example, a reference voltage such as a GND voltage.
In this state, when a certain large voltage is applied to the drain electrode, junction breakdown occurs at the PN junction on the drain side.

Once the junction breakdown occurs, a current flows from the drain region where the junction breakdown has occurred to the source region. As a result, a source region and a drain region are formed, the potential of the semiconductor region (normal well) having the surface portion as a channel formation region is increased, and the PN junction between the semiconductor region (well) and the source region is forward biased. Thereafter, the parasitic bipolar transistor having the source region, the well, and the drain region as the emitter, base, and collector, respectively, is turned on.
When the parasitic bipolar transistor is turned on, the impedance between the emitter and the collector abruptly decreases, so that a current flows on the well surface side where the impedance has decreased.

In the transistor structure of the present invention, such a junction breakdown that triggers the parasitic bipolar operation occurs in the second region having a lower breakdown voltage. The impurity concentration of the second region is determined so that the junction breakdown voltage becomes a desired value.
Although the generation location generates heat due to the junction breakdown, the second region is separated from the drain electrode in the second direction, that is, the direction perpendicular to the gate length direction. Therefore, the temperature of the drain electrode portion hardly rises due to this heat generation. For example, even when a silicide layer is formed at the drain contact portion where the drain electrode is in contact with the drain region, the silicide layer is sufficiently far from the heat generated by the junction breakdown, so that the breakdown does not occur.

As described above, in this structure, the channel current that flows when the voltage is applied when the protection transistor is turned on does not flow in the shortest distance between the source electrode and the drain electrode, but flows in the second direction (gate width direction). After the occurrence of the junction breakdown at the time of turn-on, since the parasitic bipolar transistor is turned on, a snapback phenomenon is observed in which the drain voltage decreases once due to the impedance decrease and then increases again from a certain voltage.
In such a structure that causes the channel current to be bypassed, it is not necessary to separate the drain electrode from the gate electrode in the gate length direction, so the size in the gate length direction (first direction) is small. On the other hand, the gate width direction (second direction) has a necessary gate width, but after the first junction breakdown, the current flows using the entire body region (well). There is no expansion due to the adoption, or even if it is necessary to expand, the amount is much smaller.

According to the present invention, it is possible to provide a protection transistor that has a small occupation area because the transistor size in the gate length direction is not increased, and that achieves both desired breakdown voltage and prevention of thermal breakdown. In addition, according to the present invention, a semiconductor integrated circuit having this protection transistor as a protection element for an internal circuit can be provided.

It is a figure which shows the example of application of the protection circuit using the protection element in connection with embodiment. It is a schematic plan view of the protection transistor according to the embodiment. It is a schematic sectional drawing in connection with 1st Embodiment along the AA line and BB line of FIG. It is a top view of the protection transistor of the 1st comparative example. It is an electric field distribution map obtained by simulation of the transistor structure of the 1st comparative example. It is a snapback characteristic view showing the relation between the drain potential and current in the first comparative example. It is the figure which calculated | required the heat distribution by the TCAD simulation about the structure of a 1st comparative example. It is a top view of the protection transistor of the 2nd comparative example. It is an electric field distribution map obtained by simulation of the transistor structure of the 2nd comparative example. It is a snapback characteristic view showing the relation between the drain potential and current in the second comparative example. It is a top view which shows the current course of a 1st embodiment along with the 1st comparative example. It is a dimension figure which shows a size comparison with the transistor of a medium voltage | pressure-resistant use. It is a dimension figure which shows size comparison with the transistor of a low pressure | voltage resistant use.

An embodiment of the present invention will be described with reference to the drawings in the following procedure by using an N-channel GGMOS and an application example thereof to a protection circuit.
1. First Embodiment: An embodiment in which a current bypass path is formed by a withstand voltage difference with or without a well.
2. Second Embodiment: An embodiment in which a current bypass path is formed by a difference in withstand voltage with or without an LDD region.
3. Third embodiment: An embodiment in which a current bypass path is formed by a difference in breakdown voltage depending on the presence or absence of a well and an LDD region.
4). Fourth Embodiment: An embodiment in which a withstand voltage difference is provided by a concentration difference, thereby forming a current bypass path.
5. Modified example

<1. Application example of protection circuit>
1A and 1B show application examples of a protection circuit using a protection element according to an embodiment of the present invention.

1A and 1B is a circuit for protecting an internal circuit, and in this example, is constituted by one NMOS transistor. The transistor constituting the protection circuit may be a PMOS transistor. However, since the NMOS transistor has a high current drive capability, it is desirable as a protection element of the protection circuit.
Such a MOS-type protection transistor is denoted by a symbol “protection element TRm”. Hereinafter, it is referred to as a protection transistor TRm.

  The protection transistor TRm may be a discrete component externally attached to an integrated circuit (IC) including an internal circuit. Here, it is assumed that the protection circuit and the internal circuit are integrated on a common semiconductor substrate. Therefore, the configuration shown in FIGS. 1A and 1B corresponds to an example of the “semiconductor integrated circuit” of the present invention. The protection transistor TRm corresponds to an example of the “protection transistor” in the present invention.

The drain of the protection transistor TRm is connected to the supply line of the power supply voltage VDD, and the source thereof is connected to the reference potential line (here, GND line). The gate of the protection transistor TRm is connected to a reference potential line (GND line). For this reason, the MOS transistor having such a connection form is called a GG (Gate-Grounded) MOS transistor.
An internal circuit is connected between the supply line of the power supply voltage VDD and the GND line. For this reason, the internal circuit is driven by the power supply voltage VDD.

In FIGS. 1A and 1B, a signal input line or output line (hereinafter collectively referred to as a signal) from an input / output circuit or input / output terminal (not shown) denoted by reference numeral “I / O” is shown. Are called internal lines).
Noise due to static electricity or the like may be superimposed on this signal line. Therefore, a protective diode D1 having the signal line side as an anode is connected between the signal line and the supply line of the power supply voltage VDD. Further, a protection diode D2 having the GND line side as an anode is connected between the signal line and the GND line.

  A GGMOS transistor to which the present invention is applied may be added in place of the protection diodes D1 and D2.

FIG. 1A also serves as an explanatory diagram of the operation of the protection circuit when a positive charge surge enters the power supply terminal.
When a positive charge surge enters the supply line of the power supply voltage VDD from a power supply terminal (not shown) or the like, the potential of the supply line of the power supply voltage VDD rises due to the surge. Before the potential of the supply line of the power supply voltage VDD reaches the breakdown voltage of the internal circuit, the protection transistor TRm is turned on and enters a conductive state. Therefore, the surge escapes to the GND line through the protection transistor TRm.

FIG. 1B also serves as an explanatory diagram of the operation of the protection circuit when a positive charge surge enters the I / O terminal.
When a positive charge surge enters the I / O terminal, the protection diode D1 is biased in the forward direction and is turned on, causing the surge to flow through the supply line of the power supply voltage VDD. Next, when the supply line of the power supply voltage VDD reaches a predetermined potential, the protection transistor TRm is turned on and shifts to a conductive state. Therefore, the surge escapes to the GND line through the protection diode D1 and the protection transistor TRm. In order to protect the internal circuit, it is necessary to turn on the protective diode D1 before the input / output withstand voltage of the internal circuit is exceeded. In addition, the protection transistor TRm needs to be turned on before exceeding the (drain) breakdown voltage of the transistor in the internal circuit.
As a result, the internal circuit is prevented from being damaged by the high voltage.

As described above, the protection transistor TRm needs to have the following requirements.
(1) Resistant to electrostatic breakdown that is not destroyed by high voltage or large current generated by surge.
(2) Turns on at a voltage higher than the operating voltage of the internal circuit and lower than the breakdown voltage of the internal circuit.
(3) The impedance after turn-on is sufficiently low.
(4) The impedance when not turned on is sufficiently high.

<2. Protection transistor structure>
FIG. 2 is a schematic plan view of a protection transistor according to an embodiment of the present invention. 3A is a schematic cross-sectional view taken along line AA in FIG. 2, and FIG. 3B is a schematic cross-sectional view taken along line BB in FIG.
As shown in FIGS. 3A and 3B, the protection transistor TRm illustrated in FIG. 2 is formed on the semiconductor substrate 1 which is a P-type silicon substrate having a crystal orientation plane of 100, for example. A P-type well (hereinafter referred to as P well 2) into which impurities are introduced so as to obtain a desired threshold voltage and withstand voltage of each part is formed on the surface side in the semiconductor substrate 1.
On the surface of the P well 2, for example, a gate insulating film 3 made of SiO ₂ obtained by thermally oxidizing the surface of the semiconductor substrate 1 is formed.
On the gate insulating film 3, a gate electrode 4 made of polysilicon or the like doped with N-type or P-type impurities is formed.

  The gate electrode 4 has an elongated finger portion. At least one finger portion is formed, usually a plurality of finger portions. In the plan view of FIG. 2, a portion corresponding to one of the finger portions (or the entire transistor in the case where the finger portion is single) is shown. One side of the finger portion in the width direction is a drain, and the other side is a source. Here, the width direction of the finger portion corresponds to the “gate length direction (first direction)”.

More specifically, a drain region 6 is formed by introducing an N-type impurity at a high concentration into a P well 2 portion located on one side of the gate electrode 4 (finger portion) in the gate length direction. A source region 5 is formed by introducing an N-type impurity at a high concentration into the P well 2 portion located on the other side in the gate length direction of the gate electrode (finger portion), similarly to the drain region 6.
Here, as shown in FIG. 2, the distance between the drain region 6 and the gate electrode 4 is larger than the distance between the source region 5 and the gate electrode 4. Of these, the region between the source region 5 and the gate electrode 4 is hereinafter referred to as a gate-source region REgs. A region between the drain region 6 and the gate electrode 4 is hereinafter referred to as a gate-drain region REgd.

The gate insulating film 3 may be processed into the same pattern as the gate electrode 4 or may be left almost entirely as shown in FIGS. 3 (A) and 3 (B).
An interlayer insulating film 11 is formed covering the surfaces of the gate insulating film 3 and the gate electrode 4, and a source electrode 12 and a drain electrode 13 are formed on the interlayer insulating film 11 so as to be separated from each other.

Two contact holes reaching part of the source region 5 and the drain region 6 are opened in the interlayer insulating film 11. A portion where the interlayer insulating film 11 is opened on the source region 5 is referred to as a “drain contact portion”. A silicide layer 10D is formed in the drain contact portion, and the drain electrode 13 on the interlayer insulating film 11 is electrically connected to the upper surface of the drain contact portion via a metal plug or the like.
On the other hand, a portion where the interlayer insulating film 11 is opened on the source region 5 is referred to as a “source contact portion”. A silicide layer 10S is formed in the source contact portion, and the source electrode 12 on the interlayer insulating film 11 is electrically connected to the upper surface of the source contact portion via a metal plug or the like.

The planar pattern of the above structure will be described. In the plan view of FIG. 2, the gate electrode 4 is formed in a strip shape that is long in the y direction (gate width direction; second direction). Here, the gate width direction (second direction) is a direction orthogonal to the gate length direction (first direction; x direction).
On one side in the x direction of the gate electrode 4, a drain region 6 is disposed in parallel with the gate electrode 4 via a gate-drain region REgd.
Similarly, the source region 5 is arranged in parallel to the gate electrode 4 on the other side in the x direction of the gate electrode 4 via the gate-source region REgs.

A silicide layer 10 </ b> D is formed in a part of the center of the drain region 6. From the structure of FIG. 3, the silicide layer 10 </ b> D is electrically equivalent to the drain electrode 13.
Similarly, a silicide layer 10 </ b> S is formed in a part of the center of the source region 5. From the structure of FIG. 3, the silicide layer 10 </ b> S is electrically equivalent to the source electrode 12.

  In the present embodiment, the gate-drain region REgd is divided into two regions having different structures corresponding to the positions of the two silicide layers 10D and 10S, that is, the first region REgd1 and the second region Regd2. There is a feature.

More specifically, as described above, the silicide layer 10D is a conductive part electrically equivalent to the drain electrode 13, and the silicide layer 10S is a conductive part electrically equivalent to the source electrode 12. In the present embodiment, it is assumed that the electrically conductive portion electrically equivalent to the electrode is a part of the electrode.
Therefore, it can be said that the first region REgd1 is disposed so as to include the shortest distance portion between the source electrode (more strictly, the silicide layer 10S) and the drain electrode (more strictly, the silicide layer 10D).

  In the example of FIG. 2, each of the silicide layers 10 </ b> D and 10 </ b> S has a rectangular planar shape in the x direction, and a rectangular region connecting one end and the other end of the opposing long sides is the shortest distance region. The planar shape of the gate-drain region REgd is determined so as to partially include the shortest distance region. Specifically, the positive side edge EG1 in the y direction of the gate-drain region REgd1 is located away from the shortest distance boundary region defined by the line connecting the silicide layers 10D and 10S with a straight line. is doing. Further, the negative side edge EG2 in the y direction of the gate-drain region REgd1 is located away from the shortest distance region on the negative side in the y direction.

  Two second regions REgd2 are arranged adjacent to the positive side edge EG1 and the negative side edge EG2 in the y direction of the first region REgd1.

As will be described later, a positive voltage (surge voltage such as static electricity) is applied to the drain electrode 13 with reference to the potential of the source electrode 12. With respect to the application of the drain voltage, the breakdown voltage of the second region REgd2 is set lower than the breakdown voltage of the first region REgd1.
This withstand voltage difference is determined by the impurity region distribution structure design (drain engineering) of the drain. There are various methods of providing a withstand voltage difference as in the other embodiments, but in the first embodiment, the withstand voltage difference is provided by the presence or absence of the P well 2.

3A is a cross-sectional view of the gate-drain region REgd2, and FIG. 3B is a cross-sectional view of the first region REgd1.
In the first region REgd1 and the second region REgd2, a so-called LDD region 8 is provided on the surface of the substrate. The LDD region 8 is shallower than the drain region 6 and has a low N-type impurity concentration.
However, in the second region REgd2 shown in FIG. 3A, the P well 2 exists under the LDD region 8, but in the first region REgd1 shown in FIG. 3B, the P well 2 exists under the LDD region 8. not exist. The presence or absence of the P-well 2 is a factor that causes the above-described difference in breakdown voltage.

In FIG. 2, junction breakdown is likely to occur at a portion surrounded by an ellipse A, and this portion determines the breakdown voltage of the second region REgd2. Further, junction breakdown is likely to occur in the portion surrounded by the ellipse B, and this portion determines the breakdown voltage of the first region REgd1. This is because, as can be seen from the cross sections of FIGS. 3A and 3B, electric field concentration is likely to occur at the corner portion (convex portion) of the drain region 6 on the deeper side of the substrate closer to the gate. .
In the PN junction at this convex portion, in the case of FIG. 3A, a relatively high concentration P well 2 is adjacent, but in the case of FIG. 3B, a P type semiconductor substrate 1 having a lower concentration is present. Adjacent. Since the depletion layer extends to the low concentration side, when the same drain voltage is applied, the structure of FIG. 3B has a larger depletion layer thickness and a correspondingly higher breakdown voltage (junction breakdown voltage).

  For example, the first region REgd1 (FIG. 3B) has a breakdown voltage of about 50 [V], and the second region REgd2 (FIG. 3A) has a breakdown voltage of about 30 [V]. Designed. The structural parameters that determine the breakdown voltage include the N-type impurity concentration and depth of the drain region 6 and the LDD region 8, and the P-type impurity concentration of the P well 2 and the semiconductor substrate 1.

On the other hand, in the gate-source region REgs, the channel formation region (a part of the P well 2) directly below the gate electrode and the source region 5 are connected through the single LDD region 7 in the gate width (y direction). ing.
Since the LDD region 7 is usually formed simultaneously with the LDD region 8, it has the same impurity concentration and depth.

  Since the LDD region 7 and the LDD region 8 need to form a convex portion for electric field concentration at the boundary between the LDD region 8 and the drain region 6, their depth is the same as the drain region 6 (and at the same time). Shallower than the source region 5) to be formed. However, the N-type concentration of the LDD region 7 and the LDD region 8 may be approximately the same as that of the source region 5 and the drain region 6 as long as electric field concentration occurs in the convex portion. These two shallow impurity regions may be called extension regions instead of LDD regions.

  Note that the depth and the N-type concentration of the LDD region 8 (and the LDD region 7) are depleted in the entire depth direction of the LDD region 8 when the junction breakdown occurs near the boundary between the LDD region 8 and the drain region 6. do not do. Therefore, it is desirable to set the depth and concentration so that the electrically neutral region remains as a resistance layer on the substrate surface side. This is because it is desirable that a part of the LDD region 8 acts as a resistance layer at the time of junction breakdown in that the junction breakdown also occurs in the LDD region 8 and the overheated portions are dispersed.

  Although not shown in FIGS. 2 and 3, normally, a well contact region into which a P-type impurity is introduced at a high concentration is formed in the P well 2, whereby the P well 2 has the same potential as the source. It is desirable to fix. As will be described later, after the junction breakdown on the drain side, the potential of the P well 2 rises to cause a parasitic bipolar operation. However, the parasitic bipolar operation is more stably generated when the potential of the P well 2 is fixed. It is easy.

As described above, the silicide layer 10D is provided in contact with the drain electrode 13 (or a metal plug that is a part thereof). In the case of FIG. 3, the silicide layer 10D is formed with substantially the same area as the metal plug. The same applies to the silicide layer 10S on the source electrode 12 side.
The silicide layer is formed by thermally reacting silicon and an alloy layer, but its heat resistance is lower than that of silicon itself.
The pattern layout shown in FIG. 2 intends to separate the second region REgd2 whose junction breakdown voltage is relatively low and whose drain end is a heat generating portion from a portion having low heat resistance such as a silicide layer.

  Even when there is no silicide layer, the contact resistance may increase when the drain contact portion where the drain electrode is in contact with silicon is overheated. In that sense, formation of the silicide layer is not essential, and it makes sense to separate the second region REgd2 from the contact portion of the drain electrode. However, when a silicide layer is provided, the silicide layer is particularly vulnerable to heat, so the layout of FIG. 2 has a greater meaning (effect).

[Surge removal by ESD operation]
The operation of each part when a surge enters the protection transistor TRm having the structure of FIGS. 2 and 3 will be described with reference to FIGS. Here, in describing the advantages (effects) of the above structure, the effects of application of the present invention will be clarified by comparing the operation with the structure of a comparative example that does not employ the above structure.

<< First Comparative Example >>
FIG. 4 is a plan view of the protection transistor of the first comparative example. In FIG. 4, the same components as those in FIG.
The transistor structure of the first comparative example shown in FIG. 4 is different from the structure shown in FIG. 2 in that the gate-drain region REgd existing between the gate electrode 4 and the drain region 6 is the same as the second structure shown in FIG. This is a point constituted only by the region REgd2. The other structure is common in FIG. 4 and FIG.

FIG. 5 shows a simulation result (impurity distribution diagram) based on the transistor structure of FIG. In the impurity distribution diagram used in this embodiment including FIG. 5, the higher the concentration, the darker the lighter and darker the impurity concentration distribution is.
In FIG. 5, the drain region 6, the LDD region 7, and the LDD region 8 are formed on the surface portion of the P well 2, as in FIG. For this reason, the corner (projection) of the drain region 6 near the gate near the gate is in contact with the P well 2. Junction breakdown occurs at the convex portion, but the junction between the drain region 6 and the LDD region 8 is shallow. This is because the P well 2 has a higher P-type impurity concentration than the semiconductor substrate 1.

Here, as an example, an example of density and depth is shown.
In this example, the concentration (ion implantation dose) of the P well 2 is about 1E17 [atms / cm ² ], the concentration of the LDD region 8 is about 1E18 [atms / cm ² ], and the concentration of the drain region 6 is 1E20 [atms / cm ² ]. cm ² ]. The depth of the LDD region 8 is about 0.2 [μm], and the depth of the drain region 6 is about 0.4 [μm]. The drain electrode 13 allows a current to flow to the drain via the drain contact portion, but the silicide layer 10D is often interposed between the drain electrode 13 for further relaxing the resistance (reducing connection resistance).

FIG. 6 shows the relationship between the drain electrode potential (hereinafter, drain potential Vdrain) and the drain current Idrain. The graph of FIG. 6 shows a calculation example obtained by device simulation based on the simulation structure of FIG.
In this operation calculation, the surge current is regarded as equivalent to the case where a current source that monotonously increases with a ramp function with respect to time is connected to the drain of the transistor. Therefore, although the voltage actually applied to the drain is monotonously increased, the horizontal axis in FIG. 6 corresponds to the drain potential when the drain applied voltage is increased, not the drain applied voltage.
When the drain application voltage is increased, since the channel of the protection transistor TRm is off, no current flows at first, and only the drain potential Vdrain increases in proportion to the drain application voltage. In FIG. 6, the drain potential suddenly rises to about 30 [V].

  In FIG. 6, junction breakdown occurs at a convex portion of the drain region 6 (corner portion on the deep side of the substrate near the boundary with the LDD region 8) in the vicinity of about 30 [V]. For this reason, in this element, the withstand voltage against the drain voltage is about 30 [V].

When a junction breakdown (usually an avalanche breakdown) occurs, a hole current generated by the avalanche breakdown flows through the P well 2 and is taken out from a well electrode (not shown). At this time, the hole potential rises as a hole current flows through the resistance component in the P-well 2.
The raised well potential biases the PN junction between the source region 5 and the P well 2 in the forward direction. Therefore, electrons are injected from the source region 5 into the P well 2 to start a bipolar operation, the drain voltage is reduced, and snapback is observed. Since the drain voltage is lowered, impact ionization due to avalanche breakdown at the convex portion is relatively weakened.

  On the other hand, the injected electron current flows along the shortest path from the source region 5 to the drain region 6 and is taken out from the drain electrode 13 through the LDD region 8.

When the surge current further increases, the potential of the drain region 6 rises again due to the voltage drop generated in the LDD region 8. As a result, the critical electric field for avalanche breakdown is reached at the convex portion of the drain region 6 where the electric field is concentrated, and the junction breakdown (avalanche breakdown) becomes stronger again. The ratio of the hole current generated by the avalanche breakdown is extracted from the source electrode 12 through the well avoiding the LDD region 8 having a high potential.
In this series of snapback operations, avalanche breakdown occurs in a concentrated manner on the convex portion of the drain region 6.

FIG. 7 is a diagram showing the heat distribution obtained by TCAD simulation. The higher the temperature, the darker the light and darker the heat distribution is.
From FIG. 7, it can be seen that the heat generation is most intense at the end of the drain region 6 (the convex portion at the deep part of the substrate near the gate). In addition, junction breakdown occurs partly in the middle of the LDD region 8.

In the layout of the first comparative example as shown in FIG. 4, since the silicide layer 10 </ b> D is close to the heat generation portion surrounded by the ellipse C, there is a high possibility that the device is destroyed there. Even when the silicide layer 10D is not provided, contact failure of the drain electrode is likely to occur due to heat generation.
In particular, when the silicide layer 10D is provided, the silicide has low heat resistance, and the allowable temperature of silicon is about 1600 [° C.], whereas the allowable temperature of cobalt silicide is about 800 [° C.]. If the heating exceeds the allowable temperature, the cobalt silicide may be melted to increase the resistance, or may be broken and become a defective contact.

The ESD protection element (GGMOS) needs to pass as much current as possible after snapback. The limit current that prevents current from flowing any more due to breakdown is generally referred to as breakdown current It2. The ESD protection element (GGMOS) cannot play the role of surge removal if the breakdown current It2 is reached at the same time as snapback or shortly thereafter.
The first comparative example has a drawback that the breakdown current It2 is low because the drain contact is close to the heating location.

<< Second Comparative Example >>
In the second comparative example, as a simple method for overcoming the drawbacks of the first comparative example, the fragile silicide or contact portion is separated from the heat generating place.
FIG. 8 shows a plan view of the second comparative example.
The second comparative example is different from the first comparative example of FIG. 4 in that the drain region 6 is provided large and the drain contact portion (here, silicide layer 10D) is separated from the gate side edge of the drain region 6.

  However, in the case of the second comparative example, in order to make the breakdown current It2 sufficiently large, as shown in FIG. 8, the drain contact portion (where the ellipse C is located) where the junction breakdown occurs and the drain contact portion (here, the silicide layer 10D). Must be separated considerably, which has the disadvantage of increasing the device area.

In the above-mentioned Patent Document 2, in order to make this separation distance as small as possible, an effect of suppressing the heat generation at the drain edge that is heated most by disposing the junction portion itself by alternately providing portions with high and low drain impurity concentrations. Aiming.
However, also in this case, the drain edge portion (the portion of the ellipse C) remains the most heated, and the effect is limited. This is because, as described above, since the LDD region has a high resistance due to depletion, the rate at which current flows in the well increases as the drain voltage increases.
On the other hand, if the breakdown voltage at the heating location is increased, the breakdown current It2 also increases. However, this is a tip-over, and the surge cannot protect the internal circuit.

  As in the first comparative example and the second comparative example described above, it is difficult to achieve both a desired appropriate breakdown voltage (turn-on voltage) and an increase in transistor size to prevent breakdown.

The embodiment of the present invention presents the structure shown in FIGS. 2 and 3 in order to achieve both.
In specific implementation, the depth and concentration of the impurity region used in the simulations of FIGS. 5 and 6 can be employed for the second region REgd2 of FIG.
Therefore, when limited to the second region REgd2, its breakdown voltage and operation curve are substantially the same as those described above with reference to FIGS.

FIG. 9 and FIG. 10 show electric field distribution and snapback characteristics regarding the first region REgd1 of FIG.
9 and 10 show the calculation results on the premise that the entire region of the gate-drain region REgd in the layout structure of FIG. 4 does not have the P well 2 as in the first region REgd1 of FIG. However, in the simulation of FIG. 9, the P well 2 itself is omitted including immediately under the LDD region 8.

  As is clear from comparison of FIG. 9 with FIG. 5, the junction position from the LDD region 8 and the drain region 6 becomes relatively deep unless the P well 2 is provided immediately below the LDD region 8. Since the P-type impurity concentration immediately below the LDD region 8 is lower than when a P-well is provided, the depletion layer tends to extend and the breakdown voltage is as high as about 50 [V]. Further, as shown in FIG. 10, after snapping back once, it reaches a peak again, and then the drain potential Vdrain is lowered, so that the second avalanche breakdown can be clearly seen from the characteristics.

FIG. 11B shows a current path at the time of junction breakdown in the first embodiment. For comparison, FIG. 11A shows a current path at the time of junction breakdown in the first comparative example.
The structure related to the first embodiment shown in FIG. 2 and FIG. 3 (FIG. 11B) is a hybrid of the 50 [V] breakdown voltage structure and the 30 [V] breakdown voltage structure, but the device breakdown voltage is lower. Therefore, the breakdown voltage of the protection transistor TRm is about 30 [V]. This is because, as shown in FIG. 11B, the drain current Idrain at the breakdown of the junction flows on the low side with a breakdown voltage of about 30 [V]. Once the junction breakdown occurs, thereafter, the operation shifts to the operation in which the well is a current channel by the parasitic bipolar operation. Therefore, the junction breakdown in the 50 [V] breakdown voltage structure usually does not occur.

  The current flows detouring through the first breakdown region, and junction breakdown occurs in the middle of the detour current, so that the heat generating portion and the contact portion of the drain electrode are separated. As a result, a larger amount of current can be flowed than in the first comparative example, and higher It2 can be ensured. Further, the occupied area of the element is almost the same as that of the first comparative example, and an increase in area as in the second comparative example can be avoided.

The amount of heat generated at the heat generating portion is not much different between the structure of the first comparative example and the structure of the present embodiment.
However, in the first comparative example, a silicide having low heat resistance is nearby and breaks down, whereas in this embodiment, device breakdown occurs after the temperature rises until silicon having high heat resistance breaks.
When a simulation is performed, this temperature difference is about 10 times as a current. That is, in the device structure of the present embodiment, the breakdown current It2 is about 10 times that of the first comparative example.

[Production method]
Next, a method for manufacturing the protection transistor TRm will be described. It should be noted that existing methods can be applied to the outline of the manufacturing method only in the well formation pattern.
In order to form the P well 2 on the semiconductor substrate 1 made of high-concentration P-type silicon, a low-concentration P-type silicon layer is epitaxially grown. At this time, a growth layer of the P well 2 can be defined by forming a mask layer for the epitaxial growth element on the substrate surface in advance. In the present embodiment, the epitaxial growth is also prevented by the mask layer at a location that later becomes the first region REgd1.
When the pattern accuracy by epitaxial growth is insufficient, the well may be formed by selective ion implantation using an ion implantation mask.

The gate insulating film 3 is formed by thermally oxidizing the surface of the semiconductor substrate 1. The thickness of the silicon oxide film to be the gate insulating film 3 is determined so that a desired gate breakdown voltage and threshold voltage can be obtained with MOSFETs formed on the same substrate.
Subsequently, a polysilicon layer (not shown) is deposited on the gate insulating film 3 using a thermal CVD method, and phosphorus (P) ions are ion-implanted at a high concentration into the polysilicon layer.
Subsequently, after applying a resist (not shown) to the entire surface of the semiconductor substrate, optical lithography is performed to transfer the gate pattern to the resist. Thereafter, reactive ion etching is performed using the resist pattern as a mask to remove unnecessary portions of the polysilicon layer. Thereafter, the resist is removed by ashing to obtain the gate electrode 4.

  The semiconductor substrate 1 is covered with a resist, and optical lithography is performed to open the region from the gate electrode 4 to the region that becomes the drain region 6. Subsequently, phosphorus (P) ions for forming the LDD region 7 and the LDD region 8 are implanted into the surface of the semiconductor substrate 1. The dose amount and implantation energy of phosphorus (P) may be determined according to the thickness of the gate insulating film 3 serving as a through film and a desired drain breakdown voltage. Thereafter, the resist is removed by ashing or the like.

  The semiconductor substrate 1 is covered with a resist, and optical lithography is performed to open the source region 5 and the drain region 6. Subsequently, arsenic (As) ions and phosphorus (P) ions are sequentially implanted into the surface of the semiconductor substrate 1. The dose amount and implantation energy of each ion are determined so that a surface concentration sufficient to form an ohmic contact with a source electrode and a drain electrode to be formed later and a junction depth deeper than the LDD region 8 can be obtained. . Thereafter, the resist is removed.

The semiconductor substrate 1 is covered with a resist, and optical lithography is performed to open a region for forming a well contact region. Subsequently, boron (B) ions or boron fluoride (BF ² ) ions are implanted into the surface of the semiconductor substrate 1. The dose and the implantation energy are determined so that a surface concentration sufficient to form an ohmic contact with a well electrode to be formed later is obtained. Thereafter, the resist is removed.

The substrate is subjected to a heat treatment to activate the impurity atoms implanted in the steps so far.
Subsequently, SiO ₂ is deposited thickly on the surface of the substrate by plasma CVD, and the surface is flattened using CMP, thereby obtaining the interlayer insulating film 11.
Subsequently, a resist film (not shown) is formed on the entire surface of the substrate, and optical lithography is performed to transfer the pattern of connection holes provided in the source region 5, the drain region 6, and the well contact region to the resist film. Thereafter, reactive ion etching is performed to form connection holes to the respective parts.

  Next, an alloy for forming a silicide is buried in the connection hole and reacted with silicon by heat treatment. Further, a metal such as tungsten is buried by sputtering or CVD, and a wiring layer made of aluminum is formed thereon. Thereby, the source electrode 12, the drain electrode 13, and the well electrode 14 are obtained.

With the above method, the protection transistor TRm according to the first embodiment is obtained.
The starting substrate is not necessarily a high-concentration P-type substrate, and may be a high-resistance P-type substrate or an N-type substrate.

<2. Second Embodiment>
In the first embodiment, the P-well 2 is not formed in the first region REgd1 to provide a withstand voltage difference from the second region REgd2. However, the same effect is obtained by not providing the LDD region 8 in the first region REgd1. Can also be obtained.

<3. Third Embodiment>
By applying both the first embodiment and the second embodiment, the same effect can be obtained by restricting the current at the junction breakdown substantially to the second region REgd2. In this case, the current during the bipolar operation flows through the portion of the semiconductor substrate 1 immediately below the first region REgd1.

<4. Fourth Embodiment>
In the first embodiment, the withstand voltage difference is provided depending on the presence or absence of the P well 2, but the withstand voltage difference may be provided with the concentration of the P well 2. In this case, the well concentration in the first region REgd1 is set lower than that in the second region REgd2 in FIG.

  The above first to fourth embodiments are summarized as follows: “The total impurity amount in the substrate depth direction from the surface of the first region REgd1 is smaller than the total impurity amount in the substrate depth direction from the surface of the second region Regd2”. This is a preferable application requirement of the present invention.

<5. Modification>
The above is an example in which the channel conductivity type is GGMOS, but the present invention can also be applied to P-type GGMOS.
In this case, the configuration and operation of the P-type GGMOS are described above by reversing the conductivity type of the impurities, the accompanying carrier polarity, the direction of the applied voltage to the source and drain, etc. as is well known. Can be applied by analogy.
Further, unlike the GGMOS, the gate potential may be fixed at an appropriate potential without short-circuiting the gate and the source (drain in the case of P-type).

  The semiconductor substrate 1 is not limited to a substrate made of silicon or other semiconductor material. For example, even when a substrate made of a semiconductor or a material other than a semiconductor is used as a support substrate and a semiconductor layer is formed on the substrate, the substrate is defined as belonging to the category of “semiconductor substrate” in the present invention. Therefore, an SOI substrate having an SOI layer insulated and separated from the substrate, or a substrate for forming a thin film transistor may be used as a semiconductor substrate.

  According to the first to fourth embodiments and the modifications described above, high It2 can be realized by using this method when performing ESD protection of a circuit using GGMOS or the like. The breakdown current It2 is 10 times that of the first comparative example to which the present invention is not applied. Even when the same breakdown voltage and breakdown current It2 are obtained, the area can be reduced as compared with the second comparative example.

FIGS. 12 and 13 show calculation examples of the area of the second comparative example in which the drain electrode is simply separated in the case of a medium withstand voltage application of 30 [V] and in the case of a low withstand voltage application having a lower withstand voltage. Show. 12A and 13A are dimensional views of the second comparative example, and FIG. 12B is a dimensional view of the first embodiment.
In the medium / high withstand voltage structure shown in FIG. 12 (B), the area can be reduced to almost half of 58 [%] compared to the second comparative example (FIG. 12 (A)) having the same medium withstand voltage structure. Further, in the low breakdown voltage structure shown in FIG. 13B, the area can be reduced to about 1/3, which is about 38 [%], compared with the second comparative example (FIG. 13A) having the same low breakdown voltage structure.

  As described above, according to the embodiment of the present invention, it is possible to make the withstand voltage and the breakdown current It2 at a practical level and to suppress the area increase or to reduce the area. According to the present invention, since the area can be reduced without particularly increasing the process cost, it is possible to provide a protection transistor and a semiconductor integrated circuit that are advantageous for mounting on a semiconductor integrated circuit.

DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 2 ... P well, 3 ... Gate insulating film, 4 ... Gate electrode, 5 ... Source region, 6 ... Drain region, 7, 8 ... LDD region, 10D, 10S ... Silicide layer, 11 ... Interlayer insulating film , 12 ... Source electrode, 13 ... Drain electrode, TRm ... Protection transistor, REgd ... Gate-drain region, REgd1 ... First region, REgd2 ... Second region

Claims (8)

A gate electrode stacked on a channel formation region of a semiconductor substrate via a gate insulating film;
A gate-drain region of a second conductivity type adjacent to the channel formation region on one side in a first direction defining the gate length of the gate electrode;
A drain region of a second conductivity type adjacent to the gate-drain region on the opposite side of the channel formation region in the first direction;
A second conductivity type source region located on the other side of the channel formation region in the first direction;
A source electrode and a drain electrode in contact with each of the source region and the source region;
Have
The region between the gate and drain is adjacent to each other in a second direction orthogonal to the first direction in plan view,
A first region having a relatively high breakdown voltage with respect to a drain voltage applied to the drain electrode with reference to the potential of the source electrode;
A protection transistor comprising: a second region having a distance from the drain electrode farther than the first region in plan view and a relatively low breakdown voltage. The first region is disposed so that the distance from the source contact portion where the source region and the source electrode are in contact to the drain contact portion where the drain region and the drain electrode are in contact includes the shortest region,
The second region is disposed adjacent to at least one side of the first region in the second direction;
The protection transistor according to claim 1, wherein the drain region extends on one side of the second region in the first direction. The protection transistor according to claim 2, wherein a silicide layer is formed on each of the source contact portion and the drain contact portion. The protection transistor according to claim 3, wherein a total impurity amount in a substrate depth direction from the surface of the first region is smaller than a total impurity amount in a substrate depth direction from the surface of the second region. The region between the gate and the drain is an LDD region having a lower impurity concentration of the second conductivity type than the drain region,
The portion of the LDD region to be the second region, the source region and the drain region are formed in a first conductivity type well formed in a semiconductor substrate,
The channel forming region is a surface side portion of the well;
The protection transistor according to claim 4, wherein a portion of the LDD region serving as the first region is formed in a region of a semiconductor substrate where the well is not formed. The first region and the second region are LDD regions having a lower impurity concentration of the second conductivity type than the drain region,
The protection transistor according to claim 4, wherein the first region has a lower impurity concentration of the second conductivity type in the LDD region than the second region. The protection transistor according to claim 4, wherein the protection transistor is a gate grounded MOS transistor that is turned on when a source electrode and the gate electrode are connected to a reference potential line and a voltage higher than a certain voltage is applied to the drain electrode. Transistor. Internal circuitry,
A protection transistor that turns on when a voltage greater than a certain voltage is applied to a terminal of the internal circuit;
Have
The protection transistor is
A gate electrode stacked on a channel formation region of a semiconductor substrate via a gate insulating film and electrically connected to a reference potential line of the internal circuit;
A gate-drain region of a second conductivity type adjacent to the channel formation region on one side in a first direction defining a gate length direction of the gate electrode;
A drain region of a second conductivity type adjacent to the opposite side of the channel formation region in the first direction with respect to the gate-drain region;
A second conductivity type source region located on the other side of the channel formation region in the first direction;
A source electrode formed on and in contact with the source region and electrically connected to the reference potential line;
A drain electrode formed on and in contact with the drain region and electrically connected to the terminal of the internal circuit;
Have
The region between the gate and drain is adjacent to each other in a second direction orthogonal to the first direction in plan view,
A first region having a relatively high breakdown voltage with respect to a drain voltage applied to the drain electrode with reference to the potential of the source electrode;
A semiconductor integrated circuit comprising: a second region having a distance from the drain electrode farther than the first region in plan view and a relatively low breakdown voltage.

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