JP5413693B2 - Circuit forming support substrate and method of manufacturing semiconductor device mounting package substrate - Google Patents

Description

The present invention relates to a method of manufacturing a circuit-forming support substrate and a semiconductor device mounting package substrate.

  In recent years, electronic devices have been further reduced in size, weight, and functionality, and along with this, higher integration and miniaturization of wiring are rapidly progressing, and miniaturization of wiring is progressing. In addition, a ceramic substrate has been used as a semiconductor package substrate. However, in recent years, an organic resin substrate has been used because of its price and ease of processing, and many circuit board technologies have been incorporated. In a semiconductor package using such a semiconductor package substrate, the number of input terminals increases as the degree of semiconductor integration increases. Therefore, a semiconductor package having a large number of output terminals is required.

  In general, there are a type in which input / output terminals are arranged in a single row around the package and an array type in which the input / output terminals are arranged in multiple rows not only at the periphery but also inside. The former is typically QFP (Quad Flat Package). In order to increase the number of terminals, it is necessary to reduce the terminal pitch. However, in a region having a pitch of 0.5 mm or less, advanced technology is required for connection to the wiring board. The latter array type is suitable for increasing the number of pins because terminals can be arranged with a relatively large pitch. Conventionally, an array type is generally a PGA (Pin Grid Array) having connection pins, but connection with a wiring board is an insertion type and is not suitable for surface mounting. For this reason, a package called BGA (Ball Grid Array) that can be mounted on the surface has become the mainstream.

  Further, with the downsizing of electronic devices, there is an increasing demand for further downsizing of the package size. In order to cope with this miniaturization, a so-called chip size package (CSP; Chip Size / Scale Package) having a size almost equal to that of a semiconductor chip has been proposed. This is a package having a connection portion with an external wiring board in the mounting region, not in the peripheral portion of the semiconductor chip. As a specific example, a polyimide film with bumps is bonded to the surface of a semiconductor chip, and after electrically connecting the chip and a gold lead wire, epoxy resin is potted and sealed (Non-patent Document 1) or on a temporary substrate In addition, a metal bump is formed at a position corresponding to a connection portion between the semiconductor chip and the external wiring substrate, the semiconductor chip is face-down bonded, and then transfer molded on a temporary substrate (Non-patent Document 2).

  On the other hand, also in the formation of fine wiring, the wiring that can be formed with high yield by the subtractive method of forming wiring by etching is about conductor width (L) / conductor gap (S) = 50 μm / 50 μm. Further, when the wiring becomes finer conductor width / conductor gap = about 35 μm / 35 μm, for example, as disclosed in Patent Document 1, a relatively thin plating layer is formed on the surface of the base material, and a plating resist is applied thereon. A semi-additive method in which a conductor is formed to a required thickness by electroplating, and then the thin plating layer is removed by soft etching after resist stripping has attracted attention. In addition, a method of forming a thin copper foil layer by forming a peelable copper foil with a carrier formed by a heating / pressing press method instead of a thin plating layer and then removing the carrier has been studied. Further, when the wiring is finer conductor width / conductor gap = 25 μm / 25 μm or less, there are about 1 to 3 μm of roughened shapes of copper foil, roughened plating and chemical roughening. In order to reduce the thickness of the wiring or increase the width of the wiring, it is necessary to form a plating resist on the thin film using the sputtering method. After the resist is peeled off, the wiring is formed by a semi-additive method in which the sputtered thin film layer is removed by soft etching.

  The layer structure of a normal semiconductor device mounting package substrate is an even-numbered layer (two layers, four layers, six layers,...). This is because a process in which a central layer (an even layer) called a core layer is first produced and layers are sequentially formed on both sides thereof is the mainstream. Therefore, even if the wiring structure originally fits in the odd number layer, it is necessary to add at least one layer to make the even number layer. (Fig. 6)

  In one method of manufacturing a substrate having the minimum number of layers, a first circuit is formed on a metal plate having a certain thickness, an insulating layer is formed with an insulating resin, and the first layer is formed on the insulating layer. There is a method of forming a circuit 2 and forming a non-through hole for connecting the first and second circuits and then removing the metal plate by a chemical etching method to obtain a circuit board. However, in this case, since the wiring formation is limited to one side of the metal plate (FIG. 7), there is a problem that the production efficiency is not good. Furthermore, since the number of layers is stacked on one side of the metal plate, warpage occurs in the entire substrate during the manufacturing process due to the difference in thermal expansion coefficient between the metal plate and the layer to be laminated, and the fine wiring formation accuracy is significantly reduced. There was a problem.

  On the other hand, instead of a metal plate, for example, as disclosed in Patent Document 2, if a substrate with a detachable double-sided copper foil can be used as a support substrate, a circuit pattern can be formed simultaneously on both sides. Productivity is twice that when a metal plate is used for the support layer. Further, since the layers are laminated on the front and back, the entire substrate is well balanced with respect to warpage during manufacture, and fine wiring can be stably formed.

  In the production of a substrate with the separation of the insulating resin layer from the support substrate layer, mechanical stress such as peeling work or chemical stress such as dissolution and separation of the metal layer by chemical etching at the time of separation It is necessary to minimize the load on the insulating resin layer. In addition, in order to form wiring on the copper foil after separation, it is required that there is no surface modification of the separation interface such as manufacturing chemical solution contamination, organic matter contamination, and formation of an alloy layer by heating in the manufacturing process before separation. .

NIKKEI MATERIALS & TECHNOLOGY) 94.4, no. 140, p18-19 Smallest Flip-Chip-Like Package CSP; The Second VLSI Packaging Workshop of Japan, p46-50, 1994

Japanese Patent Laid-Open No. 11-186716 JP 2005-101137 A

The present invention is superior to the wiring density, and a manufacturing method of high semiconductor element mounting package substrate connection reliability at low cost that can be thinner substrate, supporting the circuit-forming is required in the process of making same substrate The purpose is to provide.

The present invention provides a circuit in which an insulating resin layer is bonded to copper foils on both sides of a copper clad laminate via a copper foil (inner layer) having a size slightly smaller than the copper clad laminate and the copper foil of the copper clad laminate. It is a support substrate for formation, and a copper foil (inner layer) having a size slightly smaller than the copper foil of the copper clad laminate and the copper clad laminate is directly disposed on the copper foils on both sides of the copper clad laminate, the inner layer side of the insulating resin layer, and the copper foil of the copper-clad laminate are bonded at four sides end of the copper-clad laminate and a copper foil of slightly smaller size than the copper foil of the copper-clad laminate (inner layer) , the outer layer of the insulating resin layer, a copper foil (outer layer) relates to a circuit forming support substrate that will be disposed.
The present invention also relates to a method for manufacturing a package substrate for mounting a semiconductor element manufactured by the following steps a to h.
a. A copper-clad laminate, and a copper foil (inner layer) that is directly disposed on the copper foils on both sides of the copper-clad laminate, and that is slightly smaller than the copper foil of the copper-clad laminate and the copper-clad laminate, Forming a support substrate for circuit formation having an insulating resin layer having a size larger than the copper foil and a copper foil disposed on the insulating tree side (outer layer);
b. Forming a non-through hole for connection from the copper foil disposed on the insulating resin side (outer layer) toward the copper foil side (inner layer);
c. A step of connecting the non-through hole portion connecting the copper foil and the copper foil (inner layer) disposed on the insulating resin side (outer layer) by electrolytic copper plating or electroless plating;
d. Forming a first wiring conductor by forming a copper foil disposed on the insulating resin side (outer layer) by a subtractive method or a semi-additive method,
e. A roughening process for obtaining adhesion with the insulating resin on the surface of the first wiring conductor;
f. Placing the insulating resin in contact with the first wiring conductor roughened in step e, placing a copper foil on the insulating resin side (outer layer), and laminating by heating and pressing;
g. A step of cutting the size of the copper foil (inner layer) one size smaller than the size of the copper foil and releasing the insulating resin layer from the copper-clad laminate as a support;
h. A step of forming a wiring by a subtractive method or a semi-additive method by cutting the copper foil layer exposed by being separated from the support by cutting.

By using the circuit-forming support substrate of the present invention, it is possible to efficiently manufacture a semiconductor device mounting package substrate and a semiconductor package having excellent wiring density.
The method for manufacturing a package substrate for mounting a semiconductor element according to the present invention enables wiring accommodation with a minimum number of layers. Therefore, the number of layers is reduced, and the package substrate for mounting a semiconductor element is thinner than the conventional one. Make it possible.

  In addition, the copper-clad laminate of the circuit-forming support substrate in the present invention is a base material in which a normal glass cloth is impregnated with a thermosetting resin, a film material, or a base material in which an adhesive is disposed on both sides of a metal plate, etc. By forming a copper-clad laminate in which copper foil is bonded to both surfaces by heating and pressing, an insulating resin layer can be formed on both sides of the support substrate, and wiring can be formed simultaneously on both sides.

  Support substrate at the time of heating and cooling during manufacture by selecting the same material as the base material or insulating resin layer having the same thermal expansion coefficient as the insulating resin layer as the material of the copper-clad laminate, and using it as the supporting substrate Compared with the manufacture of semiconductor device mounting substrates using a pure metal plate such as aluminum or a support substrate using stainless steel, the warpage and distortion of the substrate due to the difference in thermal expansion are reduced. In addition, it is possible to suppress this, and it is not necessary to perform a chemical etching process for removing the support substrate.

  Furthermore, compared to the manufacture of semiconductor device mounting substrates using organic release materials such as release films as support substrates, organic surface contamination due to the residue of release materials on the copper foil surface that becomes the bonding surface of the release materials and modification during heating Can be prevented.

  By pressing and bonding copper foil of a size slightly smaller than the copper-clad laminate and insulating resin layer as the inner layer, the copper foil end is protected by the bonded part of the copper-clad laminate and insulating resin, and is detached during production Inflow of the plating solution or etching solution to the interface can be prevented, and chemical contamination of the copper foil surface at the separation interface can be prevented.

  By disposing the copper foil so as to face the copper-clad laminate, it is possible to prevent the copper foil surface from being deteriorated or denatured even during heating during substrate production (lamination molding at a maximum of 250 ° C.).

  By cutting with a size that is slightly smaller than the copper foil, the adhesion between the copper-clad laminate and the insulating resin layer is removed, making it possible to easily release the desired insulating resin layer, and to release organic films such as release films. Compared with manufacturing a semiconductor element mounting substrate using a mold material as a support substrate, it is possible to prevent stress that causes substrate deformation such as peeling work.

Explanatory drawing of the support substrate for circuit formation of this invention. Explanatory drawing of the process of this invention. Explanatory drawing of the process of this invention. Explanatory drawing of the process of this invention. Explanatory drawing of the process of this invention. Explanatory drawing which shows the conventional circuit formation. Explanatory drawing which shows the circuit formation which used the conventional metal plate as the support layer.

  Hereinafter, an embodiment of the present invention will be described in detail. First, the core substrate 1 is manufactured. When the core substrate 1 is manufactured, as shown in FIG. 1, copper foils 3 having a size smaller than that of the copper-clad laminate are arranged on both sides of the copper-clad laminate 2, and a prepreg 4 as an insulating resin layer 4 and an outer layer A copper foil 5 corresponding to the above is placed and bonded and laminated by heating and pressing.

  The copper foil 3 is disposed in the vicinity of the center of the copper clad laminate 2 and the insulating resin layer 4 which are constituent materials so that the copper clad laminate 2 and the insulating resin layer 4 are bonded at the four side ends of the copper foil 3. It is desirable. At this time, the size of the copper foil 3 is desirably 15 mm or more smaller than the size of the copper-clad laminate 2 in both the vertical and horizontal directions. Moreover, it is desirable that the sizes of the insulating resin layer 4 and the copper foil 5 are larger than those of the copper-clad laminate 2. Further, the size of the copper foil 3, the copper clad laminate 2, the insulating resin layer 4 and the copper foil 5 is a block shape in which a region to be a package substrate for mounting a semiconductor element on the copper foil 3 is m rows × n columns later. It is preferable that the semiconductor package is sufficiently large so that a plurality of semiconductor packages can be formed efficiently.

  When the end surface of the substrate is cut after the adhesive lamination of the core substrate 1 by heating and pressing, it is preferable that the end surface of the copper foil 3 is cut outside by 5 mm or more per side.

  It is desirable to arrange the roughened surface of the copper foil 3 so as to adhere to the insulating resin layer 4 so as to obtain a peel strength with the resin. Further, in order to obtain the adhesive strength between the copper clad laminate 2 and the insulating resin layer 4, a bumpy electrodeposit layer (referred to as bath plating) is formed on the copper foil surface of the copper clad laminate 2, or an oxidation treatment is performed. Further, roughening treatment such as reduction treatment or etching may be performed.

  The substrate used as a support substrate is a base material made by impregnating a normal glass cloth with a thermosetting resin, a film material, or a base material in which an adhesive is disposed on both sides of a metal plate. A pressure-bonded copper clad laminate is desirable.

  The prepreg 4 used for the insulating resin layer 4 and the copper-clad laminate 2 is formed by impregnating or coating an insulating composition on a substrate, and used as a substrate for various types of laminates for electrical insulating materials. Well known ones can be used. Examples of the material for the substrate include inorganic fibers such as E glass, D glass, S glass, and Q glass, organic fibers such as polyimide, polyester, and tetrafluoroethylene, and mixtures thereof. These base materials have shapes such as woven fabric, non-woven fabric, low-ink, chopped strand mat, surfacing mat, etc., and the material and shape are selected depending on the intended use and performance of the molded product, and can be used alone or as required. It can be used from more than a variety of materials and shapes. The thickness of the base material is not particularly limited, but a material having a thickness of about 0.03 to 0.5 mm is usually used, and a surface treated with a silane coupling agent or the like or a material subjected to mechanical opening treatment is heat resistant. And from the viewpoint of moisture resistance and workability.

  As the resin composition, a known and commonly used resin composition used as an insulating material for a printed wiring board can be used. Usually, thermosetting resin with good heat resistance and chemical resistance is used as the base, and as thermosetting resin, phenol resin, epoxy resin, cyanate resin, maleimide resin, isocyanate resin, benzocyclobutene resin, vinyl resin However, the present invention is not limited to these examples. One type of thermosetting resin may be used alone, or two or more types may be mixed and used.

  Among thermosetting resins, epoxy resins are particularly important because they are widely used as insulating resins because they are excellent in heat resistance, chemical resistance and electrical properties and are relatively inexpensive. Epoxy resins include bisphenol A type epoxy resin, bisphenol F type epoxy resin, bisphenol S type epoxy resin, alicyclic epoxy resin, aliphatic chain epoxy resin, phenol novolac type epoxy resin, cresol novolac type epoxy resin, bisphenol A. Novolac-type epoxy resin, diglycidyl etherified product of bisphenol, diglycidyl etherified product of naphthalenediol, diglycidyl etherified product of phenol, diglycidyl etherified product of alcohol, and alkyl-substituted products, halides, hydrogenated products, etc. Is exemplified. One type of epoxy resin may be used alone, or two or more types may be mixed and used. The curing agent used together with the epoxy resin can be used without limitation as long as it cures the epoxy resin. For example, polyfunctional phenols, polyfunctional alcohols, amines, imidazole compounds, acid anhydrides, organic There are phosphorus compounds and their halides. These epoxy resin curing agents may be used alone or in combination of two or more.

  The cyanate resin is a resin that generates a cured product having a triazine ring as a repeating unit by heating, and the cured product is excellent in dielectric characteristics, and is often used particularly when high-frequency characteristics are required. Examples of the cyanate resin include 2,2-bis (4-cyanatophenyl) propane, bis (4-cyanatophenyl) ethane, 2,2-bis (3,5dimethyl-4-cyanatophenyl) methane, 2- (4-Cyanatophenyl) -1,1,1,3,3,3-hexafluoropropane, α, α′-bis (4-cyanatophenyl) -m-diisopropylbenzene, phenol novolak and alkylphenol novolak And cyanate esterified products. Among them, 2,2-bis (4-cyanatophenyl) propane is preferable because it has a particularly good balance between the dielectric properties and curability of the cured product and is inexpensive in terms of cost. Moreover, the cyanate ester compound may be used individually by 1 type, and may mix and use 2 or more types. The cyanate ester compound used here may be partially oligomerized in advance to a trimer or a pentamer. Furthermore, a curing catalyst or a curing accelerator may be added to the cyanate resin. As the curing catalyst, metals such as manganese, iron, cobalt, nickel, copper, and zinc are used. Specifically, organic metal salts such as 2-ethylhexanoate and octylate and organic compounds such as acetylacetone complex are used. Used as a metal complex. These may be used singly or in combination of two or more. Phenols are preferably used as the curing accelerator, and monofunctional phenols such as nonylphenol and paracumylphenol, bifunctional phenols such as bisphenol A, bisphenol F, and bisphenol S, or polyfunctional phenols such as phenol novolac and cresol novolac. Etc. can be used. These may be used singly or in combination of two or more.

  The resin composition used as the insulating material may be blended with a thermoplastic resin in consideration of dielectric properties, impact resistance, film processability, and the like. Examples of the thermoplastic resin include, but are not limited to, fluororesin, polyphenylene ether, modified polyphenylene ether, polyphenylene sulfide, polycarbonate, polyether imide, polyether ether ketone, polyacrylate, polyamide, polyamide imide, and polybutadiene. I don't mean. One type of thermoplastic resin may be used alone, or two or more types may be mixed and used.

  Among thermoplastic resins, blending polyphenylene ether and modified polyphenylene ether is useful because it improves the dielectric properties of the cured product. Examples of the polyphenylene ether and the modified polyphenylene ether include poly (2,6-dimethyl-1,4-phenylene) ether, poly (2,6-dimethyl-1,4-phenylene) ether and polystyrene alloyed polymer, poly (2 , 6-dimethyl-1,4-phenylene) ether and styrene-butadiene copolymer alloyed polymer, poly (2,6-dimethyl-1,4-phenylene) ether and styrene-maleic anhydride copolymer alloyed polymer, poly (3 , 6-dimethyl-1,4-phenylene) ether and polyamide alloyed polymer, and poly (2,6-dimethyl-1,4-phenylene) ether and styrene-butadiene-acrylonitrile copolymer alloyed polymer. In addition, in order to impart reactivity and polymerizability to polyphenylenelene ether, functional groups such as amine groups, epoxy groups, carboxyl groups, and styryl groups are introduced at the ends of polymer chains, or amine groups and epoxy groups are added to polymer chain side chains. Functional groups such as a group, a carboxyl group, a styryl group, and a methacryl group may be introduced.

  Among thermoplastic resins, polyamideimide resin is useful because it has excellent heat resistance and moisture resistance and has a good adhesive to metal. Among the raw materials of polyamideimide, trimellitic anhydride, trimellitic anhydride monochloride, as the acid component, and metaphenylene diamine, paraphenylene diamine, 4,4′-diaminodiphenyl ether, 4, 4′- as the amine component. Examples include, but are not limited to, diaminodiphenylmethane, bis [4- (aminophenoxy) phenyl] sulfone, 2,2′-bis [4- (4-aminophenoxy) phenyl] propane, and the like. In order to improve the drying property, it may be modified with siloxane. In this case, siloxane diamine can be used as the amino component. In consideration of film processability, it is preferable to use a molecular weight of 50,000 or more.

  An inorganic filler may be mixed in the resin composition used as the insulating material. Examples of the inorganic filler include alumina, aluminum hydroxide, magnesium hydroxide, clay, talc, antimony trioxide, antimony pentoxide, zinc oxide, fused silica, glass powder, quartz powder, and shirasu balloon. These inorganic fillers may be used alone or in combination of two or more.

  The resin composition used as the insulating material may contain an organic solvent. Examples of the organic solvent include aromatic hydrocarbon solvents such as benzene, toluene, xylene, and trimethylbenzene; ketone solvents such as acetone, methyl ethyl ketone, and methyl isobutyl ketone; ether solvents such as tetrahydrofuran; Suitable alcohol solvents; ether alcohol solvents such as 2-methoxyethanol and 2-butoxyethanol; amide solvents such as N-methylpyrrolidone, N, N-dimethylformamide and N, N-dimethylacetamide May be. When preparing the prepreg, the amount of solvent in the varnish is preferably in the range of 40 to 80% by mass, and the viscosity of the varnish is preferably in the range of 20 to 100 cP.

  The resin composition used as the insulating material may contain a flame retardant. Flame retardants include bromine compounds such as decabromodiphenyl ether, tetrabromobisphenol A, tetrabromophthalic anhydride, tribromophenol, phosphorus compounds such as triphenyl phosphate, trixylel phosphate, cresyl diphenyl phosphate, hydroxylation Known and conventional flame retardants such as metal hydroxides such as magnesium and aluminum hydroxide, red phosphorus and modified products thereof, antimony compounds such as antimony trioxide and antimony pentoxide, and triazine compounds such as melamine, cyanuric acid and melamine cyanurate Can be used.

  Various additives and fillers such as curing agents, curing accelerators, thermoplastic particles, colorants, UV-opaque agents, antioxidants, reducing agents, etc., as necessary, for resin compositions used as insulating materials To prepare.

  Usually, after the base material is impregnated or decoated so that the amount of the resin composition attached to the base material is 20 to 90% in terms of the resin content of the prepreg after drying, the temperature is usually 100 to 200 ° C. Heat-dry for 1 to 30 minutes to obtain a semi-cured (B-stage) prepreg. Usually, 1 to 20 prepregs are stacked and heated and pressurized in a configuration in which copper foils are arranged on both sides. As a molding condition, a normal copper clad laminate technique can be applied. For example, using a multistage press, a multistage vacuum press, continuous molding, an autoclave molding machine, etc., it is usually molded at a temperature of 100 to 250 ° C., a pressure of 0.2 to 10 MPa, a heating time of 0.1 to 5 hours, or a vacuum. Using a laminating apparatus or the like, lamination is performed under conditions of vacuum or atmospheric pressure under conditions of 50 to 200 ° C. and 0.1 to 10 MPa. Although the thickness of the prepreg layer which becomes an insulating layer changes with uses, the thing of the thickness of 0.02-5 mm is good normally.

  The base material applied to the copper clad laminate 2 preferably has the same thermal expansion coefficient as the material used for the insulating resin layer 4 or is the same material from the viewpoint of the stability of the thermal dimensional behavior.

As the copper foil 3 used in the present invention, it is preferable to use a copper foil 3 having an average roughness (Rz) at 10 points shown in JISB0601 of 2.0 μm or more and 5.0 μm or less. In the case of a copper sulfate bath, the production conditions of the copper foil are: sulfuric acid 50-100 g / L, copper 30-100 g / L, liquid temperature 20-80 ° C., current density 0.5-100 A / dm ² , copper pyrophosphate In the case of a bath, conditions of potassium pyrophosphate 100-700 g / L, copper 10-50 g / L, liquid temperature 30-60 ° C., pH 8-12, current density 0.5-10 A / dm ² are generally used. In some cases, various additives may be added in consideration of the physical properties and smoothness of copper.

Preferably, as the copper foil 5 used in the present invention, a peelable type copper foil having a thickness of 1 μm or more, a copper foil surface roughness of Rz, and both surfaces of 2.0 μm or less is used. Here, the peelable-type copper foil is a copper foil having a carrier, and is a copper foil that can be peeled off by the carrier. For example, in the case of a peelable type ultra-thin copper foil, a metal oxide film or an organic layer serving as a release layer is formed on a carrier foil having a thickness of 10 to 50 μm, and a sulfuric acid 50 to 100 g / h is used on the copper sulfate bath. L, copper 30 to 100 g / L, liquid temperature 20 to 80 ° C., current density 0.5 to 100 A / dm ² , in the case of a copper pyrophosphate bath, potassium pyrophosphate 100 to 700 g / L, copper 10 to 50 g / L A copper foil having a thickness of 0.1 to 3.0 μm is formed under the conditions of L, liquid temperature 30 to 60 ° C., pH 8 to 12 and current density 0.5 to 10 A / dm ² . In consideration of punchability, the carrier foil is preferably copper, nickel, tin, zinc, chromium, molybdenum, cobalt or an alloy thereof.

The antirust treatment performed on the resin adhesive surface of the copper foil can be performed using any of nickel, tin, zinc, chromium, molybdenum, cobalt, or an alloy thereof. In these methods, a thin film is formed on a copper foil by sputtering, electroplating or electroless plating, but electroplating is preferable from the viewpoint of cost. Specifically, plating is performed using a plating layer containing one or more metal salts of nickel, tin, zinc, chromium, molybdenum, and cobalt. In order to facilitate the precipitation of metal ions, a complexing agent such as citrate, tartrate or sulfamic acid can be added in the required amount. The plating solution is usually performed in an acidic region and at a temperature of room temperature to 80 ° C. The plating is appropriately selected from a range of usually a current density of 0.1 to 10 A / dm ² , a normal time of 1 to 60 seconds, and preferably 1 to 30 seconds. The amount of the rust-proofing metal varies depending on the type of metal, but is preferably 10 to 2000 μg / dm ^{2 in} total. If the rust preventive treatment is too thick, it may cause etching inhibition and deterioration of electrical characteristics, and if it is too thin, it may cause a reduction in peel strength with the resin.

Furthermore, if a chromate treatment layer is formed on the rust prevention treatment, it is useful because a reduction in peel strength with the resin can be suppressed. Specifically, it is performed using an aqueous solution containing hexavalent chromium ions. The chromate treatment can be performed by a simple immersion treatment, but is preferably carried out by a cathode treatment. It is good to carry out on the conditions of sodium dichromate 0.1-50 g / L, pH 1-13, bath temperature 0-60 degreeC, current density 0.1-5 A / dm < ² >, current time 0.1-100 second. It can also carry out using chromic acid or potassium dichromate instead of sodium dichromate.

In the present invention, it is preferable that a coupling agent is further adsorbed on the antirust treatment. Examples of the silane coupling agent include 3-glycidoxypropyltrimethoxysilane, epoxy-functional silanes such as 2- (3,4-epoxycyclohexyl) ethyltrimethoxysilane, 3-aminopropyltrimethoxysilane, and N-2. Amine functional silanes such as-(aminoethyl) 3-aminopropyltrimethoxysilane, N-2- (aminoethyl) 3-aminopropylmethyldimethoxysilane, vinyltrimethoxysilane, vinylphenyltrimethoxysilane, vinyltris (2- Olefin-functional silanes such as methoxyethoxy) silane, acrylic-functional silanes such as 3-allytoxypropyltrimethoxysilane, methacryl-functional silanes such as 3-methacryloxypropyltrimethoxysilane, 3-mercaptopropyltrimethoxysilane, etc. And mercapto-functional silanes is used, they may be used alone or may be used by mixing plural. These coupling agents are dissolved at a concentration of 0.1 to 15 g / L of a solvent such as water and applied to a metal foil at a temperature of room temperature to 50 ° C. or electrodeposited to be adsorbed. These silane coupling agents form a film by condensation bonding with a hydroxyl group of a rust preventive metal on the surface of the copper foil. After the silane coupling treatment, a stable bond is formed by heating, ultraviolet irradiation or the like. If it is heating, it is dried for 2 to 60 seconds at a temperature of 100 to 200 ° C. In the case of ultraviolet irradiation, it is performed in the range of 200 to 400 nm and 200 to 2500 mJ / dm ² .

  The combination of the resin composition and the silane coupling agent is preferably selected so that the functional group in the resin composition and the functional group of the silane coupling agent are chemically reacted by heating. For example, when an epoxy group is contained in the resin composition, the effect is more clearly manifested when an amino functional silane is selected as the silane coupling agent. This is because the epoxy group and amino group easily form a strong chemical bond by heat, and this bond is extremely stable against heat and moisture. As a combination for forming a chemical bond in this manner, epoxy group-amino group, epoxy group-epoxy group, epoxy group-mercapto group, epoxy group-hydroxyl group, epoxy group-carboxyl group, epoxy group-cyanato group, amino group-hydroxyl group , Amino group-carboxyl group, amino group-cyanato group and the like.

  When the epoxy resin that is liquid at room temperature is included in the resin composition, the viscosity at the time of melting is greatly reduced, so that the wettability at the adhesion interface is improved, and the chemical reaction between the epoxy resin and the coupling agent is likely to occur. As a result, a strong peel strength can be obtained. Specifically, bisphenol A type epoxy resin, bisphenol F type epoxy resin, and phenol novolac type epoxy resin having an epoxy equivalent of about 200 are preferable.

  When the curing agent is included in the resin composition, it is particularly preferable to use a thermosetting latent curing agent as the curing agent. That is, when the functional group in the thermosetting resin and the functional group of the silane coupling agent chemically react, the reaction temperature of the functional group in the thermosetting resin and the functional group of the silane coupling agent is the same as that of the thermosetting resin. It is preferable to select the curing agent so that it is lower than the temperature at which the curing reaction is initiated. Thereby, since reaction of the functional group in a thermosetting resin and the functional group of a silane coupling agent can be performed preferentially and selectively, the adhesiveness of copper foil and a resin composition becomes higher. Thermosetting latent curing agents for resin compositions containing epoxy resins include dicyandiamide, dihydrazide compounds, imidazole compounds, amine-epoxy adducts and other solid dispersion-heat-dissolving curing agents, urea compounds, onium salts, boron trichloride -Reactive group block type curing agents such as amine salts and block carboxylic acid compounds.

Hereinafter, the present invention will be described with reference to the embodiments shown in FIGS.
On both sides of a copper clad laminate 2MCL-E-679FG (trade name, manufactured by Hitachi Chemical Co., Ltd.) having a nominal thickness of 0.4 mm and a size of 410 × 510 mm, having a copper foil with a thickness of 18 μm on both sides, the size is 365 × 485 mm. The copper foil 3EC-M3-VLP-23 (Furukawa Circuit Foil Co., Ltd., trade name) is uniformly distributed in the center of the copper-clad laminate 2 and the glossy surface of the copper foil 3 faces the copper-clad laminate 2 Thus, the first circuit board 10 was obtained.

  A prepreg 4GEA-679FG (trade name, manufactured by Hitachi Chemical Co., Ltd.) having a nominal thickness of 0.04 mm and a size of 420 × 520 mm is overlaid on the first circuit board 10, and further, a copper foil 5 having a size of 440 × 540 mm. The peelable copper foil MT18SDH-3 (trade name, manufactured by Mitsui Mining & Smelting Co., Ltd.), in which the carrier copper foil thickness of 18 μm is bonded to the ultrathin copper foil thickness of 3 μm, is bonded to the prepreg 4 on the 3 μm copper foil surface. And a vacuum press was performed under conditions of a temperature of 175 ± 2 ° C., a pressure of 2.5 ± 0.2 MPa, and a holding time of 60 minutes. After pressing, the end portion was cut to a size of 408 × 508 mm, a guide hole was drilled, and the carrier copper foil was peeled off to obtain the second circuit board 20.

  After forming guide holes in the second circuit board 20 with a router processing machine manufactured by Hitachi Via Mechanics Co., Ltd., dry film resist NIT225 (Nichigo Morton Co., Ltd.) at a temperature of 110 ± 10 ° C. and a pressure of 0.50 ± 0.02 MPa (Product name, product name) was laminated. Then, after pasting the negative mask, the circuit pattern is baked with a parallel exposure machine, the dry film resist is developed with a 1% aqueous sodium carbonate solution to form an etching resist, and the copper without the etching resist is chlorinated. After removing with a ferric aqueous solution, the dry film resist is removed with a sodium hydroxide aqueous solution, and a Φ0.07 mm conformal mask and a non-through hole installation place for connection with the first circuit board are provided. A position recognition pattern at the time of laser processing was formed, and the third circuit board 30 was obtained.

  A beam irradiation diameter of 0.21 mm, a frequency of 500 Hz, a pulse width of 10 μs, and a number of irradiations of 5 shots are measured on both surfaces of the third circuit board 30 by a carbon dioxide laser processing machine LC-1C / 21 (trade name, manufactured by Hitachi Via Mechanics Co., Ltd.). The holes were processed one by one under the conditions, and non-through holes were formed on the third circuit board 30 to form a fourth circuit board 40.

  The fourth circuit board 40 is desmeared using a sodium permanganate aqueous solution having a temperature of 80 ± 5 ° C. and a concentration of 55 ± 10 g / L, and is electrolessly plated with a thickness of 0.4 to 0.8 μm. After the plating, plating with a thickness of 15 to 20 μm was performed by electrolytic copper plating to obtain a circuit board 50 of 5a. As a result, the first circuit board (inner layer) and the fourth circuit board (outer layer) are electrically connected by the non-through hole.

  In the circuit board 50 of the 5a, Hitachi Via so that the size is 362 × 482 mm within the arrangement range of the copper foil 3EC-M3-VLP-23 (trade name, manufactured by Furukawa Circuit Foil Co., Ltd.) in the first circuit board 10 A 6a circuit board 60 was obtained by separating from the copper-clad laminate 2 by cutting with a router processing machine manufactured by Mechanics Co., Ltd.

  The surface of the 6a circuit board 60 was adjusted, and a dry film resist NIT225 (trade name, manufactured by Nichigo Morton Co., Ltd.) was laminated at a temperature of 110 ± 10 ° C. and a pressure of 0.50 ± 0.02 MPa. Then, after pasting the negative mask, the circuit pattern is baked with a parallel exposure machine, the dry film resist is developed with a 1% aqueous sodium carbonate solution to form an etching resist, and the copper without the etching resist is chlorinated. After removing with a ferric aqueous solution, the dry film resist was removed with an aqueous sodium hydroxide solution to form a wiring pattern, whereby a circuit board 70 of 7a was obtained.

  As shown in FIG. 3, the fourth circuit board 40 is also desmeared using a sodium permanganate aqueous solution having a temperature of 80 ± 5 ° C. and a concentration of 55 ± 10 g / L. After plating with a thickness of 4 to 0.8 μm, a dry film resist NIT225 (trade name, manufactured by Nichigo Morton Co., Ltd.) is laminated at a temperature of 110 ± 10 ° C. and a pressure of 0.50 ± 0.02 MPa, and a negative type After pasting the mask, the wiring pattern is baked with a parallel exposure machine, the dry film resist is developed with a 1% aqueous sodium carbonate solution to form a plating resist, and the copper sulfate concentration is 60 to 80 g / L, and the sulfuric acid concentration is 150 to 200 g. / L copper sulfate plating line is applied to the pattern electrolytic copper plating about 15-20μm, and dry film resist is stripped with amine resist stripping solution After removal, the copper foil portion of 3um plating is not performed is removed by hydrogen peroxide sulfate-based soft etching solution, it is possible to obtain a circuit board 55 of the 5b.

  In the circuit board 55 of the 5b, Hitachi Via so that the size is 362 × 482 mm within the arrangement range of the copper foil 3EC-M3-VLP-23 (trade name, manufactured by Furukawa Circuit Foil Co., Ltd.) in the first circuit board 10 A 6b circuit board 65 was obtained by separating from the copper-clad laminate 2 by cutting with a router processing machine manufactured by Mechanics Co., Ltd.

  On the circuit board 65 of 6b, a dry film resist NIT225 (manufactured by Nichigo Morton Co., Ltd., trade name) was laminated at a temperature of 110 ± 10 ° C. and a pressure of 0.50 ± 0.02 MPa. Then, after pasting a negative mask, a wiring pattern is printed only on the copper foil 3EC-M3-VLP-23 (product name, manufactured by Furukawa Circuit Foil Co., Ltd.) of the first substrate circuit 10 with a parallel exposure machine. The dry film resist is developed with a 1% sodium carbonate aqueous solution to form an etching resist. The copper without the etching resist is removed with a ferric chloride aqueous solution, and then the dry film resist is removed with a sodium hydroxide aqueous solution. Then, a wiring pattern was formed, and a 7b circuit board 75 was obtained.

  The 8a circuit board 80 and the 8b circuit board 85 are formed by performing solder resist formation and gold plating on the 7a circuit board 70 and the 7b circuit board 75 and cutting the package size. Obtained.

  The 8a circuit board 80 is a package substrate for mounting a semiconductor element having a two-layer structure. As shown in FIG. 4, after forming the 5a circuit board 50, a step of forming a wiring shown in [0051] is performed. The obtained copper pattern surface is roughened using a copper surface roughening solution CZ-8100 (product name, manufactured by MEC Co., Ltd.). Next, after forming the insulating resin lamination shown in [0046] to [0049], providing the non-through holes, repeating the process of forming the copper plating and the wiring pattern, and completing the formation of the desired number of layers, A three-layer structure is formed by performing steps of separating the insulating resin plate shown in [0050] to [0051], forming a wiring pattern, forming a solder resist, performing gold plating, and cutting the package size. It is possible to form a package substrate for mounting semiconductor elements having a four-layer structure,..., An n-layer structure.

  The 8b circuit board 85 is a package substrate for mounting a semiconductor element having a two-layer structure. As shown in FIG. 5, after the 5b circuit board 55 is formed, the surface of the obtained copper pattern is used as a copper surface roughening solution. Roughening is performed using CZ-8100 (product name, manufactured by MEC Co., Ltd.). Next, the steps of forming the insulating resin laminate shown in [0045] to [0048] and [0051], providing the non-through holes, and forming the copper plating and the wiring pattern are repeated to form the desired number of layers. After completion, the insulating resin plate shown in [0053] and [0054] is removed, the wiring pattern is formed, the solder resist is formed, the gold plating finish is performed, and the cutting process to the package size is performed. It is possible to form a semiconductor element mounting package substrate having a three-layer structure, a four-layer structure,..., An n-layer structure.

1 Support substrate (core substrate)
2 Copper-clad laminate (support)
3 Copper foil 4 Prepreg (insulating resin layer)
5 Copper foil

Claims (12)

Insulating resin layer is bonded to the copper foil on both sides of the copper clad laminate via a copper foil (inner layer) of a size smaller than the copper clad laminate and the copper foil of the copper clad laminate. Because
A copper foil (inner layer) having a size slightly smaller than the copper foil of the copper-clad laminate and the copper-clad laminate is directly disposed on the copper foils on both sides of the copper-clad laminate,
The inner layer side of the insulating resin layer, and the copper foil of the copper-clad laminate are bonded at four sides end of the copper-clad laminate and a copper foil of slightly smaller size than the copper foil of the copper-clad laminate (inner layer) the outer layer of the insulating resin layer, a copper foil (outer) circuit forming support substrate that will be disposed. The circuit forming support substrate according to claim 1, wherein the copper foil (outer layer) disposed on the outer layer side of the insulating resin layer is a peelable type copper foil including a carrier foil and a copper foil. The support substrate for circuit formation according to claim 2, wherein the copper foil provided in the peelable type copper foil is an ultrathin copper foil having a thickness of 0.1 to 3.0 µm. A method of manufacturing a package substrate for mounting a semiconductor element manufactured by the following steps a to h.
a. A copper-clad laminate, and a copper foil (inner layer) that is directly disposed on the copper foils on both sides of the copper-clad laminate, and that is slightly smaller than the copper foil of the copper-clad laminate and the copper-clad laminate, Forming a support substrate for circuit formation having an insulating resin layer having a size larger than the copper foil, and a copper foil disposed on the insulating resin side (outer layer);
b. Forming a non-through hole for connection from the copper foil disposed on the insulating resin side (outer layer) toward the copper foil side (inner layer);
c. A step of connecting the non-through hole portion connecting the copper foil and the copper foil (inner layer) disposed on the insulating resin side (outer layer) by electrolytic copper plating or electroless plating;
d. Forming a first wiring conductor by forming a copper foil disposed on the insulating resin side (outer layer) by a subtractive method or a semi-additive method,
e. A roughening process for obtaining adhesion with the insulating resin on the surface of the first wiring conductor;
f. Placing the insulating resin in contact with the first wiring conductor roughened in step e, placing a copper foil on the insulating resin side (outer layer), and laminating by heating and pressing;
g. A step of cutting the size of the copper foil (inner layer) one size smaller than the size of the copper foil and releasing the insulating resin layer from the copper-clad laminate as a support;
h. A step of forming a wiring by a subtractive method or a semi-additive method by cutting the copper foil layer exposed by being separated from the support by cutting. 5. The method of manufacturing a package substrate for mounting a semiconductor element having a build-up structure according to claim 4 , which is obtained by repeatedly performing the d process from the e process, the f process, and the b process after the d process. According to claim 4 or 5, after the step c, through g process, a method of manufacturing a semiconductor element mounting package substrate having a trace obtained copper foil exposed by the insulating resin side (outer layer) and g processes in subtractive process . 6. The semiconductor device mounting package substrate according to claim 4 or 5 , wherein the semiconductor substrate mounting package substrate has a wiring formed by forming a copper foil exposed by the insulating resin side (outer layer) and the g step by a semi-additive method after the step b and after the step b. Production method. The method of manufacturing a package substrate for mounting a semiconductor element according to any one of claims 4 to 7 , wherein the insulating resin layer when forming the support substrate on the copper clad laminate and the copper foil in step a is 0.03 mm or more in thickness. . The method of manufacturing a package substrate for mounting a semiconductor element according to any one of claims 4 to 8 , wherein the thickness of the copper foil (inner layer) in step a is 7 µm or more. The method of manufacturing a package substrate for mounting a semiconductor element according to any one of claims 4 to 9 , wherein the copper foil of the copper clad laminate in step a has a thickness of 7 µm or more. The method for manufacturing a package substrate for mounting a semiconductor element according to any one of claims 4 to 10 , wherein the non-through hole in step b is formed by a laser. The method of manufacturing a package substrate for mounting a semiconductor element according to any one of claims 4 to 11 , wherein the separation in step g is performed by physical cutting.

Images