JP5412678B2 - Method for forming fine pattern and method for manufacturing semiconductor light emitting device using the same - Google Patents

Description

  The present invention relates to a process for forming a fine pattern, and more particularly to a process for manufacturing a semiconductor light emitting device having a fine pattern for improving light efficiency.

  In general, various semiconductor devices such as a light emitting diode, a laser diode, a photodiode, and a transistor are manufactured based on a semiconductor.

  Such a semiconductor element may require a fine pattern such as a periodic / non-periodic pattern in a predetermined region for a specific function. Such a fine pattern can be formed on the semiconductor surface by using a known etching process.

  Typically, in the case of a nitride semiconductor light emitting device, the light extraction efficiency is limited by the difference in refractive index between the outside and the nitride semiconductor, and in order to solve this, a fine pattern structure is formed on the surface of the nitride semiconductor light emitting device. Can be formed.

  Recently, in order to improve the output of a semiconductor light emitting device, a photonic crystal structure that is a periodic fine lattice pattern has been actively studied, and the surface plasmon resonance principle has been studied. A method for improving luminance by using a similar fine lattice pattern is also used.

  However, the etching process used in such a patterning process has different problems in forming a fine pattern on the semiconductor surface by an etching method.

  For example, in the case of dry etching (RIE etching) such as RIE (Reactive Ion Etching) and ICP-RIE (Inductive Coup Light Emitting Device Plasma Reactive Ion Etching), power adjustment is possible and anisotropy is obtained. Although the obtained pattern can guarantee a precise and reproducible pattern, there is a problem that the characteristics of the semiconductor surface are easily deteriorated by physical collision with ions or neutral atoms. Even if a thin film is deposited on the p-type GaN layer with another material and then patterned by dry etching, damage to the p-type GaN layer located in the portion where the thin film is removed is unavoidable.

  The solid line in FIG. 1 shows the IV characteristics of a nitride light-emitting device intentionally damaged by ICP-RIE using a halogen gas before forming an electrode on the p-type GaN surface. Unlike (♦), the dotted line X represents the IV characteristic of the nitride light emitting device before damage. The nitride light emitting device is damaged by dry etching, and a current starts to flow from a low voltage. However, this is not a current due to normal carrier recombination but a leakage current, and there is a problem that light is not actually generated.

  Therefore, a method for recovering a crystal damaged by dry etching to its original state has been studied. However, the surface of the p-type GaN layer generates nitrogen vacancies during the etching process, which causes the phenomenon of becoming an n-type semiconductor. Therefore, there is a limit that it cannot be recovered through a general post-processing process. Such a type conversion phenomenon is a fatal defect in a pn junction diode.

  In contrast to this, in the case of the wet etching process, unlike dry etching, the semiconductor surface such as p-type GaN is not damaged, but almost no etching is performed on a specific surface of the nitride single crystal (for example, c-plane). However, it is difficult to perform a precise patterning process. Further, when the etching depth is deep, there is a problem that the upper end of the thin film is completely removed and the photoresist layer of the mask is peeled off.

  The present invention is to solve the above-mentioned problems of the prior art, and its purpose is to minimize the damage area caused by dry etching by using the horizontal etching characteristics of {0001} c-plane hexagonal semiconductor crystal after dry etching. An object of the present invention is to provide a method for forming a fine pattern to be changed.

  Another object of the present invention is to provide a method for manufacturing a semiconductor light emitting device having a fine pattern with improved light output by using the fine pattern forming method.

  In order to achieve the above technical problem, one aspect of the present invention includes a step of providing a c-plane hexagonal semiconductor crystal, a step of forming a mask having a predetermined pattern on the semiconductor crystal, and the mask. Forming a primary fine pattern on the semiconductor crystal by dry-etching the semiconductor crystal using the method, and forming the primary fine pattern by wet-etching the semiconductor crystal on which the primary fine pattern is formed. Provided is a method of forming a fine pattern including a step of forming a secondary fine pattern extending in a horizontal direction. Here, the bottom surface and the side wall of the secondary fine pattern obtained from the wet etching process can each have a unique crystal plane.

  Preferably, the semiconductor crystal may be a p-type nitride semiconductor that becomes a serious problem by dry etching.

  In the wet etching stage, since the bottom surface that is the c-plane may be hardly etched, the bottom surface obtained from the secondary fine pattern forming step is the same c-plane as the bottom surface obtained from the primary fine pattern forming step. Can be.

  In one embodiment of the present invention, the mask pattern is a plurality of line patterns formed in the <11-20> direction of the semiconductor crystal and arranged according to the <1-100> direction. The side wall can be m-plane.

  In another embodiment of the present invention, the mask pattern may be a plurality of line patterns formed in the <1-100> direction of the semiconductor crystal and arranged in the <11-20> direction. In the present embodiment, the line pattern may be provided as a dot pattern with the surface of the line pattern becoming irregular and partially thin according to the further progress time of wet etching. Further, even if necessary, even the dot pattern can be completely etched away by further etching. As a result, the etching method can be used as a method for adjusting the thickness of the semiconductor layer in which the thickness of the corresponding semiconductor layer is reduced.

  In a preferred embodiment of the present invention, the mask pattern may have a plurality of fine hole structures, and the secondary fine pattern may have a plurality of fine hole structures having hexagonal release ports. According to the wet etching time of the secondary etching process, the inner wall of the hole may have other crystal planes.

  That is, the inner side wall of the hole, which is the secondary fine pattern, can be formed by combining an m-plane component and an s-plane component. In addition, by further maintaining the wet etching time, it is possible to include an r-plane component that can provide lower coverage while the inner wall of the hole is a more stable surface.

  In a specific example, the secondary fine pattern may have a plurality of pillar structures.

  The step of forming the secondary fine pattern may be performed after the mask is removed or before the mask is removed.

  Another aspect of the present invention provides a method for manufacturing a semiconductor light emitting device. In particular, the photonic crystal structure or the structure using the surface plasmon resonance principle that requires a fine pattern can be advantageously employed.

  The method for manufacturing a semiconductor light emitting device includes providing a semiconductor stacked body having a first conductive type and a second conductive type semiconductor layer and an active layer therebetween, and forming a mask having a predetermined pattern on the semiconductor crystal. Forming a primary fine pattern on the second conductive semiconductor layer by dry etching the second conductive semiconductor layer using the mask; and forming a first fine pattern on the first conductive pattern. A step of forming a secondary fine pattern in which the primary fine pattern extends in a horizontal direction by wet-etching the two-conductivity type semiconductor layer; and the first and second conductive type semiconductor layers with the mask removed. Forming first and second electrodes to be connected to each other. Here, the second conductive semiconductor layer is a c-plane hexagonal semiconductor crystal, and the bottom surface and the side wall of the secondary fine pattern obtained from the wet etching process may have a unique crystal plane.

  The secondary fine pattern formed on the second conductive type semiconductor layer may be configured such that when light generated in the active layer is extracted to the outside through the surface of the second conductive type semiconductor layer, ambient air or a sealing material Therefore, it can act as a photonic crystal structure that reduces the total reflection effect due to the low refractive index and improves the light extraction efficiency.

  In order to utilize as a preferable photonic crystal structure, a light-transmitting conductive layer can be formed on the second conductive semiconductor layer on which the secondary fine pattern is formed. For example, a light transmissive metal layer or a light transmissive conductive oxide layer such as ITO can be formed.

  Preferably, in order to form a structure using the surface plasmon resonance principle, the step of forming the second electrode includes a high reflectivity such as Ag on the second conductive semiconductor layer on which the secondary fine pattern is formed. A step of forming a highly reflective metal layer containing metal may be included. The highly reflective metal layer may have a multilayer structure.

  In the second conductivity type semiconductor layer, surface plasmons are excited at the interface between the second conductivity type semiconductor layer and the highly reflective metal layer from energy generated by recombination of electron-hole pairs injected into the active layer. Can have a thickness that can be made.

  Preferably, a thickness of the second conductive semiconductor layer between the secondary fine pattern and the active layer may be 50 nm or less.

  The manufacturing method according to the present invention can be advantageously employed in a light emitting device in which the semiconductor laminate is a nitride semiconductor. In this case, the second conductive semiconductor layer may be a p-type nitride semiconductor layer.

  According to the present invention, only a minimum region of a desired pattern area is dry-etched, and then a structure is formed through wet etching in the horizontal direction, thereby minimizing a damaged region due to dry etching. By appropriately adjusting the crystal direction (pattern formation direction) and wet etching conditions (time and other conditions), it is possible to secure a fine pattern with high reproducibility while freely determining the height and size of the fine pattern. Can do. By applying such a fine pattern to a photonic crystal structure or a structure using surface plasmons, a semiconductor light emitting device with excellent light efficiency can be provided.

  Further, the fine pattern according to the present invention naturally forms a specific geometric pattern in the subsequent wet etching process due to the hexagonal crystallinity, so that the c-plane, m-plane, s-plane and / or Or it has an intrinsic crystal plane such as r-plane. Since such a crystal plane can be in direct contact with a metal or conductive oxide electrode layer in a semiconductor light emitting device, it is more advantageous to form a p-type ohmic contact.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

  2A to 2D are cross-sectional views for each process for explaining a fine pattern forming process using horizontal wet etching according to the present invention.

  As shown in FIG. 2 a, the fine pattern forming process starts from the stage of providing the c-plane hexagonal semiconductor crystal 11.

  The semiconductor crystal 11 can be not only a nitride semiconductor such as GaN but also other known hexagonal semiconductors. In particular, the semiconductor crystal 11 may be a p-type nitride layer that is vulnerable to damage by dry etching. In the present invention, a hexagonal semiconductor crystal whose upper surface is provided by c-plane {0001} is used.

  Next, as shown in FIG. 2B, a mask 18 having a predetermined pattern is formed on the semiconductor crystal 11.

  The mask 18 may be a photoresist pattern. In this step, a mask 18 having a desired pattern can be formed by applying a photoresist on the upper surface of the semiconductor crystal 11 and then applying a normal lithography process, a holographic lithography process, or a nanoimprint process.

  Such a pattern may be a periodic pattern if necessary, but there are various patterns of the mask 18 that can be employed in the present invention. For example, the pattern may be a periodic pattern such as a one-dimensional line pattern, a two-dimensional triangular lattice, or a quadrangular lattice pattern, and the short range periodicity is low and the periodicity is long. It may be an anti-periodic pattern having a (long range period), and may be an irregular-non-periodic pattern (non-periodic pattern).

  In the present invention, even if such periodicity or anti-periodicity is maintained, the size and shape of the pattern can be changed. This is because an isotropic (horizontal direction in the present invention) wet etching process proceeds after dry etching using a mask. This will be described in detail with reference to FIGS. 2c and 2d.

  Next, a hybrid etching process in which primary dry etching and secondary wet etching are combined is applied to the formation process of the fine pattern.

  That is, as shown in FIG. 2c, the semiconductor crystal 11 is dry-etched using the mask 18 to form the primary fine pattern P1. The primary fine pattern P1 obtained in this step is dry-etched so as to have a width corresponding to the open width W1 of the mask 18 and a predetermined depth d1 of the semiconductor crystal 11. The depth of the primary fine pattern P1 (or the height of the pattern structure) obtained by this dry etching is substantially the same as the depth of the final fine pattern (P2 in FIG. 2d), but its width W1 (or The size of the pattern is smaller than the width of the final fine pattern. This will be described in detail in FIG. 2d.

  Further, as described above, in this step, the damaged region D is generated over the entire surface of the fine pattern P1 of the semiconductor crystal 11 due to ions and neutral atoms used in dry etching. That is, not only the bottom surface of the primary fine pattern P1 but also the side wall of the primary fine pattern P1 is directly exposed to dry etching and there is a region D where the crystal is damaged, but can be minimized by the wet etching process of FIG.

  In the step of FIG. 2d, wet etching is performed on the semiconductor crystal on which the primary fine pattern P1 is formed. Here, the process is performed after the mask 18 is removed. However, the present invention is not limited to this, and the mask can be removed after the wet etching process.

  Such a wet etching process proceeds in the horizontal direction of the primary fine pattern P1, since the etching hardly proceeds on the stabilized c-plane. Such wet etching that proceeds in the horizontal direction proceeds until the side wall reaches a specific crystal plane. This can be performed with high reproducibility because the etching rate is remarkably lowered on the specific crystal plane.

  As described above, the primary fine pattern P1 can be provided as a secondary fine pattern P1 that is expanded in the horizontal direction and whose side wall has a unique crystal plane. As a result, the secondary fine pattern P1 can be provided. This is because P2 can have the same depth d2 as the depth d1 of the primary fine pattern P1 and a width W2 larger than its width W1.

  In this step, as shown in FIG. 2d, the bottom surface obtained by extending in the horizontal direction and the newly exposed side wall may not be damaged or removed. Accordingly, the damaged region D ′ remains only in the region corresponding to the bottom surface of the primary fine pattern P1.

  Therefore, the secondary fine pattern P2 can minimize the ratio of the damaged region D ′ in the entire exposed area. By applying such a principle, the mask pattern design and the dry etching process can be adjusted so as to reduce the ratio of the damaged region.

  More specifically, the width W1 of the mask 18 is decreased and the depth of the primary fine pattern P1 is increased, thereby reducing the area of the damaged bottom surface corresponding to the primary fine pattern P1 while reducing the secondary area. The new area obtained by the fine pattern P2 can be increased.

  As a result, the ratio of the damaged region D ′ to the entire exposed area of the secondary fine pattern P2 can be greatly reduced, thereby degrading the electrical characteristics due to the damaged region caused by dry etching. It can be improved on a periodic basis.

  In the present invention, the bottom surface of the primary fine pattern obtained by dry etching can be the same c-plane as the top surface of the semiconductor crystal, and since the c-plane is a very stable crystal plane, the primary fine pattern Even when wet etching proceeds on the side wall of the pattern, almost no etching occurs on the bottom surface. Accordingly, the depth of the secondary fine pattern is determined by the depth of the primary fine pattern, and the depth of the final fine pattern can be accurately adjusted through dry etching.

  Also, the horizontal wet etching according to the present invention has a very low etching rate when the side wall that appears thereby becomes a specific crystal plane. For example, a nitride single crystal can have sidewalls such as s-plane {1-101}, m-plane {1-100}, r-plane {1-102}.

  Therefore, since this wet etching process is a self-terminating process in which the etching progress is automatically interrupted, it is very advantageous to ensure process uniformity (or high reproducibility).

  Thus, in the present invention, in order to obtain the shape and size of the final pattern, not only the mask pattern but also the crystal direction of wet etching plays an important role. Such a crystal direction can be selected according to a mask pattern formed on a semiconductor crystal to be etched.

  That is, since the influence on wet etching differs depending on the crystal plane, various patterns can be obtained depending on which crystal plane is formed on the side wall of the crystal pattern exposed by the mask pattern (Examples 1A and 1B). reference).

  In particular, when the present inventor forms a substantially circular hole by dry etching, it can be changed into a fine pattern of hexagonal holes by wet etching in the horizontal direction. I discovered that. Such a fine pattern has a size of submicrometer, and each side of the hexagon forms an angle of 120 ° with each other, and can be formed very sharply (see Example 1C). This can be said to be a feature of the present invention that could not be achieved by any existing semiconductor etching method.

  Furthermore, as described above, each crystal plane exposed in a hexagon can have another crystal plane by wet etching. Particularly, since the crystal plane of the side wall can be inclined according to the wet etching condition, the side wall having coverage advantageous for deposition of further electrode material can be provided.

  Hereinafter, the operation and effect of the present invention will be described in detail through various embodiments of the present invention.

Example 1A
In this example, a line pattern mask formed in the <11-20> direction and arranged in the <1-100> direction on the c-plane GaN semiconductor crystal was formed. The period was set to about 0.6 μm. Next, after performing dry etching to a depth of 0.1 μm, the mask was removed (FIG. 3 a).

  Next, it was performed with a 4M KOH aqueous solution at about 100 ° C. for about 10 minutes, and observed with a scanning electron microscope (Scanning Electron Microscope, SEM) for another 20 minutes (total 30 minutes). )went.

  As a result of applying the wet etching for 10 minutes, as shown in FIG. 3b, the initial side wall that was slightly inclined before the horizontal wet etching formed a vertical side wall. The surface was the {1-100} plane, that is, the m plane, and etching did not proceed any further. Etching hardly progressed for the stable c-plane at the bottom.

  Through this embodiment, it can be confirmed that a damaged region after dry etching is removed from the side wall and part of the bottom surface, and a beautiful crystal plane can be obtained. Such crystal planes can ensure excellent electrical contact in semiconductor devices.

(Example 1B)
In this example, a mask having a plurality of line patterns (period: about 0.6 μm) is formed on the c-plane GaN semiconductor crystal in the same manner as in Example 1A described above, but the formation direction and arrangement are different. . That is, in this example, a plurality of line patterns formed in the <1-100> direction and arranged in the <11-20> direction were formed. Next, after performing dry etching to a depth of 0.1 μm, the mask was removed (FIG. 4a).

  Next, with 4M KOH aqueous solution at about 100 ° C. for about 10 minutes, observed with SEM (FIG. 4b), another 20 minutes (total 30 minutes), and further 20 minutes (total 50 minutes), respectively. Was observed by SEM (FIGS. 4c and 4d).

  As a result of the present example, the pattern (FIG. 4a) resulting from dry etching has a form similar to that of Example 1A (FIG. 3a).

  However, as shown in FIG. 4b, the width of the pattern increases while the wet etching in the horizontal direction progresses (the width of the pattern structure gradually decreases), and the etching progresses over time, as shown in FIG. 4c. After 30 minutes, the dot pattern arranged according to the line remains. As it proceeds further, only a completely flat plane remains (see FIG. 4d). It can be understood that since wet etching has a relatively high etching rate in the <11-20> direction compared to other stabilized crystal planes, a continuous pattern change occurs depending on the time of wet etching. it can.

  As described above, according to this embodiment, it is possible to provide a one-dimensional lattice and a dot pattern having various depths and widths having relatively low damage.

  Further, as can be confirmed in the present example (horizontal wet etching of <1-100> direction lattice), it can be confirmed that the c-plane which is not originally wet-etched can be removed with a constant thickness. That is, in the present invention, a narrow area is dry-etched to form a groove, and horizontal wet etching is used in the subsequent process. It is also possible to reduce the original thickness of the epitaxial layer as desired by adjusting the depth of the initial dry etching.

  In particular, the surface of the p-type GaN layer cannot be dry-etched due to damage and cannot be wet-etched because it is a c-plane, but the thickness of the p-type GaN layer can be reduced while minimizing the damage site using the process of the present invention. Can do.

(Example 1C)
In this example, a three-dimensional pattern was adopted unlike the above Examples 1A and 1B. A plurality of circular mask patterns having a size of about 0.3 μm were formed on the c-plane GaN semiconductor crystal in the vertical and horizontal directions with a period of about 0.6 μm.

  Next, after performing dry etching to a depth of 0.1 μm, the mask was removed. Subsequently, the film was taken with a 4M KOH aqueous solution at about 100 ° C. for about 10 minutes, and then photographed with an SEM. As shown in FIG. 5, it was confirmed that a three-dimensional pattern such as a pillar structure (diameter: about 130 nm) was formed.

(Example 1D)
In this example, a three-dimensional pattern is adopted as in Example 1C, but a mask pattern having a plurality of circular holes of about 100 nm size on a c-plane GaN semiconductor crystal is vertically and horizontally spaced at intervals of about 0.5 μm. Formed in the direction.

  Using the mask, a substantially circular hole pattern was formed on the c-plane GaN surface by dry etching (about 0.1 μm), and the mask was removed (FIG. 6a). After forming a circular hole pattern, wet etching was performed with a 4M KOH aqueous solution at about 108 ° C. for about 30 minutes. As a result, as shown in FIG. 6b, after the fine pattern of the hexagonal hole pattern in which each side is parallel to the {1-100} m plane was formed, the etching did not proceed any more.

(Example 1E)
This embodiment is applied in a similar manner to Embodiment 1D, but in order to more easily observe the change in crystal plane on the side wall of the final hole, the hole period is maintained as in Embodiment 1D, but the hole diameter is changed. Enlarged and implemented.

  A cross section of the hexagonal hole obtained after wet etching (100 ° C., 4M KOH aqueous solution) in the horizontal direction of this example was taken with an SEM photograph. FIG. 7a shows the result of applying wet etching for 10 minutes, and FIG. 7b shows the result of etching for 40 minutes.

  As a result, it can be seen that as wet etching progresses, the area occupied by the relatively unstable s-plane decreases on the side wall of the hole, and the area occupied by the m-plane increases. More specifically, in FIG. 7a, the portion where the m-plane and the c-plane at the bottom contact with each other is the s-plane, but as the etching proceeds, it gradually approaches the c-plane through the r-plane.

  As described above, as a result of checking the cross section of the hexagonal hole by SEM according to the progress time of the wet etching, the pattern of the side wall formed by the initial dry etching changes until a stable crystal plane appears as the wet etching progresses. I understood. In particular, the crystal plane of the inner side wall of the hole is the {0001} c plane which is the bottom, and the {1-101} s plane, the {1-100} m plane, the {1-102} r plane, etc. depending on the wet conditions (time). It can be composed of a combination of At this time, since the wet etching does not proceed in the c-plane direction, the depth of the hole does not change, but if there is a fine bend or inclination of the bottom surface, it may be removed by the etching action in the horizontal direction described above. It can be estimated that it is possible.

  As described above, in the fine pattern obtained by the present invention, the crystal plane shown by the horizontal etching is a clean surface from which the damaged surface originally generated by the dry etching is removed, and the electrical contact layer is formed on the crystal plane. When formed, excellent ohmic characteristics can be ensured. In addition, when the electrode material is deposited by adjusting the inclination by the crystal plane, the contact property can be improved.

  Such a fine pattern forming process can be widely applied to form functional patterns of various semiconductor devices, and is particularly useful for forming patterns for improving the light efficiency of semiconductor light emitting devices. Can be applied to. The embodiment illustrated in FIG. 8a shows a nitride semiconductor light emitting device 80 which is an application example of a photonic crystal.

  Referring to FIG. 8a, the nitride semiconductor light emitting device 80 includes a sapphire substrate 81, an n-type nitride semiconductor layer 82, an active layer 84, and a p-type nitride semiconductor layer 85 that are sequentially formed on the sapphire substrate 81. .

  The nitride semiconductor light emitting device 80 includes n-side and p-side electrodes 89a and 89b that are electrically connected to the n-type nitride semiconductor layer 82 and the p-type nitride semiconductor layer 85, respectively.

  A fine pattern having a certain periodicity is formed on the p-type nitride semiconductor layer 85. Such a fine pattern P3 can be obtained through the process (Example 1D) described in FIGS. 2a to 2d. That is, as shown in FIG. 8b, hexagonal holes are employed so as to be arranged at a constant period.

  In the present embodiment, as shown in the drawing, a light transmissive conductive layer 87 is further formed on the p-type nitride semiconductor layer 85 on which the periodic fine hole pattern P3 is formed. The light transmissive conductive layer 87 can be preferably used as long as it is a material that can ensure ohmic contact but has a light transmissive property. For example, a light transmissive metal layer such as Ni / Au or a light transmissive conductive oxide layer such as ITO can be used.

The thickness _{t s} of the p-type nitride semiconductor layer 85 can be is 50nm or less. On the other hand, if the thickness t _{s of} the p-type nitride semiconductor layer 85, that is, the distance to the lattice structure is too close, there is a problem that the leakage current increases rapidly. of thickness _{t s} is preferably equal to or greater than 10nm.

  The fine pattern P3 formed on the p-type nitride semiconductor layer 85 has a surrounding air or sealing when light generated in the active layer 84 is extracted to the outside through the surface of the p-type nitride semiconductor layer 85. It can act as a photonic crystal structure that reduces the total reflection effect due to the low refractive index of the material and improves the light extraction efficiency.

  The fine pattern forming process of the present invention can be implemented to have high precision and excellent reproducibility due to a difference in etching rate depending on crystal planes even when wet etching is used. Therefore, the present invention can be applied to the nitride semiconductor light emitting device having the photonic crystal structure illustrated in FIG.

  In the present embodiment, the nitride semiconductor light emitting device has been specified and described, but it can be beneficially applied to light emitting devices made of various other known semiconductor materials.

  In addition, although the embodiment illustrated in FIG. 8a is exemplified by a photonic crystal on the surface of a specific semiconductor layer such as a p-type nitride semiconductor layer, the periodic fine pattern employed in the surface plasmon is illustrated. Although it is applied to the forming method, it is also very useful for the method of forming a desired fine pattern while protecting the surface of the crystal even when providing irregular irregular patterns for light extraction with different materials Can be used.

  Example 2 is an experiment on a light-emitting element having a photonic crystal and the result thereof.

(Example 2)
In this example, a nitride semiconductor light emitting device having an active layer of InGaN multiple quantum wells having a green wavelength was manufactured.

  The light emitting device manufactured in the present example was subjected to a wet etching process (for 10 minutes) after dry etching at a depth of 54 nm using a circular hole mask on p-type GaN having a thickness of about 150 nm, similar to the condition of Example 1D. Implementation) was applied to form a hexagonal hole pattern. Next, similar to the structure illustrated in FIG. 8a, a light-transmitting conductive oxide such as ITO is deposited on the p-type GaN layer with a light-transmitting electrode layer to form a p-side contact. Mesa etching was performed so that the layer was partially exposed, and an n-side contact was formed on the exposed n-type GaN layer.

  Thus, in order to confirm the improvement of the electrical characteristics and the luminance of the semiconductor light emitting device manufactured by the method of the present invention, the improvement of the electrical characteristics and the luminance of the nitride semiconductor light emitting device obtained in Example 2 was performed. The measurement results are shown in FIGS. 9 and 10 in comparison with the reference example. Here, the reference example is a result of the light emitting element structure in which only the Ag contact is formed without forming a pattern on the p-type nitride semiconductor layer.

  FIG. 9 is a graph showing a current-voltage curve of the nitride semiconductor light emitting device according to this example, and FIG. 10 is a graph showing an optical output according to the current of the nitride semiconductor light emitting device according to this example.

  First, as shown in FIG. 9, the nitride semiconductor light emitting device manufactured according to Example 2 of the present invention, as confirmed in FIG. 1, has almost no leakage current due to crystal damage during dry etching. It was confirmed that it had characteristics. The nitride semiconductor light emitting device according to this example was shown to have a slightly higher voltage at the same current than the reference example (Ref), but there was no significant difference and the area ratio of the crystal plane obtained during wet etching increased. By designing in this way, it is possible to improve the contact resistance and expect electric characteristics superior to those of the present embodiment.

  FIG. 10 is a graph showing the light output according to the current of the nitride semiconductor light emitting device manufactured according to this embodiment of the present invention.

  As shown in FIG. 10, it is confirmed that the nitride semiconductor light emitting device according to this example has an improvement of about 24% in luminance at 350 mA current due to the diffraction effect of the photonic crystal compared to the reference example (Ref). did it. That is, the photonic crystal pattern manufactured through the etching process according to the present invention is formed with a precise profile, and a part of the light that is totally reflected and restrained inside the light emitting device chip is diffracted and emitted to the outside of the chip. Change the direction of travel at an angle that can be done. Through this, the luminance of the light emitting element can be greatly improved.

  FIG. 11 is a side sectional view showing a nitride semiconductor light emitting device (application example of surface plasmon resonance principle) obtained by the manufacturing method of the present invention.

  In the present specification, the surface plasmon used is a collective charge density oscillation that occurs on the surface of a metal thin film, and the surface plasmon wave generated thereby follows the interface between the metal and the dielectric. It is a traveling surface electromagnetic wave. When the coupling occurs between the surface plasmon and the active layer, the spontaneous emission generated in the active layer is increased by the surface plasmon, and a large part of the light generated by the spontaneous emission is excited by the surface plasmon. A device that improves the efficiency of a light-emitting element using such a principle can be said to be a surface plasmon semiconductor light-emitting element.

  Referring to FIG. 11, a surface plasmon nitride semiconductor light emitting device 110 mounted on a submount substrate 120 by solder is illustrated.

  The nitride semiconductor sapphire substrate 111 and an n-type nitride semiconductor layer 112, an active layer 114, and a p-type nitride semiconductor layer 115 are sequentially formed on the sapphire substrate 111.

  The nitride semiconductor light emitting device 110 includes n-side and p-side electrodes 117 and 118 that are electrically connected to the n-type nitride semiconductor layer 112 and the p-type nitride semiconductor layer 115, respectively.

  A fine pattern having a certain periodicity is formed on the p-type nitride semiconductor layer 115. Such a fine pattern P4 is a pattern in which hexagonal holes are arranged at a constant cycle through the steps (Example 1D) described in FIGS. 2a to 2d.

  In the present embodiment, as shown, a highly reflective metal layer is formed as a p-side electrode 118 on the p-type nitride semiconductor layer 115 on which the periodic fine hole pattern P4 is formed. The highly reflective metal layer can be preferably used as long as it is a material that can ensure ohmic contact but has a predetermined reflectance. For example, it can be a single layer or multiple layer metal material such as Al, Ag, Au, Cr, Ni, Pd, Pt.

  Further, in order for surface plasmon resonance to occur, the distance between the active layer 115 and the highly reflective metal layer is very important. Accordingly, the p-type nitride semiconductor layer 115 has such a thickness that surface plasmons can be excited at the interface between the p-type nitride semiconductor layer 115 and the highly reflective metal layer by the light emitted from the active layer 114. Desired.

Preferably, the p-type nitride semiconductor layer 115 may have a thickness _ts of 50 nm or less. On the other hand, when the thickness t _{s of} the p-type nitride semiconductor layer 115, that is, the distance to the lattice structure is too close, there is a problem that the leakage current increases rapidly. of thickness _{t s} is preferably equal to or greater than 10nm.

  As in the present embodiment, surface plasmon resonance can be employed in a light emitting element on the principle for improving light emission efficiency.

  In such a form, in order to reconvert the excited surface plasmon into light, a fine pattern P4 having a periodic lattice structure is required at the interface between the p-type nitride semiconductor layer 115 and the metal layer. In particular, in such a periodic lattice structure, the precise period and size of the pattern are determined by the wavelength generated from the active layer.

  Considering such circumstances, dry etching is preferable. However, as described above, the distance between the active layer 114 and the metal layer is very important among the conditions (the wavelength of incident light and the refractive index of the substance in contact with the metal) in order to cause surface plasmon resonance. In general, since the distance is relatively small at 50 nm or less, damage to the p-type nitride semiconductor layer 115 due to dry etching can be a serious problem, but the damage region finally remaining in the pattern is minimized. can do. In addition, the fine pattern forming process of the present invention can be implemented to have high precision and excellent reproducibility due to a difference in etching rate depending on crystal planes even when wet etching is used. Therefore, the present invention can be applied to the surface plasmon nitride semiconductor light emitting device shown in FIG.

(Example 3)
In this example, a nitride semiconductor light emitting device having an active layer of InGaN multiple quantum wells having a green wavelength was manufactured in the same manner as in Example 2.

  The light emitting device manufactured in this example was subjected to a wet etching process (performed for 10 minutes) after dry etching at a depth of 33 nm, similar to the condition of Example 1D, using a circular hole mask on p-type GaN having a thickness of about 66 nm. ) Was applied to form a hexagonal hole pattern. Next, similarly to the structure shown in FIG. 11, a multi-layer metal electrode including a highly reflective metal layer of Ag layer is deposited on the p-type GaN layer to form a p-type contact, and the n-type GaN layer is formed. Mesa etching was performed so as to be partially exposed, and an n-side contact was formed on the exposed n-type GaN layer.

  Thus, in order to confirm the improvement in the electrical characteristics and luminance of the semiconductor light emitting device manufactured by the method of the present invention, the improvement in the electrical characteristics and luminance of the nitride semiconductor light emitting device obtained in Example 3 was performed. The measurement results are shown in FIGS. 12 and 13 in comparison with the reference example (Ref). Here, the reference example is a result of the light-emitting element structure in which only the same multilayer metal electrode as in Example 3 is formed without forming a pattern on the p-type nitride semiconductor layer.

  FIG. 12 is a graph showing a current-voltage curve of the nitride semiconductor light emitting device according to this example, and FIG. 13 is a graph showing an optical output according to the current of the nitride semiconductor light emitting device according to this example.

  First, as shown in FIG. 12, the nitride semiconductor light emitting device manufactured according to Example 3 of the present invention has an IV current that hardly generates leakage current due to crystal damage during dry etching, as confirmed in FIG. It was confirmed that it had characteristics. However, somewhat irregular folds were observed on the IV curve due to the characteristics of this example having a p-type nitride semiconductor layer that is very thin compared to a normal nitride semiconductor light emitting device.

  The nitride semiconductor light emitting device according to this example is shown to have almost the same voltage at the same current as the reference example (Ref), and designed so that the area ratio of the crystal plane obtained during wet etching is increased. Thus, the contact resistance can be improved, and electrical characteristics superior to those of this embodiment can be expected.

  FIG. 13 is a graph showing light output according to current of a nitride semiconductor light emitting device manufactured according to another embodiment of the present invention.

  As shown in FIG. 13, it can be confirmed that the nitride semiconductor light emitting device according to this example has an improved brightness of about 64% at 350 mA current due to the surface plasmon resonance effect as compared with the reference example (Ref). It was. That is, the fine lattice structure manufactured through the etching process according to the present invention is formed with a precise profile, and the energy of electron-hole pairs injected into the multiple quantum wells inside the light emitting device chip is converted into light using the surface plasmon as a medium. And released outside the chip.

  In addition, among the light generated by spontaneous emission without using surface plasmons as a medium, the traveling direction is set at an angle at which a part of the light that is totally reflected and restrained inside the light emitting element chip can be diffracted and emitted to the outside of the chip. Convert. Through this, the luminance of the light emitting element can be greatly improved.

  The present invention is not limited by the above-described embodiments and the accompanying drawings, but is limited by the above claims. Accordingly, various forms of substitution, modification, and alteration can be made by those having ordinary knowledge in the art without departing from the technical idea of the present invention described in the claims, and this is also within the scope of the present invention. Belongs.

It is a graph which shows the change of the current-voltage curve of the nitride semiconductor light-emitting device with which the p-type GaN layer was damaged by dry etching. It is sectional drawing for every process for demonstrating the formation process of the fine pattern using the horizontal wet etching by this invention. It is sectional drawing for every process for demonstrating the formation process of the fine pattern using the horizontal wet etching by this invention. It is sectional drawing for every process for demonstrating the formation process of the fine pattern using the horizontal wet etching by this invention. It is sectional drawing for every process for demonstrating the formation process of the fine pattern using the horizontal wet etching by this invention. It is a SEM photograph which shows the pattern change by the application time of horizontal wet etching in one Example (1A) of the formation process of the fine pattern of this invention. It is a SEM photograph which shows the pattern change by the application time of horizontal wet etching in one Example (1A) of the formation process of the fine pattern of this invention. It is a SEM photograph which shows the pattern change by the application time of horizontal wet etching in one Example (1A) of the formation process of the fine pattern of this invention. It is a SEM photograph which shows the pattern change by the application time of horizontal wet etching in other Example (1B) of the formation process of the fine pattern of this invention. It is a SEM photograph which shows the pattern change by the application time of horizontal wet etching in other Example (1B) of the formation process of the fine pattern of this invention. It is a SEM photograph which shows the pattern change by the application time of horizontal wet etching in other Example (1B) of the formation process of the fine pattern of this invention. It is a SEM photograph which shows the pattern change by the application time of horizontal wet etching in other Example (1B) of the formation process of the fine pattern of this invention. It is the SEM photograph which image | photographed the three-dimensional pattern (pillar structure) obtained by other Example (1C) of the formation process of the fine pattern of this invention. It is the SEM photograph which image | photographed the fine pattern obtained after dry etching and horizontal wet etching in other Example (1D) of the formation process of the fine pattern of this invention. It is the SEM photograph which image | photographed the fine pattern obtained after dry etching and horizontal wet etching in other Example (1D) of the formation process of the fine pattern of this invention. It is a SEM photograph which shows the pattern change by the application time of horizontal wet etching in other Example (1E) of the formation process of the fine pattern of this invention. It is a SEM photograph which shows the pattern change by the application time of horizontal wet etching in other Example (1E) of the formation process of the fine pattern of this invention. It is a sectional side view which shows the nitride semiconductor light-emitting device (application example of a photonic crystal structure) obtained by the manufacturing method of this invention. FIG. 8B is a plan view of a fine pattern layer cut in the AA ′ direction of the nitride semiconductor light emitting device illustrated in FIG. 8A. It is a graph which shows the current-voltage curve of the nitride semiconductor light-emitting device manufactured by one Example (2) of the manufacturing method of the semiconductor light-emitting device of this invention. It is a graph which shows the optical output by the electric current of the nitride semiconductor light-emitting device manufactured by one Example (2) of the manufacturing method of the semiconductor light-emitting device of this invention. It is a sectional side view which shows the nitride semiconductor light-emitting device (application example of surface plasmon resonance structure) obtained by the manufacturing method of this invention. It is a graph which shows the current-voltage curve of the nitride semiconductor light-emitting device manufactured by one Example (3) of the manufacturing method of the semiconductor light-emitting device of this invention. It is a graph which shows the optical output by the electric current of the nitride semiconductor light-emitting device manufactured by one Example (3) of the manufacturing method of the semiconductor light-emitting device of this invention.

Claims (26)

providing a c-plane hexagonal semiconductor crystal;
Forming a mask having a predetermined pattern on the semiconductor crystal;
Forming a primary fine pattern by removing a portion of said semiconductor crystal in a direction perpendicular to the semiconductor crystal surface by dry-etching the semiconductor crystal by using the mask,
Forming a secondary fine pattern in which the primary fine pattern extends in a horizontal direction by wet etching the semiconductor crystal on which the primary fine pattern is formed;
A method for forming a fine pattern, wherein the bottom and side walls of the secondary fine pattern obtained by the wet etching each have a unique crystal plane.   The mask pattern has a plurality of fine hole structures,
  2. The method of forming a fine pattern according to claim 1, wherein the secondary fine pattern is a plurality of fine hole structures having hexagonal release ports.   The step of forming the secondary fine pattern includes:
  The method for forming a fine pattern according to claim 1 or 2, wherein the wet etching is performed so that a side wall of the secondary fine pattern includes a combination of an m-plane component and an s-plane component.   The step of forming the secondary fine pattern includes:
  3. The method of forming a fine pattern according to claim 1, wherein the wet etching is performed so that an r-plane component is generated on a sidewall of the secondary fine pattern. The mask pattern is a plurality of line patterns formed in the <11-20> direction of the semiconductor crystal and arranged according to the <1-100> direction,
The method for forming a fine pattern according to claim 1 , wherein the sidewall of the secondary fine pattern is an m-plane. 2. The fine pattern according to claim 1 , wherein the mask pattern is a plurality of line patterns formed in a <1-100> direction of the semiconductor crystal and arranged in a <11-20> direction. Forming method.   The fine pattern forming method according to claim 1, wherein the semiconductor crystal is a p-type nitride semiconductor.   The bottom surface obtained from the step of forming the primary fine pattern is the same c-plane as the bottom surface obtained from the step of forming the secondary fine pattern. 8. The method for forming a fine pattern according to any one of 7 above. The method of forming a fine pattern according to claim 8 , wherein the secondary fine pattern has a pillar structure. The forming of the second fine pattern, the fine pattern forming method of according to any one of claims 1 to 9, characterized in that it is carried out after removing the mask. The forming of the second fine pattern, the fine pattern forming method of according to any one of claims 1 to 9, characterized in that it is performed prior to removing the mask. Providing a semiconductor laminate having a first conductive type and a second conductive type semiconductor layer and an active layer therebetween;
Forming a mask having a predetermined pattern on the second conductive type semiconductor layer of the semiconductor laminate;
A primary fine pattern in which a part of the second conductive semiconductor layer is removed in a direction perpendicular to the surface of the second conductive semiconductor layer is formed by dry etching the second conductive semiconductor layer using the mask. And the stage of
Forming a secondary fine pattern in which the primary fine pattern extends in a horizontal direction by wet etching the second conductive semiconductor layer on which the primary fine pattern is formed;
Forming first and second electrodes to be connected to the first conductive type and second conductive type semiconductor layers with the mask removed;
The second conductive semiconductor layer is a c-plane hexagonal semiconductor crystal, and the bottom surface and the side wall of the secondary fine pattern obtained by the wet etching each have a unique crystal surface. Manufacturing method.   The mask pattern has a plurality of fine hole structures,
  The method according to claim 12, wherein the secondary fine pattern has a plurality of fine hole structures having hexagonal opening.   The step of forming the secondary fine pattern includes:
  14. The method of manufacturing a semiconductor light emitting device according to claim 12, wherein the wet etching is performed so that a side wall of the secondary fine pattern includes a combination of an m-plane component and an s-plane component.   The step of forming the secondary fine pattern includes:
  14. The method of manufacturing a semiconductor light emitting device according to claim 12, wherein the wet etching is performed so that an r-plane component is generated on a sidewall of the secondary fine pattern.   The mask pattern is a plurality of line patterns formed in the <11-20> direction of the semiconductor crystal and arranged according to the <1-100> direction,
  The method of claim 12, wherein the sidewall of the secondary fine pattern is an m-plane.   13. The semiconductor light emitting device according to claim 12, wherein the mask pattern is a plurality of line patterns formed in the <1-100> direction of the semiconductor crystal and arranged in accordance with the <11-20> direction. Manufacturing method. Bottom obtained from the step of forming the primary fine pattern from claim 12, characterized in that, characterized in that the same c-plane and the bottom surface resulting from the forming of the second fine pattern 18. A method for manufacturing a semiconductor light emitting device according to any one of items 17 to 17 . It said step of forming a second electrode, a semiconductor according to any one of claims 12 to 18 including the step of forming a transparent electrode layer on the second conductive type semiconductor layer on said second fine pattern is formed Manufacturing method of light emitting element. The forming of the second electrode, according to any one of claims 12 to 19 including the step of forming a highly reflective metal layer on the second conductive type semiconductor layer on said second fine pattern is formed Manufacturing method of the semiconductor light-emitting device. The second conductivity type semiconductor layer has a thickness that allows surface plasmons to be excited at an interface between the second conductivity type semiconductor layer and the highly reflective metal layer by light emitted from the active layer. The method of manufacturing a semiconductor light emitting element according to claim 20 . The method of manufacturing a semiconductor light emitting device according to claim 20 or 21 , wherein the thickness of the second conductivity type semiconductor layer is 50 nm or less. The semiconductor laminate is a nitride semiconductor,
Said first conductivity type and the second conductivity type semiconductor layer, a method of manufacturing a semiconductor light-emitting device according to any one of claims 12 to 22, characterized in that the respective n-type and p-type nitride semiconductor layer . 20. The method of manufacturing a semiconductor light emitting device according to claim 19 , wherein the secondary fine pattern has a pillar structure. Removing the mask, according to any one of claims 24 claim 13, characterized in that it is performed during the step of forming a step between the second fine pattern forming the primary fine pattern A method for manufacturing a semiconductor light emitting device. Removing the mask, a method of manufacturing a semiconductor light emitting device according to claims 13 to any one of claims 24, characterized in that it is performed after the forming of the second fine pattern.