JP2007116057A - Semiconductor element manufacturing method, semiconductor element, semiconductor laser, surface light-emitting element, and optical waveguide - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method for a semiconductor element having an end face with a smooth surface, the semiconductor element having the end face with the smooth surface, a semiconductor laser using the semiconductor element, a surface light-emitting element using the semiconductor element, and an optical waveguide using the semiconductor element. <P>SOLUTION: The semiconductor element 10 is formed using a GaN epitaxially-grown layer 12 having a (0001) face as a main face. The semiconductor element 10 is provided with a substrate 11, and the epitaxially-grown layer 12 formed on the substrate 11. A side wall 12a is formed by an m face in the GaN epitaxially-grown layer 12. The manufacturing method for the semiconductor element 10 has a step for preparing the GaN epitaxially-grown layer having the (0001) face as the main face, and a wet etching step for executing wet etching so as to make the m face perpendicular to the (0001) face as a reaction rate-controlling face. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device, a semiconductor device, a semiconductor laser, a surface light emitting device, and an optical waveguide.

In a laser structure using a GaN epitaxial growth layer formed on the surface of a sapphire substrate, Fabry-Perot (Fabry- It has been disclosed that dry etching such as RIE (Reactive Ion Etching) is used to form a mirror end face of a Perot: FP (Non-Patent Document 1).
Jpn.J.Appl.Phys.Vol.35 (1996), pp.L74-L76 Part2, No.1B, 15 January 1996

  However, in the Fabry-Perot laser disclosed in Non-Patent Document 1, when high-perpendicular chlorine-based RIE is performed, the surface roughness RMS roughness of the mirror end face increases to 50 nm or more. For this reason, the Fabry-Perot laser has a problem in that the reflection efficiency of the mirror forming the resonator is poor and the threshold value becomes high.

  The reason is that GaN crystals are strong and brittle because their atomic bonds are strong. Therefore, the etching side wall at the time of dry etching is likely to be rough, and it is difficult to make the surface smooth. That is, it is difficult to suppress the roughness of the end face of the Fabry-Perot laser using the GaN crystal or the side wall of the waveguide.

  Further, the Fabry-Perot laser mainly uses a milling reaction, which is a physical reaction process, as a dry etching condition in order to achieve verticality. However, it is difficult to maintain the verticality of etching and maintain a sufficient etching rate mainly in the chemical reaction process.

  Further, in the Fabry-Perot laser, it is possible to produce the side wall by using a polishing technique so as to obtain perpendicularity. However, in order to realize the fabrication of a fine element, it is necessary to perform a very difficult process. Further, the damage of the side wall due to polishing is often larger than that of dry etching. As a result, there is a problem that the performance of the element is impaired.

  SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a method for manufacturing a semiconductor element having a smooth end surface, a semiconductor element having a smooth end surface, a semiconductor laser using the semiconductor element, and a surface light emitting element using the semiconductor element. And an optical waveguide using the semiconductor element.

  A method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device using a GaN epitaxial growth layer having a (0001) plane as a main surface, and preparing a GaN epitaxial growth layer having a (0001) plane as a main surface. And a wet etching step of performing wet etching in which the m-plane perpendicular to the (0001) plane is a reaction-controlled surface.

  Preferably, the semiconductor device manufacturing method further includes a plasma etching step using a gas containing at least one of chlorine, iodine, and fluorine, which is performed prior to the wet etching step.

  Preferably, in the method for manufacturing a semiconductor device, in the wet etching step, a thermal SPM (sulfuric acid hydrogen peroxide mixture) or an organic alkaline cleaning solution is used as an etching solution.

  In the semiconductor device manufacturing method, preferably, the temperature of the thermal SPM is set to 90 ° C. or higher and 130 ° C. or lower to perform wet etching.

  A semiconductor element in one aspect of the present invention is a semiconductor element using a GaN epitaxial growth layer having a (0001) plane as a main surface, and a step of preparing a GaN epitaxial growth layer having a (0001) plane as a main surface; The m-plane is a side wall formed in a wet etching process in which wet etching is performed in which the m-plane perpendicular to the (0001) plane is a reaction-controlled surface.

  A semiconductor device according to another aspect of the present invention is a semiconductor device using a GaN epitaxial growth layer having a (0001) plane as a main surface, and includes a substrate and a GaN epitaxial growth layer formed on the substrate, and includes a GaN epitaxial growth. In the layer, side walls are formed by the m-plane.

  Preferably, in the semiconductor device, the side wall is formed so as to surround the GaN epitaxial growth layer, and the planar shape of the GaN epitaxial growth layer is a hexagon.

  In the semiconductor element, the RMS roughness of the surface of the sidewall is preferably 0.1 nm or more and 10 nm or less.

  A semiconductor laser according to the present invention is a semiconductor laser using the above-described semiconductor element, and an end face for emitting light in the semiconductor laser is a side wall made of an m-plane of the semiconductor element.

  A surface light emitting device according to the present invention is a surface light emitting device using the above semiconductor element, wherein a side wall of the surface light emitting element is a side wall formed of an m-plane of the semiconductor element.

  An optical waveguide according to the present invention is an optical waveguide using a GaN epitaxial growth layer having a (0001) plane as a main surface, and a step of preparing a GaN epitaxial growth layer having a (0001) plane as a main surface; The side surface of the optical waveguide formed in the GaN epitaxial growth layer is a m-plane manufactured by a wet etching process in which the m-plane which is perpendicular to the plane) is a reaction-controlled surface.

  As described above, according to the method for manufacturing a semiconductor device of the present invention, a rigid and brittle GaN epitaxial growth layer can be obtained by using wet etching in which the m-plane of the GaN epitaxial growth layer is a reaction-controlling surface and using the m-plane as a sidewall. The semiconductor element which has a smooth side wall can be manufactured by using.

  In addition, according to the semiconductor element of the present invention, a semiconductor element having a smooth side wall can be obtained by using wet etching in which the m-plane of the GaN epitaxial growth layer becomes a reaction-controlled surface to make the m-plane a side wall. .

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following drawings, the same or corresponding parts are denoted by the same reference numerals, and description thereof will not be repeated.

  FIG. 1 is a schematic perspective view of a semiconductor element according to an embodiment of the present invention. A semiconductor element according to an embodiment of the present invention will be described with reference to FIG.

  As shown in FIG. 1, a semiconductor element 10 in the embodiment is a semiconductor element 10 using a GaN epitaxial growth layer 12 having a (0001) plane as a main surface. The semiconductor element 10 includes a substrate 11 and an epitaxial growth layer 12 formed on the substrate 11. In the GaN epitaxial growth layer 12, side walls 12a are formed by the m-plane.

  Specifically, the side wall 12a is formed so as to surround the GaN epitaxial growth layer 12, and the planar shape of the GaN epitaxial growth layer 12 is a hexagon. The RMS roughness of the surface of the side wall 12a is not less than 0.1 nm and not more than 10 nm.

  In the embodiment, the semiconductor element 10 includes a substrate 11, an epitaxial growth layer 12, and electrodes 13 and 14. The substrate 11 is, for example, a GaN substrate or a sapphire substrate. However, when a sapphire substrate is used, the lowermost layer of the epitaxial growth layer 12 is extended on the sapphire substrate, and the electrode 13 is disposed in the extended portion.

  Further, as shown in FIG. 1, the GaN epitaxial growth layer 12 is a hexagonal hexagonal planar shape on the surface 11a of the substrate 11, that is, vertically upward with respect to the (0001) plane that is the main surface of the GaN epitaxial growth layer 12. It is formed to be a pillar.

  The six side walls 12a of the GaN epitaxial growth layer 12 are m-planes (cleavage planes). Specifically, the side wall 12a is formed from the (1-100) plane, (0-110) plane, (-1010) plane, (-1100) plane, (01-10) plane, and (10-10) plane. Become. Here, the (0001) plane (c-plane) means a hexagonal basal plane. The m-plane (cleavage plane) is the (1-100) plane, (0-110) plane, (-1010) plane, (-1100) plane, (01) of the plane orientation perpendicular to the c-plane. It means six equivalent planes, the -10) plane and the (10-10) plane. In the GaN epitaxial growth layer 12, the (0001) plane is a plane in which Ga (gallium) is 100% aligned and the (000-1) plane is a plane in which N (nitrogen) is 100% aligned.

  The RMS (Root Mean Square: surface roughness) roughness of the surface of the side wall 12a whose m-plane is the side wall 12a is 0.1 nm or more and 10 nm or less. RMS means the square root of the value obtained by averaging the squares of deviations from the average line to the measurement curve. The RMS roughness of the side wall 12a was measured by separately preparing the side wall 12a so that the area of the side wall 12a was increased, and directly evaluating the unevenness of the side wall surface with an AFM (atomic force microscope).

  In addition, although the semiconductor element 10 in the embodiment is formed with all the side walls 12a of the epitaxial growth layer 12 as m-planes, it is not particularly limited to this configuration. Of the sidewalls of the GaN epitaxial growth layer, the sidewall that requires a smooth surface may be the m-plane. Therefore, the planar shape of the epitaxial growth layer 12 is not limited to the hexagon as shown in FIG. 1, but may be any shape such as a polygonal shape such as a triangle or a quadrangle, or a shape in which a straight portion and a curved portion are combined. Can do.

  Next, a method for manufacturing the semiconductor element 10 will be described. FIG. 2 is a flowchart showing a method for manufacturing the semiconductor element 10 according to the embodiment of the present invention. With reference to FIG. 1 and FIG. 2, the manufacturing method of the semiconductor element 10 in embodiment of this invention is demonstrated.

  First, as shown in FIG. 2, a step (S10) of preparing the GaN epitaxial growth layer 12 is performed. In this step (S10), a GaN epitaxial growth layer 12 is formed on the substrate 11.

  Next, a wet etching step (S20) is performed. In this step (S20), wet etching is performed on the GaN epitaxial growth layer 12 having the (0001) plane as the main surface, with the m-plane being a reaction-controlled plane.

  When performing the wet etching, as will be described later, a mask layer such as a resist pattern serving as a mask is previously formed on the GaN epitaxial growth layer 12, and the GaN epitaxial growth layer 12 is anisotropically formed using the mask layer as a mask. The planar shape may be processed into a hexagonal prism shape by reactive etching. After the processing, the GaN epitaxial growth layer 12 may be partially removed so that the side wall 12a becomes the m-plane by performing wet etching in which the m-plane becomes the reaction-controlling plane. In this way, the smooth side wall 12a can be obtained while reducing the processing time required for wet etching. Then, electrodes 14 and 13 are formed on the upper surface of the GaN epitaxial growth layer 12 and on the back surface of the substrate 11 (surface opposite to the surface on which the GaN epitaxial growth layer 12 is formed), respectively. The electrodes 14 and 13 may be formed in advance before the wet etching step (S20).

  By performing the above steps (S10, S20), the semiconductor element 10 in the embodiment of the present invention as shown in FIG. 1 can be manufactured.

  FIG. 3 is a flowchart showing in detail a method for manufacturing the semiconductor element 10 in the embodiment of the present invention. With reference to FIG. 1 and FIG. 3, the manufacturing method of the semiconductor element 10 in embodiment of this invention is demonstrated in detail.

  First, as shown in FIG. 3, a step (S10) of preparing the GaN epitaxial growth layer 12 is performed. In this step (S10), a GaN epitaxial growth layer 12 is formed on the substrate 11.

  Next, a step (S30) of forming a mask layer on the GaN epitaxial growth layer 12 is performed. In this step (S30), for example, a photoresist is used as the mask layer. In this step (S30), a general photoresist is used as the mask layer, but it is not particularly limited to this. For example, a photolithography pattern can be transferred by etching onto an insulating film such as SiN to form a mask. A multilayer mask can also be used.

  Next, an exposure step (S40) is performed. In the exposure, for example, a resist mask pattern is directly drawn on the photoresist applied on the GaN epitaxial growth layer 12 by ultraviolet exposure. This resist mask pattern has a predetermined shape, and in this embodiment, has a hexagonal shape.

  Next, a developing step (S50) is performed. In this step (S50), for example, in the case of a positive type, a portion exposed by ultraviolet rays is melted. On the other hand, in the case of the negative type, the part other than the part exposed with the ultraviolet rays is dissolved by the development process. In the present embodiment, a mask layer having a hexagonal planar shape is formed from the shape of the resist mask. Since each side of the hexagon has a side wall 12a in a direction (plane) perpendicular to the substrate 11 of the GaN epitaxial growth layer 12, a mask layer is formed so that the side wall 12a matches the m-plane. That is, the direction in which each side of the outer periphery of the mask layer having a hexagonal plane shape extends is a direction substantially parallel to the m-plane of the GaN epitaxial growth layer 12.

  Next, a step of performing dry etching (S60) is performed. In this step (S60), for example, ICP (inductively coupled plasma) etching is performed using the mask layer described above as a mask in an atmosphere of Cl (chlorine) gas or HI (hydroiodic acid) gas. An inert gas such as argon gas or xenon gas may be mixed with Cl gas or HI gas. In this case, the ratio of Cl gas or HI gas to inert gas is preferably 2: 1. ICP etching is performed, for example, by setting the atmospheric pressure to 0.3 Pa to 1 Pa and applying a bias of 200 W.

  In this step (S60), the side wall 12a of the GaN epitaxial growth layer 12 can be formed by etching in a portion other than the hexagon that is not covered with the mask layer by the mask layer having a hexagonal plan shape. However, the surface of the side wall 12a formed by this dry etching is not smooth but is in a so-called rough state.

  Finally, a wet etching step (S20) is performed. In this step (S20), the resist mask layer is removed, and wet etching is performed on the GaN epitaxial growth layer 12 having a hexagonal planar shape so that the m-plane becomes a reaction-controlled surface.

  In the embodiment, in this step (S20), a thermal SPM (sulfuric acid hydrogen peroxide mixture) or an organic alkaline cleaning solution is used as an etching solution. The thermal SPM is sulfuric acid (content 96%): hydrogen peroxide (concentration 30%) = (4-6): 1, and is heated to room temperature or higher (for example, 50 ° C. or higher), preferably Is sulfuric acid (content 96%): hydrogen peroxide (concentration 30%) = 5: 1. It is more preferable to perform wet etching with a thermal SPM of 90 ° C. or higher and 130 ° C. or lower. This is because when the wet etching is performed at a temperature lower than 90 ° C., the reaction rate decreases. On the other hand, when wet etching is performed at a temperature higher than 130 ° C., the hydrogen peroxide solution in the hot SPM boils.

  The organic alkaline cleaning liquid has an ammonia group and has a pH of 9 to 14. As the organic alkali cleaning liquid, for example, Semico Clean (manufactured by Furuuchi Chemical Co., Ltd.) can be used.

  In the step (S20), the (0001) plane of the GaN epitaxial growth layer 12 is not etched by the etchant. Etching with the etching solution proceeds at a very low speed with respect to a plane perpendicular to the (0001) plane. And the (0-110) plane, the (-1010) plane, the (-1100) plane, the (01-10) plane, and the (10-10) plane, which are equidirectional with the (1-100) plane, Etching with the etchant hardly proceeds on the m-plane (the etching rate is extremely slow compared to other surfaces). For this reason, the side wall 12a after the dry etching step (S60) is rough, but after the wet etching step (S20), the etching does not proceed on the m-plane, so that it is formed by the dry etching step (S60). The protrusions that are not the m-plane on the surface of the side wall 12a are preferentially removed by etching, so that the m-plane becomes the side wall 12a and the surface of the side wall 12a becomes smooth. In the dry etching step (S60), the portion damaged by the dry etching is removed by performing the wet etching step (S20). The electrodes 13 and 14 may be formed prior to the step (S30) or after the step (S20).

  By performing the above steps (S10 to S60), the semiconductor element 10 according to the embodiment of the present invention in which the side wall 12a is smooth as shown in FIG. 1 can be manufactured.

  In the embodiment, the dry etching step (S60) is performed, but the present invention is not limited to this. For example, prior to the wet etching step (S20), the step of processing the GaN epitaxial growth layer 12 into a hexagonal column shape can be performed by polishing or other mechanical processing methods.

  Next, a modified example of the semiconductor element 10 in the embodiment will be described. FIG. 4 is a schematic perspective view showing a semiconductor element in a modification of the embodiment of the present invention. With reference to FIG. 4, the semiconductor element in a modification is demonstrated. The semiconductor element 20 in the modified example has basically the same configuration as the semiconductor element 10 shown in FIG. 1, but differs in the shape of the GaN epitaxial growth layer.

  Specifically, as shown in FIG. 4, the semiconductor element 20 includes a substrate 11, a GaN epitaxial growth layer 22, and electrodes 13 and 14. The GaN epitaxial growth layer 22 is formed so as to extend vertically upward with respect to the (0001) plane (c-plane) and to have a square planar shape. Further, the side wall 22 a is composed of the m-plane of the GaN epitaxial growth layer 22, and the side wall 22 b is composed of the a-plane of the GaN epitaxial growth layer 22.

  The a-plane is a (1-210) plane, a (-1-120) plane, a (-2110) plane, a (-12-10) plane, ( 11-20) plane and (2-1-10) plane.

  The RMS roughness of the side wall 22a is not less than 0.1 nm and not more than 10 nm, and becomes a smooth surface. On the other hand, the RMS roughness of the side wall 22b is greater than 10 nm, resulting in surface roughness.

  Next, a method for manufacturing the semiconductor element 20 in the modification will be described. The manufacturing method of the semiconductor element 20 in the modification is basically the same as the manufacturing method of the semiconductor element 10 in the embodiment, but differs in the exposure step (S40) and the dry etching step (S60). .

  Specifically, in the exposure step (S40), the resist mask pattern formed by ultraviolet exposure is a quadrangle. Thus, in the developing step (S50), a mask layer having a quadrangular planar shape is formed from the shape of the resist mask pattern. One set of opposing sides of the mask layer extends in substantially the same direction as the direction in which the m-plane of the GaN epitaxial growth layer 12 extends (direction parallel to the m-plane).

  Further, in the step of performing dry etching (S60), the GaN epitaxial growth layer 22 is etched in a portion not covered with the mask layer, and the outer shape (rectangle) of the GaN epitaxial growth layer 22 can be formed.

  Thereafter, when the wet etching step (S20) is performed, the epitaxial growth layer 22 has a smooth side wall 22a and a rough surface by performing wet etching in which the m-plane is a reaction-controlled surface on the square side wall 22a. Is formed in a quadrangular prism including the side wall 22b in a state in which is left.

  Since other processes are the same as those of semiconductor element 10 in the embodiment of the present invention, description thereof will not be repeated.

  As described above, the method for manufacturing the semiconductor elements 10 and 20 in the embodiment of the present invention includes the steps (S10) of preparing the GaN epitaxial growth layers 12 and 22 having the (0001) plane as the main surface, and (0001). A wet etching step (S20) for performing wet etching in which the m-plane which is perpendicular to the plane is a reaction-controlling plane. By utilizing the fact that the m-plane (cleavage plane) is the reaction-controlling plane in the wet etching step (S20), the side walls 12a and 22a of the semiconductor elements 10 and 20 are made m-plane, thereby smoothing the side walls 12a and 22a. be able to. Therefore, according to the manufacturing method of the semiconductor elements 10 and 20 in the embodiment of the present invention, the semiconductor elements 10 and 20 having the smooth side walls 12a and 22a can be manufactured.

  The semiconductor elements 10 and 20 use GaN epitaxial growth layers 12 and 22. Although GaN is hard and brittle, according to the method for manufacturing the semiconductor elements 10 and 20 in the embodiment of the present invention, the smooth side walls 12a and 22a can be easily formed. Therefore, the semiconductor elements 10 and 20 having the smooth side walls 12a and 22a can be manufactured using GaN having a wide range of applicability.

  In the method of manufacturing the semiconductor elements 10 and 20, in the wet etching step (S20), a thermal SPM (sulfuric acid hydrogen peroxide mixture) or an organic alkaline cleaning solution may be used as an etching solution. Thereby, in the wet etching step (S20), the etching with the m-plane as a reaction-controlling surface can be reliably performed.

  In the manufacturing method of the semiconductor elements 10 and 20, it is preferable that the temperature of the thermal SPM is 90 ° C. or higher and 130 ° C. or lower to perform wet etching. Thereby, when using heat | fever SPM as an etching liquid in a process (S20), a wet etching process (S20) can be accelerated | stimulated more. As a result, the processing time of the wet etching step (S20) can be shortened and the semiconductor device manufacturing efficiency can be improved.

  In the semiconductor elements 10 and 20 in the embodiment of the present invention, the step (S10) of preparing the GaN epitaxial growth layers 12 and 22 having the (0001) plane as the main surface, and the m plane perpendicular to the (0001) plane Sidewalls 12a and 22a formed in the wet etching step (S20) for performing wet etching to become a reaction-controlling surface and formed in the GaN epitaxial growth layers 12 and 22 are m-planes. By using wet etching in which the m-plane is reaction-controlled, the m-plane is used as a side wall, whereby the semiconductor elements 10 and 20 having smooth side walls 12a and 22a formed on the substrates 11 and 21 can be obtained.

  Semiconductor elements 10 and 20 in the embodiment of the present invention are semiconductor elements 10 and 20 using GaN epitaxial growth layers 12 and 22 having a (0001) plane as a main surface, and include substrates 11 and 21, and substrates 11 and 21. GaN epitaxial growth layers 12 and 22 formed on the substrate 21, and side walls 12 a and 22 a are formed by m-planes in the GaN epitaxial growth layers 12 and 22. Thus, the semiconductor elements 10 and 20 formed on the substrates 11 and 21 and having the smooth side walls 12a and 22a can be obtained.

  In the semiconductor element 10, the side wall 12 a is formed so as to surround the GaN epitaxial growth layer 12, and the planar shape of the GaN epitaxial growth layer 12 can be a hexagon. Thereby, all m surfaces can be made into the side wall 12a. Therefore, the semiconductor element 10 in which the side walls 12a of the epitaxial growth layer 12 are all smooth can be obtained.

  In the semiconductor elements 10 and 20, the RMS roughness of the side wall 12a can be set to 0.1 nm or more and 10 nm or less. Thereby, the surface roughness of the side walls 12a and 22a of the semiconductor elements 10 and 20 becomes very low. Therefore, the performance as the semiconductor elements 10 and 20 can be further improved.

  FIG. 5 is a schematic perspective view showing the semiconductor laser in Example 1 of the present invention. With reference to FIG. 5, the semiconductor laser in Example 1 of this invention is demonstrated. The semiconductor laser 100 according to the first embodiment of the present invention is, for example, a Fabry-Perot laser.

  As shown in FIG. 5, the semiconductor laser 100 includes a substrate 101, an n-type buffer layer 102, an n-type cladding layer 103, an undoped guide layer 104, an active layer 105, a p-type electron blocking layer 106, p A type guide layer 107, a p-type cladding layer 108, a p-type contact layer 109, an n-type electrode 120, and a p-type electrode 130 are provided.

  On the substrate 101, an n-type buffer layer 102, an n-type cladding layer 103, an undoped guide layer 104, and a p-type electron blocking layer 106 are formed so as to be stacked. It is sandwiched between the type electron block layers 106. The layer composed of the n-type cladding layer 103, the undoped guide layer 104, the active layer 105, the p-type electron blocking layer 106, the p-type guide layer 107, the p-type cladding layer 108, and the p-type contact layer 109 is the (0001) of the substrate 101. ) Epitaxial growth layer 110 having a main surface as the GaN surface. In the epitaxial growth layer 110, one set of opposing side walls (front-rear direction in FIG. 5) 110a is an m-plane, and another set of opposing side walls (left-right direction in FIG. 5) 110b is an a-plane.

  More specifically, the structure of the semiconductor laser 100 shown in FIG. 5 will be described. On the substrate 101, an n-type buffer layer 102, an n-type cladding layer 103, an undoped guide layer 104, an active layer 105, and p-type electrons. The block layer 106, the p-type guide layer 107, the p-type cladding layer 108, and the p-type contact layer 109 are laminated in this order.

  In the first embodiment, the substrate 101 is made of sapphire. Since the substrate 101 is insulative and no voltage can be applied to the n-type cladding layer 103 even if an electrode is formed on the back surface of the substrate 101, the electrical connection between the n-type cladding layer 103 and the external power supply at another location It is necessary to secure the connection. For this reason, an n-type buffer layer 102 is formed on the substrate 101, and an n-type cladding layer 103 is formed on the n-type buffer layer 102. The n-type buffer layer 102 is made of, for example, n-type GaN and extends rightward in FIG. 5, and a part of the surface 102 a of the n-type buffer layer 102 is exposed on the right side of the n-type buffer layer 102. An n-type electrode 120 is formed on the exposed surface 102a.

  A p-type electrode 130 is formed on the p-type contact layer 109. The p-type electrode 130 and the n-type electrode 120 are made of, for example, Au (gold).

  The active layer 105 has a multiple quantum well structure made of, for example, InGaN / GaN. It may be made of a single semiconductor material. The active layer 105 is provided along the n-type cladding layer 103 and the p-type cladding layer 108, and can be formed as a plurality of quantum wires extending in a predetermined direction or as each quantum box. Each quantum wire has a dimension (for example, about several tens of nanometers) such that the energy level of electrons becomes discrete in two directions orthogonal to the longitudinal direction. Each quantum box has dimensions (for example, about several tens of nanometers) such that the energy levels of electrons are discrete in three directions orthogonal to each other. With such a quantum structure, the density of states increases, so that the light emission efficiency is increased and the emission spectrum is sharpened.

  As shown in FIG. 5, the n-type cladding layer 103 is made of, for example, n-type AlGaN. The undoped guide layer 104 is made of undoped GaN, for example. The p-type electron block layer 106 is made of, for example, p-type AlGaN. The p-type guide layer 107 is made of, for example, p-type GaN. The p-type cladding layer 108 is made of, for example, p-type AlGaN. The n-type cladding layer 103 and the p-type cladding layer 108 function as conductive layers through which carriers to be given to the active layer 105 are conducted. For this reason, the n-type cladding layer 103 and the p-type cladding layer 108 are provided so as to sandwich the active layer 105. The n-type cladding layer 103, the p-type electron blocking layer 106, the p-type guide layer 107, and the p-type cladding layer 108 function as confinement layers that confine carriers (electrons and holes) in the active layer 105, respectively. That is, the n-type cladding layer 103, the active layer 105, and the p-type cladding layer 108 form a double heterojunction. For this reason, carriers contributing to light emission can be concentrated in the active layer 105.

  The p-type contact layer 109 is formed to make an ohmic contact with the p-type electrode 130. The p-type contact layer 109 is made of, for example, p-type GaN.

  The dimensions of each part of the semiconductor laser 100 in Example 1 are listed below as an example. The thickness of the substrate 101 is, for example, 100 μm, the thickness of the n-type buffer layer 102 is, for example, 5 μm, and the n-type. The thickness of each of the cladding layer 103 and the p-type cladding layer 108 is 0.5 μm, for example, and the thickness of each of the undoped guide layer 104, the active layer 105, the p-type electron blocking layer 106, and the p-type guide layer 107 is For example, it is 0.1 μm, and the thickness of the p-type contact layer 109 is, for example, 0.2 μm.

  Next, a method for manufacturing the semiconductor laser 100 in Example 1 will be described. First, as shown in FIG. 5, a substrate 101 made of non-conductive sapphire is prepared. For example, the n-type buffer layer 102, the n-type cladding layer 103, the undoped guide layer 104, the active layer 105, and the p-type electrons are formed on the (0001) surface of the substrate 101 by using a MOCVD (Metal-organic chemical vapor deposition) method. The block layer 106, the p-type guide layer 107, the p-type cladding layer 108, and the p-type contact layer 109 are epitaxially grown on the substrate 101 in this order.

  Next, it was taken out from the film forming apparatus (for example, an epitaxial growth furnace), and sidewalls were formed on the GaN epitaxial growth layer 110. As a method of forming this side wall, the above-described mask layer forming step (S30), exposing step (S40), developing step (S50), dry etching step (S60), and wet etching step. (S20) was performed.

  Specifically, in the step of forming the mask layer (S30), the pair of side walls 110a facing each other of the GaN epitaxial growth layer 110 are parallel to the m-plane and set in a direction perpendicular to the pair of side walls 110a. A stripe-pattern mask layer was formed so as to be parallel to the a-plane. Next, an exposure step (S40) and a development step (S50) were performed.

  In the dry etching step (S 60), chlorine-based RIE etching was performed on the GaN epitaxial growth layer 110. The dry etching was performed until the n-type buffer layer 102 was reached, and the n-type buffer layer 102 was exposed.

  Next, a wet etching step (S20) was performed. Thermal SPM was used as an etchant. The hot SPM used was a mixture of 96% sulfuric acid and 30% hydrogen peroxide water in a ratio of 5: 1, and wet etching was performed at a temperature of 120 ° C.

  Thereafter, an insulating film (not shown) made of silicon nitride (SiN) or the like for current confinement and a p-type electrode 130 were formed on the upper surface of the p-type contact layer 109. Next, an n-type electrode 120 was formed on the exposed surface 102a of the n-type buffer layer 102, and facet (end face) coating was performed. As a result, the semiconductor laser 100 in Example 1 shown in FIG. 5 was manufactured.

  On the other hand, the semiconductor laser of Comparative Example 1 was subjected to facet coating without performing the wet etching step (S20). Thus, the semiconductor laser in Comparative Example 1 was manufactured.

  The threshold for oscillation was measured for the semiconductor laser 100 in Example 1 and the semiconductor laser in Comparative Example 1.

As a result, in the semiconductor laser 100 in Example 1, the threshold value was 2.5 kA / cm ² . On the other hand, in the semiconductor laser in Comparative Example 1, the threshold value was 3.0 kA / cm ² .

  It was found that the threshold value of the semiconductor laser 100 in Example 1 was lower than the threshold value of the semiconductor laser in Comparative Example 1. Thereby, the semiconductor laser 100 in Example 1 which performed the wet etching process (S20) was able to improve the reflection characteristic of the side wall 110a having the m-side wall as a side wall, and to improve the laser characteristic.

  In addition, although the semiconductor laser 100 in Example 1 is a Fabry-Perot type laser, it is not particularly limited thereto. The semiconductor laser is preferably a Fabry-Perot laser. This is because a Fabry-Perot laser can improve the characteristics of a semiconductor laser having an m-plane as a side wall.

  As described above, according to the semiconductor laser 100 in the first embodiment, the semiconductor laser 100 using the semiconductor element in the embodiment, and the end surface of the semiconductor laser 100 that emits light has a wet etching step (S20). The side wall 110a which is the m-plane of the semiconductor element smoothed by performing the above is used. That is, the surface of the side wall 110a corresponding to the m-plane is smooth. Therefore, the semiconductor laser 100 has excellent characteristics.

  FIG. 6A is a schematic perspective view showing an optical waveguide in the second embodiment of the present invention, and FIG. 6B is a top view showing the optical waveguide in the second embodiment of the present invention. With reference to FIG. 6 (A) and FIG. 6 (B), the optical waveguide in Example 2 of this invention is demonstrated.

  The optical waveguide 200 in Example 2 is an optical waveguide using a GaN epitaxial growth layer having a (0001) plane as a main surface. The optical waveguide 200 includes a substrate 210 and a GaN epitaxial growth layer that forms the optical waveguide 200 formed on the substrate 210. In the GaN epitaxial growth layer, a side wall 223a of the optical waveguide 200 is formed by an m-plane.

  In the second embodiment, the optical waveguide 200 includes an incident part 221, an emission part 222, and a waveguide part 223. One set of opposing side walls 223a of the waveguide portion 223 is the m-plane of the GaN epitaxial growth layer.

  The substrate 210 was sapphire. The GaN epitaxial growth layer was an undoped GaN epitaxial growth layer. The width W was 5 μm, the thickness T was 2 μm, and the length L was 10 mm. The planar shapes of the incident part 221 and the emission part 222 are tapered so as to become narrower in the direction of connection with the waveguide part 223.

  Next, the manufacturing method of the optical waveguide 200 in Example 2 is demonstrated. First, as shown in FIG. 6, a substrate 210 made of non-conductive sapphire is prepared. Then, for example, an undoped GaN layer was epitaxially grown on the (0001) surface of the substrate 210 by using the MOCVD method.

  Next, the substrate 210 on which the undoped GaN epitaxial growth layer is formed is once taken out from the film forming apparatus (for example, an epitaxial growth furnace), and the optical waveguide 220 including the incident portion 221, the emission portion 222, and the waveguide portion 223 in the GaN epitaxial growth layer. Formed. The optical waveguide 220 can be formed by the above-described mask layer forming step (S30), exposing step (S40), developing step (S50), dry etching step (S60), and wet. An etching step (S20) was performed.

  Specifically, in the step of forming the mask layer (S30), the pair of opposing side walls 223a of the waveguide portion 223 (see FIG. 6A) formed by the GaN epitaxial growth layer is made parallel to the m-plane. A mask layer having an appropriate pattern was formed. Next, an exposure step (S40) and a development step (S50) were performed.

  In the dry etching step (S60), an ICP-RIE method using an HI etching gas was performed on the GaN epitaxial growth layer so that the shape of the optical waveguide 200 appeared. Dry etching was performed until the substrate 210 was reached to expose the substrate 210.

  Next, a wet etching step (S20) was performed. Semicoclean (Furuuchi Chemical Co., Ltd.) was used as an etching solution. In the wet etching step (S20), cleaning was performed at an etching solution temperature of 30 degrees or less for 10 minutes or more.

  Thereby, the optical waveguide 200 in Example 2 in which the side wall 223a of the waveguide portion 223 formed in the GaN epitaxial growth layer is an m-plane could be manufactured.

  On the other hand, the optical waveguide in Comparative Example 2 was not subjected to the wet etching step (S20). Thereby, the optical waveguide in the comparative example 2 was manufactured.

  And green light was introduce | transduced with respect to the optical waveguide 200 in Example 2, and the comparative example 2, and the attenuation factor was measured.

  As a result, in the optical waveguide 200 in Example 2, the attenuation factor was 8%. On the other hand, in the optical waveguide in Comparative Example 2, the attenuation factor was 12%.

  It was found that the attenuation factor of the optical waveguide 200 in Example 2 was lower than the attenuation factor of the optical waveguide in Comparative Example 2. Thereby, the optical waveguide 200 in Example 2 which performed the wet etching process (S20) can suppress the scattering in the side wall 223a of the waveguide part 223, and was able to aim at the performance improvement.

  As described above, according to the optical waveguide 200 of the second embodiment, the optical waveguide uses the GaN epitaxial growth layer having the (0001) plane as the main surface, and the GaN epitaxial growth layer having the (0001) plane as the main surface. And a side wall 223a of the optical waveguide formed in the GaN epitaxial growth layer manufactured by the wet etching step (S30) in which the m-plane perpendicular to the (0001) plane is a reaction-controlled surface. Is the m-plane. Therefore, the surface of the side wall 223a of the optical waveguide 200 becomes smooth. Therefore, the optical waveguide 200 has excellent characteristics.

  FIG. 7A is a top view showing a surface light emitting device in Example 3 of the present invention, and FIG. 7B is a side view showing the surface light emitting device in Example 3 of the present invention. With reference to FIG. 7 (A) and FIG. 7 (B), the surface emitting element in Example 3 of this invention is demonstrated. The surface light emitting element in Example 3 is a vertical cavity surface emitting laser (VCSEL) 300.

  As shown in FIGS. 7A and 7B, the surface emitting laser 300 includes a substrate 301, an n-type buffer layer 302, an n-type DBR mirror layer 303, an n-type cladding layer 304, and an undoped guide. Layer 305, active layer 306, p-type electron blocking layer 307, p-type guide layer 308, p-type cladding layer 309, p-type DBR mirror layer 310, p-type contact layer 311, and n-type electrode 330. And a p-type electrode 340.

  On the substrate 301, an n-type buffer layer 302, an n-type DBR mirror layer 303, an n-type cladding layer 304, an undoped guide layer 305, and a p-type electron blocking layer 307 are formed to be laminated. An active layer 306 is sandwiched between the undoped guide layer 305 and the p-type electron blocking layer 307. n-type buffer layer 302, n-type DBR mirror layer 303, n-type cladding layer 304, undoped guide layer 305, active layer 306, p-type electron blocking layer 307, p-type guide layer 308, p-type cladding layer 309, p-type DBR The layer composed of the mirror layer 310 and the p-type contact layer 311 is a GaN epitaxial growth layer whose main surface is the (0001) plane of the substrate 301. Among the epitaxial growth layers, the n-type cladding layer 304, the undoped guide layer 305, the active layer 306, the p-type electron block layer 307, the p-type guide layer 308, the p-type cladding layer 309, the p-type DBR mirror layer 310, and the p-type contact layer The epitaxial growth layer 320 made of 311 has a hexagonal column shape with m-side walls.

  More specifically, the structure of the surface emitting laser 300 shown in FIG. 7 is described. On the substrate 301, an n-type buffer layer 302, an n-type DBR mirror layer 303, an n-type cladding layer 304, and an undoped guide layer 305 are provided. The active layer 306, the p-type electron blocking layer 307, the p-type guide layer 308, the p-type cladding layer 309, the p-type DBR mirror layer 310, and the p-type contact layer 311 are laminated in this order.

  In Example 3, the n-type electrode 330 is formed on the back surface of the substrate 301. The p-type electrode 340 has an annular planar shape, is formed on the p-type contact layer 311, and a part of the surface 311 a of the p-type contact layer 311 is exposed on the inner peripheral side of the p-type electrode 340. is doing. The n-type electrode 340 has a circular hollow shape as a planar shape and a circular outer shape. The n-type electrode 330 and the p-type electrode 340 are made of, for example, Au (gold).

The substrate 301 is made of, for example, n-type GaN. The n-type buffer layer 302 is made of, for example, n-type GaN. The n-type DBR mirror layer 303 is formed of, for example, a multilayer film in which a plurality of layers made of n-type AlGaN and n-type GaN are stacked. The n-type cladding layer 304 is made of, for example, n-type AlGaN. The undoped guide layer 305 is made of, for example, undoped GaN. The active layer 306 includes, for example, an Al _x Ga _1-x N layer and an Al _x In _y Ga _1-xy N layer. The p-type electron block layer 307 is made of p-type AlGaN, for example. The p-type guide layer 308 is made of, for example, p-type GaN. The p-type cladding layer 309 is made of, for example, p-type AlGaN. The p-type DBR mirror layer 310 is made of a multilayer film in which a plurality of layers made of p-type AlGaN and n-type GaN are stacked, for example. The p-type contact layer 311 is made of, for example, p-type GaN.

  The substrate 301, the n-type buffer layer 302, the n-type cladding layer 304, the undoped guide layer 305, the active layer 306, the p-type electron block layer 307, the p-type guide layer 308, the p-type cladding layer 309, and the p-type contact layer 311 Since it is the same as that of Example 1, the description is not repeated. However, the wavelength of the active layer 306 was 410 nm.

  The n-type DBR mirror layer 303 and the p-type DBR mirror layer 310 are a distributed reflection type (Distributed Bragg Reflector: DBR). In addition, the n-type DBR mirror layer 303 and the p-type DBR mirror layer 310 were designed to have a reflectance of 98% for light having a wavelength of 410 nm.

  The dimensions of each part of the surface-emitting laser 300 in Example 3 are listed below as an example. The thickness of the substrate 301 is, for example, 100 μm, the thickness of the n-type buffer layer 302 is, for example, 1 μm, and n The thickness of the type DBR mirror layer 303 is, for example, 3 μm, and the thickness of each of the n-type cladding layer 304 and the p-type cladding layer 309 is, for example, 0.5 μm. The undoped guide layer 305, the active layer 306, and the p-type electrons Each of the block layer 307 and the p-type guide layer 308 has a thickness of 0.1 μm, for example, and the p-type contact layer 311 has a thickness of 0.2 μm, for example. In addition, the planar shape of the epitaxial growth layer 320 is a hexagon, and the diameter of the hexagon that is the longest distance connecting the apexes is, for example, 100 μm.

  Next, the manufacturing method of the surface emitting laser 300 in Example 3 is demonstrated. First, as shown in FIG. 7, a substrate 301 made of conductive GaN is prepared. Then, for example, a GaN epitaxial growth layer was formed on the (0001) plane of the substrate 301 by using the MOCVD method.

  Next, the GaN substrate 301 on which the GaN epitaxial growth layer was formed was taken out from a film forming apparatus (for example, an epitaxial growth furnace), and sidewalls were formed in the epitaxial growth layer 320 of the GaN epitaxial growth layer. As a method of forming this side wall, the above-described mask layer forming step (S30), exposing step (S40), developing step (S50), dry etching step (S60), and wet etching step. (S20) was performed.

  Specifically, in the step of forming a mask layer (S30), a mask layer having a hexagonal planar shape is formed so that the side wall of the epitaxial growth layer 320 of the GaN epitaxial growth layer is parallel to the m-plane. Next, an exposure step (S40) and a development step (S50) were performed.

  In the dry etching step (S60), an ICP-RIE method using a chlorine-based etching gas was performed so that a hexagonal column shape appeared in the epitaxial growth layer 320 of the GaN epitaxial growth layer. Dry etching was performed until the n-type DBR mirror layer 303 was reached, and the n-type DBR mirror layer 303 was exposed.

  Next, a wet etching step (S20) was performed. Semicoclean (Furuuchi Chemical Co., Ltd.) was used as an etching solution. In the wet etching step (S20), cleaning was performed at an etching solution temperature of 30 degrees or less for 10 minutes or more.

  Finally, an n-type electrode 330 and a p-type electrode 340 were formed. Thereby, the surface emitting laser 300 in Example 3 in which the side wall of the epitaxial growth layer 320 of the GaN epitaxial growth layers has an m-plane could be manufactured.

  On the other hand, the surface emitting laser in Comparative Example 3 did not perform the wet etching step (S20). Thereby, the surface emitting laser in Comparative Example 3 was manufactured.

  For the surface emitting laser 300 of Example 3 and the surface emitting laser of Comparative Example 3, the threshold for oscillation was measured in the same manner as in Example 1.

As a result, in the surface emitting laser 300 in Example 3, the threshold value was 6.0 kA / cm ² . On the other hand, in the surface emitting laser in Comparative Example 3, the threshold value was 7.5 kA / cm ² .

  In the third embodiment, the surface emitting laser 300 is described as an example of the surface emitting element, but the present invention is not particularly limited thereto. Examples of the surface light emitting element include an LED (Light Emitting Diode).

  It was found that the threshold value of the surface emitting laser 300 in Example 3 was lower than the threshold value of the surface emitting laser of Comparative Example 3. From this, it was found that by performing the wet etching step (S20), the RIE plasma damage layer was removed on the sidewall of the epitaxial growth layer 320, the surface recombination rate of the carriers was reduced, and non-radiative recombination was reduced. . Therefore, it was found that the surface emitting laser 300 in Example 3 in which the wet etching step (S20) was performed was able to improve the reflection characteristics of the side walls of the epitaxial growth layer 320 and improve the laser characteristics.

  As described above, according to the surface-emitting laser 300 that is an example of the surface-emitting element in Example 3, the surface-emitting element using the semiconductor element in the embodiment, the sidewall of the surface-emitting laser is a semiconductor element The side walls. Since the wet etching step (S20) in which the side wall is an m-plane and the m-plane is a reaction-controlled surface is performed, the surface of the side wall becomes smooth. Therefore, the surface emitting laser 300 can be a high-performance element.

  As Example 4 of the present invention, the structure of the semiconductor element was confirmed. Specifically, the semiconductor element in Example 4 is the semiconductor element 30 shown in FIG. Using this semiconductor element 30, in the wet etching step (S30), it was confirmed by experiments that the m-plane reacted as a rate-determining plane.

  FIG. 8 is a schematic diagram showing a semiconductor element before removing the mask layer in Example 4 of the present invention. With reference to FIG. 8, the semiconductor element in Example 4 is demonstrated. The semiconductor element 30 according to the fourth embodiment is basically the same as the semiconductor element 10 shown in FIG. 1 in the stacked structure of the GaN epitaxial growth layer, but differs in the shape of the GaN epitaxial growth layer.

  Specifically, the semiconductor element 30 includes a substrate 31 and a GaN epitaxial growth layer 32 as shown in FIG. The planar shape of the GaN epitaxial growth layer 32 is two squares, and the GaN epitaxial growth layer 32 is two cubes. The GaN epitaxial growth layer 32 extends upward perpendicularly to the (0001) plane (c-plane). Further, the side wall 32 a is composed of the m-plane of the GaN epitaxial growth layer 32, and the side wall 32 b is composed of the a-plane of the GaN epitaxial growth layer 32.

  The substrate 31 is a sapphire substrate. The (1-100) plane of the GaN epitaxial growth layer on the sapphire substrate and the (1-100) plane of the sapphire substrate have the (0001) axis as the axis of rotation that is perpendicular to the c plane of the sapphire substrate and the GaN epitaxial growth layer. , 30 ° is known to shift.

  Next, a method for manufacturing the semiconductor element 30 in Example 4 will be described. The manufacturing method of the semiconductor element 30 in Example 4 is basically the same as the manufacturing method of the semiconductor element 10 in the embodiment, but in the exposure step (S40) and the dry etching step (S60). Different.

  Specifically, in the exposure step (S40), the resist mask pattern formed by ultraviolet exposure is a stripe pattern. Thus, in the developing step (S50), the mask layer 33 having a two-sided planar shape was formed from the shape of the resist mask pattern.

  In the dry etching step (S60), the GaN epitaxial growth layer 32 was etched in a portion not covered with the mask layer 33 to form the outer shape (two squares) of the GaN epitaxial growth layer 32. In Example 4, in this step (S60), chlorine-based RIE was performed.

  Thereafter, a wet etching step (S20) was performed. In Example 4, wet etching was performed on the two rectangular side walls 32a and 32b by thermal SPM.

  Since other processes are the same as those of semiconductor element 10 in the embodiment of the present invention, description thereof will not be repeated.

  Next, the semiconductor element 30 in Example 4 will be described with reference to FIGS. FIG. 9 is an overhead view by an SEM (electron microscope) showing the side wall after the dry etching step (S60) of the semiconductor element 30 in the fourth embodiment of the present invention. FIG. 10 is an overhead view by an SEM (electron microscope) showing the m-side and a-side sidewalls after the wet etching step (S20) of the semiconductor element 30 according to the fourth embodiment of the present invention.

  When the dry etching step (S60) is performed, it can be seen that the side wall 32a becomes a rough surface as shown in FIG. Note that it is considered that the m-plane does not completely appear on the side wall 32a.

  Next, when the wet etching step (S20) was performed, as shown in FIG. 10, the side wall 32a having the m-plane as a side wall became a smooth surface.

  Therefore, by performing the wet etching step (S20), the rough portion of the side wall 32a is removed by wet etching until the m-plane appears, and the m-plane is exposed, so that the side wall 32a becomes smooth. all right. Further, since the etching did not proceed after the m-plane was exposed, it was found that the m-plane reacted as a rate-limiting surface.

  Further, by using the thermal SPM in the wet etching step (S20), the mask layer 33 can be removed if the wet etching is performed under a certain condition (for example, a condition in which the wet etching is performed even after the m-plane appears on the side wall 32a). At the same time, the etching did not react in the direction perpendicular to the c-plane constituting the semiconductor element 30. Therefore, it has been found that by using the thermal SPM in the wet etching step (S20), the step of removing the mask layer 33 becomes unnecessary, and thus the step of manufacturing the semiconductor element 30 can be simplified.

  On the other hand, when the wet etching process (S20) is performed on the side wall 32b having the side a as a side wall, as shown in FIG. 10, only the facet appears on the surface, and the surface remains rough. Also from this, it was found that the wet etching step (S20) reacted with the m-plane as the rate-limiting surface.

  In Example 4, although the thermal SPM was used in the wet etching step (S20), it was found that, for example, an organic alkaline cleaning liquid has the same effect as an etching liquid having the same effect as the thermal SPM. Moreover, as an example of the organic alkali cleaning solution, it was also found that Semico Clean (manufactured by Furuuchi Chemical Co., Ltd.) has a similar effect at room temperature.

  As for the semiconductor element 30 in Example 4, the a-plane of the GaN epitaxial growth layer on the side wall 32b and the (1-100) plane that is the cleavage plane of sapphire as the substrate are parallel to each other. It is easy to separate in a direction parallel to 32b, and it becomes possible to make a rectangular parallelepiped element having the side wall 32b as a longitudinal direction. This is advantageous when forming a long cavity Fabry-Perot laser element.

  As described above, according to the semiconductor device 30 of the fourth embodiment, when the wet etching step (S20) is performed on the GaN epitaxial growth layer formed on the substrate 31, the side wall 32a that is the side wall on which the m-plane appears is smooth. The side wall 32b, which is the side wall where the a-plane appeared, was a rough surface. That is, it can be seen that in the wet etching step (S20), the m-plane of the GaN epitaxial growth layer becomes the reaction rate-determining plane.

  In the wet etching step (S20), since the m-plane of the GaN epitaxial growth layer becomes a reaction-controlled surface, a smooth surface can be easily formed by forming a side wall along the hexagonal m-plane.

  It should be understood that the embodiments and examples disclosed herein are illustrative and non-restrictive in every respect. The scope of the present invention is shown not by the embodiments and examples described above but by the scope of claims for patent, and is intended to include all modifications within the meaning and scope equivalent to the scope of claims for patent.

1 is a schematic perspective view of a semiconductor element in an embodiment of the present invention. It is a flowchart which shows the manufacturing method of the semiconductor element in embodiment of this invention. It is a flowchart which shows the manufacturing method of the semiconductor element in embodiment of this invention in detail. It is a schematic perspective view which shows the semiconductor element in the modification of embodiment of this invention. It is a schematic perspective view which shows the semiconductor laser in Example 1 of this invention. (A) is a schematic perspective view which shows the optical waveguide in Example 2 of this invention, (B) is a top view which shows the optical waveguide in Example 2 of this invention. (A) is a top view which shows the surface emitting element in Example 3 of this invention, (B) is a side view which shows the surface emitting element in Example 3 of this invention. It is a schematic diagram which shows the semiconductor element before removing the mask layer in Example 4 of this invention. It is an overhead view by SEM (electron microscope) which shows the side wall after the dry etching process of the semiconductor element in Example 4 of this invention. It is a bird's-eye view by SEM (electron microscope) which shows the side wall of m surface after the wet etching process of the semiconductor element in Example 4 of this invention, and the side wall of a surface.

Explanation of symbols

  10, 20, 30 semiconductor device, 11, 21, 31, 101, 210, 301 substrate, 11a surface, 12, 22, 32, 110, 320 epitaxial growth layer, 12a, 22a, 22b, 32a, 32b, 110a, 110b, 223a side wall, 13, 14, 120, 130, 330, 340 electrode, 33 mask layer, 100 semiconductor laser, 102, 302 n-type buffer layer, 102a, 311a surface, 103, 304 n-type cladding layer, 104, 305 undoped guide Layer, 105,306 active layer, 106,307 p-type electron blocking layer, 107,308 p-type guide layer, 108,309 p-type cladding layer, 109,311 p-type contact layer, 200 optical waveguide, 221 incident portion, 222 Emitting part, 223 waveguide part, 300 surface light emitting layer The, 303 n-type DBR mirror layer, 310 p-type mirror layer, W width, T the thickness, L the length.

Claims (11)

A method of manufacturing a semiconductor device using a GaN epitaxial growth layer having a (0001) plane as a main surface,
Preparing a GaN epitaxial growth layer having a (0001) plane as a main surface;
And a wet etching step of performing wet etching in which an m-plane that is perpendicular to the (0001) plane is a reaction-controlled surface.   The method for manufacturing a semiconductor device according to claim 1, further comprising a plasma etching step using a gas containing at least one of chlorine, iodine, and fluorine, which is performed prior to the wet etching step.   3. The method of manufacturing a semiconductor device according to claim 1, wherein in the wet etching step, a thermal SPM (sulfuric acid hydrogen peroxide mixture) or an organic alkaline cleaning solution is used as an etching solution. 4.   The method of manufacturing a semiconductor element according to claim 3, wherein wet etching is performed at a temperature of the thermal SPM of 90 ° C. to 130 ° C. A semiconductor device using a GaN epitaxial growth layer having a (0001) plane as a main surface,
Preparing a GaN epitaxial growth layer having a (0001) plane as a main surface;
Manufactured by a wet etching step of performing wet etching in which an m-plane perpendicular to the (0001) plane is a reaction-controlled surface,
A semiconductor element, wherein a side wall formed in the GaN epitaxial growth layer is the m-plane. A semiconductor device using a GaN epitaxial growth layer having a (0001) plane as a main surface,
A substrate,
A GaN epitaxial growth layer formed on the substrate,
In the GaN epitaxial growth layer, a side wall is formed by an m-plane.   The semiconductor device according to claim 5, wherein the side wall is formed so as to surround the GaN epitaxial growth layer, and the planar shape of the GaN epitaxial growth layer is a hexagon.   The semiconductor element according to claim 5, wherein RMS of the surface of the side wall is 0.1 nm or more and 10 nm or less. A semiconductor laser using the semiconductor device according to any one of claims 5 to 8,
The semiconductor laser according to claim 1, wherein an end face of the semiconductor laser that emits light serves as the side wall of the semiconductor element. A surface light emitting device using the semiconductor device according to any one of claims 5 to 8,
A surface light emitting element, wherein a side wall of the surface light emitting element is the side wall of the semiconductor element. An optical waveguide using a GaN epitaxial growth layer having a (0001) plane as a main surface,
Preparing a GaN epitaxial growth layer having a (0001) plane as a main surface;
Manufactured by a wet etching step of performing wet etching in which an m-plane perpendicular to the (0001) plane is a reaction-controlled surface,
An optical waveguide, wherein a side wall of the optical waveguide formed in the GaN epitaxial growth layer is the m-plane.