DE102018107483A1 - Optoelectronic component with a variety of steps and method for producing the optoelectronic component - Google Patents

Optoelectronic component with a variety of steps and method for producing the optoelectronic component

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Publication number
DE102018107483A1
DE102018107483A1 DE102018107483.2A DE102018107483A DE102018107483A1 DE 102018107483 A1 DE102018107483 A1 DE 102018107483A1 DE 102018107483 A DE102018107483 A DE 102018107483A DE 102018107483 A1 DE102018107483 A1 DE 102018107483A1
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Germany
Prior art keywords
layer
light
doped
substrate
semiconductor
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DE102018107483.2A
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German (de)
Inventor
Adrian Avramescu
Hans-Jürgen Lugauer
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Osram Opto Semiconductors GmbH
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Osram Opto Semiconductors GmbH
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Priority to DE102018107483.2A priority Critical patent/DE102018107483A1/en
Publication of DE102018107483A1 publication Critical patent/DE102018107483A1/en
Application status is Pending legal-status Critical

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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L33/00Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005Processes
    • H01L33/0095Post-treatments of the devices, e.g. annealing, recrystallisation, short-circuit elimination
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier specially adapted for light emission
    • H01L27/153Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier specially adapted for light emission in a repetitive configuration, e.g. LED bars
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L33/00Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/025Physical imperfections, e.g. particular concentration or distribution of impurities
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L33/00Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/04Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction

Abstract

An optoelectronic component (10, 20) comprises a substrate (100) and a semiconductor layer structure (129) arranged on the substrate (100). The semiconductor layer structure (129) has a p-doped layer (124, 125, 156, 157, 192, 203, 204), a first light-active layer (123, 158) and an n-doped layer (121, 122, 154 , 155, 189), wherein the n-doped layer (121, 122, 154, 155, 189) is arranged at a greater distance from a main surface (110) of the substrate (100) than the p-doped layer. The semiconductor layer structure (129) is structured to form a plurality of webs (130) whose lateral dimension is smaller than a lateral dimension of the substrate (100).

Description

  • BACKGROUND
  • Light-emitting diodes (LEDs) based on gallium nitride or gallium nitride-containing compound semiconductor materials are widely used in a variety of applications including display devices, lighting devices, automotive lighting, projectors and others. Much efforts are being made to improve the properties of light emitting diodes.
  • The present invention has for its object to provide an improved optoelectronic device and a method for its production.
  • According to the present invention, the object is achieved by the subject matter or the method of the independent patent claims. Advantageous developments can be found in the dependent claims.
  • SUMMARY
  • An optoelectronic component comprises a substrate and a semiconductor layer structure arranged on the substrate. The semiconductor layer structure or the semiconductor layer stack has a p-doped layer, a first luminescent active layer and an n-doped layer, wherein the n-doped layer is arranged at a greater distance from a main surface of the substrate than the p-type layer. doped layer. The semiconductor layer structure is structured into a multiplicity of webs whose lateral dimension is smaller than a lateral dimension of the substrate in each case.
  • For example, the lateral dimension of the webs may be less than 15 microns. The p-doped layer may contain GaN. It may be composed of GaN or contain a ternary or quaternary compound semiconductor containing GaN.
  • According to embodiments, a side surface of a ridge is parallel to a crystallographic a-axis of a layer of the semiconductor layer structure.
  • According to embodiments, the light-active layer is arranged on a crystallographic c-plane of a layer of the semiconductor layer structure.
  • For example, in the optoelectronic component, the uppermost layer of the semiconductor layer structure may be an n-doped layer. The semiconductor layer structure may further include a first tunnel junction or tunnel junction between the first light active layer and the substrate. The semiconductor layer structure may further comprise a second luminescent active layer. By way of example, the first tunneling contact can be arranged between the first and second luminous active layer.
  • According to embodiments, the p-doped layer may be disposed between the first and second luminescent active layers. The optoelectronic component may further include a p-contact region adjacent to the p-doped layer and electrically connected to the p-doped layer.
  • The semiconductor layer structure may further comprise a second light-active layer and a second tunnel junction. The first tunnel junction may be disposed between the first light-active layer and the substrate, and the second tunnel junction may be disposed between the first and second light-active layers. The webs may differ from one another with respect to their lateral or horizontal dimensions.
  • According to further embodiments, an optoelectronic component comprises a substrate and a semiconductor layer structure arranged on the substrate, which is structured to form a plurality of webs whose lateral dimension is in each case smaller than a lateral dimension of the substrate. The plurality of webs has a first web, a second web and a third web. In the first land, a first luminous active layer capable of emitting light of a first wavelength is arranged. In the second land is disposed a second light-active layer capable of emitting light of a second wavelength, and in the third land is disposed a third light-active layer capable of emitting light of a third wavelength.
  • The optoelectronic component may have a first contact structure and a second contact structure. The first contact structure is suitable for driving the first light-active layer, and the second contact structure is suitable for driving the second light-active layer.
  • A method for producing an optoelectronic component comprises forming a plurality of webs from a semiconductor layer structure on a substrate. The semiconductor layer structure has a p-doped layer, a first luminescent active layer and an n-doped layer, wherein the n-doped layer is arranged at a greater distance from a main surface of the growth substrate than the p-doped layer. A lateral dimension of the webs is in each case smaller than a lateral dimension of the substrate. The The method may further comprise a heat treatment for the outdiffusion of hydrogen.
  • For example, forming the lands may include growing the semiconductor layer structure on a masked substrate. Alternatively, forming the lands may include growing the semiconductor layer structure and then etching the lands.
  • According to further embodiments, the method may include forming the ridges, growing a first sub-structure, subsequently etching, and then growing a second sub-structure on a masked workpiece.
  • list of figures
  • The accompanying drawings serve to understand embodiments of the invention. The drawings illustrate embodiments and together with the description serve to explain them. Further exemplary embodiments and numerous of the intended advantages emerge directly from the following detailed description. The elements and structures shown in the drawings are not necessarily to scale. Like reference numerals refer to like or corresponding elements and structures.
    • 1A is a perspective view of an optoelectronic device according to embodiments.
    • 1B to 1E are plan views of examples of optoelectronic devices.
    • 2A to 2F illustrate steps for fabricating an optoelectronic device according to one or more embodiments.
    • 3 1 illustrates a semiconductor layer structure for producing an optoelectronic component according to further embodiments.
    • 4A shows a schematic cross-sectional view of an optoelectronic device according to one or more embodiments.
    • 4B shows a schematic cross-sectional view through part of an optoelectronic component according to embodiments and an equivalent circuit diagram.
    • 4C illustrates a band structure of parts of the optoelectronic device.
    • 5A and 5B illustrate steps of a method of manufacturing another optoelectronic device.
    • 6A to 6C illustrate method steps for producing an optoelectronic component according to further embodiments.
    • 7A shows a schematic cross-sectional view through part of an optoelectronic component according to embodiments and an equivalent circuit diagram.
    • 7B shows a schematic cross-sectional view through part of an optoelectronic component according to embodiments and an equivalent circuit diagram.
    • 8th shows a schematic cross-sectional view through part of an optoelectronic component according to embodiments and an equivalent circuit diagram.
    • 9A shows a schematic cross-sectional view through part of an optoelectronic component according to embodiments and an equivalent circuit diagram.
    • 9B shows a cross-sectional view through a portion of an optoelectronic device according to embodiments and an equivalent circuit diagram.
    • 10A to 10C schematically illustrate a method for producing an optoelectronic component according to further embodiments.
    • 11A shows a cross-sectional view of an example of an optoelectronic device, by the in the 10A to 10C illustrated method can be produced.
    • 11B shows an equivalent circuit diagram for the in 11A shown optoelectronic component.
    • 12A to 12C illustrate a method of manufacturing an optoelectronic device according to embodiments.
    • 13A to 13E illustrate a method of manufacturing an optoelectronic device according to embodiments.
    • 14 summarizes a method according to embodiments.
  • LONG DESCRIPTION
  • In the following detailed description, reference is made to the accompanying drawings, which form a part of the disclosure, and in which is shown by way of illustration specific embodiments. In this A directional terminology such as "top", "bottom", "front", "back", "over", "up", "forward", "behind", "front", "back", etc. is related to the orientation of the just described figures related. Since the components of the embodiments may be positioned in different orientations, the directional terminology is illustrative only and is in no way limiting.
  • The description of the embodiments is not limiting, as other embodiments exist and structural or logical changes can be made without departing from the scope defined by the claims. In particular, elements of embodiments described below may be combined with elements of other of the described embodiments, unless the context dictates otherwise.
  • The terms "wafer" or "semiconductor substrate" used in the following description may include any semiconductor-based structure having a semiconductor surface. Wafers and structure are understood to include doped and undoped semiconductors, epitaxial semiconductor layers, optionally supported by a base pad, and other semiconductor structures. For example, a layer of a first semiconductor material may be grown on a growth substrate of a second semiconductor material or of an insulating material, for example sapphire. Depending on the intended use, the semiconductor can be based on a direct or an indirect semiconductor material. Examples of semiconductor materials which are particularly suitable for generating electromagnetic radiation include, in particular, nitride semiconductor compounds, by means of which, for example, ultraviolet, blue or longer wavelength light can be generated, for example GaN, InGaN, AlN, AlGaN, AlGaInN, phosphide semiconductor compounds, for example green or long-waved light Light can be generated, such as GaAsP, AlGaInP, GaP, Al-GaP, and other semiconductor materials such as AlGaAs, SiC, ZnSe, GaAs, ZnO, Ga 2 O 3 , diamond, hexagonal BN and combinations of the materials mentioned. The stoichiometric ratio of the ternary compounds may vary. Other examples of semiconductor materials may include silicon, silicon germanium and germanium. In the context of the present description, the term "semiconductor" also includes organic semiconductor materials.
  • The description illustrates relative dopant concentrations by indicating "+" or " ++ "Next to the doping type" n "Or" p ". For example, "p" denotes a lower dopant concentration " p + "Doped area, and" p ++ "Denotes a higher dopant concentration than a" p + "Doped area. Doped regions of the same relative dopant concentration need not necessarily have the same absolute dopant concentration. For example, two "n" doped regions may have the same or a different absolute dopant concentration, respectively.
  • In the context of the present description, a n ++ doped region is a material with a very high relative concentration of free electrons. For example, the concentration of free electrons may be greater than 10E19 / cm 3 . One p ++ doped material refers to a semiconductor material with a very high relative concentration of free holes. For example, the concentration of free holes may be greater than 10E18 / cm 3 .
  • The terms "lateral" and "horizontal" as used in this specification are intended to describe an orientation or orientation that is substantially parallel to a first surface of a semiconductor substrate or semiconductor body. This may be, for example, the surface of a wafer or a die or a chip.
  • The term "vertical" as used in this specification is intended to describe an orientation that is substantially perpendicular to the first surface of the semiconductor substrate or semiconductor body.
  • As used herein, the terms "having," "containing," "comprising," "having," and the like, are open-ended terms that indicate the presence of said elements or features, but the presence of other elements or features do not exclude. The indefinite articles and the definite articles include both the plural and the singular, unless the context clearly dictates otherwise.
  • In the context of this description, the term "electrically connected" means a low-resistance electrical connection between the connected elements. The electrically connected elements need not necessarily be connected directly to each other. Further elements may be arranged between electrically connected elements. The term "electrically connected" also includes tunneling contacts between the connected elements.
  • 1A shows a schematic perspective view of an optoelectronic component according to one or more embodiments. The optoelectronic component 10 includes a substrate 100 as well as one on the substrate 100 arranged semiconductor layer structure 129 , The substrate 100 for example, a Growth substrate, for example, be sapphire. It is possible, however, that the substrate 100 is a substrate other than a growth substrate, for example, a semiconductor material or an insulating material. The substrate 100 has a lateral dimension b. The lateral dimension b is, for example, along the x-direction as in 1A shown measured. The on a first main surface 110 of the substrate arranged semiconductor layer structure 129 includes variously doped semiconductor materials. For example, the semiconductor layer structure may include layers of nitride semiconductor compounds. Respective examples of nitride semiconductor compounds are given above.
  • According to embodiments, the nitride semiconductor material used may be GaN, In x Ga 1-x N (0 <x <1), Al x Ga 1 -x N (0 <x <1) or In x Al y Ga 1-xy N ( FIG . 0 <x, y <1) (hereinafter referred to as "GaN-based"). The semiconductor layer structure has a p-doped layer 124 . 125 and an n-doped layer 121 . 122 on. The n-doped layer 121 . 122 is at a greater distance to a major surface 110 of the substrate is arranged as the p-doped layer 124 . 125 , The semiconductor layer structure 129 also has a light active layer 123 on that between the n-doped layer 121 . 122 and the p-doped layer 124 . 125 is arranged. The semiconductor layer structure 129 is to a variety of jetties 130 structured. A lateral dimension d each of the lands is smaller than the lateral dimension b of the substrate. As in 1A Illustrated are the p-doped layers 124 . 125 each buried in the layer structure. For example, the uppermost layer may be an n-doped layer. At least one of the p-doped layers may be GaN-based. Examples of composition and function of the layers 126 . 127 are described below inter alia with reference to 2C described.
  • A width d of the webs is for example 50 nm to about 15 microns or 100 nm to 10 microns. The width d of a land does not necessarily have to be uniform, but may vary. For example, the width of the lands may vary within a range of ± 50nm to ± 500nm. The webs may, for example, form a regular pattern and be formed at a constant pitch p. For example, a grid width, which results in each case from the width d of the webs and the distance s between adjacent webs, can be between 75 nm and 15 μm. For example, the grid width p 250 nm to 15 microns. According to further embodiments, the width d or the distance s between adjacent webs may vary for different webs. The distance s between adjacent lands may be 50 nm to 500 nm.
  • The 1B to 1D show top views of examples of optoelectronic devices. As in 1B 1, a structuring of the semiconductor layer structure can take place not only along the x-direction but also along the y-direction. For example, the semiconductor layer structure can be structured into blocks of different sizes. A lateral dimension in the y-direction is denoted by f. For example, can f be as large as a dimension a of the substrate 100 in the y direction. The dimension f but can also be smaller than a. For example, can f be as large as the lateral dimension d in the x-direction. According to further embodiments f also be a multiple of d. The dimension a may be the same or different from the dimension b. For example, the dimensions a and b each greater than 1 micron and less than 10 mm. For example, a typical chip size is in a range of 2 to 6 mm, for example 4 mm.
  • 1C shows an example of a plan view in which the webs are formed with variable lateral dimension d. For example, the webs 130 be formed with a wave-shaped cross-section. In a similar way, the distance s between adjacent webs 130 vary. As in 1C is shown, the shape of different webs of an optoelectronic device may be different.
  • According to further embodiments, as in 1D is shown, a dielectric material 135 between adjacent bridges 130 be arranged. The dielectric material 135 Of course, also in the in the 1B and 1C illustrated embodiment of the webs 130 be provided. As a result, the emission characteristic can be changed. For example, a dielectric material 135 with a refractive index lower than 2.2 inserted between the bars. As a result, the light extraction can be improved without patterning the substrate accordingly. Examples of a suitable dielectric material include silicon dioxide, silicon nitride and aluminum oxide.
  • According to further embodiments, as in 1E illustrates the bridge width d1 . d2 . d3 the webs of an optoelectronic component vary and, for example, each be different from each other. Furthermore, the grid width of the individual webs of an optoelectronic component can also vary. For example, the web width may be constant or variable, and the distance s between the individual webs may be variable, or even constant. According to further embodiments, each web width and grid width can be selected at random.
  • The width of the webs or the distance between adjacent webs can vary both in the horizontal direction and in the vertical direction. As a result, the emission characteristic of the optoelectronic component can be changed.
  • The fact that the semiconductor layer structure is structured into webs promotes lateral outdiffusion of hydrogen. As a consequence, for example, hydrogen can laterally diffuse out of the p-doped semiconductor layers. As a result, p-type impurities in the p-type semiconductor layer can be activated even when the p-type semiconductor layer is buried and is not present on the surface of the semiconductor layered structure. For example, the buried p-type semiconductor layers are GaN-based and doped with magnesium. Due to the energy difference between acceptor energy level of magnesium in gallium nitride and valence band, only a small percentage of the acceptors are activated. It thus requires a very high number of impurities to ensure sufficient conductivity. Furthermore, the Mg atoms are bound to magnesium-hydrogen complexes and inactive. A remedy is to remove by diffusion hydrogen stored during the deposition process. Due to the fact that the semiconductor layer structure is structured into webs, it is possible to laterally diffuse hydrogen under the action of heat, even if the p-doped nitride semiconductor layers are not present on the surface of the semiconductor layer structure.
  • For example, the lateral dimension d of the ridges is selected in dependence on the diffusion length of hydrogen in the GaN-based semiconductor material so that hydrogen can diffuse out. For example, the width of the webs may be less than 5 microns or even less than 3 microns. Depending on the web width, the duration of the diffusion process may vary in a subsequent process for the outdiffusion of hydrogen.
  • Due to the fact that the semiconductor layer structure becomes webs 130 is patterned, it is possible to provide buried p-type doped layers in the semiconductor layered structure and yet achieve satisfactory or sufficient activation of the p-type doped regions. Accordingly, a large number of optoelectronic components can be realized with the described basic structure. This will be discussed in more detail below.
  • The 2A to 2E illustrate a method of manufacturing the described optoelectronic device according to embodiments. Starting point can, as in 2A shown, any substrate 100 with a n + doped semiconductor layer 128 For example, be made of gallium nitride. For example, the substrate 100 an electrically non-conductive material such as sapphire. An arbitrary n-doped layer, for example of gallium nitride, SiC or Si, can be applied thereon. But it is also possible that the growth substrate 100 n + doped GaN-based semiconductor material or another semiconductor material and no additional layer 128 is provided. In a subsequent step becomes a structured mask 140 applied. By way of example, the structured mask can be produced by applying a whole-area mask layer with a layer thickness of at least 20 nm, for example more than 50 nm, and subsequent structuring. For example, the thickness of the mask layer is less than 600 nm, for example less than 150 nm. When structuring the mask, it should be noted that the distance between adjacent lands will approximately correspond to the later land width. The layer thickness of the mask layer depends on the web width to be achieved. The mask layer may comprise, for example, silicon oxide (SiOx), silicon nitride (SiN) or a silicon oxide / silicon nitride layer stack.
  • 2 B shows the cross section of a resulting structure. For example, the individual SiO x spokes can each be the same width and be applied at the same distance from each other. But it is also possible depending on the dimensions of the webs to be achieved to vary the corresponding widths.
  • Then, as in 2C shown, a semiconductor layer structure or a semiconductor layer stack grown epitaxially. For example, a MOCVD ("metal organic chemical vapor deposition") or MBE ("molecular beam epitaxy") method can be used. For example, a surface 110 of the substrate or the n + -Layer 128 on the substrate may be a crystallographic c-plane of gallium nitride. The semiconductor layer structure becomes on the exposed areas of the first main surface 110 of the n + -Layer 128 or the substrate 100 grew up. For example, the layer sequence can be a first n + doped GaN-based semiconductor layer 127 contain. Then follow layers for a tunnel contact 137 , For example, the tunnel contact may be an n ++ doped layer 126 as well as one p ++ doped layer 125 contain. Examples of layer stacks for forming the tunnel junction include n ++ GaN / p ++ -GaN or n ++ In x Ga 1-x n / AlN / p ++ In x Ga 1-x N or n ++ GaN / Al / p ++ GaN. The n-doping can be carried out by Si or Ge, the p-doping is carried out by Mg. The optional intermediate layer 138 Al or AlN improves the crystal quality of the adjacent semiconductor layers. It prevents diffusion of the dopants from one semiconductor layer to another and thus provides a sharp doping profile of each doped layers ready. The intermediate layer 138 has a similar crystal structure as the adjacent semiconductor materials and compensates for a piezoelectric effect caused in the polar semiconductor materials.
  • Then one p + doped layer 124 , a light active layer 123 , one n + doped layer 122 as well as one n ++ doped layer 121 applied. The light active layer 123 For example, it may be constructed of a material such as InGaN, GaN, AlGaN, which has a smaller bandgap than the adjacent semiconductor materials. A layer thickness of the light-active layer 123 may be smaller than the de Broglie wavelength of the electrons. As a result, forms between the p + doped layer 124 and the n + doped layer 122 in the area of the light-active layer 123 a quantum well out. In the context of the present disclosure, the term "luminescent active layer" also encompasses stacks of a plurality of different semiconductor materials which constitute a plurality of quantum wells and barriers. For example, the light-active layer 123 more than 5 Quantum wells, for example 9 Quantum wells included.
  • Because the alignment of the semiconductor layer on the first major surface 110 the c-direction is the webs 130 Have side surfaces that are parallel to the crystalline a-direction or m-direction.
  • Subsequently, a temperature treatment step for the outdiffusion of H + Ions and to activate the p-doped semiconductor region instead. For example, the grown structure is heated to a temperature of over 400 ° C, for example, 400/450 ° C or 500/600 ° C or 900 ° C for, for example, 2 to 5 minutes. As a result, hydrogen diffuses out, and the p-type regions are activated.
  • Because of the surface 120 the surface of the n ++ - layer 121 corresponds to defects or defects that may occur at high temperatures are not negative for the operation of the device.
  • 2D shows a cross-sectional view of a layer structure in performing the diffusion process. Subsequently, contacts (not shown) for contacting the layer 121 as well as the layer 128 applied.
  • According to embodiments, as shown in FIG 2E shown after applying the n ++ doped layer 126 a lateral overgrowth of the subsequent layers take place. As a result, for example, part of the p ++ doped layer 125 along the vertical side surfaces of the already applied layers 127 . 126 Growing up, part of p + doped layer 124 becomes horizontally adjacent to the vertical side layer 125 applied, etc. These vertically deposited layers can be removed by an etching step. For example, a crystal surface selective wet etching process may be used to remove the vertically grown layers. For example, KOH (potassium hydroxide) TMAH (tetramethylammonium hydroxide) and others may be used for this process. The etching of the vertically grown layers should be performed prior to performing the activation step to allow a vertical side surface of the p-doped layers 124 . 125 exposed and hydrogen can diffuse out. 2F shows an example of a ridge after performing this etching step.
  • According to further embodiments, it is also possible to first grow a layer stack of the individual layers over the entire surface and then the webs 130 for example, by etching to structure. 3 shows an example of a substrate 100 with grown on it semiconductor layer structure 129 , The areas to be etched can be defined photolithographically, for example. Subsequently, an etching process, for example a plasma etching process, optionally followed by a wet-chemical process, for example with KOH or TMAH, is carried out. After defining the bars 130 becomes, as with reference to 2D shown, a heat treatment carried out to H + To diffuse out. As a result, the p + doped areas activated.
  • 4A shows an example of a resulting structure. The semiconductor layer structure 129 has a luminous active layer 123 between n-doped layers 121 . 122 and p-doped layers 124 . 125 on. Furthermore, a tunnel contact 137 between the fluorescent layer 123 and the substrate. Further, a positive electrode (not shown in FIG 4A) with the n + doped layer 127 be brought into contact. In addition, a negative electrode (not shown in FIG 4A) with the n ++ doped layer 121 representing the top layer of the layered structure 129 forms are brought into contact.
  • 4B illustrates on the left side an equivalent circuit diagram for parts of the optoelectronic semiconductor device. The p ++ doped layer 125 as well as the n ++ doped layer 126 and optionally the intermediate layer 138 make a tunnel diode 167 dar. The n ++ doped layer 126 the tunnel diode 167 is about the n + doped layer 127 with the positive electrode 170 electrically connected. The p + -Layer 124 , the most active layer 123 as well as the n + -Layer 122 represent a light-emitting diode, wherein the n + -Layer 122 about the n ++ -doped layer 121 with the negative electrode 171 connected is. Through the tunnel diode 167 whose n-side is connected to the positive electrode 170 is connected holes in the light emitting diode 165 injected. In the area of the light-active layer 123 recombine the injected holes with those through the negative electrode 171 provided electrons with emission of photons.
  • The left part of the 4C schematically shows the band structure in the region of the light emitting diode 165 , The light active layer 123 is between n + -Layer 122 and p + -Layer 124 arranged. The band gap of the light-active layer 123 is smaller than the adjacent one n + - and p + -Layer. Accordingly, a quantum well structure is formed. Because of the light-active layer 123 grown on the c-crystal plane, which represents a polar plane, and in addition by the occurrence of piezoelectric effects as a result of tensions in the growth of materials with different lattice constants, an additional electric field is generated, which in the region of the luminous layer 123 leads to a tilting of the bands, as in the left part of the 4C is shown. A the layer 122 leaving electron thus sees a potential barrier before reaching the quantum well. Similarly, the layer sees this 124 leaving hole before reaching the quantum well a potential barrier. Due to the configuration in which the n + Layer a greater distance to the main surface 110 of the substrate 100 has as the p + doped layer and the light-active layer 123 between n + -doped layer and p + - doped layer is arranged, an improved charge carrier injection and a better confinement of the charge carriers can be achieved.
  • For comparison, in the right-hand part of 4C a case is shown in which the p-type layer and the n-type layer are interchanged with each other. In this case, the carrier injection is impaired because of the risk that, for example, a hole will not be in the quantum well of the luminous active layer 123 is caught.
  • In the 4A shown structure in which the light-active layer 123 between p + doped layer 124 and n + doped layer 122 is arranged and the n + doped layer 122 has a greater distance to the substrate than the p + doped layer 124 , is thus advantageous. A connection of the p + doped area 124 to the n + -doped area 128 can via a tunnel diode 167 to be provided. Furthermore, it can be characterized by the fact that now on the surface 120 one n ++ doped area 121 is present, an ohmic contact to a negative electrode 171 be provided in a simple manner. In principle it is easier to combine one electrode n + to provide a doped semiconductor region as one p + doped region, since the n-doped region can be doped higher and thus the ohmic resistance between n + doped region and adjacent electrode can be reduced. In that, as in 4A illustrates the optoelectronic device exclusively via n + - and n ++ doped areas can be contacted, the properties of the device can be further improved.
  • As has been described, the patterning of the semiconductor layer structure 129 opens up a possibility in webs, p-doped nitride semiconductor materials, which are not present on the surface of the semiconductor layer structure, but in the layer structure 129 are buried to provide. As a result, based on nitride semiconductor materials, optoelectronic devices having increased efficiency and improved properties can be provided. These optoelectronic components can contain, for example, a semiconductor layer structure which has an n-doped layer on the surface and buried p layers. According to further embodiments, the semiconductor layer structure may comprise a p-doped layer on the surface as well as buried p-layers.
  • According to further embodiments, it is possible to connect a plurality of LED structures via tunnel junctions with each other and within a ridge 130 to stack on top of each other. The 5A to 5B show an example for the production of a corresponding optoelectronic component. On the in 2 B shown substrate with n + layer applied thereon 128 and one on the surface of the layer 128 trained mask 140 becomes a semiconductor layered structure 129 applied, which is a first luminescent layer 158 and a second luminescent layer 153 having. A tunnel contact 137 is provided between these structures. For example, a first n + doped layer 159 , then a first luminescent layer 158 and finally a p + -doped layer 157 be applied, whereby a first light-emitting diode 165 is realized with quantum well structure, as described above. Subsequently, to form a tunnel contact, a p ++ -doped layer 156 and an n ++ doped layer 155 applied. Optionally, a conductive intermediate layer 138 between the layers 156 and 155 be provided. The structure of the layers may correspond to the structure described with reference to FIG 2C has been described. Then, to form a second light-emitting diode 166 with quantum well structure an n + doped layer 154 , the second active layer 153 as well as the p + -doped layer 152 applied. Subsequently, the p ++ -doped layer 151 applied.
  • On the surface 150 the in 5A shown layer structure 129 is thus a p ++ -doped layer 151 intended. However, the semiconductor layer structure also has buried p-doped layers from which hydrogen can be diffused out by a heat treatment. The semiconductor layer structure 129 may in turn have been applied by MOCVD or MBE. The semiconductor layer structure forms individual webs 130 for example, whose side surfaces may be parallel to a crystalline a direction or m direction. The light active layers 153 . 158 For example, you can emit light of the same wavelength or light of different wavelengths.
  • Subsequently, by heating the p-doped layers can be activated by H + ions are diffused out. 5B shows a cross-sectional view of the optoelectronic device. As a result, the p + and p ++ doped regions are activated. In particular, a tunnel contact 137 be provided with good features. In a similar way as in 2E shown here, a lateral overgrowth of the semiconductor layers can be carried out by subsequently applied semiconductor layers.
  • 6A shows an example of an optoelectronic device with vertically grown semiconductor layers. These can be removed again by etching. For example, a crystal surface selective wet etching method may be used to remove these vertical semiconductor layers. For example, KOH or TMAH and others may be used for this process.
  • 6B shows an example of an optoelectronic device with completely removed vertically grown semiconductor layers.
  • According to further embodiments, as in 6C illustrates the vertically grown semiconductor layers are only partially removed. This can be done, for example, to the first light-active layer 158 short-circuit. As in 6C can be shown, for example, over the vertically overgrown parts of the n + -doped layers 154 . 155 , with suitable contacting only the second active layer 153 be electrically connected to a corresponding terminal. As a result, the first luminescent layer 158 turned off and only the first active layer 153 to be activated.
  • 7A shows an equivalent circuit diagram for the in 6B respectively. 5B shown optoelectronic component. The layers 155 . 156 form a tunnel diode 167 from, through the electrons in the second light-emitting diode 166 be injected. At the same time, holes are made in the first light-emitting diode 165 injected. The n + layer 159 is electrically conductive with a negative electrode 160 connected while the p + + layer 151 with a positive electrode 161 connected is. This in 7A Furthermore, the fact that the two light-emitting diodes are connected to each other via a tunnel diode, two photons are emitted per electron, which flows from negative to positive electrode, illustrated optoelectronic component. Accordingly, the photon quantity achievable with respect to the current intensity can be increased in comparison to optoelectronic components with only one light-emitting diode.
  • It is self-evident that as an alternative to the procedure described, the stack of different LEDs can also be produced by application of a semiconductor layer structure over the entire area and subsequent structuring into bars, as described with reference to FIG 3 has been described.
  • 7B shows an example of a layer stack of a series connection of three light-emitting LEDs 165 . 166 . 168 , The light-emitting LEDs 165 . 166 . 168 have, for example, the semiconductor layers shown in the right part. It is about one n + doped layer 159 a first light active layer 158 followed by a p-doped layer 157 arranged. This layer sequence forms a first light-emitting diode 165 out. Above it is a tunnel diode 167 containing a p ++ -doped layer 156 , followed by an n ++ -doped layer 155 and, moreover, as with reference to 2C described can be formed. This is followed by the second light-emitting diode 166 , which is an n + -doped layer 154 , a second light-active area 153 and a p-doped layer 152 having. This is followed by a second tunnel diode 169 from a p ++ -doped layer 151 and an n ++ -doped layer 179 , which may be formed in the manner described. This is followed by a third light-emitting diode 168 from an n + -doped layer 178 , a third light-emitting area 176 and a p + -doped layer 175 , A positive electrode 161 is over the p ++ -doped layer 174 with the p + doped layer 175 connected. Of course, more LEDs can be stacked on top of each other.
  • Such stacking of light emitting diodes can increase the luminance per area compared to a simple LED structure. At the same time, it is not necessary to increase the current, since two, three or four photons can be emitted from a single injected electron because of the existing tunnel junctions. Thus, a light emitting diode with greatly increased quantum efficiency can be provided.
  • For example, the substrate 100 be insulating and transparent. According to further embodiments, dielectric material may be introduced between adjacent lands to enhance light extraction. According to further embodiments, the ridges may be further etched with suitable etchants to increase the surface roughness. As a result, better extraction into the low refractive index dielectric can be achieved.
  • The described principle of stacking a plurality of light-emitting regions via one or more tunnel junctions can also be applied to those described with reference to FIG 2D or 4A described structure can be applied. 8th shows a cross-sectional view through a semiconductor layer structure having a first light-emitting region 123 and a second light-active area 183 , A first tunnel contact 137 is between the first luminous area 123 and the substrate. Furthermore, a second tunnel contact 139 between the first luminous area 123 and the second light-active area 183 arranged. The conclusion of the layer structure is the n ++ layer 181 that with the negative electrode 171 connected is.
  • The optoelectronic component thus has an n + -layer 127 on, over which a first tunnel diode 167 is arranged, which is an n ++ layer 126 and a p ++ layer 125 contains and otherwise can be realized in the manner described above. Above is a first light emitting diode 165 containing the p + layer 124 , the first active layer 123 and the n + layer 122 contains. Above this is a second tunnel diode 169 arranged the n ++ layer 121 and the p ++ layer 185 contains. Above this is a second light-emitting diode 166 arranged, which is the p + layer 184 , the second active layer 183 and the n + layer 182 contains. Above that is an n ++ -doped layer 181 arranged over which the n + -doped layer with the negative electrode 171 is connectable. This component contains, on the one hand, a stacked stack of two light-emitting diodes 165 . 166 with the resulting benefits. It also forms an n ++ -doped layer 181 the completion of the structure. Overall, by this arrangement of the layers, the advantages, with reference to the 4C have been described. Furthermore, with a suitable selection of the active layers 123 . 183 this in 8th illustrated optoelectronic component emit two different wavelengths.
  • According to further embodiments, the p-doped layer of the semiconductor layer structure does not necessarily have to be part of a tunneling contact between the luminous layer and the substrate. According to in 9A In embodiments shown, the p-doped layer may also be used to provide a p-contact. The right-sided part of 9A shows a schematic representation of a portion of a semiconductor layer structure of an optoelectronic device, while the left-hand part of 9A an equivalent circuit diagram shows.
  • A first negative electrode 190 is with a first light emitting diode 165 connected. The first light-emitting diode 165 contains, for example, an n + -layer 193 , a first light-emitting layer 194 and a p-doped layer 195 , A p ++ -doped layer 196 is above the p + -doped layer 195 arranged. For example, the p ++ -doped layer 196 with a positive electrode 192 be electrically connected. A p + -doped layer 197 forms part of a second light emitting diode 166 , The second light emitting diode 166 also includes a second luminescent layer 198 and an n + -doped layer 199 , The n + -doped layer 199 is over a n ++ -doped layer 189 with a second negative electrode 191 connected.
  • In the 9A illustrated semiconductor layer structure thus represents a part of an optoelectronic component, wherein the two light-emitting diodes 165 . 166 for example, simultaneously or separately, for example, can be operated with alternating current. For example, the two light emitting diodes 165 . 166 be able to emit different wavelengths each. For example, with the illustrated semiconductor layer structure, which has two light-emitting diodes, a color shift over the course of the operating period can be compensated. According to further embodiments, the two light-emitting diodes 165 . 166 be able to emit the same wavelength each. In this case, a greater light dynamics can be gained.
  • As in 9B is shown, this structure can still around a third light-emitting diode 168 be extended, which has a tunnel diode 167 with the second light emitting diode 166 can be connected. On the in 9A Layer structure shown are still an n ++ -doped layer 189 and a p ++ doped layer 143 applied. These layers form the left part of the 9B illustrated tunnel diode 167 , Above it is a p + -doped layer 144 , a third active layer 145 and an n + -doped layer 146 , The layers 144 . 145 . 146 set the third LED 168 Above that is an n ++ -doped layer 147 , via which an electrical contact to the second negative electrode 191 he follows.
  • According to further embodiments, the described structuring of the semiconductor layer stack or of the layer structure be used to form webs of semiconductor layer structures, each emitting light of different wavelengths, on a single semiconductor substrate. 10A shows, for example, a first, second and third bridge 131 . 132 . 133 from semiconductor layer structures such as those in 7B are illustrated. The bridges 131 . 132 . 133 are on a common substrate (not shown in 10A) arranged. In addition, a first contact layer 220 made of an electrically conductive material on vertical side walls of the layer structure. The electrically conductive material may be, for example, a metal, an n ++ doped layer, or a TCO ("transparent conductive oxide") such as ITO (indium tin oxide) or an aluminum doped zinc oxide. The semiconductor layer structure includes an n + layer 201 , a first fluorescent layer 202 and a p + layer 203 , whereby a first light-emitting diode 230 (S. 11B) provided. Above this are a first tunnel diode 235 ( 11B) that has a p ++ layer 204 and an n ++ layer 205 includes and may be formed as described above, arranged. This is followed by an n + layer 206 , a second light-active layer 207 and a p + layer 208 , whereby a second light-emitting diode 231 ( 11B) provided. Above this is another tunnel diode 235 ( 11B) from a p ++ layer 209 and an n ++ layer 210 arranged. Above this is a third LED 232 from an n + layer 211 , a third active layer 212 and a p + layer 213 , Above this layer is a p ++ layer 214 arranged, through which the layer structure with a positive electrode (not shown) is connectable.
  • The light active layers 202 . 207 . 212 are selected so that they each emit light of different wavelengths.
  • For further processing of the optoelectronic component, the first web 131 subsequently masked and an etching step is performed, whereby the layers 214 . 213 . 212 and 211 be etched. The conclusion of the resulting structure is the n ++ layer 210 , The n ++ layer 210 is connectable in a later process step via a tunnel contact with a positive electrode. By doing that, the n ++ layer 210 is present at the surface of the layer structure, the underlying p ++ layer 209 not damaged by a plasma etching process. The first vertical contact layer 220 will be at the second and third footbridge 132 . 133 etched back so that the second contact layer 221 results. 10B shows a schematic cross-sectional view of the second and third ridge 132 . 133 after performing the etching step.
  • In a subsequent etching step, the surface of the first ridge becomes 131 and the second bridge 132 covered, leaving only the surface of the third bridge 133 exposed. An etching step is performed, whereby the layers 210 . 209 . 208 . 207 and 206 be etched. The result is the third bridge 133 with a first light emitting diode. The second contact layer 221 will be at the third jetty 133 completely removed. Here as well, after the etching step, the top layer of the layer structure remains the n ++ layer 205 , which is connectable via a tunnel contact with the positive electrode. 10C shows a schematic cross-sectional view of the third ridge 133 after performing the etching step.
  • 11A shows an example of a resulting optoelectronic device 20 , The optoelectronic component 20 includes a substrate 100 as well as one on the substrate 100 arranged semiconductor layer structure 129 , which is structured into a plurality of webs, whose lateral dimension is smaller in each case than a lateral dimension of the substrate 100 is. The plurality of webs includes a first land 131 , a second jetty 132 and a third jetty 133 , A first light active layer 212 which is capable of emitting light of a first wavelength is in the first land 131 arranged. Furthermore, a second light-active layer 207 capable of emitting light of a second wavelength into the second land 132 arranged. In addition, a third active light layer 202 capable of emitting light of a third wavelength in the third land 133 arranged.
  • The first connection area 220 is provided to the n ++ doped area 210 of the first footbridge 131 with the n + layer 201 short-circuit. As a consequence, the third light-emitting diode, which is the third light-active layer 212 contains, connectable to a negative electrode, without the first and the second active layer 202 . 207 be connected to the negative electrode. For this reason, in the first bridge 131 only the third light-emitting diode with the third light-active layer 212 operated.
  • Similarly, in the second bridge 132 through the second connection area 221 the n ++ -Layer 205 with the n + layer 201 shorted. Accordingly, in the second bridge 132 only the second light-emitting diode with the light-active layer 207 operated. In the third footbridge 133 is only the third active layer 202 in front. This is operated when a suitable voltage is applied. In this way, it is possible by a simple method different light emitting areas on a substrate 100 provided.
  • 11B shows an equivalent circuit diagram for the corresponding layer structures in the individual webs 131 . 132 and 133 , A negative electrode 225 is with the third LED 232 connected. The third LED 232 is via a second tunnel diode 235 with a second light emitting diode 231 connected. The second LED 231 is over a first tunnel diode 234 with the first light emitting diode 230 connected. The first light-emitting diode 230 is with the positive electrode 220 connected. By appropriate provision of the electrical connection areas 220 . 221 is it possible, for example, within the second bridge 132 the third light emitting area 232 to bridge. Accordingly, it is possible within the first bridge 131 the second light emitting diode 231 and the third light-emitting diode 232 to bridge. The respective light-emitting diodes 230 . 231 . 232 For example, they can be controlled separately or in the area 225 be shorted.
  • According to further embodiments, it is possible to use the various methods of manufacturing the semiconductor ridges, i. the method which comprises a selective growth of semiconductor ridges or the etching of semiconductor ridges to combine with each other.
  • In principle, defects in the surface or in the crystal are produced by structuring of the semiconductor bars by etching. Furthermore, with larger wafer diameters or with a large mismatch of the thermal expansion coefficients, it is more favorable to grow the semiconductor bridges structured by selective epitaxy. Conversely, structured waxing can be tedious to remove by etching over the laterally overgrown layers. By combining the methods, the respective disadvantages can be mitigated.
  • 12A shows an example of a semiconductor substrate 100 with semiconductor layers grown over the whole area. For example, an n + -doped layer 201 , a first fluorescent layer 202 , a p + -doped layer 203 , a p ++ -doped layer 204 as well as an n ++ -doped layer 205 on the semiconductor substrate 100 be upset. The layers 204 . 205 form part of a tunnel contact and may additionally contain a conductive intermediate layer as described above. In a next step, an etching process for structuring the applied layer structures takes place in webs. Subsequently, a mask is applied. This can be done, for example, by application of an SiO x layer over the entire area and subsequent etching. 12B shows an example of a resulting structure.
  • Subsequently, a process for growing subsequent layers is performed, as in 12C is shown. This may include, for example, an MOCVD or MBE method as described above. By way of example, an n + -doped layer will subsequently be used 206 , a second active light layer 207 and a p + -doped layer 208 deposited. The layers 206 . 207 . 208 form, for example, a second light emitting diode. Subsequently, a p ++ -doped layer 209 as well as an n ++ -doped layer 210 applied. These layers 209 . 210 For example, they represent a tunneling contact and may optionally include a conductive interlayer as discussed above. Finally, another n + doped layer 211 , another light active layer 212 and a p + -doped layer 213 be applied. The layers 211 . 212 . 213 represent, for example, a third LED. Subsequently, a p ++ -doped layer 214 applied, through which, for example, an electrical contact to a positive electrode can be represented. As in 12C is shown, the trained semiconductor ridges can be overgrown by subsequently grown semiconductor layers laterally. These vertical semiconductor regions can be removed by etching.
  • The following is with reference to the 13A to 13C another method of producing the in 9A shown structure. On a semiconductor substrate 100 become an n + -doped layer 193 , a light active layer 194 , a p + -doped layer 195 and a p ++ -doped layer 196 applied over the entire surface ( 13A) , The layers 193 . 194 . 195 set a first light emitting diode 165 as in the 9A and 9B The layer 196 is as a terminal layer for contacting the adjacent p + layers 195 or 197 (shown in 13C ) intended. Then a mask 140 applied. For example, an SiO x layer is applied over the entire surface and structured using a photolithographic process ( 13B) , Then, an MBE or MOCVD process for growing the subsequent layers is performed. It becomes a p + doped layer 197 , a second active light layer 198 and an n + -doped layer 199 applied. The layers 197 . 198 . 199 represent a second light emitting diode, for example, the second light emitting diode 166 in 9A or 9B Subsequently, an n ++ -doped layer 189 applied.
  • 13C shows a cross-sectional view of a resulting structure. Optionally laterally overgrown parts of the grown semiconductor layers can be removed by an etching process. Subsequently, a heat treatment takes place for activating the p-doped layers. For this purpose, the workpiece is heated, so that H + ions diffuse out. Subsequently, a layer 238 , For example, made of silicon oxide (SiOx), applied for lateral passivation. Then the mask 140 away.
  • 13D FIG. 12 shows a cross-sectional view of an example of a resulting structure. FIG. The passivation layer 238 covers the sidewalls of the layer structure of the layers 197 . 198 . 199 and 189 , A conductive layer to form a p-contact 192 is on the exposed surfaces of the p ++ doped layer 196 applied ( 13E) , For the completion of the optoelectronic component, further method steps can be carried out, in particular for contacting the respectively n + or n ++ -doped layers 193 . 189 ,
  • 14 summarizes a method according to embodiments. The method comprises the formation ( S100 ) a plurality of ridges of a semiconductor layer structure on a substrate. The semiconductor layer structure has a p-doped layer, a first luminescent active layer and an n-doped layer, wherein the n-doped layer is arranged at a greater distance from a main surface of the growth substrate than the p-doped layer. A lateral dimension of the ridges is smaller than a lateral dimension of the substrate, respectively. The method may further include a heat treatment ( S110 ) for the diffusion of hydrogen.
  • As has been described, the fact that the semiconductor layer structure is patterned into webs or formed as structured webs makes it possible to achieve activation of the p + doped layers in a simple manner, in particular in the case of nitride-based semiconductor materials. As a result, optoelectronic devices having a semiconductor layered structure including a "buried" p-doped gallium nitride-based semiconductor layer can be realized. This makes it possible to provide optoelectronic devices with increased efficiency.
  • According to embodiments, it is possible to provide tunnel contacts for optoelectronic components, via which a buried p-doped layer can be electrically connected in an improved manner. By way of example, as a result of the p-doped layer being buried, damage to the p-doped layer, for example due to a plasma during an etching process, can be prevented. Furthermore, an improved terminal resistance can be achieved since an electrode in direct contact with an n-doped layer can be connected via a tunnel contact with the p-doped layer.
  • Although specific embodiments have been illustrated and described herein, those skilled in the art will recognize that the specific embodiments shown and described may be substituted for a variety of alternative and / or equivalent embodiments without departing from the scope of the invention. The application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Therefore, the invention is limited only by the claims and their equivalents.
  • LIST OF REFERENCE NUMBERS
  • 10
    optoelectronic component
    20
    optoelectronic component
    100
    substratum
    110
    first main surface
    120
    first main surface of the semiconductor layered structure
    121
    n-doped layer
    122
    n-doped layer
    123
    first active light layer
    124
    p-doped layer
    125
    p-doped layer
    126
    n-doped layer
    127
    n-doped layer
    128
    n-doped layer
    129
    Semiconductor layer structure
    130
    web
    131
    first jetty
    132
    second bridge
    133
    third jetty
    135
    dielectric material
    137
    first tunnel contact
    138
    conductive intermediate layer
    139
    second tunnel contact
    140
    structured dielectric mask
    143
    p-doped layer
    144
    p-doped layer
    145
    third active layer
    146
    n-doped layer
    147
    n-doped layer
    150
    first main surface of the semiconductor layered structure
    151
    p-doped layer
    152
    p-doped layer
    153
    second active layer
    154
    n-doped layer
    155
    n-doped layer
    156
    p-doped layer
    157
    p-doped layer
    158
    first active light layer
    159
    n-doped layer
    160
    negative electrode
    161
    positive electrode
    165
    first light emitting diode
    166
    second light emitting diode
    167
    first tunnel diode
    168
    third light emitting diode
    169
    second tunnel diode
    170
    positive electrode
    171
    negative electrode
    174
    p-doped layer
    175
    p-doped layer
    176
    third active layer
    178
    n-doped layer
    179
    n-doped layer
    181
    n-doped layer
    182
    n-doped layer
    183
    second active layer
    184
    p-doped layer
    185
    p-doped layer
    189
    n-doped layer
    190
    first negative electrode
    191
    second negative electrode
    192
    positive electrode
    193
    n-doped layer
    194
    first active light layer
    195
    p-doped layer
    196
    p-doped layer
    197
    p-doped layer
    198
    second active layer
    199
    n-doped layer
    201
    n-doped layer
    202
    first active light layer
    203
    p-doped layer
    204
    p-doped layer
    205
    n-doped layer
    206
    n-doped layer
    207
    second active layer
    208
    p-doped layer
    209
    p-doped layer
    210
    n-doped layer
    211
    n-doped layer
    212
    third active layer
    213
    p-doped layer
    214
    p-doped layer
    220
    first contact layer
    221
    second contact layer
    222
    first positive electrode
    223
    second positive electrode
    224
    third positive electrode
    225
    negative electrode
    230
    first diode
    231
    second diode
    232
    third diode
    234
    first tunnel contact
    235
    second tunnel contact
    238
    passivation

Claims (19)

  1. Optoelectronic component (10, 20) comprising: a substrate (100); and a semiconductor layered structure (129) disposed on the substrate (100), wherein the semiconductor layer structure (129) has a p-doped layer (124, 125, 156, 157, 192, 203, 204), a first light-active layer (123, 158) and an n-doped layer (121, 122, 154, 155, 189), wherein the n-doped layer (121, 122, 154, 155, 189) is arranged at a greater distance from a main surface (110) of the substrate (100) than the p-doped layer, and the semiconductor layered structure (129) is patterned into a plurality of ridges (130) whose lateral dimension is in each case smaller than a lateral dimension of the substrate (100).
  2. Optoelectronic component (10) according to Claim 1 in which the lateral dimension of the webs (130) is less than 15 μm.
  3. Optoelectronic component (10) according to Claim 1 or 2 in which the p-doped layer contains GaN.
  4. Optoelectronic component (10) according to one of Claims 1 to 3 in which a side surface a web (130) is parallel to a crystallographic a-axis of a layer of the semiconductor layer structure (129).
  5. Optoelectronic component (10) according to one of Claims 1 to 4 in which the light-active layer is arranged on a crystallographic c-plane of a layer of the semiconductor layer structure (129).
  6. An optoelectronic component (10) according to any one of the preceding claims, wherein the uppermost layer of the semiconductor layered structure (129) is an n-doped layer (121).
  7. Optoelectronic component according to one of Claims 1 to 6 in which the semiconductor layer structure (120) further comprises a first tunnel junction (137) between the first luminescent active layer (123) and the substrate (100).
  8. Optoelectronic device according to Claim 7 in which the semiconductor layer structure further comprises a second luminescent active layer (153).
  9. Optoelectronic device according to Claim 8 in which the first tunnel contact (137) is arranged between the first (158, 202) and second light-active layer (153, 207).
  10. Optoelectronic component (10) according to Claim 8 in which the p-doped layer is arranged between the first and the second light-active layer (194, 198), with a p-contact region (192) which adjoins the p-doped layer (196) and is electrically connected to the p-type doped layer (196) is connected.
  11. Optoelectronic component (10, 20) according to one of Claims 1 to 7 in which the semiconductor layer structure further comprises a second luminescent active layer (183) and a second tunnel junction (139), the first tunnel junction (137) between the first luminescent layer (123) and the substrate (100) and the second tunnel junction (139) is disposed between the first (123) and second luminous active layers (183).
  12. Optoelectronic component (10, 20) according to one of Claims 1 to 11 in that the webs differ from one another with respect to their lateral or horizontal dimension.
  13. Optoelectronic component (20) comprising: a substrate (100); and a semiconductor layer structure (129) arranged on the substrate (100), which is structured into a plurality of webs (131, 132, 133) whose lateral dimension is in each case smaller than a lateral dimension of the substrate (100), wherein the plurality of lands comprise a first land (131), a second land (132) and a third land (133), a first light active layer (212) capable of emitting light of a first wavelength is disposed in the first land (131), a second light active layer (207) capable of emitting light of a second wavelength is disposed in the second land (132), and a third light active layer (202) capable of emitting light of a third wavelength is disposed in the third land (133).
  14. Optoelectronic component (20) according to Claim 13 , comprising a first contact structure (220) and a second contact structure (221), wherein the first contact structure (220) is adapted to drive the first light active layer (212) and the second contact structure (221) is adapted to drive the second light active layer ,
  15. A method of manufacturing an optoelectronic device, comprising forming (S100) a plurality of ridges from a semiconductor layer structure on a substrate, wherein the semiconductor layer structure comprises a p-doped layer, a first luminous layer, and an n-type layer, wherein the n-type layer is located at a greater distance from a major surface of the growth substrate than the p-type layer; a lateral dimension of the webs is in each case smaller than a lateral dimension of the substrate.
  16. Method according to Claim 15 further comprising a heat treatment for outdiffusion (S110) of hydrogen.
  17. Method according to Claim 15 or 16 wherein forming the lands comprises growing the semiconductor layer structure on a masked substrate.
  18. Method according to Claim 15 or 16 in which the formation of the webs comprises the growth of the semiconductor layer structure and subsequent etching of the webs.
  19. Method according to Claim 15 or 16 in which the forming of the webs comprises growing a first sub-stack, subsequent etching, and then growing a second sub-stack on a masked workpiece.
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