JP5412561B2 - Analog-to-digital converter and conversion method thereof - Google Patents

Description

  The present invention relates to an analog-to-digital converting (ADC) device.

  Referring to the block diagram of the conventional sub-ranging analog-to-digital converter 100 shown in FIG. 1, the analog-to-digital converter 100 includes a plurality of stages of comparison modules 101, 102, and 103, an encoder, and an encoder. (Encoder) 120 and reference signal generator 130. The comparison modules 101, 102 and 103 all receive an analog input signal VIN. The comparison module 101 performs a coarse comparing action between the input signal VIN and the reference signal VREF1, and generates a digital comparison result D1.

  After the comparison module 101 finishes the rough comparison operation, the comparison module 102 receives the first-stage pre-encoding result DEN1 generated by the encoder 120. First, the comparison module 102 selects a set of reference signals from the reference signal VREF2 based on the first-stage pre-encoding result DEN1, and performs a comparison operation between the input signal and the selected reference signal. Based on this, a digital comparison result D2 is generated. Similarly, after the comparison module 102 finishes the fine comparing action, the comparison module of the next stage performs further fine comparison operation based on the second-stage pre-encoding result DEN2 generated by the encoder 120. Do. The comparison module 103 in the final stage is a selected reference signal selected from the input signal VIN and the reference signal VREFi based on the last encoded result DEN (i-1) from the last stage generated by the encoder 120. After completing the comparison operation of a set of reference signals, the encoder 120 performs encoding based on a plurality of digital comparison results D1 to Di (i indicates a positive integer) generated by the comparison modules 101 to 103. The encoding result DOUT is generated as the analog-digital conversion result of the input signal VIN.

  Accordingly, the present invention provides an analog-digital conversion apparatus and a conversion method thereof for reducing the data conversion time of analog-digital conversion.

  The present invention provides an analog-to-digital conversion method for reducing the data conversion time of analog-to-digital conversion. The present invention provides an analog-to-digital converter that includes a coarse comparison module, at least one pre-switching detection module, at least one fine comparison module, and an encoder. The coarse comparison module receives the input signal, compares the input signal with the plurality of first reference signals, and sequentially generates a pre-comparison result and a coarse comparison result. The pre-switching detection module receives the pre-comparison result and generates a pre-selection signal based on the pre-comparison result. The encoder generates a pre-encoding result based on the rough comparison result. The fine comparison module is coupled to the pre-switching detection module and receives the input signal, the pre-select signal and the first pre-encode result, and based on the pre-select signal and the pre-encode result, a plurality of primary signals from the plurality of second reference signals. A reference signal is selected as a selection reference signal, and the selection reference signal from the input signal and the primary reference signal is compared to generate a fine comparison result.

  The present invention receives an input signal, compares the input signal with a plurality of first reference signals, sequentially generates a pre-comparison result and a rough comparison result, and a pre-selection signal based on the pre-comparison result. Generating a selection reference signal by selecting a plurality of primary reference signals from a plurality of second reference signals based on the pre-selection signal and the pre-encoding result, and the input signal and the primary reference signal An analog-to-digital conversion method is provided that includes comparing selected selection reference signals to generate a fine comparison result.

  As described above, in the present invention, when the rough comparison module performs a comparatively wide range of comparison operations, the pre-selection signal is generated using the quick comparison result generated earlier, and is generated by the rough comparison module. Using the rough comparison result, a first-stage pre-encoding result is generated. In this way, the fine comparison module can select a reference signal to be compared with the input signal from the primary reference signal based on the pre-encoding result and the pre-selection signal, and can generate a fine comparison result. . As described above, when the comparison module at the current stage performs the comparison operation of the input signal, the primary reference signal corresponding to the fine comparison module at the next stage can be simultaneously selected. Therefore, the conversion time of analog-digital conversion can be effectively saved, thereby achieving the purpose of speeding up data conversion.

  In order to make the above and other objects, features and advantages of the present invention more comprehensible, several embodiments accompanied with figures are described below.

  In the conventional analog-digital conversion apparatus 100, after the comparison module 101 finishes the rough comparison operation based on the difference between the input signal and the first reference signal VREF1 generated by the reference signal generator 130, the encoder Based on the comparison result D1, the first stage pre-encoding result DEN1 is generated. The comparison module of the next stage of the analog-to-digital converter, that is, 102 performs a fine comparison operation based on the same input signal and the second reference signal VREF2. VREF2 is a set of reference signals selected from the reference signal generator 130 based on the pre-encoding result of the first stage.

  However, in the data conversion procedure, the comparison module must wait not only for the pre-comparison module to finish but also for the fine reference voltage or sub-range voltage to stabilize. The comparison module can then perform data conversion. Therefore, in the conventional multi-stage or sub-ranging type analog-to-digital converter, the data conversion speed is limited by the delay of the comparison result of the comparator in the previous stage and the stabilization time of the sub-range voltage.

  When the coarse comparison module of the analog-to-digital converter, that is, the first stage comparison module performs the comparison, a pre-selection signal is generated according to the previously generated previous comparison result, and the next comparison module, that is, The primary reference signal or preamplifier used in the fine comparison module is preset via the preselection signal. After the coarse comparison module finishes the coarse comparison operation, a pre-encoded result is generated by the encoder. Based on the pre-encoding result, the next-stage comparison module of the analog-to-digital conversion device has an input signal and a set of reference signals or usable pre-amplifiers selected from the primary reference signal or pre-amplifiers available according to the pre-encoding result. Based on the difference, a precise comparison operation is performed. Thus, the preselection signal generated by the first comparison module can be used to quickly switch or enable the fine reference voltage or preamplifier. This is called pre-switching technology.

  According to the pre-switching technique, the data conversion speed of the analog-digital converter is limited only by the delay of the comparison result of the comparator in the previous stage, and it is not necessary to wait for the stabilization time of the subrange voltage. Similarly, the concept can also be applied to the operation process of two adjacent stages of the fine comparison module. Therefore, the sampling rate of the analog-digital conversion device is effectively improved.

1 is a block diagram of a conventional subranging analog-to-digital converter 100. FIG. 1 is a schematic diagram of an analog-digital conversion apparatus 200 according to an embodiment of the present invention. 2 is a schematic diagram of an implementation method of a rough comparison module 201. FIG. It is a figure which shows the relationship between the delay time until it determines that the output result was stabilized after the comparator became usable by control signal CTL, and the input voltage difference of the comparison signal of a corresponding comparator. The different implementation methods of the rough comparison module 201 are shown. The different implementation methods of the rough comparison module 201 are shown. 1 illustrates an implementation method of a pre-switching detection module according to an embodiment of the present invention. 2 shows an implementation method of a pre-switching detection circuit 600 according to an embodiment of the present invention. FIG. 5 is a schematic diagram of the operation of the pre-switching detection circuit 600. FIG. 5 is a schematic diagram of the operation of the pre-switching detection circuit 600. FIG. 5 is a schematic diagram of the operation of the pre-switching detection circuit 600. 2 shows an implementation method of a fine comparison module according to an embodiment of the present invention. Fig. 4 shows different implementation methods of a fine comparison module according to an embodiment of the present invention. 3 is a flowchart of an analog-digital conversion method according to an embodiment of the present invention.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the drawings and the related description, the same reference numerals are used for the same or similar components.

  Referring to FIG. 2, FIG. 2 is a schematic diagram of an analog-digital conversion apparatus 200 according to an embodiment of the present invention. The analog-digital conversion apparatus 200 includes a rough comparison module 201, fine comparison modules 211 to 21P, pre-switching detection modules 221 to 22P, an encoder 230, and a reference signal generator 250. The reference signal generator 250 is coupled to the coarse comparison module 201 and the fine comparison modules 211 to 21P, and the reference signal generator 250 is used to provide the reference signals VREFC and VREF1 to VREFi (i is a positive integer). The The coarse comparison module 201 receives the analog input signal VIN, compares the input signal VIN with a plurality of reference signals VREFC, and sequentially generates a pre-comparison result DP1 and a coarse comparison result DC. In the pre-switching detection modules 221 to 22P, the first-stage pre-switching detection module 221 is coupled to the rough comparison module 201 and the fine comparison module 211. It should be noted that the pre-comparison result DP1 is generated before the coarse comparison result DC. That is, before the final rough comparison result DC of the rough comparison module 201 is generated, the previous comparison result DP1 is generated first.

  The pre-switching detection module 221 receives the pre-comparison result DP1, and generates the pre-selection signal PS1 based on the pre-comparison result DP1. Further, the encoder 230 generates the previous encoding result DEN1 based on the rough comparison result DC. The pre-selection signal PS1 and the pre-encoding result DEN1 are provided in order and coupled to the fine comparison module 211. After receiving the pre-selection signal PS1, the fine comparison module 211 selects a plurality of first reference signals or pre-amplifiers to be compared with the input signal VIN from a plurality of reference signals VREFF1 or a preamplifier (not shown). To do. Further, after the pre-encoding result DEN1 is stably generated, the fine comparison module 211 selects a set of reference signals from a plurality of primary reference signals as selection reference signals. The selected reference signal that is the selection reference signal is then compared with the input signal VIN to generate a fine comparison result DF1. Alternatively, the fine comparison module 211 may select a set of usable preamplifiers from a plurality of usable preamplifiers installed in the fine comparison module 211. The selected usable preamplifier is then compared with the input signal VIN to generate a fine comparison result DF1.

  Here, when the fine comparison module 211 performs a comparison operation between the input signal VIN and the selected reference signal or a usable preamplifier, first, the pre-comparison result DP2 is generated similarly to the coarse comparison module 201, and then, A fine comparison result DF1 is generated. The pre-comparison result DP2 is provided to the next stage pre-switching detection module 222. Based on this, the pre-switching detection module 222 generates a pre-selection signal to be provided to the next-stage fine comparison module. The pre-switching detection module 22P generates a pre-selection signal PSi based on the received pre-comparison result DPi. The fine comparison module 21P receives the pre-selection signal PSi generated by the pre-switching detection module 22P and performs a fine comparison operation.

  It should be noted that the number of fine comparison modules is not fixed, but can be set based on the requirements of the system to which the analog-digital conversion apparatus 200 belongs. The number of fine comparison modules is an integer greater than or equal to at least one.

  The encoder 230 is coupled to the coarse comparison module 201 and the fine comparison modules 211 to 21P, receives the coarse comparison result DC and the fine comparison results DF1 to DFi (i is a positive integer), performs encoding, and obtains an encoding result DOUT. . The encoding result is an analog-digital conversion result corresponding to the input signal VIN.

  With reference to FIG. 3A regarding the implementation method of the rough comparison module 201, FIG. 3A is a schematic diagram of the implementation method of the rough comparison module 201. The rough comparison module 201 includes a control signal CTL, a plurality of comparators CMP1 to CMP3, and a plurality of reference signals CREF11 to CREF13. Reference signals CREF11-CREF13 are coupled to comparators CMP1-CMP3, respectively. The relationship of the voltage amount of the reference signal is as follows: reference signal CREF11 <reference signal CREF12 <reference signal CREF13.

  The comparators CMP1 to CMP3 jointly receive the input signal VIN, determine a time for performing a comparison operation between the input signal VIN and the reference signals CREF11 to CREF13 based on the control signal CTL, and generate comparison results T0 to T2. Referring to FIG. 3B, FIG. 3B shows the delay time from when the comparator is enabled by the control signal CTL to when it is determined that the output result is stable, and the input voltage difference of the compared signal of the corresponding comparator. It is a figure which shows the relationship. As is apparent from FIG. 3, when the input voltage difference of the compared signals received by the comparator is relatively small, the time delay that the comparator requires for the comparison operation is relatively large (the comparison result is generated more slowly). . In contrast, when the input voltage difference of the compared signals received by the comparator is relatively large, the time delay that the comparator requires for the comparison operation is relatively small (comparison results are generated faster).

Referring to FIG. 3A, compared with the relationship diagram of FIG. 3B, when the input signal VIN approaches the reference signal CREF13, the comparison result T2 of the comparator CMP3 is generated at the slowest speed, but the comparison result T0 of the comparator CMP1. Is generated at the fastest speed. That is, in this situation, when the comparison result T0 is determined, the logic states of the comparison results T0 to T2 at this time are the previous comparison results. After the comparison result T2 is determined, the logic state of the comparison results T0 to T2 at this time is a rough comparison result. More specifically, when the pre-comparison result (for example, the comparison result T0) of the comparison result generated by the comparator is determined, only the logic state of the comparison result T0 is determined. However, the logic states of the comparison results T1 and T2 are unknown at this point. Similarly, after the logic state of the comparison result T2 is determined, Ru Tei be determined logic state of the comparison result T1.

Correspondingly, when the input signal VIN approaches the reference signal CREF11, the comparison result T2 of the comparator CMP3 is generated at the fastest speed, and the comparison result T0 of the comparator CMP1 is generated at the slowest speed. That is, in this situation, when the comparison result T2 is determined, the logic state of the comparison results T0 to T2 at this time is used as the previous comparison result. After the comparison result T0 is determined, the logic state of the comparison results T0 to T2 at this time is used as the rough comparison result. More specifically, when the pre-comparison result is determined, only the logic state of the comparison result T2 is determined. However, the logic states of the comparison results T1 and T0 are unknown at this point. Similarly, after the logic state of the comparison result T0 is determined, Ru Tei be determined logic state of the comparison result T1.

  Of course, the rough comparison module 201 described above is not limited to the case where the three comparators CMP1 to CMP3 are used. Referring to FIGS. 4A and 4B, FIGS. 4A and 4B show different implementations of the coarse comparison module 201. In FIG. 4A, reference signals CREF11 and CREF12 are coupled to comparators CMP1 and CMP2, respectively. The relationship between the reference signal voltage amounts is the reference signal CREF11 <reference signal CREF12. The comparators CMP1 and CMP2 jointly receive the input signal VIN, determine the time during which the input signal VIN is compared with the reference signals CREF11 and CREF12 based on the control signal CTL, and generate comparison results T0 and T1.

  In FIG. 4B, reference signals CREF11-CREF17 are coupled to comparators CMP1-CMP7, respectively. The reference signals CREF11 to CREF17 are arranged in order based on an arithmetic series. The reference signal CREF11 has a minimum reference voltage, and the reference signal CREF17 has a maximum reference voltage. The comparators CMP1 to CMP7 jointly receive the input signal VIN, determine the time for performing the comparison operation of the input signal VIN and the reference signals CREF11 to CREF17 based on the control signal CTL, and generate comparison results T0 to T6.

It should be noted that the comparison results T4 to T6 are generated faster than the comparison results T0 to T2 when the input signal VIN is within the range of the reference signals CREF11 to CREF13 in the implementation method of FIG. 4B. The That is, the comparison results T0 to T2 are generated later than the comparison results T4 to T6. That is, when the comparison results T4 to T6 are determined, the logic states of the comparison results T0 to T6 at this time are the previous comparison results. After the comparison results T0 to T2 are determined, the logic states of the comparison results T0 to T6 at this time are rough comparison results. More specifically, when the pre-comparison result is determined, the logic states of the comparison results T4 to T6 are determined. However, the logic state of the comparison results T0 to T3 is unknown at this point. Similarly, after the logic state of the comparison result T0~T2 is determined, Ru Tei be determined logic state of the comparison result T3.

  Referring to FIG. 5, FIG. 5 illustrates an implementation method of the pre-switching detection module according to the embodiment of the present invention. The pre-switching detection module 221 will be described as an example. The pre-switching detection module 221 includes pre-switching detection circuits 510 to 530. Referring to the coarse comparison module 201 of FIG. 4B, the pre-switching detection module 221 is coupled to the comparison results T0 to T2 and T4 to T6 generated by the coarse comparison module 201. The pre-switching detection circuit 510 receives the comparison results T0 and T6. The pre-switching detection circuit 520 receives the comparison results T1 and T5. On the other hand, the pre-switching detection circuit 530 receives the comparison results T2 and T4. Taking the case where the input signal VIN is within the range of the reference signals CREF11 to CREF13 as an example, when the logic state of the comparison results T4 to T6 is determined, the comparison results T0 to T6 are compared as the previous comparison results at this time. Results T0 to T2 and comparison results T4 to T6 affect the pre-switching detection circuits 510 to 530, and generate pre-selection signals PSA1 to PSA3 and PSB1 to PSB3, respectively. In other words, the preselection signal PS1 generated by the pre-switching detection module 221 of the present embodiment is a set of 6-bit signals including the preselection signals PSA1 to PSA3 and PSB1 to PSB3.

  It should be noted that the number of pre-switching detection circuits installed in the pre-switching detection module is determined based on the number of comparators in the previous coarse comparison module (or fine comparison module). When the number of comparators in the previous coarse comparison module (or fine comparison module) is equal to N (N is a positive integer), the number of pre-switching detection circuits installed in the pre-switching detection module is N / 2 (remaining The number is unconditionally rounded down to the quotient).

  Referring to FIG. 6A, FIG. 6A shows a method of implementing the pre-switching detection circuit 600 according to the embodiment of the present invention. Pre-switching detection circuit 600 includes a pre-charge switch circuit 610, buffers BUF1 to BUF4, and a voltage transmission switch circuit 620. The precharge switch circuit 610 receives a reference power supply VDD and is controlled by a control signal CTRL1. The precharge switch circuit 610 is turned on when the control signal CTRL1 is at a logic low-level voltage, charges the potentials of the endpoints PSAb and PSBb to the reference power supply VDD, and ends the precharge operation.

  When the control signal CTRL1 is a logic high-level voltage, the precharge switch circuit 610 is switched off. The buffers BUF1 and BUF2 receive the inverse signal T2b and the comparison result T0 of the comparison result T2 generated by the previous comparison module (coarse comparison module or fine comparison module), respectively (see the schematic diagram of the comparison module in FIG. 6B). Buffers BUF 1 and BUF 2 provide the generated output to voltage transfer switch circuit 620. In the present embodiment, the buffers BUF1 and BUF2 are both inverters.

  The voltage transfer switch circuit 620 determines whether to transmit the output of the buffer BUF2 to the endpoint PSAb based on the output of the buffer BUF1. Further, the voltage transmission switch circuit 620 determines whether or not to transmit the output of the buffer BUF1 to the endpoint PSBb based on the output of the buffer BUF2.

  In the present embodiment, the precharge switch circuit 610 is formed by transistors M1 and M2. The first terminals (eg, sources) of transistors M1 and M2 are coupled to reference power supply VDD. The control terminals (eg, gates) of transistors M1 and M2 are coupled to control signal CTRL1. On the other hand, the second terminals (eg, drains) of transistors M1 and M2 are coupled to endpoints PSAb and PSBb, respectively. A case where the transistors M1 and M2 are P-type transistors will be described as an example. The transistors M1 and M2 are P-type transistors, which are turned on when the control signal CTRL1 is at a logic low level voltage, and perform a precharge operation for charging the end points PSAb and PSBb with respect to the reference power supply VDD.

  Buffers BUF1 and BUF2 are formed by an inverter and are used to drive a parasitic capacitance load. The buffer BUF1 transmits an output signal opposite to the reverse signal T2b to the voltage transmission switch circuit 620. On the other hand, the buffer BUF2 transmits an output signal opposite to the comparison signal T0 to the voltage transmission switch circuit 620. The voltage transfer switch circuit 620 is formed by transistors M3 and M4. A case where the transistors M3 and M4 are N-type transistors will be described as an example. The second terminals (eg, drains) of transistors M3 and M4 are coupled to endpoints PSAb and PSBb, respectively. The control terminals (eg, gates) of transistors M3 and M4 are coupled to the output terminals of buffers BUF1 and BUF2, respectively. The first terminals (eg, sources) of transistors M3 and M4 are coupled to the output terminals of buffers BUF2 and BUF1, respectively.

  The pre-switching detection circuit 600 further includes buffers BUF3 and BUF4 and is used to drive a parasitic capacitance load. The input terminals of buffers BUF3 and BUF4 are coupled to endpoints PSAb and PSBb, respectively. Buffers BUF3 and BUF4 generate pre-selection signals PSA and PSB at these output terminals, respectively.

For details of the operation of the pre-switching detection circuit 600, please refer to FIGS. 6A, 6B, 6C, and 6D simultaneously. 6C and 6D are operation schematic diagrams of a circuit corresponding to the pre-switching detection circuit 600. FIG. First, at time point t0, control signals CTRL1 and CTL1 are both logic low level voltages. Referring to FIG. 6B, the comparison results T0 to T2 and T0b to T2b of the previous comparison module (coarse comparison module or fine comparison module) are all reset to the logic low level voltage. The precharge switch circuit 610 provides the reference power supply VDD to the endpoints PSAb and PSBb and produces preselection signals PSA and PSB that are equal to logic low level voltages (eg, equal to ground voltage). As can be seen from FIG. 6D, the primary reference signal is set within the range of the reference signal 0.25FS to -0.25FS. FS indicates the full-oscillating amplitude range of the analog-digital converter. After the control signals CTRL1 and CTL1 both increase to the logic high level voltage, the above-described precharge operation and the comparator reset mechanism in the previous comparison module are completed.

  Subsequently, referring to FIGS. 6A, 6B, 6C, and 6D simultaneously, a case where the input signal VIN is substantially equal to the reference signal 0.25FS will be described as an example. At this time, the comparators CMP1 to CMP3 are used to compare the input signal VIN with the three reference signals -0.25FS, 0, and 0.25FS. As can be seen from FIG. 6C, at time point t1, the comparison results T0 and T2b increase to a voltage level equal to the intermediate voltage Vcm generated by the corresponding comparator. In this state, the comparison result of the comparator cannot exceed the logic threshold voltage Vlt of the buffers BUF1 and BUF2 of the pre-switching detection circuit 600. Therefore, the outputs of the buffers BUF1 and BUF2 maintain the logic high level voltage as they are, and as a result, the transistors M3 and M4 are not effectively conducted. At this time, the primary reference signal is set within the range of the reference signal 0.25FS to -0.25FS. Subsequently, the comparison result T0 is generated faster than the comparison result T2b. Therefore, at time point t2 (the logic states of the comparison results T0 to T2 and T0b to T2b at this time indicate the previous comparison results), the comparison result T0 exceeds the logic threshold voltage Vlt of the buffer BUF2. The BUF2 generates an output lower than the threshold voltage VTHn of the transistor M4, and the transistor M4 enters a cut-off region.

  Further, the buffer BUF1 continuously receives the comparison result T2b equal to the intermediate voltage Vcm. Therefore, the output of the buffer BUF1 maintains the logic high level voltage as it is, and the transistor M3 is effectively turned on at the time point t2. Thus, an output lower than the threshold voltage VTHn of the transistor M4 generated by the buffer BUF2 is transmitted to the endpoint PSAb via the transistor M3. That is, at the time point t2, the voltage of the end point PSAb is a voltage value lower than the threshold voltage VTHn of the transistor M4. On the other hand, the voltage value of the pre-selection signal PSA generated by the buffer BUF3 changes from the logic low level voltage to the logic high level voltage. The primary reference signal changes to be set in the range of the reference signal 0.5FS to 0 via the multiplexer MUX1 (see FIG. 6D). Thus, the primary reference signal is effectively set based on the previous selection signal.

  At time point t3, the comparison result T2b of the comparator CMP3 in FIG. 6B begins to change as the difference between the input signal VIN and the reference signal 0.25FS varies. Assume that the input signal VIN is slightly smaller than the reference signal 0.25FS. Thereafter, the inverse signal T2b of the comparison result T2 increases to the logic high level voltage. In FIG. 6D, a voltage value that changes with time is indicated by a line segment T2b1. As a result, the output of the buffer BUF1 is reduced to a logic low level voltage. Alternatively, when the input signal VIN is slightly larger than the reference signal 0.25FS, the inverse signal T2b of the comparison result T2 falls to a logic low level voltage. In FIG. 6D, a voltage value that changes with time is indicated by a line segment T2b2. The output of the buffer BUF1 maintains the logic high level voltage as it is. Therefore, based on the description of FIGS. 6A to 6D, the circuit operation relationship among the pre-switching detection circuit, the previous comparison module (coarse comparison module or fine comparison module), and the reference signal can be clearly shown.

  Therefore, the control signals CTRL1 and CTL1 described above may be the same signal.

  Referring to FIGS. 7A and 7B, FIGS. 7A and 7B respectively show different implementation methods of the fine comparison module according to the embodiment of the present invention. 7A, the fine comparison module 710 includes preamplifiers 701 to 70Q and comparators 711 to 71Q. Preamplifiers 701-70Q jointly receive input signal VIN. Preamplifiers 701 to 70Q receive reference signals VREF11 to VREF1Q, respectively. It should be noted that in the present embodiment, the reception signals VREF11 to VREF1Q received by the preamplifiers 701 to 70Q are fixed. Further, the preamplifiers 701 to 70Q receive the preselection signal PS provided by the prestage pre-switching detection module. Further, some of the preamplifiers 701 to 70Q determine whether to enter an enable state based on the received preselection signal PS. The remaining part of the preamplifier is kept in a disabled state.

  The comparators 711 to 71Q respectively perform the pre-encoding generated by the encoder based on the control signal CTL and the coarse comparison result DC (or fine comparison result DF) provided by the coarse comparison module (or fine comparison module) in the previous stage. The result DEN is received. The plurality of comparators are selected from the comparators 711 to 71Q based on the previous encoding result DEN and the control signal CTL, and perform comparison operations. Note that the inputs of comparators 711-71Q are coupled to the outputs of preamplifiers 701-70Q, respectively, but are not connected to input signal VIN and reference signals VREF11-VREF1Q.

  For example, when the primary preamplifiers set by the pre-selection signal PS are the preamplifiers 701 and 702, the preamplifiers 701 and 702 are set as usable primary preamplifiers. Preamplifiers 701 and 702 perform the function of a preamplifier based on the respective voltage differences between input signal VIN and reference signals VREF11 and VREF12. After the pre-encoding result DEN is generated (based on the rough comparison result DC or the fine comparison result DF), if the preamplifier 701 selected by the pre-encoding result is a selected usable preamplifier, the comparator 711 is also selected. Set to the specified comparator. At this time, the comparator 711 actually performs a comparison operation based on the selected preamplifier output result of the usable preamplifier 701.

  In FIG. 7B, the fine comparison module 720 includes comparators 721 to 72J and a selector 730. The selector 730 receives the reference signal VREF and the previous selection signal PS. The selector 730 selects a plurality of reference signals from the reference signal VREF as primary reference signals VREFS1 to VREFSJ based on the previous selection signal PS. Comparators 721-72J are coupled to selector 730 and receive primary reference signals VREFS1-VREFSJ. Further, the comparators 721 to 72J further generate the pre-encoding result DEN generated by the control signal CTL and the coarse comparison result DC (or the fine comparison result DF) provided by the coarse comparison module (or the fine comparison module) in the previous stage. Receive. The plurality of comparators are selected from the comparators 721 to 72J based on the pre-encoding result DEN and the control signal CTL, and perform a comparison operation. A case where the reference signal VREFS1 is the selected reference signal will be described as an example. The comparators 721 to 72J set the comparator 721 as the selected comparator based on the previous encoding result DEN. That is, the comparator 721 compares the selected reference signal VREFS1 and the input signal VIN based on the previous encoding result DEN.

  Next, referring to FIG. 8, FIG. 8 is a flowchart of an analog-digital conversion method according to an embodiment of the present invention. The analog-digital conversion method in this embodiment is as follows. First, an input signal is received, the input signal is compared with a plurality of reference signals, and a pre-comparison result and a rough comparison result are generated in order (S810). Further, a pre-selection signal and a pre-encoding result are generated based on the pre-comparison result and the rough comparison result, respectively (S820). Then, based on the previous selection signal and the previous encoding result, a plurality of primary reference signals are selected from the plurality of reference signals, and the reference signal selected from the primary reference signal is compared with the input signal to generate a fine comparison result. (S830). Similarly, this process is applicable to two adjacent stages of the fine comparison module. The details of each step have been described in the above-described embodiments and implementation methods, and thus will not be described repeatedly here.

  The analog-to-digital conversion device according to the embodiment of the present invention can increase the data conversion speed between analog data and digital data, and can reduce the data conversion time of the analog-to-digital conversion device. Data processing efficiency can be increased.

100, 200 Analog-to-digital converter 101, 102, 103 Comparison module 201 Coarse comparison module 211-21P Fine comparison module 221-22P Pre-switching detection module 120, 230 Encoder 130, 250 Reference signal generator 510-530 Pre-switching detection circuit DEN1 to DEN (i-1) Pre-encoding comparison result DC Coarse comparison result DP, DP to DPi Pre-comparison result VIN Input signal VREF, VREF1 to VREFi, VREFC, CREF11 to CREF17, VR EF11 to VREF1Q Reference signal DF1 to DFi Fine comparison Result DOUT encoding result PS1 to PSi, PSA, PSB, PSA1 to PSA3, PSB1 to PSB3 Preselection signal D1 to Di, T0 to T6, T0b to T2b Comparison result 701 to 70Q Preamplifiers CMP1 to CMP7, 711 to 71Q, 721 to 72J Comparator CTRL1, CTL1, CTL Control signal 610 Precharge switch circuit 620 Voltage transmission switch circuit 730 Selector Vcm Intermediate voltage Vlt Logic threshold voltage VREFS1 to VREFFSJ Primary reference signal PSAb , PSBb Endpoint MUX1, MUX2 Multiplexer VDD Reference power supply BUF1-BUF4 Buffer M1-M4 Transistor t0-t3 Time point S810-S830 Analog-to-digital conversion step

Claims (18)

A coarse comparison module that receives an input signal, compares the input signal with a plurality of first reference signals, and sequentially generates a pre-comparison result and a coarse comparison result;
At least one pre-switching detection module that receives the pre-comparison result and generates a pre-selection signal based on the pre-comparison result;
An encoder coupled to the coarse comparison module and generating a pre-encoding result based on the coarse comparison result;
Coupled to the pre-switching detection module and the encoder, receiving the input signal, the pre-selection signal and the pre-encoding result, and based on the pre-select signal, a plurality of primary reference signals from a plurality of second reference signals And selecting a reference signal to be compared with the input signal from the plurality of primary reference signals based on the pre-encoding result as a selection reference signal, and at least one fine comparison module that generates a fine comparison result. Including
The coarse comparison module is
The coarse comparison module compares the input signal and the plurality of first reference signals to generate an N-bit comparison result, and the plurality of comparison results are converted to the N-bit pre-comparison. Used to provide the result or the coarse comparison result of N bits, where N is an integer greater than 1,
The pre-switching detection module is
A precharge switch circuit that receives a reference power supply and is controlled by a control signal;
A first buffer for receiving an inverse signal of one of the plurality of comparison results;
A second buffer arranged to receive another signal of the comparison result;
Said first, said second output terminal and said first, look including a voltage transfer switch circuit coupled to said second buffer,
The voltage transmission switch circuit is controlled by the output voltage of the first buffer to transmit the output voltage of the second buffer to the first output terminal, and is controlled by the output voltage of the second buffer; An analog-to-digital converter that transmits the output voltage of the first buffer to the second output terminal . The fine comparison module is
A plurality of comparators each receiving the plurality of second reference signals and jointly receiving the input signal, wherein the fine comparison module includes a plurality of primary comparators from the plurality of comparators based on the pre-selection signal. The analog-to-digital converter according to claim 1, wherein at least one of the plurality of primary comparators is selected as a selected comparator based on the result of the previous encoding.   The reference signal received correspondingly by the plurality of primary comparators is the plurality of primary reference signals, respectively, and the reference signal received correspondingly by the selected comparator is the selected reference signal. Analog-to-digital converter. The fine comparison module is
A plurality of comparators, wherein the fine comparison module provides the plurality of primary reference signals to the plurality of comparators based on the pre-selection signal, and at least one from the plurality of comparators based on the pre-encoding result The analog-to-digital converter according to claim 1, wherein one of the two is selected as a selected comparator and a comparison operation is performed.   5. The analog-to-digital converter according to claim 4, wherein the reference signal received correspondingly by the selection comparator is the selection reference signal. 2. The analog-to-digital converter according to claim 1, wherein the precharge switch circuit is turned on based on the control signal and transmits the reference power source to the first output terminal and the second output terminal. The precharge switch circuit is
A first terminal; a second terminal; and a control terminal, wherein the first terminal receives the reference power supply, the control terminal receives the control signal, and the second terminal is the first output terminal. A first transistor coupled to
A first terminal; a second terminal; and a control terminal, wherein the first terminal receives the reference power supply, the control terminal receives the control signal, and the second terminal is the second output terminal. 7. The analog-to-digital converter according to claim 6, further comprising: a second transistor coupled to the first and second transistors.   8. The analog-to-digital converter according to claim 7, wherein the first and second transistors are P-type transistors. The voltage transmission switch circuit is
A first terminal; a second terminal; and a control terminal, wherein the second terminal is coupled to the first output terminal, the control terminal is coupled to an output terminal of the first buffer, and the first terminal is A third transistor coupled to the output terminal of the second buffer;
A first terminal; a second terminal; and a control terminal, wherein the second terminal is coupled to the second output terminal, the control terminal is coupled to an output terminal of the second buffer, and the first terminal is The analog-to-digital converter according to claim 7, further comprising: a fourth transistor coupled to an output terminal of the first buffer.   The analog-digital conversion apparatus according to claim 9, wherein the third and fourth transistors are N-type transistors.   7. The analog-to-digital converter according to claim 6, wherein the first and second buffers are first and second inverters, respectively. The pre-switching detection module further comprises:
A third buffer having an input terminal coupled to the first output terminal and generating one bit of the pre-selection signal;
7. The analog-to-digital converter according to claim 6, further comprising: a fourth buffer having an input terminal coupled to the second output terminal and generating another bit of the pre-selection signal.   13. The analog-to-digital converter according to claim 12, wherein the third and fourth buffers are third and fourth inverters, respectively.   The analog-digital conversion apparatus according to claim 1, wherein the encoder further generates an analog-digital conversion result based on the rough comparison result and the fine comparison result. A step of receiving an input signal, comparing the input signal and a plurality of first reference signal to generate a pre-comparison result and the coarse comparison result in order,
A step of based on said prior comparison result and the crude comparison result, generates a pre-selection signal and prior to encoding result respectively,
A plurality of primary reference signals are selected from a plurality of second reference signals based on the pre-selection signal, and a reference signal to be compared with the input signal is selected from the plurality of primary reference signals based on the pre-encoding result. a selection reference signal Te, and generating a fine comparison result,
The step of comparing the input signal and the plurality of first reference signals to sequentially generate the pre-comparison result and the rough comparison result,
Each comparing the first reference signal said input signal and of said plurality, the coarse comparison result of the previous comparison result of N bits and N bits comprises generating sequentially, N is Ri integer greater than 1 der ,
Generating the pre-selection signal and the pre-encoding result based on the pre-comparison result and the coarse comparison result, respectively;
Reception of a reference power supply is controlled by a control signal, receiving an inverse signal of one of the plurality of comparison results and another signal of the comparison result;
An analog-to-digital conversion method of outputting a signal based on the reverse signal by controlling the signal based on the other signal and outputting a signal based on the other signal by controlling the signal based on the reverse signal . Selecting the plurality of primary reference signals from the plurality of second reference signals based on the pre-selection signal; selecting the selection reference signal from the plurality of primary reference signals based on the pre-encoding result; Said step of generating said fine comparison result in comparison with an input signal,
Based on the previous selection signal, selecting a plurality of primary comparator from a plurality of comparators,
Based on the prior encoding result, the the at least one selected selected comparator from the primary comparator, and a step of performing a comparison operation, said plurality of comparators, receiving the plurality of second reference signals, respectively, 16. The analog-to-digital conversion method according to claim 15, wherein the input signal is received jointly. Selecting the plurality of primary reference signals from the plurality of second reference signals based on the pre-selection signal; selecting the selection reference signal from the plurality of primary reference signals based on the pre-encoding result; Said step of generating said fine comparison result in comparison with an input signal,
And providing, based on the previous selection signal, the plurality of primary reference signals to a plurality of comparators,
Based on the prior encoding result, the a plurality of selected comparator to select at least one comparator, the analog of claim 15 further comprising the step of performing a comparison result - digital conversion method.   16. The analog-to-digital conversion method according to claim 15, wherein the rough-comparison result and the fine-comparison result are encoded to generate an analog-to-digital conversion result.

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