CN101662285B - Low power consumption folded interpolating analog-to-digital converter for sharing sub-converters - Google Patents

Low power consumption folded interpolating analog-to-digital converter for sharing sub-converters Download PDF

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Publication number
CN101662285B
CN101662285B CN2009101954567A CN200910195456A CN101662285B CN 101662285 B CN101662285 B CN 101662285B CN 2009101954567 A CN2009101954567 A CN 2009101954567A CN 200910195456 A CN200910195456 A CN 200910195456A CN 101662285 B CN101662285 B CN 101662285B
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circuit
output
folding electric
electric circuit
comparator
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CN101662285A (en
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任俊彦
林俪
陆焱
王明硕
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Fudan University
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Fudan University
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Abstract

The invention belongs to the integrated circuit technical field, and particularly relates to a low power consumption folded interpolating analog-to-digital converter for sharing sub-converters. The analog-to-digital converter is composed of a track and hold circuit, a reference voltage resistor string, a pre-enlarging circuit, N-grade (N is more than 1) cascade folded circuit, an interpolating circuit, a comparator and a coding circuit. In the invention, according to a part of output of the pre-enlarging circuit and the first N-1-grade folded circuit quantitative information originally provided by a crude converter can be obtained, thus saving power consumption of crude analog pre-processing circuit; and meanwhile all the quantitative results are generated on the same signal channel, thus inhibiting quantitative error between a fine converter and a crude converter. The converter has saved hardware expense and low circuit power consumption.

Description

The low power consumption folded interpolating analog to digital converter that one seed transducer is shared
Technical field
The invention belongs to technical field of integrated circuits, be specifically related to a kind of low power consumption folded interpolating analog to digital converter that suppresses quantization error between the sub-transducer of folded interpolating A/D converter.
Background technology
Folded interpolating A/D converter structural representation commonly used is as shown in Figure 1; Mainly constitute by track and hold circuit 10, reference voltage resistance string 11, thick sub-transducer 12, thin sub-transducer 13 and coding circuit 14; Wherein, Thick sub-transducer is made up of preparatory amplifying circuit of thick son 120 and thick sub-comparator 121, and thin sub-transducer is made up of the preparatory amplifying circuit of thin son 130, folding electric circuit 131, interpolating circuit 132 and thin sub-comparator 133.For the folded interpolating A/D converter of a N bit, Fig. 2 is its output sketch map.What thin sub-transducer was exported is the circulating temperature sign indicating number, can't represent the transformation result in the whole range ability, and the quantitative information of low N-M bit can only be provided, and therefore, needs thick sub-transducer to confirm the quantitative information of high M bit.Point of quantification 20 in the dashed circle; It is the input point that thick sub-transducer and thin sub-transducer all need quantize; Can see by structure shown in Figure 1; Thick sub-transducer and thin sub-transducer are to be quantized by two parallel passages in fact, and when having mismatch in two signal paths, both quantized result will produce deviation.Fig. 3 is the sketch map that quantizes deviation, and the output that wherein thick son quantizes is 3 bit thermometer codes, and the output that thin son quantizes is 4 bit circulating temperature sign indicating numbers; Quantize 000 and 001 place at thick son; Do not have quantization error between the two, behind coding, analog to digital converter output is normal; Locate in thick careful sub-quantization error 1 (30), there is error in both for the quantification of same point, and shown in dash area, the input that is in dash area can produce frame hopping, and dash area thick sub-quantized result originally should be 011, and actual be 111; Locate in thick careful sub-quantization error 2 (31), have the frame hopping phenomenon equally, dash area thick sub-quantized result originally should be 011, and actual be 001.
The paper " A Wide Input Bandwidth 7-bit 300-MSample/s Folding and Current-Mode InterpolatingADC " that Yunchu Li in 2003 and Edgar S á nchez-Sinencio deliver on IEEE J.Solid-State Circuits has proposed a kind of method that suppresses thick sub-transducer and thin sub-transducer quantization error.Fig. 4 is the sketch map of thick sub-transducer input point of quantification, adopted the method in the document after, thick sub-point of quantification 40 is by original 2 M-1+ 1 is increased to 2 MIndividual, for the common point of quantification of each thick careful son, thick sub-transducer has provided certain error margin 41, decides final quantized result by the quantized result of thin sub-transducer.This method can effectively suppress thick sub-transducer and thin sub-transducer quantization error, but its cost is more hardware spending and power consumption consumption.
Summary of the invention
The objective of the invention is to propose a kind of hardware spending and economize the folded interpolating A/D converter that circuit power consumption is low.
The folded interpolating A/D converter that the present invention proposes; It is the low power consumption folded interpolating analog to digital converter that a seed transducer is shared; This analog to digital converter adopts the folding electric circuit of N (N＞1) level cascade; Part output according to preparatory amplifying circuit and preceding N-1 level folding electric circuit can obtain script by the quantitative information that thick sub-transducer provides, and has saved thick submodule and has intended the pre-process circuit power consumed.Simultaneously, all quantized result all are on same signal path, to produce, and can suppress the quantization error between thick careful sub two sub-transducers, are a kind of low power consumption folded interpolating analog-digital converter structures that suppresses quantization error between the sub-transducer.
Particularly; The folded interpolating A/D converter that the present invention proposes is formed by connecting track and hold circuit 50, reference voltage resistance string 51, preparatory amplifying circuit 52, N level cascade folding electric circuit 53, interpolating circuit 54, comparator 55 and coding circuit 56; Compare with original folded interpolating A/D converter; Omitted thick submodule and intended pre-process circuit, amplifying circuit and preceding N-1 level folding electric circuit all have part output to be directly connected to comparator in advance.Wherein, analog input signal is through the track and hold circuit signal that is maintained; The reference level that inhibit signal and reference voltage resistance string produce is as the input signal of preparatory amplifying circuit, and amplifying circuit is output as the difference amplifying signal between inhibit signal and the reference level in advance; The output signal of amplifying circuit is the input signal of first order folding electric circuit in advance, and some of them output signal directly becomes the input signal of comparator; The output signal of first order folding electric circuit is the input signal of second level folding electric circuit, and some of them output signal directly becomes the input signal of comparator; The rest may be inferred, and the output signal of N-1 level folding electric circuit is the input signal of N level folding electric circuit, and some of them output signal directly becomes the input signal of comparator; The input signal of the interpolating circuit that the output signal of N level folding electric circuit becomes, the output signal of interpolating circuit is connected to comparator; The output signal of comparator obtains the binary system output code of analog to digital converter through behind the coding of coding circuit.
For N level cascade folding electric circuit, the collapse factors of first order folding electric circuit is F 1, total N 1Individual folding amplifier; The collapse factors of second level folding electric circuit is F 2, total N 2Individual folding amplifier; The rest may be inferred, and the collapse factors of N level folding electric circuit is F N, total N NIndividual folding amplifier.Total collapse factors of this analog to digital converter is F, satisfies relational expression:
F＝F 1×F 2×…×F N (1)
The folding amplifier number N of folding electric circuits at different levels i(1≤i≤N-1), satisfy relational expression:
N i＝F i+1N i+1 (2)
The 1st grade of output number q that is directly connected to comparator to N-1 level folding electric circuit 1(1≤i≤N-1) be:
q i＝F i+1 (3)
For i level folding electric circuit, every at a distance from N I+1-1 output is got an output and is connected to comparator.
The number of prime amplifier is P, satisfies relational expression:
P＝F 1×N 1 (4)
The output number p that prime amplifier is directly connected to comparator is:
p＝F 1 (5)
And it is every at a distance from N 1-1 output is got an output and is connected to comparator.
The folded interpolating A/D converter hardware spending that the present invention proposes is economized; Circuit power consumption is low; Part output according to preparatory amplifying circuit and preceding N-1 level folding electric circuit can obtain script by the quantitative information that thick sub-transducer provides, and has saved thick submodule and has intended the pre-process circuit power consumed.Simultaneously, all quantized result all are on same signal path, to produce, and can suppress the quantization error between thick careful sub two sub-transducers.
Description of drawings
Fig. 1 shows the folded interpolating A/D converter structural representation.
Fig. 2 shows folded interpolating A/D converter output sketch map.
Fig. 3 shows that thick son quantizes and thin sub-quantization error sketch map.
Fig. 4 shows a kind of sketch map that suppresses thick son quantification and thin sub-quantization error method.
Fig. 5 shows that sub-transducer shares the folded interpolating A/D converter sketch map.
Fig. 6 shows the analog input and output sketch map of the shared folded interpolating A/D converter of sub-transducer.
Label 10 expression track and hold circuits among the figure, 11 expression reference voltage resistance string, the thick sub-transducer of 12 expressions, the thick son of 120 expressions is amplifying circuit in advance; The thick sub-comparator of 121 expressions, the thin sub-transducer of 13 expressions, the thin son of 130 expressions is amplifying circuit in advance, 131 expression folding electric circuits; 132 expression interpolating circuits, the thin sub-comparator of 133 expressions, 14 presentation code circuit, the point that 20 thick sub-transducers of expression and thin sub-transducer quantize simultaneously; The thick sub-transducer input point of quantification of thick careful sub-quantization error 2,40 expressions of thick careful sub-quantization error 1,31 expression of 30 expressions, the thick careful sub-quantization error tolerance limit of 41 expressions; 50 expression track and hold circuits, 51 expression reference voltage resistance string, the preparatory amplifying circuit of 52 expressions, 53 expression N level cascade folding electric circuits; 530 expression first order folding electric circuits, 531 expression second level folding electric circuits, 532 expression N level folding electric circuits; 54 expression interpolating circuits, 55 expression comparators, 56 presentation code circuit; The preparatory amplifying circuit output of 60 expressions unfolded waveform, the folding waveform of 61 expression first order folding electric circuit outputs, the folding waveform of 62 expression second level folding electric circuit outputs; The analog input point that the thick sub-transducer of 63 expressions need quantize, 64 expression first order folding electric circuits directly output to the point of quantification of comparator, and the preparatory amplifying circuit of 65 expressions directly outputs to the point of quantification of comparator.
Embodiment
Further describe the present invention below in conjunction with accompanying drawing.
Fig. 5 has shown the shared folded interpolating A/D converter of sub-transducer that the present invention proposes, and is made up of track and hold circuit 50, reference voltage resistance string 51, preparatory amplifying circuit 52, N level cascade folding electric circuit 53, interpolating circuit 54, comparator 55 and coding circuit 56.Its operation principle is:
(1) analog input signal is through track and hold circuit 50 signal that is maintained.
(2) reference level of inhibit signal and reference voltage resistance string 51 generations is as the input signal of preparatory amplifying circuit 52; Amplifying circuit is output as the difference amplifying signal between inhibit signal and the reference level in advance; The output signal of amplifying circuit is the input signal of folding electric circuit 53 in advance, and is wherein, every at a distance from N 1-1 output is got an output and is connected to comparator 55, exports the input signal that signal directly becomes comparator 55 for p altogether.
(3) input signal of first order folding electric circuit 530 is the output signal of preparatory amplifying circuit, and the output signal of first order folding electric circuit is the input signal of second level folding electric circuit 531, and is wherein, every at a distance from N 2-1 output is got an output and is connected to comparator 55, altogether q 1Individual output signal directly becomes the input signal of comparator 55.
(4) input signal of second level folding electric circuit 531 is the output signal of first order folding electric circuit 530, and the output signal of second level folding electric circuit is the input signal of third level folding electric circuit, and is wherein, every at a distance from N 3-1 output is got an output and is connected to comparator 55, altogether q 2Individual output signal directly becomes the input signal of comparator 55.
(5) the rest may be inferred, and the output signal of N-1 level folding electric circuit is the input signal of N level folding electric circuit 532, wherein, every at a distance from N N-1 output is got an output and is connected to comparator 55, altogether q N-1Individual output signal directly becomes the input signal of comparator 55.
The output signal of (6) N level folding electric circuits becomes the input signal of interpolating circuit 54, and the output signal of interpolating circuit is connected to comparator 55.
(7) the output signal of comparator 55 obtains the binary system output code of analog to digital converter through behind the coding of coding circuit 56.
Fig. 6 has shown the analog input and output sketch map of the shared folded interpolating A/D converter of sub-transducer that the present invention proposes.In this example, adopt the two-stage cascade folding electric circuit, first order collapse factors is F 1, second level collapse factors is 3.Output waveform 60 unfoldeds of preparatory amplifying circuit, the output waveform 61 of first order folding electric circuit has been carried out F 1Inferior folding, the output waveform 62 of second level folding electric circuit has been carried out 3F 1Inferior folding.According to the method that Yunchu Li and Edgar S á nchez-Sinencio proposed in 2003, the analog input point 63 that thick sub-transducer need quantize is shown in dashed circle.These analog input points can be mapped on the output waveform of first order folding electric circuit 64.We can obtain the quantitative information that provided by thick sub-transducer according to the output signal of first order folding electric circuit.Yet; First order folding electric circuit output waveform also circulates; The mapping point that appears on rising edge and the trailing edge can be distinguished; But can't distinguish for any appearing between the mapping point that the Y shaft position is identical on the different rising edges, same situation also occurs in the identical mapping point of Y shaft position on the different trailing edges.Therefore, we can distinguish different risings and trailing edge according to the output 65 of preparatory amplifying circuit.Like this, the quantitative information of thick sub-transducer can be provided by the part output of preparatory amplifying circuit and folding electric circuit fully.
The preparatory amplifying circuit 52 that the sub-transducer that the present invention proposes is shared folded interpolating A/D converter corresponds respectively to preparatory amplifying circuit 130 of the thin son of folded interpolating A/D converter and folding electric circuit 131 among Fig. 1 with folding electric circuit 53; I.e. partial circuit output with thin sub-transducer has obtained the quantized result of thick sub-transducer, and has no the additional hardware expense.All quantized result all produce on same signal path, so this structure has suppressed the quantization error between the thick careful sub-transducer when saving power consumption.

Claims (1)

1. the shared low power consumption folded interpolating analog to digital converter of a seed transducer is characterized in that being formed by connecting track and hold circuit (50), reference voltage resistance string (51), preparatory amplifying circuit (52), N level cascade folding electric circuit (53), interpolating circuit (54), comparator (55) and coding circuit (56); Wherein, analog input signal is through the track and hold circuit signal that is maintained; The reference level that inhibit signal and reference voltage resistance string produce is as the input signal of preparatory amplifying circuit, and amplifying circuit is output as the difference amplifying signal between inhibit signal and the reference level in advance; The output signal of amplifying circuit is the input signal of first order folding electric circuit in advance, and is wherein every at a distance from N 1-1 output is got an output and is connected to comparator (55), exports the input signal that signal directly becomes comparator (55) for p altogether; The output signal of first order folding electric circuit is the input signal of second level folding electric circuit, and is wherein every at a distance from N 2-1 output is got an output and is connected to comparator (55), altogether q 1Individual output signal directly becomes the input signal of comparator (55); The rest may be inferred, and the output signal of N-1 level folding electric circuit is the input signal of N level folding electric circuit, wherein every at a distance from N N-1 output is got an output and is connected to comparator (55), altogether q N-1Individual output signal directly becomes the input signal of comparator (55); The input signal of the interpolating circuit that the output signal of N level folding electric circuit becomes, the output signal of interpolating circuit is connected to comparator; The output signal of comparator obtains the binary system output code of analog to digital converter through behind the coding of coding circuit;
Wherein, p=F 1, N i=F I+1N I+1, q i=F I+1, 1≤i≤N-1; F 1Be the collapse factors of first order folding electric circuit, N 1Amplifier number for first order folding electric circuit; F 2Be the collapse factors of second level folding electric circuit, N 2Amplifier number for second level folding electric circuit; The rest may be inferred, F NBe the collapse factors of N level folding electric circuit, N NIt is the amplifier number of N level folding electric circuit.
CN2009101954567A 2009-09-10 2009-09-10 Low power consumption folded interpolating analog-to-digital converter for sharing sub-converters Expired - Fee Related CN101662285B (en)

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TWI462487B (en) * 2011-12-23 2014-11-21 Ind Tech Res Inst Analog to digital converting apparatus and method thereof
CN102611450B (en) * 2012-03-15 2014-11-05 西安交通大学 Signal predication folding and interpolating ADC (Analog to Digital Converter) method based on power spectrum estimation
CN106656189B (en) * 2016-12-26 2020-04-21 中国科学院微电子研究所 Multi-stage folding interpolation type analog-to-digital converter and decoding method thereof

Citations (1)

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Publication number Priority date Publication date Assignee Title
CN101047386A (en) * 2007-03-15 2007-10-03 复旦大学 6-bit 600 MHz sample frequency folding interpolation A/D converter

Patent Citations (1)

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Publication number Priority date Publication date Assignee Title
CN101047386A (en) * 2007-03-15 2007-10-03 复旦大学 6-bit 600 MHz sample frequency folding interpolation A/D converter

Non-Patent Citations (2)

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Title
Cheng Chen, JuYan Ren.An 8-bit 200-MSample/s Folding and Interpolating ADC in 0.25mm2.《Analog Integrated Circuits and Signal Processing》.2006,203-206. *
朱樟明等.嵌入式折叠内插式CMOS模/数转换器设计.《固体电子学研究与进展》.2004,第24卷(第3期),322-326. *

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