US20090040087A1 - Data weighted average circuit and dynamic element matching method - Google Patents
Data weighted average circuit and dynamic element matching method Download PDFInfo
- Publication number
- US20090040087A1 US20090040087A1 US12/187,869 US18786908A US2009040087A1 US 20090040087 A1 US20090040087 A1 US 20090040087A1 US 18786908 A US18786908 A US 18786908A US 2009040087 A1 US2009040087 A1 US 2009040087A1
- Authority
- US
- United States
- Prior art keywords
- output code
- circuit
- input signal
- circuit according
- lookup table
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
- H03M1/0617—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence
- H03M1/0634—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence by averaging out the errors, e.g. using sliding scale
- H03M1/0656—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence by averaging out the errors, e.g. using sliding scale in the time domain, e.g. using intended jitter as a dither signal
- H03M1/066—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence by averaging out the errors, e.g. using sliding scale in the time domain, e.g. using intended jitter as a dither signal by continuously permuting the elements used, i.e. dynamic element matching
- H03M1/0665—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence by averaging out the errors, e.g. using sliding scale in the time domain, e.g. using intended jitter as a dither signal by continuously permuting the elements used, i.e. dynamic element matching using data dependent selection of the elements, e.g. data weighted averaging
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/66—Digital/analogue converters
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M3/00—Conversion of analogue values to or from differential modulation
- H03M3/30—Delta-sigma modulation
- H03M3/50—Digital/analogue converters using delta-sigma modulation as an intermediate step
- H03M3/502—Details of the final digital/analogue conversion following the digital delta-sigma modulation
Definitions
- the invention relates to a data weighted average circuit, which is applied to a data conversion system such as a sigma-delta modulator (SDM) or a digital-to-analog converter (DAC).
- a data conversion system such as a sigma-delta modulator (SDM) or a digital-to-analog converter (DAC).
- SDM sigma-delta modulator
- DAC digital-to-analog converter
- a multibit quantizer needs to include a corresponding number of bits only to be linear, whereas the linearity of a multibit DAC has to be greater than the integral linearity of the SDM.
- SNR signal-to-noise ratio
- a 3-bit (8-level) DAC includes 7 digital-to-analog converting (D/A converting) cells, each of which includes one capacitor C S .
- the mismatch between the capacitors C S has to be low enough for achieving a high linearity.
- previous paper has proposed a method of dynamic selecting capacitors of the DAC cells, which moves the distortion caused by the mismatch out of the signal band. This is called dynamic element matching.
- an object of the invention is to provide a data weighted average circuit, using a lookup table to speed up circuit operation with operation delays not affected by various orders of the data weighted average circuit and various bit-widths of input data.
- the data weighted average circuit of the invention comprises: a lookup unit comprising a lookup table for receiving both a input signal and a second output code and generating a first output code according to the lookup table; and, a storage unit for receiving the first output code and updating the second output code according to a control signal.
- Another object of the invention is to provide a dynamic element matching method for selecting a plurality of D/A converting cells according to an input signal, the method comprising: retrieving a first output code from a predetermined lookup table according to the input signal and a second output code; and, updating the second output code according to a control signal and the first output code, wherein the second output code is used to select the plurality of D/A converting cells.
- a feature of the invention is that the lookup table is employed to retrieve the output of the data weighted average circuit, thereby suitable for various orders and various bit widths of the data weighted average circuit. If the order of the data weighted average circuit does not correspond to the bit width of the input data, with the same hardware configuration and circuit complexity, only the contents of the lookup table embedded in either the lookup unit or the lookup logic circuit need to be modified, thus capable of speeding up circuit operation and reducing operation delay.
- FIG. 1 is a block diagram of a data weighted average circuit according to a first embodiment of the invention.
- FIG. 2 is a block diagram of a data weighted average circuit according to a second embodiment of the invention.
- FIG. 3 is an example showing a content of a lookup table embedded in the lookup logic circuit of FIG. 2 .
- all possible outputs of a data weighted average circuit with a specific order and a specific bit width are pre-stored in an embedded lookup table.
- a lookup unit 110 or a lookup logic circuit 210 retrieves a corresponding output from the lookup table.
- the operation speed is significantly increased and the operation delay is not affected by various orders of the data weighted average circuit and various bit-widths of input data.
- FIG. 1 is a block diagram of a data weighted average circuit according to a first embodiment of the invention.
- a data weighted average circuit 100 of the invention includes a lookup unit 110 and a set of D flip-flops 120 .
- the number of D flip-flops in the set of D flip-flops 120 is equal to the number of the bit width of the output M ⁇ 6:0> of the lookup unit 110 .
- a backend circuit of the invention is equipped with 3-bit DAC with 7 D/A converting cells.
- the number of D flip-flops in the set of D flip-flops 120 is equal to 7.
- the lookup unit 110 with a lookup table is embedded in the data weighted average circuit 100 .
- an output Din ⁇ 6:0> i.e., a thermometer code
- the lookup unit 110 retrieves a corresponding output M ⁇ 6:0> from the lookup table.
- the Q outputs (Dout ⁇ 6:0>) simultaneously take on the states of the D inputs (Din ⁇ 6:0>) according to a control signal (e.g., at the moment of a rising clock edge).
- FIG. 2 is a block diagram of a data weighted average circuit according to a second embodiment of the invention.
- FIG. 3 is an example showing a content of a lookup table embedded in the lookup logic circuit of FIG. 2 .
- a data weighted average circuit 200 of the invention includes a lookup logic circuit 210 , a set of D flip-flops 120 and a pointer holding and generating circuit 230 .
- the pointer holding and generating circuit 230 is inserted in the data weighted average circuit 200 .
- the pointer holding and generating circuit 230 includes a multiplexer 231 , a set of D flip-flops 232 and a pointer decoder 233 .
- a lookup table (please refer to FIG. 3 ) is embedded in the lookup logic circuit 210 .
- the lookup logic circuit 210 retrieves a corresponding output M′ ⁇ 6:0> from the lookup table.
- the architecture and operations of the set of D flip-flops 120 are similar to those described in FIG. 1 and therefore the reiteration is omitted.
- a bit number of a specific bit set to 1 corresponds to the first D/A converting cell number for the next selection.
- the lookup logic circuit 210 Assuming that a pointer has a value of “0000100” and an input Din ⁇ 6:0> is equal to “0000111”, the lookup logic circuit 210 generates an output M′ ⁇ 6:0> of “0011100”. Therefore, the selected D/A converting cell numbers are 3, 4 and 5. A special case is that in which the input Din ⁇ 6:0> has a value of “0000000” and then no D/A converting cell will be selected. Accordingly, a current pointer value has to be held or saved until the next input arrives. This embodiment implements this function by using the multiplexer 231 and the set of D flip-flops 232 .
- the multiplexer 231 selects one value from two values of channel one and channel zero to be an output. If Din ⁇ 6:0> has a value of “0000000”, the value Y ⁇ 6:0> (the previous output of the lookup logic circuit 210 ) of channel one is selected for the output X ⁇ 6:0>. If there is a bit within Din ⁇ 6:0> not equal to zero, the value M′ ⁇ 6:0> of channel zero is selected for the output X ⁇ 6:0>.
- the architecture and operations of the set of D flip-flops 232 are the same as those of the set of D flip-flops 120 and therefore will not be described herein.
- the number of the D flip-flops in the set of D flip-flops 232 are equal to the number of the bit width (i.e., equal to 7) of X ⁇ 6:0>. Similar to the set of D flip-flops 120 , each D flip-flop in the set of D flip-flops 232 has their Q outputs (Y ⁇ 6:0>) simultaneously take on the state of the D inputs (X ⁇ 6:0>) according to a common control signal (e.g., at the moment of a rising clock edge). Finally, the pointer 233 decodes the output Y ⁇ 6:0> of the set of D flip-flops 232 into a pointer.
- each set of D flip-flops ( 120 , 232 ) can be replaced by a 7-bit register.
- the lookup unit 110 or the lookup logic circuit 210 can be implemented by using a read-only memory or a combinational logic circuit, the complexity of both circuits ( 110 , 210 ) are different in practice. Obviously, circuit complexity of the lookup logic circuit 210 with two inputs of Din ⁇ 6:0> and a pointer is relatively lower. By contrast, circuit complexity of the lookup logic circuit 110 with two inputs of Din ⁇ 6:0> and Dout ⁇ 6:0> is relatively higher. Further, the invention is suitable for various orders and various bit widths of the data weighted average circuit. For example, regarding the lookup table of FIG. 3 , its values are suitable for 1-order data weighted average circuit and the bit width equal to 7.
- the invention needs to modify the contents of the lookup table only without changing other hardware configuration or complexity. Thus, operation speed is not affected. As the number of orders of the data weighted average circuit gets higher or the bit width gets wider, the operation speed difference between the invention and the prior art becomes bigger.
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Compression, Expansion, Code Conversion, And Decoders (AREA)
- Analogue/Digital Conversion (AREA)
Abstract
Description
- This application claims the benefit of the filing date of Taiwan Application Ser. No. 096129496, filed on Aug. 10, 2008, the content of which is incorporated herein by reference.
- 1. Field of the Invention
- The invention relates to a data weighted average circuit, which is applied to a data conversion system such as a sigma-delta modulator (SDM) or a digital-to-analog converter (DAC).
- 2. Description of the Related Art
- In general, there are three common approaches to increasing the resolution of SDMs, i.e., reducing the quantization noise within the signal bandwidth. The first approach is to increase the over-sampling ratio (OSR). The second approach is to increase the number of orders of SDMs. The third approach is to increase the resolution of quantizers, i.e., increasing the number of bits. The third approach directly reduces the overall quantization noise to achieve a higher resolution. A multibit quantizer needs to include a corresponding number of bits only to be linear, whereas the linearity of a multibit DAC has to be greater than the integral linearity of the SDM. For example, a 3-order 2-bit SDM with a 14-bit signal-to-noise ratio (SNR) includes a 2-bit DAC with linearity of at least a 14-bit level.
- For example, a 3-bit (8-level) DAC includes 7 digital-to-analog converting (D/A converting) cells, each of which includes one capacitor CS. The mismatch between the capacitors CS has to be low enough for achieving a high linearity. However, in practical, it is not realizable since the capacitors CS need to have large capacitance. Thus, previous paper has proposed a method of dynamic selecting capacitors of the DAC cells, which moves the distortion caused by the mismatch out of the signal band. This is called dynamic element matching. Nys et, al, “A 19-Bit Low-Power Multibit Sigma-Delta ADC Based on Data Weighted Averaging,” IEEE Journal of Solid-State Circuits, VOL. 32, No. 7, July 1997, discloses a circuit architecture of a Sigma-Delta ADC. And, Baird et, al, “Linearity Enhancement of Multibit ΔΣA/D and D/A Converters Using Data Weighted Averaging,” IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, VOL. 42, No. 12, December 1995, discloses a method of linearity enhancement.
- In view of the above-mentioned problems, an object of the invention is to provide a data weighted average circuit, using a lookup table to speed up circuit operation with operation delays not affected by various orders of the data weighted average circuit and various bit-widths of input data.
- To achieve the above-mentioned object, the data weighted average circuit of the invention comprises: a lookup unit comprising a lookup table for receiving both a input signal and a second output code and generating a first output code according to the lookup table; and, a storage unit for receiving the first output code and updating the second output code according to a control signal.
- Another object of the invention is to provide a dynamic element matching method for selecting a plurality of D/A converting cells according to an input signal, the method comprising: retrieving a first output code from a predetermined lookup table according to the input signal and a second output code; and, updating the second output code according to a control signal and the first output code, wherein the second output code is used to select the plurality of D/A converting cells.
- A feature of the invention is that the lookup table is employed to retrieve the output of the data weighted average circuit, thereby suitable for various orders and various bit widths of the data weighted average circuit. If the order of the data weighted average circuit does not correspond to the bit width of the input data, with the same hardware configuration and circuit complexity, only the contents of the lookup table embedded in either the lookup unit or the lookup logic circuit need to be modified, thus capable of speeding up circuit operation and reducing operation delay.
- Further scope of the applicability of the present invention will become apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.
- The present invention will become more fully understood from the detailed description given hereinbelow and the accompanying drawings which are given by way of illustration only, and thus are not limitative of the present invention, and wherein:
-
FIG. 1 is a block diagram of a data weighted average circuit according to a first embodiment of the invention. -
FIG. 2 is a block diagram of a data weighted average circuit according to a second embodiment of the invention. -
FIG. 3 is an example showing a content of a lookup table embedded in the lookup logic circuit ofFIG. 2 . - The data weighted, average circuit and the dynamic element matching method of the invention will be described with reference to the accompanying drawings.
- According to the invention, all possible outputs of a data weighted average circuit with a specific order and a specific bit width are pre-stored in an embedded lookup table. According to two sets of input data, a
lookup unit 110 or alookup logic circuit 210 retrieves a corresponding output from the lookup table. According to the invention, without data conversion between thermometer codes and binary codes and without operations of adders, the operation speed is significantly increased and the operation delay is not affected by various orders of the data weighted average circuit and various bit-widths of input data. - Hereinafter, each back-end circuit of two embodiments of the invention is described with a 3-bit (N=3) DAC with 7 D/A converting cells. It should be understood, however, that the invention is not limited to these particular numbers described above.
-
FIG. 1 is a block diagram of a data weighted average circuit according to a first embodiment of the invention. Referring toFIG. 1 , a data weightedaverage circuit 100 of the invention includes alookup unit 110 and a set of D flip-flops 120. In this embodiment, the number of D flip-flops in the set of D flip-flops 120 is equal to the number of the bit width of the output M<6:0> of thelookup unit 110. Take, as an example, a backend circuit of the invention is equipped with 3-bit DAC with 7 D/A converting cells. The number of D flip-flops in the set of D flip-flops 120 is equal to 7. According to this embodiment, thelookup unit 110 with a lookup table is embedded in the data weightedaverage circuit 100. According to an output Din<6:0> (i.e., a thermometer code) of a quantizer (not shown) and an output Dout<6:0> of the set of D flip-flops 120 during the previous clock cycle, thelookup unit 110 retrieves a corresponding output M<6:0> from the lookup table. Afterward, for all D flip-flops in the set of D flip-flops 120, the Q outputs (Dout<6:0>) simultaneously take on the states of the D inputs (Din<6:0>) according to a control signal (e.g., at the moment of a rising clock edge). -
FIG. 2 is a block diagram of a data weighted average circuit according to a second embodiment of the invention.FIG. 3 is an example showing a content of a lookup table embedded in the lookup logic circuit ofFIG. 2 . Referring toFIG. 2 , a data weightedaverage circuit 200 of the invention includes alookup logic circuit 210, a set of D flip-flops 120 and a pointer holding and generatingcircuit 230. A difference between the first and the second embodiments is that the pointer holding and generatingcircuit 230 is inserted in the data weightedaverage circuit 200. In this embodiment, the pointer holding and generatingcircuit 230 includes amultiplexer 231, a set of D flip-flops 232 and apointer decoder 233. - Likewise, a lookup table (please refer to
FIG. 3 ) is embedded in thelookup logic circuit 210. According to an output Din<6:0> (i.e., a thermometer code) of a quantizer and a pointer generated by the pointer holding and generatingcircuit 230, thelookup logic circuit 210 retrieves a corresponding output M′<6:0> from the lookup table. The architecture and operations of the set of D flip-flops 120 are similar to those described inFIG. 1 and therefore the reiteration is omitted. Referring to pointers in the lookup table ofFIG. 3 , a bit number of a specific bit set to 1 corresponds to the first D/A converting cell number for the next selection. Assuming that a pointer has a value of “0000100” and an input Din<6:0> is equal to “0000111”, thelookup logic circuit 210 generates an output M′<6:0> of “0011100”. Therefore, the selected D/A converting cell numbers are 3, 4 and 5. A special case is that in which the input Din<6:0> has a value of “0000000” and then no D/A converting cell will be selected. Accordingly, a current pointer value has to be held or saved until the next input arrives. This embodiment implements this function by using themultiplexer 231 and the set of D flip-flops 232. Based on the value of Din<6:0>, themultiplexer 231 selects one value from two values of channel one and channel zero to be an output. If Din<6:0> has a value of “0000000”, the value Y<6:0> (the previous output of the lookup logic circuit 210) of channel one is selected for the output X<6:0>. If there is a bit within Din<6:0> not equal to zero, the value M′<6:0> of channel zero is selected for the output X<6:0>. The architecture and operations of the set of D flip-flops 232 are the same as those of the set of D flip-flops 120 and therefore will not be described herein. Please be noted that, in this embodiment, the number of the D flip-flops in the set of D flip-flops 232 are equal to the number of the bit width (i.e., equal to 7) of X<6:0>. Similar to the set of D flip-flops 120, each D flip-flop in the set of D flip-flops 232 has their Q outputs (Y<6:0>) simultaneously take on the state of the D inputs (X<6:0>) according to a common control signal (e.g., at the moment of a rising clock edge). Finally, thepointer 233 decodes the output Y<6:0> of the set of D flip-flops 232 into a pointer. Here, each set of D flip-flops (120, 232) can be replaced by a 7-bit register. - It should be noted that although the
lookup unit 110 or thelookup logic circuit 210 can be implemented by using a read-only memory or a combinational logic circuit, the complexity of both circuits (110, 210) are different in practice. Obviously, circuit complexity of thelookup logic circuit 210 with two inputs of Din<6:0> and a pointer is relatively lower. By contrast, circuit complexity of thelookup logic circuit 110 with two inputs of Din<6:0> and Dout<6:0> is relatively higher. Further, the invention is suitable for various orders and various bit widths of the data weighted average circuit. For example, regarding the lookup table ofFIG. 3 , its values are suitable for 1-order data weighted average circuit and the bit width equal to 7. To implement a data weighted average circuit with a different order and a different bit width, the invention needs to modify the contents of the lookup table only without changing other hardware configuration or complexity. Thus, operation speed is not affected. As the number of orders of the data weighted average circuit gets higher or the bit width gets wider, the operation speed difference between the invention and the prior art becomes bigger. - While certain exemplary embodiments have been described and shown in the accompanying drawings, it is to be understood that such embodiments are merely illustrative of and not restrictive on the broad invention, and that this invention should not be limited to the specific construction and arrangement shown and described, since various other modifications may occur to those ordinarily skilled in the art.
Claims (26)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW096129496A TWI337810B (en) | 2007-08-10 | 2007-08-10 | Look-up table type data weighted average circuit and method of dynamic element matching |
TW096129496 | 2007-08-10 | ||
TW96129496A | 2007-08-10 |
Publications (2)
Publication Number | Publication Date |
---|---|
US20090040087A1 true US20090040087A1 (en) | 2009-02-12 |
US7868807B2 US7868807B2 (en) | 2011-01-11 |
Family
ID=40345967
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/187,869 Active US7868807B2 (en) | 2007-08-10 | 2008-08-07 | Data weighted average circuit and dynamic element matching method |
Country Status (2)
Country | Link |
---|---|
US (1) | US7868807B2 (en) |
TW (1) | TWI337810B (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102624398A (en) * | 2011-01-31 | 2012-08-01 | 剑桥硅无线电通信有限公司 | Multi-bit digital to analogue converter and a delta-sigma analogue to digital converter |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11094354B2 (en) | 2019-10-10 | 2021-08-17 | Stmicroelectronics International N.V. | First order memory-less dynamic element matching technique |
US11563443B2 (en) * | 2020-08-31 | 2023-01-24 | Stmicroelectronics International N.V. | High speed data weighted averaging (DWA) to binary converter circuit |
TWI792438B (en) * | 2021-07-22 | 2023-02-11 | 瑞昱半導體股份有限公司 | Signal converter device, dynamic element matching circuit, and dynamic element matching method |
US11979167B2 (en) | 2021-08-16 | 2024-05-07 | Stmicroelectronics International N.V. | Low power and high speed data weighted averaging (DWA) to binary converter circuit |
Citations (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4309772A (en) * | 1980-01-24 | 1982-01-05 | Motorola, Inc. | Soft quantizer for FM radio binary digital signaling |
US4558370A (en) * | 1983-11-21 | 1985-12-10 | International Business Machines Corporation | Image processing method for graphics images |
US4791406A (en) * | 1986-07-21 | 1988-12-13 | Deutsche Itt Industries Gmbh | Monolithic integrated digital-to-analog converter |
US5691719A (en) * | 1994-08-29 | 1997-11-25 | Mitsubishi Denki Kabushiki Kaisha | Analog/digital converter capable of defining and storing A/D converted data |
US6065107A (en) * | 1996-09-13 | 2000-05-16 | International Business Machines Corporation | System for restoring register data in a pipelined data processing system using latch feedback assemblies |
US20020008649A1 (en) * | 2000-03-28 | 2002-01-24 | Mitsuru Nagata | Selecting circuit, digital/analog converter and analog/digital converter |
US6489908B2 (en) * | 2001-04-30 | 2002-12-03 | Texas Instruments Incorporated | Wireless local loop terminal and system having high speed, high resolution, digital-to-analog converter with off-line sigma-delta conversion and storage |
US6633250B2 (en) * | 2001-03-28 | 2003-10-14 | Realtek Semiconductor Corp. | Average bubble correction circuit |
US6853322B2 (en) * | 2001-03-21 | 2005-02-08 | Fujitsu Limited | Reducing jitter in mixed-signal integrated circuit devices |
US7061272B2 (en) * | 2003-07-07 | 2006-06-13 | Infineon Technologies Ag | Finite state machine circuit |
US7183955B1 (en) * | 2005-06-14 | 2007-02-27 | Faraday Technology Corp. | Sigma-delta modulator, D/A conversion system and dynamic element matching method |
US7218133B2 (en) * | 2002-10-24 | 2007-05-15 | Altera Corporation | Versatile logic element and logic array block |
US7385416B1 (en) * | 2007-03-20 | 2008-06-10 | Xilinx, Inc. | Circuits and methods of implementing flip-flops in dual-output lookup tables |
US7561088B1 (en) * | 2008-04-16 | 2009-07-14 | Adtran, Inc. | Multi-loop data weighted averaging in a delta-sigma DAC |
US7760121B2 (en) * | 2008-09-03 | 2010-07-20 | Intel Corporation | Dual data weighted average dynamic element matching in analog-to-digital converters |
-
2007
- 2007-08-10 TW TW096129496A patent/TWI337810B/en active
-
2008
- 2008-08-07 US US12/187,869 patent/US7868807B2/en active Active
Patent Citations (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4309772A (en) * | 1980-01-24 | 1982-01-05 | Motorola, Inc. | Soft quantizer for FM radio binary digital signaling |
US4558370A (en) * | 1983-11-21 | 1985-12-10 | International Business Machines Corporation | Image processing method for graphics images |
US4791406A (en) * | 1986-07-21 | 1988-12-13 | Deutsche Itt Industries Gmbh | Monolithic integrated digital-to-analog converter |
US5691719A (en) * | 1994-08-29 | 1997-11-25 | Mitsubishi Denki Kabushiki Kaisha | Analog/digital converter capable of defining and storing A/D converted data |
US6065107A (en) * | 1996-09-13 | 2000-05-16 | International Business Machines Corporation | System for restoring register data in a pipelined data processing system using latch feedback assemblies |
US20020008649A1 (en) * | 2000-03-28 | 2002-01-24 | Mitsuru Nagata | Selecting circuit, digital/analog converter and analog/digital converter |
US6853322B2 (en) * | 2001-03-21 | 2005-02-08 | Fujitsu Limited | Reducing jitter in mixed-signal integrated circuit devices |
US6633250B2 (en) * | 2001-03-28 | 2003-10-14 | Realtek Semiconductor Corp. | Average bubble correction circuit |
US6489908B2 (en) * | 2001-04-30 | 2002-12-03 | Texas Instruments Incorporated | Wireless local loop terminal and system having high speed, high resolution, digital-to-analog converter with off-line sigma-delta conversion and storage |
US7218133B2 (en) * | 2002-10-24 | 2007-05-15 | Altera Corporation | Versatile logic element and logic array block |
US7061272B2 (en) * | 2003-07-07 | 2006-06-13 | Infineon Technologies Ag | Finite state machine circuit |
US7183955B1 (en) * | 2005-06-14 | 2007-02-27 | Faraday Technology Corp. | Sigma-delta modulator, D/A conversion system and dynamic element matching method |
US7385416B1 (en) * | 2007-03-20 | 2008-06-10 | Xilinx, Inc. | Circuits and methods of implementing flip-flops in dual-output lookup tables |
US7561088B1 (en) * | 2008-04-16 | 2009-07-14 | Adtran, Inc. | Multi-loop data weighted averaging in a delta-sigma DAC |
US7760121B2 (en) * | 2008-09-03 | 2010-07-20 | Intel Corporation | Dual data weighted average dynamic element matching in analog-to-digital converters |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102624398A (en) * | 2011-01-31 | 2012-08-01 | 剑桥硅无线电通信有限公司 | Multi-bit digital to analogue converter and a delta-sigma analogue to digital converter |
US20120194366A1 (en) * | 2011-01-31 | 2012-08-02 | Cambridge Silicon Radio Limited | Multi-bit digital to analogue converter and a delta-sigma analogue to digital converter |
EP2482461A3 (en) * | 2011-01-31 | 2013-03-27 | Cambridge Silicon Radio Limited | A multi-bit digital to analogue converter and a delta-sigma analogue to digital converter |
US8537042B2 (en) * | 2011-01-31 | 2013-09-17 | Cambridge Silicon Radio Limited | Multi-bit digital to analogue converter and a delta-sigma analogue to digital converter |
CN102624398B (en) * | 2011-01-31 | 2015-06-17 | 剑桥硅无线电通信有限公司 | Multi-bit digital to analogue converter and a delta-sigma analogue to digital converter |
Also Published As
Publication number | Publication date |
---|---|
US7868807B2 (en) | 2011-01-11 |
TWI337810B (en) | 2011-02-21 |
TW200908564A (en) | 2009-02-16 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
Kwak et al. | A 15-b, 5-Msample/s low-spurious CMOS ADC | |
EP2269311B1 (en) | Apparatus and method for dynamic circuit element selection in a digital-to-analog converter | |
US10790842B1 (en) | System and method for a successive approximation analog-to-digital converter | |
US7719455B2 (en) | Dynamic element-matching method, multi-bit DAC using the method, and delta-sigma modulator and delta-sigma DAC including the multi-bit DAC | |
US7030799B2 (en) | Current-steering digital-to-analog converter | |
EP1182781B1 (en) | Multistage converter employing digital dither | |
US8564469B2 (en) | Pipelined analog digital convertor | |
US7868807B2 (en) | Data weighted average circuit and dynamic element matching method | |
US9219494B2 (en) | Dual mode analog to digital converter | |
WO2019119349A1 (en) | Interpolation digital-to-analog converter (dac) | |
US7760121B2 (en) | Dual data weighted average dynamic element matching in analog-to-digital converters | |
US20060022857A1 (en) | Suppressing digital-to-analog converter (dac) error | |
US7250896B1 (en) | Method for pipelining analog-to-digital conversion and a pipelining analog-to-digital converter with successive approximation | |
JP5069340B2 (en) | Integrated circuit, system, and AD conversion method for converting analog signal to digital signal | |
US8487792B2 (en) | Method of gain calibration of an ADC stage and an ADC stage | |
WO2007008044A1 (en) | Series sampling capacitor and analog-to-digital converter using the same | |
Venerus et al. | Simplified logic for tree-structure segmented DEM encoders | |
CN113452369B (en) | Analog-to-digital converter and digital calibration method thereof | |
CN101471670B (en) | Table-look-up type data weighting balance circuit and dynamic component matching method | |
CN110048719B (en) | Segmented parallel comparison type ADC | |
EP1222741B1 (en) | D/a conversion method and d/a converter | |
CN112838866A (en) | Calibration logic control circuit and method, successive approximation type analog-to-digital converter | |
JP5129298B2 (en) | DWA (Data-Weighted-Averaging) circuit and delta-sigma modulator using the same | |
US6816098B2 (en) | High-speed oversampling modulator device | |
JP2013187696A (en) | Δς ad converter and signal processing system |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: REALTEK SEMICONDUCTOR CORP., TAIWAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:LIU, CHANG-SHUN;TU, YI-CHANG;WANG, WEN-CHI;REEL/FRAME:021501/0708;SIGNING DATES FROM 20080805 TO 20080827 Owner name: REALTEK SEMICONDUCTOR CORP., TAIWAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:LIU, CHANG-SHUN;TU, YI-CHANG;WANG, WEN-CHI;SIGNING DATES FROM 20080805 TO 20080827;REEL/FRAME:021501/0708 |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
FPAY | Fee payment |
Year of fee payment: 4 |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 8TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1552) Year of fee payment: 8 |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 12TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1553); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Year of fee payment: 12 |