CN104333384A - Folding and interpolating analog-digital converter employing offset averaging and interpolation shared resistance network - Google Patents
Folding and interpolating analog-digital converter employing offset averaging and interpolation shared resistance network Download PDFInfo
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- CN104333384A CN104333384A CN201410638509.9A CN201410638509A CN104333384A CN 104333384 A CN104333384 A CN 104333384A CN 201410638509 A CN201410638509 A CN 201410638509A CN 104333384 A CN104333384 A CN 104333384A
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Abstract
The invention relates to the technical field of the integrated circuits and specifically relates to a folding and interpolating analog-digital converter employing an offset averaging and interpolation shared resistance network. The folding and interpolating analog-digital converter is composed of a single T/H circuit, a reference resistor string, a pre-amplifying circuit array, an offset averaging and interpolation shared resistance network (having the interpolation coefficient of 1), a folding circuit (levels 1-N) having the folding coefficient of F, a comparator array, a digital coding circuit and a binary digit code output drive motor, wherein interpolation is performed in a passive resistance mode, and passive interpolation resistance and offset averaging resistance are shared and fused. The folding and interpolating analog-digital converter employing the offset averaging and interpolation shared resistance network has the advantages that the influence of the passive interpolation resistance on the offset averaging resistance when the offset averaging resistance is cascaded with the passive interpolation resistance, other independent interpolation circuit modules in a traditional structure are omitted and the power consumption is reduced, the cascade bandwidth in a folding and interpolating signal path can be designed smoothly and the design of system high bandwidth can be realized more easily.
Description
Technical field
The invention belongs to technical field of integrated circuits, be specifically related to a kind of high bandwidth, the low power consumption folded interpolating analog to digital converter that adopt the average and interpolation of imbalance to share resistor network.
Background technology
Traditional folded interpolating A/D converter structure as shown in Figure 1, primarily of the folding electric circuit level 5,8,11 that single track and hold circuit 1, reference voltage resistance string 2, pre-amplification gate array 3, prime amplifier output imbalance average resistance network 4, N level collapse factors are F, N level interpolation coefficient is the interpolating circuit level 6,9,12 of I, interpolating circuit level output imbalance average resistance network 7,10,13 at different levels, comparator array circuit module 14, digital encoding circuit module 15 and binary digital code output driving circuit module 16 are formed.
Folded interpolating A/D converter is the low-power consumption structure in all-parallel A/D converter framework, in folded interpolating A/D converter, adopts folding to reduce the number of comparator; Interpositioning is adopted to reduce the number of pre-amplification array.Therefore interpositioning is absolutely necessary for the low power dissipation design of folding interpolating structure analog to digital converter.As shown in Figure 1 be traditional folded interpolating A/D converter structure, every grade of folding electric circuit rear class has one-level interpolation coefficient to be the interpolating circuit module of I, the implementation of interpolating circuit module can be divided into passive interpolation and active interpolation two kinds of modes, and passive interpolation implementation normally adopts the form of passive resistance to realize.In addition, the implementation of traditional passive resistance interpolation can be divided into two kinds of circuit implementations equally, the passive resistance interpolation schematic diagram between the folders circuit of to be the collapse factors of two-stage neighboring be F as shown in Figure 3, comprising: resistor insertion R
i30, lack of proper care average resistance R
a31, folders ohmic load 32 folders input difference is to 33,34,35, i-th grades of folders 36 and the i-th+1 grade folders 37.The difference output of the folders of i-th grade is F respectively
outp (i)and F
outn (i), the difference output of the folders of i-th+1 is F respectively
outp (i+1)and F
outn (i+1).First by imbalance average resistance R between two groups of difference output
aeliminate non-linear shift error, then by resistor insertion R
irealize the interpolation between signal, produce interpolated signal F
p_Cand F
n_C, interpolation coefficient be by adjacent signals between resistor insertion R
iproportionality coefficient determine, be for interpolation coefficient 2 in Fig. 3, namely interpolation coefficient is 2.The implementation of this passive resistance interpolation is rear class resistor insertion being directly cascaded to imbalance average resistance, according to Kirchhoff's current law (KCL), and passive resistor insertion R
ican to offset resistor R
ahave an impact, the imbalance average resistance between adjacent folds device output signal is changed, and this will affect imbalance mean effort, has an impact to the performance of analog to digital converter.In order to isolate impact between the two, forefathers improve in the implementation of traditional passive resistance interpolation, as shown in Figure 4 be imbalance average resistance and passive resistor insertion between add voltage driver 44, for isolating imbalance average resistance and resistor insertion, eliminate influencing each other between the two, ensure the linearity of imbalance mean effort and passive interpolation.But the inherent shortcoming of this implementation increases the high power dissipation that voltage driver brings, be disadvantageous for the low-power consumption of folded interpolating A/D converter structure, energy efficient design.In addition, for another interpolation implementation---active interpolation, as shown in Figure 5, comprising imbalance average resistance R
a47, folders input difference is to 48,49,50 and active interpolating circuit 52, folders ohmic load 53, i-th grade of folders (51) and the i-th+1 grade folders 54.Active interpolation implementation is that the superposition obtaining corresponding signal at the output of active interpolater realizes interpolation using the input of adjacent folds device output signal as active interpolater.Simultaneously, in order to mate the gain of interpolated signal and primary signal, the output signal of original folders needs to amplify through active interpolater equally, interpolation coefficient as shown in Figure 5 is in the active interpolation realizing circuit of 2, realizes needing 6 active interpolaters altogether when interpolation coefficient is the interpolating operations of 2 between adjacent two foldings device.This interpolation method can increase the power consumption of analog to digital converter equally, is unfavorable for the low-power consumption of folded interpolating A/D converter structure, energy efficient design.
Summary of the invention
Under the object of the present invention is to provide a kind of prerequisite ensureing interpolating circuit low-power consumption, high bandwidth, the low power consumption folded interpolating analog to digital converter of interpolating circuit on the impact of imbalance average resistance network can be eliminated.
High bandwidth provided by the invention, low power consumption folded interpolating analog to digital converter, adopt the implementation of passive resistance interpolation, share between passive resistor insertion and imbalance average resistance simultaneously, so both can eliminate the impact of passive resistor insertion for imbalance average resistance, omit the power consumption of active interpolating circuit and isolation Voltag driving circuit reduction analog to digital converter simultaneously, be conducive to the low-power consumption of folded interpolating A/D converter structure, energy efficient design.
The present invention proposes the average and interpolation of a kind of imbalance and share resistor network low consumption circuit design, initial imbalance average resistance is split into I equal portions by the program, each equal portions tap as the output of interpolated signal, thus realizes the passive resistance interpolation that interpolation coefficient is I.This implementation is conventional active interpolation method comparatively, eliminates active interpolating circuit, reduces power consumption.The passive resistance interpolation method that this implementation is more traditional, eliminates the impact of passive resistor insertion for imbalance average resistance, eliminates the voltage driver circuits of isolating between imbalance average resistance and passive resistor insertion and reduces power consumption.Meanwhile, this technique simplifies the design of the cascade signal path cascade bandwidth of folding interpolating structure, be conducive to the design of folded interpolating A/D converter high bandwidth.
Average and the interpolation of the imbalance that the present invention proposes shares resistor network, and as shown in Figure 6, it mainly comprises its structure: the imbalance average resistance R after division
a55, folders input difference is to 56,57,59, and folders ohmic load 60, i-th grade of folders 58 and the i-th+1 grade folders 61.Imbalance average resistance R original in the structure shown here
abe split into two equal R
a, thus realize 2 times of interpolating operations generation interpolated signal F
p_Cand F
n_Cimbalance average resistance network is only had in this structure, there is not other any independently passive and active interpolating circuit module, average and the interpolation of imbalance shares same group of resistor network, eliminate the impact of resistor insertion for imbalance average resistance, eliminate other active interpolating circuit module and reduce power consumption.The like, the average and interpolation of the imbalance of to be interpolation coefficient be I as shown in Figure 7 shares resistor network schematic diagram, original imbalance average resistance R in this figure
abe split into the R of I equal portions
a, thus realize the Interpolation of signals operation that interpolation coefficient is I, namely realize I times of interpolating operations, produce interpolated signal F
p_Cand F
n_C.It mainly comprises: the imbalance average resistance R after division
a62, folders input difference is to 63,64,65, and folders ohmic load 66, i-th grade of folders 67 and the i-th+1 grade folders 68.
Average and the interpolation of imbalance is adopted to share the folded interpolating A/D converter structure of resistor network low consumption circuit, as shown in Figure 2, this structure mainly comprises: single track and hold circuit 17, reference voltage resistance string 18, pre-amplification gate array 19, prime amplifier output is lacked of proper care on average and interpolation shares resistor network 20, N level collapse factors is the folding electric circuit level 21 of F, 23, 25, and N level interpolation coefficient is that the average and interpolation of the imbalance of I shares resistor network 22, 24, 26, comparator array circuit module 27, digital encoding circuit module 28 and binary digital code output driving circuit module 29.
Wherein, the average and interpolation of the N level interpolation coefficient imbalance that is I shares resistor network 22,24,26 for shown in Fig. 7.Average and the interpolation of this imbalance is shared in resistor network, and traditional single imbalance average resistance is split into I equal portions, and tap output interpolated signal between each equal portions imbalance averaging unit resistance, interpolation coefficient is I.
Average and the interpolation of this imbalance is shared resistor network and is applied to pre-amplification array output end, supposes that the number of initial zero crossing is N
p, the number of traditional pre-amplification gate array is N
p, then the number of pre-amplification gate array is N
p/ I.
Average and the interpolation of this imbalance is shared resistor network and is applied to the output that first order collapse factors is the folding electric circuit module of F, and in first order folding electric circuit module, the number of folding electric circuit is N
p/ F.
The output of the folders circuit of every one-level is all lost leveling and is all shared resistor network with interpolation, and in the folding electric circuit module of the second level, the number of folding electric circuit is (N
p× I)/F
2, in N level folding electric circuit module, the number of folding electric circuit is (N
p× I
n-1)/F
n.
Average and the interpolation shared network of imbalance is applied to pre-amplification gate array 19 output in the structure shown here, makes the number of prime amplifier in pre-amplification array by traditional N
pindividual, be reduced to (N
p/ I), reduce the power consumption of analog to digital converter.
The course of work of this structure is: analog input signal first by single boot-strapped switch by signal sampling in fixing holding capacitor; The reference level that inhibit signal and reference voltage resistance string produce is as the input signal of pre-amplification circuit, the output of pre-amplification circuit is the difference amplifying signal between inhibit signal and reference level, shares the initial crossover point signal required for resistor network generation first order folders circuit by the average and interpolation of lacking of proper care; An initial crossover point signal part is input in first order folding electric circuit, and the input signal that the initial crossover point signal of some of them directly becomes comparator carries out thick son quantification; The output signal of first order folding electric circuit shares the input signal of resistor network generation second level folding electric circuit by the average and interpolation of lacking of proper care; Equally, some output signals of first order folding electric circuit directly become the input signal of comparator, carry out thick son and quantize; The rest may be inferred, and the output signal of N-1 level folding electric circuit is shared resistor network by the average and interpolation of lacking of proper care and produced input signal as N level folding electric circuit, and some of them output signal directly becomes the input signal of comparator, carries out thick son quantification; The output signal of N level folding electric circuit shares by the average and interpolation of lacking of proper care the input signal that resistor network produces comparator, carries out thin son quantification; The output signal of comparator is after the coding of digital encoding circuit, and the binary system output code obtaining analog to digital converter is exported by binary digital code drive circuit.
In folded interpolating A/D converter of the present invention, interpolation adopts the interpolation of passive resistance mode, passive resistor insertion and imbalance average resistance is shared and merges.This technology comparatively conventional interpolation technique, when eliminating imbalance average resistance and passive resistor insertion cascade, passive resistor insertion is on the impact of imbalance average resistance; Omit other the independent interpolating circuit module in traditional structure, such as: active interpolating circuit module, reduce power consumption; Be conducive to the design of folded interpolating signal path cascade bandwidth, make system be easier to realize high bandwidth design.
Accompanying drawing explanation
Fig. 1 is that tradition adopts single tracking to keep folded interpolating A/D converter Organization Chart.
Fig. 2 is the single tracking maintenance folded interpolating A/D converter Organization Chart adopting the average and interpolation of imbalance to share resistor network.
Fig. 3 to be interpolation coefficient be 2 passive resistance interpolation schematic diagram.
Fig. 4 to be the interpolation coefficient of band isolation voltage driver be 2 passive resistance interpolation schematic diagram.
Fig. 5 to be interpolation coefficient be 2 active interpolation schematic diagram.
Fig. 6 to be interpolation coefficient be 2 the average and interpolation of imbalance share resistor network schematic diagram.
Average and the interpolation of the imbalance of Fig. 7 to be interpolation coefficient be I shares resistor network schematic diagram.
Number in the figure: 1,17 is that in folded interpolating A/D converter, single Differential Input follows the tracks of maintenance boot-strapped switch circuit; 2,18 is that in folded interpolating A/D converter, resistor string reference produces circuit; 3,19 is pre-amplification array in folded interpolating A/D converter; 4,7,10,13 is average resistance network of lacking of proper care in folded interpolating A/D converter; 5,8,11,21,23,25 for collapse factors be the folders circuit-level of F; 6,9,12 for interpolation coefficient be the interpolation circuit level of I; 14,27 is comparator array circuit module in folded interpolating A/D converter; 15,28 is digital encoding circuit module in folded interpolating A/D converter; 16,29 is binary digital code output driving circuit module in folded interpolating A/D converter; 20,22,24,26 for interpolation coefficient be that the average and interpolation of the imbalance of I shares resistor network; 30,38 is passive resistor insertion R
i; 31,39,47 is original imbalance average resistance R
a; 32,45,53,60,67 is folders ohmic load R
l; 33 ~ 35,40 ~ 42,48 ~ 50,56,57,59,63,64,66 is the folders differential pair of collapse factors F; 36,43,51,58,65 be i-th grade of collapse factors is the folders of F; 37,46,54,61,68 be the i-th+1 grade collapse factors is the folders of F; 44 for isolating the voltage driver of imbalance average resistance and passive resistor insertion; 52 is active interpolating circuit; 55 for interpolation coefficient is 2, the average and interpolation of imbalance shares resistor network; 62 for interpolation coefficient be that the average and interpolation of the imbalance of I shares resistor network.
Embodiment
Average and the interpolation of imbalance the present invention proposed below in conjunction with accompanying drawing share resistor network structure and adopt the high bandwidth of this technology, low power consumption folded interpolating analog-digital converter structure is described in detail.
Average and the interpolation of imbalance shares resistor network structure as shown in Figure 6, and this structure is by the imbalance average resistance R after division
a55, folders input difference is to 56,57,59, and folders ohmic load 60, i-th grade of folders 58 and the i-th+1 grade folders 61 are formed.Imbalance average resistance R original in the structure shown here
abe split into two equal R
a, thus realize 2 times of interpolating operations generation interpolated signal F
p_Cand F
n_C, initialize signal F
p_Aand F
n_Aand F
p_Band F
n_Bdirect output.After adopting this technology, imbalance average resistance and resistor insertion share a set of resistor network, and only have imbalance average resistance network to there is not other any independently passive and active interpolating circuit module in folding interpolation electric circuit structure.Average and the interpolation of imbalance shares same group of resistor network, eliminates the impact of resistor insertion for average resistance of lacking of proper care, eliminates other active interpolating circuit module and reduce power consumption.In addition, it is that the average and interpolation of the imbalance of I shares resistor network that this technology can extend to interpolation coefficient, the imbalance of to be interpolation coefficient be I as shown in Figure 7 on average and interpolation share resistor network schematic diagram, original imbalance average resistance R in this figure
abe split into the R of I equal portions
a, every a R
abetween tap export as interpolated signal, thus realize interpolation coefficient be I Interpolation of signals operation.
Average and the interpolation of the employing imbalance that the present invention proposes shares the high bandwidth of resistor network, low power consumption folded interpolating analog-digital converter structure is by single track and hold circuit 17, reference voltage resistance string 18, pre-amplification gate array 19, prime amplifier output is lacked of proper care on average and interpolation shares resistor network 20, N level collapse factors is the folding electric circuit level 21 of F, 23, 25, and N level interpolation coefficient is that the average and interpolation of the imbalance of I shares resistor network 22, 24, 26, comparator array circuit module 27, digital encoding circuit module 28 and binary digital code output driving circuit module 29 are formed.The more traditional folded interpolating A/D converter structure of this structure: 1, the average and interpolation shared network of imbalance is applied to pre-amplification array output end, makes the number of prime amplifier in pre-amplification array by traditional N
pindividual, be reduced to (N
p/ I) individual, reduce the power consumption of analog to digital converter; 2, the average and interpolation of imbalance is shared resistor network and is applied to every grade of folders output, simplifies the cascade bandwidth Design of folded interpolating signal path, is conducive to the design of folded interpolating A/D converter high bandwidth.
The basic functional principle of this structure is:
(1) analog input signal to be maintained signal through single track and hold circuit 17.
(2) reference level that produces of inhibit signal and reference voltage resistance string 18 is as the input signal of pre-amplification gate array 19, the output of pre-amplification circuit is the difference amplifying signal between inhibit signal and reference level, the output signal of pre-amplification circuit is lacked of proper care on average by prime amplifier output and interpolation shares the input signal that resistor network 20 produces first order folding electric circuit 21, wherein, each ((N
p× I)/F)-1 output get an output and be connected to comparator array 27, QC altogether
0individual output signal directly becomes the input signal of comparator array 27.
(3) first order collapse factors is the number of the folders array 21 of F is ((N
p× I)/F), to be pre-amplification gate array 19 by the imbalance of prime amplifier output average and interpolation shares the output signal that resistor network 20 produces for its input signal, the output signal of first order folding electric circuit by interpolation coefficient be I imbalance on average and interpolation share resistor network and produce ((N
p× I
2)/F) individual signal is the input of the folders array 23 of F as second level collapse factors, wherein every ((N
p× I
2)/F
2)-1 output get an output and be connected to comparator array 27, QC altogether
1individual output signal directly becomes the input signal of comparator array 27.
(4) second level collapse factors is the number of the folders array 23 of F is ((N
p× I
2)/F
2), its input signal is the output signal of first order folding electric circuit is that the average and interpolation of the imbalance of I is shared resistor network and produced by interpolation coefficient.The output signal of second level folding electric circuit is that the average and interpolation of the imbalance of I is shared resistor network and produced ((N by interpolation coefficient
p× I
3)/F
2) individual signal is the input of the folders array of F as third level collapse factors, wherein every ((N
p× I
3)/F
3)-1 output get an output and be connected to comparator array 27, QC altogether
2individual output signal directly becomes the input signal of comparator array 27.
(5) the rest may be inferred, the output signal of N-1 level folding electric circuit is that the average and interpolation of the imbalance of I is shared resistor network and produced the input signal that N level collapse factors is the folders circuit 25 of F by interpolation coefficient, the output signal of N level folding electric circuit 25 is that the average and interpolation of the imbalance of I is shared resistor network and produced and output signal by interpolation coefficient, is connected to comparator array 27.
(6) output signal of comparator 27 is after the coding of coding circuit 28, obtains the binary system output code 29 of analog to digital converter.
Average and the interpolation of the imbalance that the present invention proposes shares resistor network, imbalance average resistance and resistor insertion share a set of resistor network, and only have imbalance average resistance network to there is not other any independently passive and active interpolating circuit module in folding interpolation electric circuit structure.Average and the interpolation of imbalance shares same group of resistor network, eliminates the impact of resistor insertion for average resistance of lacking of proper care, eliminates other active interpolating circuit module and reduce power consumption.
In addition, those skilled in the art average and interpolation can share resistor network design concept and adopts the shared resistor network of other similar type to be out of shape according to imbalance in the present invention, be applied to folded interpolating A/D converter, if therefore these amendments of the present invention and modification belong within the scope of the claims in the present invention and equivalent technologies thereof, then the present invention comprises these change and modification.
Claims (2)
1. the folded interpolating A/D converter adopting the average and interpolation of imbalance to share resistor network, it is characterized in that: by single track and hold circuit (17), reference voltage resistance string (18), pre-amplification gate array (19), average and the interpolation of the imbalance of prime amplifier output shares resistor network (20), N level collapse factors is the folding electric circuit level (21 of F, 23, 25), N level interpolation coefficient is that the average and interpolation of the imbalance of I shares resistor network (22, 24, 26), comparator array circuit module (27), digital encoding circuit module (28) and binary digital code output driving circuit module (29),
Wherein, the average and interpolation of described imbalance is shared resistor network and is comprised: the imbalance average resistance R after division
a(62), folders input difference is to (63,64,65), folders ohmic load (66), i-th grade of folders (67) and the i-th+1 grade folders (68); Wherein, original imbalance average resistance R
abe split into the R of I equal portions
a, thus realize the Interpolation of signals operation that interpolation coefficient is I, namely realize I times of interpolating operations, produce interpolated signal F
p_Cand F
n_C;
Average and the interpolation of this imbalance is shared resistor network and is positioned at pre-amplification array output end, supposes that the number of initial zero crossing is N
p, the number of traditional pre-amplification gate array is N
p, then the number of pre-amplification gate array is N
p/ I;
Average and the interpolation of this imbalance is shared resistor network and is positioned at the output that first order collapse factors is the folding electric circuit module of F, and in first order folding electric circuit module, the number of folding electric circuit is N
p/ F;
The output of the folders circuit of every one-level is all lost leveling and is all shared resistor network with interpolation, and in the folding electric circuit module of the second level, the number of folding electric circuit is (N
p× I)/F
2, in N level folding electric circuit module, the number of folding electric circuit is (N
p× I
n-1)/F
n.
2. folded interpolating A/D converter according to claim 1, is characterized in that: analog input signal first by single boot-strapped switch by signal sampling in fixing holding capacitor; The reference level that inhibit signal and reference voltage resistance string produce is as the input signal of pre-amplification circuit, the output of pre-amplification circuit is the difference amplifying signal between inhibit signal and reference level, shares the initial crossover point signal required for resistor network generation first order folders circuit by the average and interpolation of lacking of proper care; An initial crossover point signal part is input in first order folding electric circuit, and the input signal that the initial crossover point signal of some of them directly becomes comparator carries out thick son quantification; The output signal of first order folding electric circuit shares the input signal of resistor network generation second level folding electric circuit by the average and interpolation of lacking of proper care; Equally, some output signals of first order folding electric circuit directly become the input signal of comparator, carry out thick son and quantize; The rest may be inferred, and the output signal of N-1 level folding electric circuit is shared resistor network by the average and interpolation of lacking of proper care and produced input signal as N level folding electric circuit, and some of them output signal directly becomes the input signal of comparator, carries out thick son quantification; The output signal of N level folding electric circuit shares by the average and interpolation of lacking of proper care the input signal that resistor network produces comparator, carries out thin son quantification; The output signal of comparator is after the coding of digital encoding circuit, and the binary system output code obtaining analog to digital converter is exported by binary digital code drive circuit.
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| CN110383693A (en) * | 2017-03-03 | 2019-10-25 | 德克萨斯仪器股份有限公司 | Resistive interpolation for amplifier array |
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Cited By (10)
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| CN106533446A (en) * | 2016-10-26 | 2017-03-22 | 苏州迅芯微电子有限公司 | Folding and interpolating high-speed analog-to-digital converter with cardinal number of 4 |
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| CN106656189A (en) * | 2016-12-26 | 2017-05-10 | 中国科学院微电子研究所 | Multilevel folding-interpolation type analog-digital converter and decoding method thereof |
| CN106656189B (en) * | 2016-12-26 | 2020-04-21 | 中国科学院微电子研究所 | Multi-stage folding interpolation type analog-to-digital converter and decoding method thereof |
| CN106656184B (en) * | 2016-12-26 | 2020-05-19 | 中国科学院微电子研究所 | Folding interpolation type analog-digital converter with folding rate of 3 and error correction method thereof |
| CN110383693A (en) * | 2017-03-03 | 2019-10-25 | 德克萨斯仪器股份有限公司 | Resistive interpolation for amplifier array |
| CN110383693B (en) * | 2017-03-03 | 2023-07-07 | 德克萨斯仪器股份有限公司 | Resistive interpolation for amplifier arrays |
| CN107508598A (en) * | 2017-08-08 | 2017-12-22 | 中国科学院半导体研究所 | The self-calibration system and method for folded interpolating A/D converter |
| CN107508598B (en) * | 2017-08-08 | 2021-11-30 | 中国科学院半导体研究所 | Self-calibration system and method of folding interpolation analog-to-digital converter |
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