CN106533446B

CN106533446B - Radix-4 folded interpolation high-speed analog-to-digital converter

Info

Publication number: CN106533446B
Application number: CN201610945690.7A
Authority: CN
Inventors: 周磊; 陈冬梅
Original assignee: Acela Micro Co ltd
Current assignee: Xunxin Microelectronics Suzhou Co ltd
Priority date: 2016-10-26
Filing date: 2016-10-26
Publication date: 2023-10-13
Anticipated expiration: 2036-10-26
Also published as: CN106533446A

Abstract

The invention provides a folding interpolation high-speed analog-to-digital converter with a base number of 4, which comprises a first comparator unit, a second comparator unit, an analog processor unit and at least two stages of folding interpolation units, wherein each stage of folding interpolation unit in the at least two stages of folding interpolation units respectively comprises a folding amplifier and interpolation networks, the folding factors of the folding amplifiers are 4, and the interpolation factors of the interpolation networks are 4. The invention simplifies the structure of the folding interpolation ADC system by arranging at least two stages of folding interpolation units, and the folding factors and the interpolation factors are 4, and the quantization curve corresponding to each bit output by the ADC is the power of 2, so that the folding curve and the quantization curve have natural corresponding relation, thereby simplifying the coding of low bits, omitting the coarse quantization of high bits, improving the precision and the speed of the system, and avoiding unstable factors caused by excessive increase of scale and power consumption.

Description

Radix-4 folded interpolation high-speed analog-to-digital converter

Technical Field

The invention relates to the technical field of integrated circuits, in particular to a folding interpolation high-speed analog-to-digital converter with the base number of 4.

Background

High-speed Analog-to-Digital Converter (ADC) with medium and high precision and gigahertz (GHz) or more plays an important role in systems such as acquisition cards, radars, oscilloscopes and the like. The general structure of the ADC with the index is folded interpolation, as shown in fig. 1, the general folded interpolation ADC is composed of a coarse quantization unit 101 and a fine quantization unit 102, which respectively obtain high-order and low-order, wherein the folded interpolation unit outputs low-order information, the coarse quantization unit obtains high-order information, and the coarse quantization unit is generally in a Flash structure, thereby increasing the complexity of the system.

Disclosure of Invention

The invention aims to provide a folding interpolation high-speed analog-to-digital converter with a base number of 4, which is used for solving the problem of complex folding interpolation ADC systems in the prior art.

In order to achieve the above object, the present invention provides a radix-4 folding interpolation high-speed analog-to-digital converter, which includes a first comparator unit, a second comparator unit, an analog processor unit, and at least two stages of folding interpolation units, wherein each stage of folding interpolation unit in the at least two stages of folding interpolation units includes a folding amplifier and interpolation networks, the folding factor of each folding amplifier is 4, and the interpolation factor of each interpolation network is 4; the analog processor unit is used for processing the signals output by the folding amplifier and transmitting the processed signals to the first comparator unit, the first comparator unit also receives the signals output by the interpolation network, and the second comparator unit receives the signals output by the at least two stages of folding interpolation units.

Further, the digital encoder unit is further included for processing the signal output by the second comparator unit and outputting the processed signal.

Further, the synchronous processor is used for processing and outputting the signal output by the first comparator unit and the signal output by the second comparator unit.

The technical scheme of the invention has the beneficial effects that: by arranging at least two stages of folding interpolation units, and the folding factors and the interpolation factors are 4, the structure of the folding interpolation ADC system is simplified, and the quantization curve corresponding to each bit output by the ADC is the power of 2, so that the folding curve and the quantization curve have a natural corresponding relation, the encoding of low bits is simplified, the coarse quantization of high bits is omitted, the precision and the speed of the system are improved, and unstable factors caused by excessive increase of scale and power consumption are avoided.

Drawings

FIG. 1 is a schematic diagram of a prior art folding-interpolation high-speed analog-to-digital converter;

FIG. 2 is a schematic diagram of a radix 4 folding interpolation high-speed analog-to-digital converter according to the present invention;

FIG. 3 is a folding plot of the output of FIG. 2;

fig. 4 is a graph of the folding curve output in fig. 2 and quantization curve corresponding to the high order bits.

In the drawings, the list of components represented by the various numbers is as follows:

101. coarse quantization unit, 102, fine quantization unit, 201, first comparator unit, 202, second comparator unit, 203, analog processor unit, 204, folded interpolation unit, 205, folded amplifier, 206, interpolation network, 207, digital encoder unit, 208, synchronization processor, 209, reference network unit.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention.

The invention discloses a folding interpolation high-speed analog-to-digital converter with the base number of 4, which is shown in fig. 2, and comprises a first comparator unit 201, a second comparator unit 202, an analog processor unit 203 and at least two stages of folding interpolation units 204, wherein each stage of folding interpolation unit 204 in the at least two stages of folding interpolation units 204 respectively comprises a folding amplifier 205 and an interpolation network 206, the folding factor of each folding amplifier 205 is 4, and the interpolation factor of each interpolation network 206 is 4; the analog processor unit 203 is mainly configured to process the signal output by the folding amplifier 205, and send the processed signal to the first comparator unit 201, where the first comparator unit 201 further receives the signal output by the interpolation network 206, and the second comparator unit 202 receives the signal output by the at least two-stage folding interpolation unit 204. In the present embodiment, a digital encoder unit 207 and a synchronization processor 208 may be further included, wherein the digital encoder unit 207 is configured to process and output the signal output by the second comparator unit 202; the synchronization processor 208 is configured to process and output the signal output from the first comparator unit 201 and the signal output from the second comparator unit 202. In the present embodiment, the reference levels are provided by the reference network unit 209, so that in the process of acquiring the actual low-order information, the input signal has been compared with each reference level, and thus the high-order quantized output can be acquired by extracting the intermediate signal in the folding interpolation process, so that a separate coarse quantization unit is not required, and the structure of the folding interpolation ADC system is simplified.

The present invention is further described below by the working principle, in this embodiment, an 8bit ADC is taken as an example, and a two-stage folding interpolation unit is used, where each stage of folding factor and interpolation factor are both 4, and the folding times of all folding curves are all powers of 4, and naturally are also powers of 2. As shown in fig. 3, the finally output folding curve divides the quantization interval into 28=256 parts, thereby realizing 8-bit quantization. The output of each stage of folding interpolation unit is divided into powers of 2 by equally dividing the quantization interval, so that the coding and decoding unit for obtaining the low order is simpler, and the 1-of-n code is used for carrying out 2-system coding.

In addition, the acquisition of the higher order bits is simplified, and as shown in fig. 4, in the folding interpolation structure with the radix of 4, the folding curve and the quantization curve corresponding to the higher order bits have a natural corresponding relationship as can be seen from the observation of fig. 4. The first folding curve output by the second-stage interpolation network directly corresponds to the 5 th bit quantization curve (folding multiple is 16), the first folding curve output by the first-stage interpolation network directly corresponds to the 7 th bit quantization curve (folding multiple is 4), and although the 6 th bit quantization curve and the 8 th bit quantization curve cannot be directly obtained (corresponding folding multiple is 8 and 2 respectively), the folding multiple of the folding curve is the power of 2, so that the folding amplifier can be obtained by simply processing an intermediate signal of the folding amplifier.

Similarly, for a 10bit ADC, a first-stage folding interpolation unit is added on the basis of FIG. 2; for a 12bit ADC, a two-stage folding interpolation unit is added on the basis of FIG. 2.

The invention simplifies the structure of the folding interpolation ADC system by arranging at least two stages of folding interpolation units, and the folding factors and the interpolation factors are 4, and the quantization curve corresponding to each bit output by the ADC is the power of 2, so that the folding curve and the quantization curve have natural corresponding relation, thereby simplifying the coding of low bits, omitting the coarse quantization of high bits, improving the precision and the speed of the system, and avoiding unstable factors caused by excessive increase of scale and power consumption.

Those of ordinary skill in the art will appreciate that: all or part of the steps for implementing the method embodiments described above may be performed by hardware associated with program instructions. The foregoing program may be stored in a computer readable storage medium. The program, when executed, performs steps including the method embodiments described above; and the aforementioned storage medium includes: various media that can store program code, such as ROM, RAM, magnetic or optical disks.

Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the invention.

Claims

1. The folding interpolation high-speed analog-to-digital converter with the base number of 4 is characterized by comprising a first comparator unit, a second comparator unit, an analog processor unit, at least two stages of folding interpolation units, a synchronous processor and a reference network unit, wherein each stage of folding interpolation unit in the at least two stages of folding interpolation units respectively comprises a folding amplifier and an interpolation network, the folding factor of each folding amplifier is 4, and the interpolation factor of each interpolation network is 4; the analog processor unit is used for processing the signals output by the folding amplifier and transmitting the processed signals to the first comparator unit, the first comparator unit also receives the signals output by the interpolation network, and the second comparator unit receives the signals output by at least two stages of folding interpolation units;

the synchronous processor is used for processing and outputting the signals output by the first comparator unit and the signals output by the second comparator unit, and the reference network unit is used for providing a reference level for comparison with the input signals.

2. The radix-4 folded interpolating high-speed analog-to-digital converter of claim 1, further comprising a digital encoder unit for processing and outputting the signal output by the second comparator unit.