CN101217281A - A double sampling two-step folded interpolating A/D converter of ultra-wideband system - Google Patents
A double sampling two-step folded interpolating A/D converter of ultra-wideband system Download PDFInfo
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- CN101217281A CN101217281A CNA200810032497XA CN200810032497A CN101217281A CN 101217281 A CN101217281 A CN 101217281A CN A200810032497X A CNA200810032497X A CN A200810032497XA CN 200810032497 A CN200810032497 A CN 200810032497A CN 101217281 A CN101217281 A CN 101217281A
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Abstract
The invention belongs to the integrated circuit technical field, in particular to a double-sampling two-step type folding interpolating analog-to-digital converter of an ultra-wideband system (OFDM-UWB). The double-sampling two-step type foldable interpolating analog-to-digital converter provided by the invention consists of a sample-hold circuit, an rough modulus converter, a reference level choosing circuit, a fine modulus converter and a numerical coding circuit, with all the elements in connection. The invention adopts the structure combining two-step type with foldable interpolating, and adopts the sample-hold circuit which carries out time-sharing sampling so as to realize the low-consumption requirement of the OFDM-UWB system. The invention can meet the need of low-consumption and low power supply of communication equipment by adopting battery as electric power source.
Description
Technical field
The invention belongs to technical field of integrated circuits, be specifically related to a kind of Orthodoxy Frequency Division Multiplex that is applied to---6 600 megahertz double sampling two-step folded interpolating analog to digital converters of ultra broadband (OFDM-UWB) system.
Background technology
The analog to digital converter of high speed intermediate resolution has a wide range of applications at aspects such as high-speed data communication, liquid crystal display driving, digital oscilloscope, hard drive circuit at present.Analog to digital converter is one of most important core technology in the high performance mixed signal system, and the CMOS high-speed AD converter designs one of them technical bottleneck especially, is the focus and emphasis of studying in the world all the time.The high-speed AD converter of using in the OFDM-UWB system also needs to satisfy the requirement of low-voltage, low-power consumption, especially the difficult point in the design.
For high-speed AD converter, the normal circuit structure that adopts is full parallel organization.Fig. 1 is the schematic diagram of one 3 bit all-parallel A/D converter.All-parallel A/D converter mainly amplifies array 11, the second level in advance by reference resistance string 10, the first order and amplifies array 12, comparator array 13 and digital coding circuit 14 in advance and form, and wherein reference resistance string 10, the first order are amplified array 11, the second level in advance and amplified the simulation part that array 12, comparator array 13 have constituted all-parallel A/D converter in advance.The hardware spending of its simulation part all with the precision exponent function relation of analog to digital converter.The pre-arrays consume prime amplifier 7 (2 that amplifies of each level of the all-parallel A/D converter of 3 bits
3-1) individual, consume comparator 7 (2
3-1) individual.
In order to reduce the power consumption of prime amplifier, introduced the number that interpositioning reduces prime amplifier.Fig. 2 is that one 3 bit, interpolated coefficient is 2 all-parallel A/D converter.It comprises that mainly reference resistance string 20, the first order amplify array 21, the second level in advance and amplify array 22, comparator array 23 and digital coding circuit 24 in advance, and wherein the first order is amplified in advance and also comprised prime amplifier 210 and interpolation resistance 211 in the array 21.After having adopted interpositioning, the number that the first order is amplified the prime amplifier of array in advance is reduced to 4 (2
3÷ 2) individual.Interpolation coefficient is big more, and it is many more that the first order is amplified the number that the prime amplifier of array reduces in advance.If amplify in advance in the second level and also to adopt interpositioning in the array, the second level prime amplifier number of amplifying array in advance also can reduce so.But the number of comparator can not reduce because of the introducing of interpositioning, and along with the improving constantly of operating frequency, the power consumption of comparator also improves constantly.
In order to reduce the power consumption of comparator, folding is introduced into, thereby has produced the analog to digital converter of folding interpolating structure.It has inherited the good speed ability of full parallel organization, and after precision improved, its power consumption can be much smaller than full parallel organization especially.Fig. 3 is that one 3 bit all-parallel A/D converter has adopted folding schematic diagram afterwards.It mainly comprises reference resistance string 30, amplifies array 31, folded array 32, comparator array 33 and digital coding circuit 34 in advance, wherein amplifies in advance also to comprise prime amplifier 310 and interpolation resistance 311 in the array 31.Folding electric circuit is exported the zero crossing that a plurality of prime amplifiers produce by an output, thereby has reduced the number of comparator, the power consumption of having saved comparator.
Fig. 4 is the fundamental diagram that folds.Through 8 times folding, the number of comparator can be less to original
, but output can produce periodic the variation, therefore needs extra circuit to specify output to be in which in cycle.So sub-transducer of complete two parallel processings of folded interpolating A/D converter needs.One of them is called thick sub-transducer, and another is called thin sub-transducer.Generally, thick sub-transducer is realized by full parallel organization, and thin sub-transducer adopts folding interpolating structure.Thick sub-transducer is to be used for determining which cycle the output of thin sub-transducer is in.In fact the thin son of folded interpolating A/D converter and thick sub-transducer all need to handle the signal in the whole analog input scope, and therefore for more high-precision analog to digital converter, this structure still needs bigger hardware spending.
Summary of the invention
The objective of the invention is to propose a kind of folded interpolating A/D converter that is applied to Orthodoxy Frequency Division Multiplex one radio ultra wide band system 6 6-bit 600 megahertz double sampling two-step formula structures that can further save hardware consumption.
The folded interpolating A/D converter that the present invention proposes adopts the two-step structure, and its structure as shown in Figure 5.It comprises sampling hold circuit, thick sub-transducer, reference level selection circuit, thin sub-transducer and digital coding circuit; In the two-step structure, analog signal is at first by sampling hold circuit, and the signal in its maintenance stage is sent to thick sub-transducer and quantizes, and also is sent to thin sub-transducer simultaneously; The quantized result of thick sub-transducer is sent into reference level selection circuit, and the output of reference level selection circuit enters thin sub-transducer, and thin sub-transducer quantizes according to the reference level of the reference level selection circuit output maintenance result to sampling hold circuit; The result of thick sub-transducer and thin sub-transducer sends into the digital coding circuit.Than folded interpolating A/D converter, adopted after the two-step structure, thin sub-transducer need not to handle the signal in the whole analog input scope, and it only needs to quantize to get final product according to the scope that thick sub-transducer is determined.Therefore reduced the hardware complexity of folded interpolating A/D converter.
Among the present invention, above-mentioned sampling hold circuit adopts a kind of sampling hold circuit of two samplings, as shown in Figure 6.It comprises 6 switches and 2 maintenance electric capacity; Carry out the switch 1 and the switch 2 of signal sampling and all realize that by the grid voltage bootstrapped switch switch 3, switch 4, switch 5 and switch 6 are all realized by cmos switch; Clock Φ 1, clock Φ 2, clock Φ 3, clock Φ 4, clock Φ 5 and clock Φ 6 be control switch 1, switch 2, switch 3, switch 4, switch 5 and switch 6 respectively; The V1 output provides thick sub-transducer input signal, and the V2 output provides thin sub-transducer input signal.
When sampling hold circuit is operated in time period I, switch 1, switch 3 and switch 6 closures, switch 2, pass 4 and switch 5 disconnect.Keep the voltage-tracing input signal on the capacitor C 1, the V1 end is consistent with the voltage that keeps capacitor C 1 two ends, also follows the tracks of input signal.Keep keeping on the capacitor C 2 signal of one-period sampling on the clock Φ 2, the V2 end is consistent with the voltage that keeps capacitor C 2 two ends, that is to say, this moment, thin sub-transducer quantized the signal of last clock cycle sampling.
When sampling hold circuit was operated in time period II, switch 1, switch 2, switch 4 and switch 5 disconnected switch 3 and switch 6 closures.Keep keeping on the capacitor C 1 signal of clock Φ 1 sampling, from the V1 end inhibit signal is flowed to thick sub-transducer, thick sub-transducer quantizes inhibit signal.This moment, thin sub-transducer still quantized previous inhibit signal.
When sampling hold circuit was operated in time period III, switch 1, switch 3 and switch 6 disconnected switch 2, switch 4 and switch 5 closures.The signal of clock Φ 1 sampling is given thin sub-transducer this signal conveys from the V2 end before keeping keeping on the capacitor C 1, and thin sub-transducer quantizes this signal.The voltage-tracing input signal of capacitor C 2 during the guarantor, the V1 end is consistent with the voltage that keeps capacitor C 2 two ends, also follows the tracks of input signal.
When sampling hold circuit was operated in time period IV, switch 1, switch 2, switch 3 and switch 6 disconnected switch 4 and switch 5 closures.Keep still keeping on the capacitor C 1 signal of clock Φ 1 sampling before, and quantize to thin sub-transducer signal conveys from the V2 end.Keep keeping on the capacitor C 2 signal of clock Φ 2 samplings, and from the V1 end inhibit signal is flowed to thick sub-transducer and quantize.
Sample frequency of the present invention is 600 megahertzes, but for 6 clocks of sampling hold circuit, their frequency only needs 300 megahertzes.The duty ratio of clock Φ 1 and clock Φ 2 is 1: 7, and clock Φ 3, clock Φ 4, clock Φ 5 and clock Φ 6 duty ratios are 1: 1.
The advantage of the sampling hold circuit that the present invention adopts is low in energy consumption, and speed is fast.In traditional two-step structure, usually in sampling hold circuit, use operational amplifier, and both having influenced speed, the use of operational amplifier also consumed bigger power consumption.The utilization operational amplifier there is no need in the analog to digital converter of 6 bit accuracy, and sampling hold circuit of the present invention can guarantee enough precision.
Thick sub-transducer adopts full parallel organization, as shown in Figure 7.It comprises reference resistance string 70, first order prime amplifier 71, second level prime amplifier 72 and comparator 73.They link to each other successively, constitute thick sub-transducer, are used for differentiating high 3.
Thin sub-transducer adopts folding interpolating structure, as shown in Figure 8.It comprises prime amplifier 80, interpolation resistance 81, the active interpolation 82 of the first order, folding electric circuit 83, the active interpolation 84 in the second level, the active interpolation 85 of the third level and comparator 86.They link to each other successively, constitute thin sub-transducer, are used for differentiating low 4.
Thick sub-transducer and thin sub-transducer can be differentiated 7 altogether, and wherein the highest order of the lowest order of thick sub-transducer and thin sub-transducer is represented the information of same position, is to be used for proofreading and correct two errors between the sub-transducer.
Reference level selection circuit as shown in Figure 9, it comprises reference resistance string 90 and switch arrays 91, wherein the switch that label is identical is all used same signal controlling.The comparative result of thick sub-transducer is controlled the switch arrays 19 (switch 1 is to switch 8) of reference level selection circuit, and the operation level of thin sub-transducer is provided.Reference level when working in order to obtain thin sub-transducer apace, each switch of switch arrays 9 (switch 1 is to switch 8) all adopts the grid voltage bootstrapped switch.
The digital coding circuit is encoded according to the comparator results of thick sub-transducer and thin sub-transducer, has also adopted the metastable coding techniques of inhibition bubble effect and comparator, at last the comparative result of thick son and thin sub-transducer is exported synchronously.
Description of drawings
Fig. 1 is one 3 bit all-parallel A/D converter.
Fig. 2 is that one 3 bit, interpolated coefficient is 2 all-parallel A/D converter.
Fig. 3 is that one 3 bit all-parallel A/D converter has adopted folding schematic diagram afterwards.
Fig. 4 is folding fundamental diagram.
The two-step structural representation that Fig. 5 adopts for the present invention.
The sampling hold circuit schematic diagram that Fig. 6 adopts for the present invention.
The thick sub-transducer schematic diagram that Fig. 7 adopts for the present invention.
The thin sub-transducer schematic diagram that Fig. 8 adopts for the present invention.
The reference level selection circuit schematic diagram that Fig. 9 adopts for the present invention.
Number in the figure: 10 expression reference resistance strings, the 11 expression first order are amplified array in advance, the 12 expression second level are amplified array in advance, 13 expression comparator arrays, 14 expression digital coding circuit, 20 expression reference resistance strings, the 21 expression first order are amplified array in advance, 210 expression prime amplifiers, 211 expression interpolation resistance, the 22 expression second level are amplified array in advance, 23 expression comparator arrays, 24 expression digital coding circuit, 30 expression reference resistance strings, the pre-array that amplifies of 31 expressions, 310 expression prime amplifiers, 311 expression interpolation resistance, 32 expression folded array, 33 expression comparator arrays, 34 expression digital coding circuit, holding circuit is adopted in 51 expressions, the thick sub-transducer of 52 expressions, 53 expression reference level selection, the thin sub-transducer of 54 expressions, 55 expression digital coding circuit, 70 expression reference resistance strings, 71 expression first order prime amplifiers, 72 expression second level prime amplifiers, 73 expression comparators, 80 expression prime amplifiers, 81 expression interpolation resistance, the active interpolation of the 82 expression first order, 83 expression folding electric circuits, the active interpolation in the 84 expression second level, the active interpolation of the 85 expression third level, 86 expression comparators, 90 expression reference resistance strings, 91 expression switch arrays.
Embodiment
Further describe the present invention below in conjunction with accompanying drawing.
6 6-bit 600 MHz sample frequency two-step folded interpolating A/D converters among the present invention mainly are made of sampling hold circuit, thick sub-transducer, reference level selection circuit, thin sub-transducer and digital coding circuit, link as shown in Figure 5.Wherein thick sub-transducer adopts full parallel organization, is connected and composed successively by first order prime amplifier 71, second level prime amplifier 72 and comparator 73; Thin sub-transducer adopts folding interpolating structure, is connected and composed successively by prime amplifier 80, interpolation resistance 81, the active interpolation 82 of the first order, folding electric circuit 83, the active interpolation 84 in the second level, the active interpolation 85 of the third level, comparator 86.Sampling hold circuit is connected with the first order prime amplifier 71 of thick sub-transducer and the prime amplifier 80 of thin sub-transducer respectively.The output of thick sub-transducer connects reference level selection circuit, and the output of reference level selection circuit connects thin sub-transducer.The output linking number word code circuit of thick sub-transducer and thin sub-transducer.
Analog input signal at first passes through sampling hold circuit.Therefore inhibit signal is sent to thick sub-transducer, and thick sub-transducer is used for differentiating 3 bits, comprises respectively 9 of needs of the first order prime amplifier 71, second level prime amplifier 72 and the comparator 73 that overflow in the judgement and descend overflow thick sub-transducer.The difference of inhibit signal and 9 reference voltages is amplified by first order prime amplifier 71, obtains difference and amplifies the result.The difference output result of 72 pairs of first order prime amplifiers 71 of second level prime amplifier further amplifies, and provides signal enough gains, determines with the erroneous judgement that reduces the comparator that causes because of comparator imbalance.The output of 73 pairs of second level prime amplifiers 72 of comparator compares, if positive terminal voltage is higher than negative phase end voltage, and comparator output high level; Otherwise, the comparator output low level.Thick sub-transducer is output as thermometer code, can obtain the effective information of 3 bits.
The output result of 9 comparators can obtain 8 groups of switch controlling signals of reference level selection circuit through the one-level NAND gate.According to the comparative result of thick sub-transducer each time, 1 group of work reference level in these 8 groups of reference level scopes as thin sub-transducer.
The signal that sampling hold circuit offers the front thick sub-transducer is keeping a sampling period to offer thin sub-transducer.Thin sub-transducer will be differentiated 4 bits, therefore will produce 15 (2 altogether
4-1) individual zero crossing.The difference that the prime amplifier 80 of thin sub-transducer amplifies inhibit signal and reference voltage obtains two zero crossings.The output signal of prime amplifier 80 obtains 3 zero crossings by interpolation resistance 81, and interpolation resistance has the average effect of imbalance concurrently.Signal process interpolation coefficient after the resistance interpolation is 2 the active interpolation 82 of the first order, obtains 5 zero crossings.Zero crossing 1, zero crossing 3 and zero crossing 5 are as one group, and zero crossing 2 and zero crossing 4 provide the input signal of two folders of folding electric circuit 83 respectively as one group.Therefore the collapse factors of folders is 3, and the output at first folders can obtain 3 zero crossing informations, can obtain 2 zero crossing informations at the output of second folders.The output signal process interpolation coefficient of folding electric circuit 83 is 2 the active interpolation 84 in the second level, obtains 9 zero crossing informations.Its output process interpolation coefficient is 2 the active interpolation 85 of the third level, can obtain 17 zero crossing informations, has comprised in these 17 zero crossings to be used for differentiating 15 required zero crossing informations of 4 bits.The output of third level interpolation 85 obtains comparative result through the judgement of comparator 86.Thin sub-transducer is output as the circulating temperature sign indicating number, and therefore the output of 8 comparators just can provide the information of 4 bits.
The comparative result of thick son and thin sub-transducer is as the input of digital coding circuit.Coding circuit converts the comparative result of two sub-transducers to Gray code respectively, with the coding result delay one-period of thick sub-transducer, two passage comparative results is proofreaied and correct again, and converts binary code output at last to.
Claims (5)
1. the double sampling two-step folded interpolating analog to digital converter of a radio ultra wide band system adopts the two-step structure, it is characterized in that comprising sampling hold circuit, thick sub-transducer, reference level selection circuit, thin sub-transducer and digital coding circuit; In the two-step structure, analog signal is at first by sampling hold circuit, and the signal in its maintenance stage is sent to thick sub-transducer and quantizes, and also is sent to thin sub-transducer simultaneously; The quantized result of thick sub-transducer is sent into reference level selection circuit, and the output of reference level selection circuit enters sub-transducer just, and thin sub-transducer quantizes according to the reference level of the reference level selection circuit output maintenance result to sampling hold circuit; The result of thick sub-transducer and thin sub-transducer sends into the digital coding circuit.
2. analog to digital converter according to claim 1 is characterized in that described sample circuit adopts the sampling hold circuit of two samplings, and it comprises 6 switches and 2 maintenance electric capacity; Carry out the switch 1 and the switch 2 of signal sampling and all realize that by the grid voltage bootstrapped switch switch 3, switch 4, switch 5 and switch 6 are all realized by cmos switch; Clock Φ 1, clock Φ 2, clock Φ 3, clock Φ 4, clock Φ 5 and clock Φ 6 be control switch 1, switch 2, switch 3, switch 4, switch 5 and switch 6 respectively; The V1 output provides thick sub-transducer input signal, and the V2 output provides thin sub-transducer input signal.
3. analog to digital converter according to claim 1 is characterized in that described thick sub-transducer adopts full parallel organization, is connected to form successively by reference resistance string (70), first order prime amplifier (71), second level prime amplifier (72) and comparator (73).
4. analog to digital converter according to claim 1, it is characterized in that described thin sub-transducer adopts folding interpolating structure, is connected to form successively by prime amplifier (80), interpolation resistance (81), the active interpolation of the first order (82), folding electric circuit (83), the active interpolation in the second level (84), the active interpolation of the third level (85) and comparator (86).
5. analog to digital converter according to claim 1, it is characterized in that described reference level selection circuit is made up of reference resistance string (90) and switch arrays (91), the comparative result of thick sub-transducer is controlled the switch arrays (91) of reference level selection circuit, and the operation level of thin sub-transducer is provided; Switch all adopts the grid voltage bootstrapped switch in the described switch arrays (91).
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103475370A (en) * | 2013-09-04 | 2013-12-25 | 苏州苏尔达信息科技有限公司 | High-speed two-stage analog-digital conversion circuit |
| CN108880545A (en) * | 2018-07-06 | 2018-11-23 | 北京时代民芯科技有限公司 | Offset foreground calibration circuit and method for comparator of pipeline analog-to-digital converter |
| CN110383693A (en) * | 2017-03-03 | 2019-10-25 | 德克萨斯仪器股份有限公司 | Resistive interpolation for amplifier array |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100471069C (en) * | 2001-10-03 | 2009-03-18 | Nxp股份有限公司 | Analogue to digital converter |
| DE602004005570D1 (en) * | 2003-01-17 | 2007-05-10 | Koninkl Philips Electronics Nv | ANALOG / DIGITAL IMPLEMENTATION ARRANGEMENT, METHOD FOR ANALOG / DIGITAL IMPLEMENTATION AND SIGNAL PROCESSING SYSTEM USING THE IMPLEMENTATION ARRANGEMENT |
| CN101047386B (en) * | 2007-03-15 | 2010-05-19 | 复旦大学 | 6-bit 600 MHz sample frequency folding interpolation A/D converter |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103475370A (en) * | 2013-09-04 | 2013-12-25 | 苏州苏尔达信息科技有限公司 | High-speed two-stage analog-digital conversion circuit |
| CN110383693A (en) * | 2017-03-03 | 2019-10-25 | 德克萨斯仪器股份有限公司 | Resistive interpolation for amplifier array |
| CN110383693B (en) * | 2017-03-03 | 2023-07-07 | 德克萨斯仪器股份有限公司 | Resistive interpolation for amplifier arrays |
| CN108880545A (en) * | 2018-07-06 | 2018-11-23 | 北京时代民芯科技有限公司 | Offset foreground calibration circuit and method for comparator of pipeline analog-to-digital converter |
| CN108880545B (en) * | 2018-07-06 | 2022-05-13 | 北京时代民芯科技有限公司 | Offset foreground calibration circuit and method for comparator of pipeline analog-to-digital converter |
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