JP5397169B2 - Image processing system and method - Google Patents

Description

  The present invention relates to an image processing system and method, and more particularly, to a technology that uses resources of an auxiliary arithmetic device from an image processing device that is not associated with the arithmetic processing device.

  2. Description of the Related Art There is provided a digital multifunction peripheral called a so-called MFP (Multi Function Peripheral) that combines a copy function, a facsimile (FAX) function, a print function, and a scanner function. According to such a digital multi-function peripheral, handwritten documents and paper materials can be digitized and shared and utilized on a network. In recent years, image processing and information processing have been performed on these digitized data. Specifically, complex compression processing (high compression PDF), OCR (Optical Character Recognition), embedded code detection, automatic rotation, and the like.

  In general, the amount of digital data when a paper document is digitized is enormous. For example, in the case of an A4, 300 dpi, 8-bit full-color document, the size is about 25 MB without being compressed, and the image processing for such huge data has a very large calculation amount. When image processing is performed on such huge image data only with a CPU of a general controller, the processing cannot often be completed within the time desired by the user. In order to speed up such processing, an auxiliary arithmetic device (accelerator) has been proposed. However, since such an auxiliary arithmetic device is not always necessary, it may be desirable to be detachable.

  However, the conventional auxiliary arithmetic device (accelerator) can be used only from the body on which it is mounted. Therefore, if there are multiple MFPs in a local area network (hereinafter referred to as “LAN”) and there is a need to use the arithmetic processing function of an auxiliary arithmetic device (accelerator) from any MFP, An auxiliary arithmetic device (accelerator) must be mounted on the MFP, which increases the cost.

  Therefore, we tried to build a server / client system with the machine equipped with an auxiliary computing device (accelerator) as the server and the other machine without the client as the client, but simply built the server / client system. However, since all processing passes through the server side, there is a problem that the load is heavy and the required performance of the image processing apparatus serving as the server increases.

  In the prior art, for example, in Patent Document 1, a plurality of accelerators are connected to a server device via a high-speed bus for the purpose of speeding up display requests from a plurality of client devices. A configuration is disclosed in which the use efficiency of an accelerator is increased by automatically assigning the calculation request of However, the above-described problem that the load on the server becomes heavy because all processing goes through the server has not been solved.

  The present invention has been made in view of the above-described problems, and does not increase the load on the machine associated with the auxiliary arithmetic device (accelerator), and performs processing of the image processing device without the auxiliary arithmetic device. Another object of the present invention is to provide an image processing system and method that can be executed by an auxiliary arithmetic device.

  In order to solve the above-described problems, an image processing system according to the present invention is an image processing system in which a high-speed arithmetic processing device, a parent device, and an image processing device are connected via a network. The processing device includes: an acceptability determination unit that determines whether the calculation target data is acceptable; a high-speed calculation unit that calculates the received data; and a calculation result transmission unit that transmits the calculation result to the image processing device. The image processing apparatus includes: a use request issuing unit that issues a request for use of the high-speed arithmetic processing device to the parent device; and the operation target based on permission to use the high-speed arithmetic processing device from the parent device. Data transmitting means for transmitting data to the high-speed arithmetic processing device, and the parent device has network address information for holding network address information of the high-speed arithmetic processing device And an operation arbitration unit that determines whether the image processing apparatus can use the high-speed arithmetic processing unit based on a use request issued by the use request issuing unit and a determination result of the acceptability determination unit. And use permission transmitting means for transmitting the use permission to the image processing device based on the result of determination by the operation arbitration means.

  In the image processing method according to the present invention, a high-speed arithmetic processing device, a parent device, and an image processing device are connected via a network, and the parent device is network address information of the high-speed arithmetic processing device. An image processing method of an image processing system that holds a use request issuance step for issuing a request for use of the high-speed arithmetic processing device from the image processing device to the parent device; and The network address information is used to inquire to the high-speed arithmetic processing unit whether it is possible to accept the calculation target data related to the use request, and it is possible to accept whether the calculation target data is acceptable. Based on the determination result of the determination step and the acceptability determination step, the image processing device is permitted to use the high-speed arithmetic processing device for the image. And use permission transmission step of transmitting to the management apparatus, the image processing apparatus, based on the use permission, characterized in that it comprises the steps of: transmitting the data operands to said high-speed arithmetic processor.

  According to the present invention, it is possible to cause an auxiliary arithmetic device to execute the processing of an image processing device that is not equipped with an auxiliary arithmetic device, without increasing the load on a machine linked to the auxiliary arithmetic device (accelerator). It becomes possible to provide an image processing system and method that can be used.

It is a block diagram of the image processing system which concerns on this embodiment. It is a block diagram which shows another structural example of the image processing system which concerns on this embodiment. 1 is a configuration diagram of an image processing apparatus 100 according to the present embodiment. It is an example of the high-speed arithmetic processing part setting table which concerns on this embodiment. It is an example of the use request information table which concerns on this embodiment. 2 is a power supply system diagram of the image processing apparatus 100 according to the present embodiment. FIG. 1 is a configuration diagram of an image processing apparatus 201 with no accelerator according to the present embodiment. It is a figure which shows the data processing flow of the image processing system which concerns on this embodiment. It is a figure which shows the process sequence of the usability determination which concerns on this embodiment.

  FIG. 1 is a configuration diagram of an image processing system according to an embodiment of the present invention. This system has a configuration in which a high-speed arithmetic processing unit 102, an image processing unit 101, and an image processing apparatus 201 not equipped with an accelerator are connected to each other via a network 200 so as to communicate with each other.

  The high-speed arithmetic processing unit 102 (hereinafter sometimes referred to as “slave unit 102”) and the image processing unit 101 (hereinafter also referred to as “base unit 101”) are physically and electrically connected via the high-speed bus 103. Connected to each other and configured as an integrated image processing apparatus 100. However, the high-speed bus 103 can be omitted. The present embodiment may be configured as shown in FIG.

  The configuration of the accelerator non-installed image processing apparatus 201 (hereinafter may be referred to as “non-master device 201”) may be the same as that of the master device 101. The difference between the parent device 101 and the non-parent device 201 is whether or not the child device 102 is linked. The master unit 101 is linked to the slave unit 102. The non-parent device 201 is not linked to the child device 102.

(Configuration of the image processing apparatus 100)
FIG. 3 is a configuration diagram of the image processing apparatus 100. This apparatus includes an image processing unit 101 and a high-speed arithmetic processing unit 102.

  As an example of the image processing apparatus, for example, a case of a digital multifunction peripheral will be described. The image processing unit 101 includes a CPU 10, a ROM 11, a compression / decompression unit 12, a RAM 13, an HDD 14, an image reading control unit 15, an image reading unit 16, a reading completion detection unit 20, a print control unit 17, An image printing unit 18, an operation unit 19, an operation arbitration unit 21, a use determination unit 22, and a communication interface 30 are provided.

  The high-speed calculation processing unit 102 includes a CPU 1, a high-speed calculation unit 2, a RAM 3, a communication control unit 4, a compression / decompression unit 5, a data acceptability determination unit 7, an internal bus 6, and a communication interface 30. Prepare. The high-speed arithmetic processing unit 102 can be installed later, replaced with one that is optimal for the arithmetic processing contents, or changed to a higher-performance one in accordance with the arithmetic processing to be processed. ing.

(Configuration of the image processing unit 101)
The image processing unit 101 including the printing unit 18 and the image reading unit 16 includes an image processing control unit that controls the overall image processing in the image processing apparatus. The image processing control unit controls the printing unit 18. A print control unit 17 and an image reading control unit 15 that controls the image reading unit 16 are connected.

  The image reading control unit 15 is connected to a reading completion detection unit 20 that detects when a paper document can be read and transferred in units of one document. It also has a compression / decompression unit 12 that compresses the read image data or decompresses the compressed data.

  The print control unit 17 outputs a print instruction including image data to the print unit 18 under the control of the image processing control unit, and causes the print unit 18 to form and output an image on a medium such as transfer paper. The printing unit 18 is capable of full-color printing. In addition to the electrophotographic method, the printing unit 18 employs various methods such as an inkjet method, a sublimation type thermal transfer method, a silver salt photography method, a direct thermal recording method, and a melt type thermal transfer method. be able to.

  The image reading control unit 15 drives the image reading unit 16 under the control of the image processing control unit, and collects the reflected light of the lamp irradiation on the surface of the document in a light receiving element (for example, a CCD (Charge Coupled Device)) by a mirror and a lens. It reads by light and A / D converts to generate RGB 8-bit digital image data.

  Such an image processing control unit includes a CPU 10 (Central Processing Unit) that is a main processor, a memory device that temporarily stores image data read from the image reading unit 16 for image formation by the printing unit 18, and a control. The microcomputer 11 has a microcomputer configuration in which a ROM 11 storing a program and the like and an NVRAM 13 capable of holding data even when the power is turned off for recording system logs / system settings / log information and the like are connected by a bus.

  The image processing unit 101 is connected to an HDD 14 (Hard Disk Drive) serving as a storage device for storing a large amount of image data and a job history, and a communication control unit 13 for connecting to the network 200. The communication control unit 13 is connected to the network 200 via the communication interface 30.

  The image processing unit 101 may transmit the input data as an image file (JPEG, TIFF, PDF, etc.) in the form of an e-mail via the network 200 or to a folder to another computer. it can.

  Further, the communication control unit 13 may exchange data with the high-speed arithmetic processing unit 102 via the high-speed bus 103.

  In addition, the image processing unit 101 includes a use determination unit 22. The use determination unit 22 determines whether or not the high-speed arithmetic processing unit 102 is required to perform the process in performing the process instructed by the user. These are preferably determined in advance by the application.

  Further, the image processing unit 101 holds the network address and setting information of the high-speed arithmetic processing unit 102 in the HDD 14 as a high-speed arithmetic processing unit setting table. With this, the association between the image processing unit 101 and the high-speed arithmetic processing unit 102 is defined. The network address assigned to the high-speed arithmetic processing unit 102 is preferably unique to each device because there may be a plurality of high-speed arithmetic processing devices in the network 200. For example, an IP address is preferable.

  FIG. 4 shows an example of the high-speed arithmetic processing unit setting table. As illustrated, the high-speed arithmetic processing unit setting table holds, for example, a network address, hardware version, OS version, program version, and usable application for each apparatus. Based on these pieces of information, the image processing unit 101 controls each high-speed arithmetic processing device at the operation arbitration unit 21. Hereinafter, it will be described that the operation arbitration unit 21 controls the high-speed arithmetic processing unit 102 without assuming a case where a plurality of high-speed arithmetic processing devices exist in the network 200.

  The control to be performed includes, for example, status monitoring of the high-speed arithmetic processing unit 102, permission / non-permission of processing, updating of a program or OS, resetting in case of abnormality, and the like.

  In addition, the image processing unit 101 includes an operation arbitration unit 21. The operation arbitration unit 21 receives a use request from the image processing unit 101 or the image processing apparatus 201 not equipped with an accelerator, and creates a use request list. The high-speed arithmetic processing unit 102 executes processing in the order of arrival of the usage request list.

  FIG. 5 shows an example of a usage request (usage request information table). The use request issued by the image processing unit 101 or the image processing apparatus 201 not equipped with an accelerator may be a use request information table as shown in FIG. Based on this information, the operation arbitration unit 21 determines whether or not the processing requested for use can be executed by the high-speed arithmetic processing unit 102. In addition, when the high-speed calculation processing unit 102 determines whether the calculation target data can be received, it is determined whether or not the request source device can use the high-speed calculation processing unit 102 based on the determination. (Usability determination) The communication control unit 13 notifies the request source of availability.

  It should be noted that the acceptance request notification to the high-speed arithmetic processing unit 102 has the same content as the use request shown in FIG. In addition, the use request list created by the operation arbitration unit 21 is assumed to be the use requests shown in FIG.

(Configuration of high-speed arithmetic processing unit 102)
A high-speed arithmetic processing unit 102 is connected to a CPU 1 (Central Processing Unit) 1 that performs control processing, a high-speed arithmetic unit 2 that can perform high-speed arithmetic operations, a RAM (memory) 3 that holds data and programs, and an image processing unit 101. And a communication control unit 4 capable of exchanging data. In addition, the image processing unit 101 includes a compression / expansion unit 5 that expands compressed data sent from the image processing unit 101 or compresses image data after image processing.

  Of these, at least the communication control unit 4, the high-speed calculation unit 2, the compression / decompression unit 5, and the RAM 3 are preferably connected to a high-speed internal bus 6.

  The high-speed arithmetic processing unit 102 having the configuration of the present embodiment has the following characteristics. The high-speed calculation unit 2 has a calculation capability capable of sufficiently high-speed image processing and information processing. The image processing unit 101 and the high-speed calculation processing unit 102 have significantly higher calculation capabilities than the CPUs.

  The high-speed calculation unit 2 is a fixed circuit that calculates a specific process at high speed, a flexible circuit (FPGA) that can change the process depending on the situation, or a single instruction multiple that can process a large number of data for one instruction. Data), a VLIW (Very Long Instruction Word) that simultaneously executes a plurality of instructions that are not dependent on each other as a single instruction, a reconfigurable arithmetic circuit that performs processing by connecting a large number of processor elements having simple arithmetic functions, etc. Various configurations can be taken. The high-speed calculation unit 2 may be realized by any one of these or a combination thereof.

  This is because the optimum configuration differs depending on the application and further individual operations within the application. For example, in order to realize high-speed processing of the JPEG codec, it is effective to speed up the color conversion from the RGB space to the YUV space by SIMD, but it is desirable that the Huffman codec is performed by a dedicated circuit. Therefore, it can be said that it is reasonable to realize high-speed processing by combining these plural functions.

  Although the optimum configuration varies depending on the application, it is desirable to be programmable as much as possible in order to support a large number of processes on the same platform.

  The high-speed arithmetic processing unit 102 can perform arithmetic processing and transfer processing in parallel regardless of the state of the image processing unit 101.

  The high-speed arithmetic processing unit 102 includes a data acceptability determination unit 7 that determines that data can be received, and thereby determines that data can be received. The determination result can be detected by the communication control unit 13 by the image processing unit 101. In addition, in order to be able to receive data, it is necessary to secure a memory area in which data to be transferred and temporary data for calculating data can be stored.

  The high-speed arithmetic processing unit 102 desirably has a memory (such as a RAM) having a size capable of storing at least one document image so that the document can be processed in units of one sheet. If one original image cannot be stored, the data must be divided and transmitted and processed.

  The memory area of the high-speed arithmetic processing unit 102 includes an OS use area, a program use area, an input image data holding area, an output image data holding area, and a work memory. The high-speed arithmetic processing unit 102 needs to have a memory size larger than the sum of these memory use areas. In this embodiment, a large-capacity memory capable of storing at least one original image is provided.

  Control by the CPU of the high-speed arithmetic processing unit 102 will be described. The CPU 1 and the memory 3 execute the OS and execute programs on the OS. Control of data input from the communication control unit 4 and control at the time of processing by the high-speed arithmetic unit 2 are also performed. Further, in the processing for data, when the execution by the high-speed arithmetic unit 2 is difficult or there is no processing performance merit at the time of execution, a part of the data processing may be performed by the CPU 1. Generally, the high-speed calculation unit 2 is inferior in flexibility to the CPU 1, and there are cases where there are few merits to be executed by the high-speed calculation unit 2. Specifically, codec header processing and the like.

(Connection between image processing unit 101 and high-speed arithmetic processing unit 102)
Communication means between the image processing unit 101 and the high-speed arithmetic processing unit 102 will be described. The connection between the communication control unit 13 and the communication control unit 4 may be wired or wireless. However, the transfer speed of the network connected to the high-speed bus 103 is desirably high enough to transmit a target image within an appropriate time, and is preferably 100 Mbps or higher. A general high-speed interface such as PCI Express or SATA may be used instead of the LAN control unit 21, but the speed may not be so high. According to the configuration of the present embodiment, the transfer time is concealed by the read operation by the parallel operation of the read operation, transfer, and arithmetic processing described later. This is because the processing efficiency can be improved even when an interface is used. In the present embodiment, the high-speed bus 103 is not always necessary.

  FIG. 6 shows a power supply system of the image forming apparatus 100 of the present embodiment. Since the image processing unit 101 and the high-speed arithmetic processing unit 102 are physically different units, they may have separate power sources. However, as shown in FIG. 6, a power supply line 104 is used for the image processing unit 101. Alternatively, AC power may be supplied, and the high-speed arithmetic processing unit 102 may receive DC power supply from the image processing unit 101 using the power supply line 105. In this case, since it is not necessary to prepare a separate AC power supply unit, a low-cost system can be realized. Further, as described above, the image processing unit 101 and the high-speed arithmetic processing unit 102 may be physically connected.

(Configuration of image processing apparatus 201 without accelerator)
FIG. 7 shows a configuration diagram of the image processing apparatus 201 not equipped with an accelerator. As illustrated, the basic configuration is the same as that of the image processing unit 101. The accelerator non-installed image processing apparatus 201 (non-master device 201) and the image processing unit 101 (master device 101) are image processing units having similar functions. The master device 101 is a high-speed arithmetic processing unit 102 (slave device 102). The non-master unit 201 can be said to be an image processing unit that is not linked to the slave unit 102.

  Similar to the image processing unit 101, the image processing apparatus 201 not equipped with an accelerator has a use determination unit 22. The use determination unit 22 determines whether or not the high-speed arithmetic processing unit 102 is required to perform the process in performing the process instructed by the user. These are preferably determined in advance by the application. In the image processing apparatus 201 not equipped with an accelerator, the use determination unit 22 determines whether or not the high-speed calculation processing unit 102 needs to be used, and if it is determined that the high-speed calculation processing unit 102 is necessary, the high-speed calculation processing unit 102 is linked. A use request is issued to the image processing unit 101.

(Data processing flow)
FIG. 8 shows a data processing flow of the image processing system of this embodiment. This data processing flow is a data processing flow in which data to be processed is transmitted from a machine (non-master device 201) to which the high-speed calculation processing unit 102 is not linked to the high-speed calculation processing unit 102 to perform calculation. The following processes (1) to (13) are performed.

(1) The non-parent device 201 determines whether the processing in the high-speed arithmetic processing unit 102 is necessary in the use determination unit 22.
(2) The non-master unit 201 extracts the machine (master machine 101) to which the high-speed arithmetic processing unit 102 is linked.
(3) The non-master unit 201 issues a use request for the high-speed arithmetic processing unit 102 to the master unit 101 (S101). When the use request is made, a use request information table (FIG. 5) is transmitted.

(4) The parent device 101 uses the operation arbitration unit 21 to create a use request list from the non-parent device 201 including itself. The usage request list is on a first-come-first-served basis. Further, it is desirable that the high-speed arithmetic processing unit 102 does not perform simultaneous arithmetic processing on a plurality of data.
(5) Based on the priority order of the use request list, the operation arbitration unit 21 confirms whether the requested processing can accept data in the high-speed arithmetic processing unit 102 (S102).
(6) The data acceptability determination unit 7 determines whether or not data can be received, and the high-speed arithmetic processing unit 102 returns a data reception determination result (S103).

(7) The base unit 101 determines whether or not the high-speed arithmetic processing unit 102 is usable in the operation arbitration unit 21 according to the status of the base unit itself and the high-speed arithmetic processing unit 102 (usability determination).
(8) If the master unit 101 is usable, the master unit 101 notifies the non-master unit 201 of the use permission together with the network address information of the high-speed arithmetic processing unit 102 (S105). In addition, a command is issued to the high-speed arithmetic processing unit 102 so as to perform processing for accepting data from the requested non-parent device 201 (S104).

(9) The non-master device 201 transmits data to the high-speed arithmetic processing unit 102 (S106).
(10) The high-speed arithmetic processing unit 102 receives data from the non-parent device 201 and executes processing.
(11) When the processing is completed, the high-speed arithmetic processing unit 102 notifies the non-parent device 201 (S107).
(12) The non-master device 201 takes the processed data of the high-speed arithmetic processing unit 102 (S108).
(13) The high-speed arithmetic processing unit 102 notifies the master unit 101 that the processing has been completed (S109).

  With this data processing method, it is possible to perform calculation on the data of the non-parent device 201 by the high-speed arithmetic processing unit 102 without the data to be calculated passing through the parent device 101. That is, it is possible to cause the auxiliary arithmetic device to execute the processing of the image processing apparatus without the auxiliary arithmetic device without increasing the load on the machine body linked to the auxiliary arithmetic device (accelerator). In other words, according to the present embodiment, it is possible to use the resources of the auxiliary arithmetic device even from an image processing device that is not linked to the arithmetic processing device.

  Further, according to this data processing method, the use request list management between the image processing units is performed by the image processing unit, so that it is not necessary for the high-speed arithmetic processing unit 102 to perform these processes. Further, since high-speed arithmetic execution arbitration and advanced processing such as setting and control for the high-speed arithmetic processing unit 102 are performed by the machine (master unit 101) associated with the high-speed arithmetic processing unit 102, the high-speed arithmetic processing unit 102 Does not have to have those functions.

  Note that when the parent device 101 uses the high-speed arithmetic processing unit 102, the operation of the non-parent device 201 in the above flow is executed by the parent device 101.

(Usability determination)
The usability determination performed by the operation arbitration unit 21 will be described.
In accordance with the use request list, the operation arbitration unit 21 determines whether or not the operation processing related to the use request can be executed by the high-speed operation processing unit 102 from the one with the highest priority.

FIG. 9 is a diagram illustrating a processing procedure for determining availability.
When the image processing unit 101 receives the use request (S201), the operation arbitration unit 21 creates a use request list by listing the use requests (S202), and determines whether the calculation target data related to the received use request can be received. An inquiry is made to the high-speed arithmetic processing unit 102 (S203).

  The data acceptability determination unit 7 of the high-speed arithmetic processing unit 102 that has received the inquiry calculates a free space that can be secured, and checks whether there is a sufficient free space in the work memory (S204, S205). Here, the data size of the data to be calculated and whether or not there is free space for the work memory in which intermediate data necessary for processing is placed are checked. A memory area that can expand the intermediate data obtained by expanding the image must be secured.

  The work memory may be the estimated capacity when checking the free capacity. Also, if the previous process is being executed at the time of confirmation, the free capacity in the near future can be estimated. For the work memory, it is desirable that the data acceptance determination unit 7 can calculate from the acceptance request notification in each process. It is assumed that the calculation formula is created at the design stage.

Next, the data acceptability determination unit 7 examines conditions other than the data size and the free memory capacity, and determines acceptability (S206).
Examples of non-acceptable non-free memory are:
A process that cannot be executed by the high-speed arithmetic processing unit 102.
The high-speed arithmetic processing unit 102 is performing some processing.
-The high-speed arithmetic processing unit 102 is turned off or malfunctions.
The request was from a terminal that was prohibited from using the high-speed arithmetic processing unit 102.
and so on.

  The determination result by the data acceptance determination unit 7 is received by the operation arbitration unit 21 via the communication control unit 13 of the image processing unit 101 (S207). The operation arbitration unit 21 determines availability based on the received determination result and the priority order of the use request list (S208), and the determination result is used together with the network address information of the high-speed arithmetic processing unit 102 to issue the use request. Send to. When the determination result is “use permission”, the processing from S106 onward in FIG. 8 becomes possible.

1 CPU
2 High-speed calculation unit 3 RAM
4 Communication Control Unit 5 Compression / Expansion Unit 6 Internal Bus 7 Data Acceptability Determination Unit 10 CPU
11 ROM
12 Compression / decompression unit 13 RAM
14 HDD
DESCRIPTION OF SYMBOLS 15 Image reading control part 16 Image reading part 17 Print control part 18 Image printing part 19 Operation part 20 Reading completion detection part 21 Operation arbitration part 22 Use determination part 30 Communication interface 100 Image processing apparatus 101 High-speed arithmetic processing part (slave unit)
102 Image processing unit (base unit)
103 High-speed bus 200 Network 201 Non-accelerator image processing device (non-master)

JP 2007-265208 A

Claims (5)

An image processing system in which a high-speed arithmetic processing device, a parent device, and an image processing device are connected via a network,
The high-speed arithmetic processing device includes:
Acceptability judging means for judging whether or not calculation target data can be accepted;
A high-speed computing means for computing received data;
A calculation result transmitting means for transmitting the calculation result to the image processing apparatus;
With
The image processing apparatus includes:
Use request issuing means for issuing a request for use of the high-speed arithmetic processing device to the master unit;
Data transmission means for transmitting the calculation target data to the high-speed arithmetic processing device based on permission to use the high-speed arithmetic processing device from the master unit;
With
The base unit is
Network address information holding means for holding network address information of the high-speed processing unit;
An operation arbitration unit that determines whether or not the image processing apparatus can use the high-speed arithmetic processing unit based on a use request issued by the use request issuing unit and a determination result of the acceptability determination unit;
Use permission transmission means for transmitting the use permission to the image processing apparatus based on a result of determination by the operation arbitration means;
An image processing system comprising: The image processing apparatus includes:
Use determination means for determining whether or not the image processing needs to be performed using the high-speed arithmetic processing device in performing image processing,
The image processing system according to claim 1, wherein the use request issuing unit issues the use request when the use determining unit determines that the use request is necessary. The request for use includes attribute information of data to be calculated,
When the operation arbitration means receives the use request, it transmits an acceptance request notification including the attribute information to the high-speed arithmetic processing device,
3. The image processing system according to claim 1, wherein the acceptability determination unit determines whether the calculation target data is acceptable based on the attribute information.   The image processing system according to claim 3, wherein the attribute information is at least one of a file size, the number of pixels, the number of layers, and the number of bits. Image processing of an image processing system in which a high-speed arithmetic processing device, a parent device, and an image processing device are connected via a network, and the parent device holds network address information of the high-speed arithmetic processing device A method,
A use request issuing step for issuing a request for using the high-speed arithmetic processing device from the image processing device to the master unit;
Inquiring whether it is possible to accept operation target data related to the use request to the high-speed arithmetic processing device using the network address information in the base unit;
An acceptance determination step for determining whether the calculation target data is acceptable;
A use permission transmitting step for transmitting, to the image processing device, a use permission for the image processing device to use the high-speed arithmetic processing device, based on a determination result by the acceptability determining step;
The image processing apparatus, based on the use permission, transmitting data to be calculated to the high-speed arithmetic processing apparatus;
An image processing method comprising:

Images