JP5395551B2 - Drawing device - Google Patents

Description

  The present invention relates to a drawing apparatus that converts a wiring pattern of a printed circuit board designed by, for example, CAD into an exposure pattern used in an exposure apparatus.

  A direct exposure apparatus, which is one of the exposure apparatuses, is an apparatus that exposes a wiring pattern on a printed circuit board without using a mask film. At the time of exposure, a wiring pattern designed by CAD or the like is converted into an exposure pattern ( This conversion is hereinafter referred to as “raster conversion”).

  The wiring pattern is composed of a set (vector data) of unit graphic data expressed in a vector format (the unit graphic is a simple shape such as a circle, a rectangle, or a triangle). That is, as shown in FIG. 4, for example, one oval wiring pattern P is a set of circles P <b> 1 and P <b> 2 that are two unit graphics and a rectangle P <b> 3 that is one unit graphic. The exposure pattern is composed of a bitmap image (raster data) having a size corresponding to the exposure resolution.

  The rendering device has a vector memory that stores vector data, a raster conversion unit that performs raster conversion, and a raster memory that stores raster data. The raster conversion unit generates raster data by raster-converting vector data extracted from the vector memory. And stored in raster memory. The raster data stored in the raster memory is used as an exposure pattern during exposure.

  The exposure accuracy can be significantly improved by detecting the distortion for each substrate and correcting the exposure pattern. In this case, in order to perform highly accurate correction, it is desirable in terms of calculation load to perform correction calculation at the stage of the wiring pattern that is vector data. That is, in order to improve the exposure accuracy, it is necessary to raster-convert the corrected wiring pattern for each substrate. To improve the work efficiency, the raster conversion time is within the exposure time of one substrate. It is necessary to fit in. That is, raster conversion needs to be performed in real time at a speed corresponding to the exposure speed.

  For this necessity, for example, Patent Document 1 prepares a plurality of raster conversion processing circuits each composed of a processor or dedicated hardware, and divides the printed circuit board into regions corresponding to the number of raster conversion processing circuits. A technique has been proposed for raster-converting a wiring pattern in an area in which each raster conversion processing circuit is designated. In this technique, since the raster memory can be divided in accordance with the divided areas, the connection between the raster conversion processing circuit and the memory and the memory access control are simplified.

JP 2005-300809 A

  However, there is a case where the wiring patterns are biased in a specific area. In such a case, only a specific raster conversion processing circuit operates, and the others are not operated because there is no data to be processed. That is, depending on the wiring pattern, the parallel processing efficiency may decrease. In such a case, for example, if the unit graphic data constituting the wiring pattern is distributed to each raster conversion processing circuit in order from the top of the data set, the load on each raster conversion processing circuit can be made equal.

  However, in order to store raster data generated by a plurality of raster conversion processing circuits in one raster memory, it is necessary to connect the raster conversion processing circuit and the memory and perform memory access control. The number of raster conversion processing circuits As this increases, connection and memory access control become more complex. Furthermore, the overall performance may deteriorate due to an access conflict with the raster memory.

  An object of the present invention is to provide a drawing apparatus that enables efficient parallel processing of a plurality of raster conversion processing circuits and is excellent in processing efficiency.

To solve the above problems, the present invention is designated in advance and vector data generating means, said first vector data generated as the first vector data composed of a wiring pattern to be drawn on the printed board from each unit figure data Vector data sorting means that generates second vector data by sorting on the basis of the arrangement coordinates on the printed circuit board in units of areas, and correction for detecting printed circuit board distortion and correcting the wiring pattern according to the distortion Correction parameter generation means for generating parameters, correction means for correcting the second vector data based on the correction parameters to generate third vector data, and the third vector data on the printed circuit board vector data to generate a plurality of fourth vector data coordinates of location coordinates and distributed to each of the unit graphic data to the original Interface unit and said plurality of raster conversion processing means for generating a first raster data receives a fourth vector data, raster data to generate a second raster data coupling said first raster data a drawing apparatus comprising: a coupling means, wherein the raster conversion processing means, respectively, a processing area management means for setting a current process area in the processing areas partitioned in size that has been set in advance, the fourth When the unit graphic data included in the vector data is included in the current processing area, the fifth vector data is used, and the unit graphic data included in the fourth vector data is stored in the current processing area and other areas. When straddling, vector data dividing means that divides the part included in the current processing area to be the fifth vector data, and the remaining part is the sixth vector data; Buffer means for temporarily storing the sixth vector data, and inputting the fourth vector data to the vector data dividing means when the current processing area is changed by the processing area management means; Raster conversion means for converting the vector data to generate first raster data, a plurality of cache means for temporarily storing a part of the first raster data, and a raster for storing the first raster data And the size of the processing area is the same as the memory size of the cache means, and the vector data sorting means multiplies the number of bits in the X direction of the processing area by the number of raster conversion processing means. The number of bits obtained by multiplying the number of bits in the X direction by the number of bits in the Y direction and the number of bits in the cache area multiplied by the number of cache means. The vector data distribution unit repeatedly distributes the plurality of fourth vector data to the plurality of raster conversion processing units in order, with a number area as a sorting unit .

  According to the present invention, it is possible to perform efficient parallel processing of a plurality of raster conversion processing circuits, and it is possible to provide a drawing apparatus with excellent processing efficiency.

It is a block diagram of the drawing apparatus which concerns on embodiment of this invention. It is a figure which shows the conversion procedure until it converts vector data into raster data in the embodiment of the present invention. It is a figure which shows the process area | region and sort area | region in embodiment of this invention. This is an example of dividing a wiring pattern into a set of unit graphics.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is a configuration diagram of a drawing apparatus according to an embodiment of the present invention, and FIG. 2 is a diagram showing a conversion procedure until vector data is converted into raster data. In the drawing, a drawing apparatus 100 includes a vector data generating unit 101, a vector data sorting unit 102, a correction parameter generating unit 103, a vector memory 104, a correcting unit 105, a vector data distributing unit 106, and first to eighth raster conversion processes. It basically comprises means 200 (200-0 to 7) and raster data combining means 113.

  A wiring pattern PN generated by a commercially available CAD or the like is input to the vector data generating means 101, and this wiring pattern PN is converted into a set of unit graphic data by the vector data generating means 101 to generate the first vector data D1. Is done. Since the unit graphic is a closed graphic, each unit graphic data is described by the start point (which is also the end point) and the coordinates of other feature points (corner points). The start point may be any feature point, but here, the feature point having the smallest X coordinate is selected as the start point.

  As can be seen from the processing area and sort area in FIG. 3, the wiring pattern drawing area is divided into areas of a predetermined size in the X and Y directions, and this divided area is divided into a matrix. This is the processing area 10. In the example of FIG. 3, the processing area 10 is set to an area of 256 bits × 256 bits. Further, the size in the X direction is the number of bits obtained by multiplying the number of raster conversion processing means 200 by the X direction size of the processing area 10 (256 bits in the example of FIG. 3), and the size in the Y direction is the number of cache means 111 and the processing area 10. An area that is the number of bits multiplied by the size in the Y direction (256 bits in the example of FIG. 3) is set as the sort area 20. The sort area 20 in FIG. 3 is an example in which the number of raster conversion processing means 200 is 8, and the number of cache means 111 is 4, and the size of the sort area 20 is 2048 bits × 1024 bits.

  The vector data sorting means 102, to which the first vector data D1 is inputted from the vector data generating means 101, sorts the first vector data in units of areas designated in advance based on the arrangement coordinates on the printed circuit board, and secondly sorts the second vector data. The unit graphic data which is a component of the first vector data D1 is sorted based on the sort area 20 to be second vector data D2 and stored in the vector memory 104. .

  The correction parameter generation unit 103 detects distortion for each printed circuit board, and generates a correction parameter PA for correcting the wiring pattern PN from an error between the original printed circuit board shape and the detected distortion. The correction unit 105 receives the correction parameter PA generated by the correction parameter generation unit 103 and the second vector data D2 stored in the vector memory 104. The correction unit 105 receives the second vector data based on the correction parameter PA. D2 is corrected to generate third vector data D3.

  The third vector data D3, which is a unit graphic, is input to the X-axis direction data distribution unit 106, and the X-axis direction data distribution unit (vector data distribution unit) 106 performs raster conversion processing unit 200 for each X-axis direction of the processing area 10. Are assigned to the corresponding raster conversion processing means 200 based on the X coordinate of the starting point. Here, the distributed third vector data D3 is referred to as fourth vector data D4. That is, the X-axis direction data distribution unit 106 generates the fourth vector data D4 by distributing the third vector data D3 for each unit graphic data based on the coordinate values of the arrangement coordinates on the printed circuit board.

  For example, when the X direction size of the processing area 10 is 256 bits and the number of raster conversion processing means 200 is 8, when the X coordinate of the starting point of the unit graphic data is 0 to 255, the processing area 10 is distributed to the raster conversion processing means 200-0. When the X coordinate of the unit graphic data is 256 to 511, the unit graphic data is distributed to the raster conversion processing unit 200-1, and similarly to the raster conversion processing unit 200-7. Similarly, unit graphic data having an X coordinate of 2048 or later is repeatedly distributed in the order of raster conversion processing means 200-0 to 200-7.

  Here, since the unit graphic data is sorted in units of 256 bits × 8 in the X-axis direction in advance by the vector data sorting means 102, the unit is averaged by the first to eighth raster conversion processing means 200-0 to 7. Graphic data is distributed.

  Each of the raster conversion processing means 200-0 to 7 includes a processing area management means 107, a vector data dividing means 108, a buffer means 109, a raster conversion means 110, a cache means (0 to 3) 111, and a raster memory 112, respectively. The raster memory 112 stores first raster data R1.

  Among these, the processing area management unit 107 sets the current processing area in the processing area 10 divided into an arbitrary size set in advance, and the number of processing areas 10 set at a time is the cache means 111 described later. Is the same number. The vector data dividing means 108 processes the fourth vector data D4 for each unit graphic data as described below.

  That is, if the unit graphic data is included in the processing area (current processing area) 10 to be preferentially processed, the fifth vector data D5 is used as it is, and if it is not included, the sixth vector data D6 is used. In addition, when the processing area 10 to be preferentially processed and the other processing areas 10 are straddled, the portion of the unit graphic data included in the processing area 10 to be preferentially processed is divided into unit graphic data to obtain fifth vector data. The other vector data is D6, and the other vector data is D6.

  The buffer means 109 temporarily stores the sixth vector data D6. When the processing area 10 to be preferentially processed is switched by the processing area management means 107, the sixth vector data D6 is changed to the fourth vector data D4. Similarly to the above, processing is performed by the vector data dividing means 108 to generate fifth vector data D5 and sixth vector data D6. For example, if the fourth vector data D4 includes unit graphic data extending over three processing areas 10, the vector data dividing means 108 generates three unit graphic data as the fifth vector data D5 through two division procedures. Is done.

  The raster conversion means 110 raster-converts the fifth vector data D5 for each unit graphic data to generate first raster data R1. The cache unit 111 is composed of a memory having the same size as the processing area 10 and temporarily stores unit graphic data constituting the first raster data R1 included in the same processing area 10. The raster memory 112 stores all unit graphic data included in the first raster data R1. Here, the raster memory 112 is constituted by a DRAM having a large capacity but capable of only burst access, and the cache means 111 is constituted by an SRAM having a small capacity but capable of random access.

  The plurality of unit graphic data constituting the first vector data D1 are arranged in an arbitrary order. Therefore, the first raster data R1 is also generated in an arbitrary order. For this reason, when the first raster data R1 is stored in the raster memory 112 as it is, the access efficiency is lowered because of random access. In order to avoid this, the cache unit 111 stores the first raster data R1 in the same processing area in random access in the cache unit 111 which is a temporary SRAM, and collectively stores the first raster data R1 in the cache unit 111 later. Are stored in the raster memory 112 which is a DRAM by burst access.

  The area stored in the cache means 111 is the processing area 10 set by the processing area management means 107, and the processing area 10 set in the processing area management means 107 is changed when there is no free memory area in the buffer means 109. At the same time, the first raster data R 1 stored in the cache unit 111 is moved to the raster memory 112. The number of cache units 111 is the number of processing areas that can be processed at one time by one raster conversion processing unit 200. The larger the number, the higher the processing efficiency, but generally the memory size that can be mounted is limited, so it can be mounted. It is mounted on the drawing device as many as possible. Here, since the unit graphic data is sorted in advance in the area of 256 bits × the number of cache means 111 by the vector data sort means 102, the cache means 111 can be used efficiently.

  The raster data combining unit 113 combines the first raster data R1 divided and stored in the raster memory 112 of the plurality of raster conversion processing units 200 into the second raster data R2, which is used as an exposure pattern for exposure. use.

  According to this embodiment, even when the number of parallel processing circuits for raster conversion is increased in order to improve the processing performance of raster conversion executed by the raster conversion processing means 200, the number of parallel processing circuits for raster conversion (raster conversion processing means) Number) and the number of cache 111 means, it is possible to efficiently perform parallel processing while reducing the processing load by sorting, and to improve the processing performance of raster conversion. Can do. In other words, since the data density of the processing area 10 units is non-uniform, if the processing is performed as it is, the parallel processing capability of the raster conversion processing cannot be fully exerted, and the vector data is divided into the areas. Sorting in advance enables efficient parallel processing, but the preprocessing load is too great. However, in this embodiment, the vector data is presorted easily in a rough area called a sort area, and the detailed sort is performed in the raster conversion processing unit. Efficiency can be improved.

  In addition, this invention is not limited to this embodiment, All the technical matters contained in the technical idea of the invention described in the claim are object.

DESCRIPTION OF SYMBOLS 101 Vector data generation means 102 Vector data sort means 103 Correction parameter generation means 104 Vector memory 105 Correction means 106 X-axis direction data distribution means 107 Processing area management means 108 Vector data division means 109 Buffer means 110 Raster conversion means 111 Cache means 112 Raster Memory 113 Raster data combining means 200 Raster conversion processing means

Claims (3)

A vector data generating means for generating a wiring pattern to be drawn on the printed circuit board as vector data composed of unit graphic data,
Vector data sorting means for sorting the vector data generated by the vector data generating means based on arrangement coordinates on the printed circuit board in a predetermined area unit;
A vector data distribution means for distributing the sorted vector data for each unit graphic data to generate a plurality of divided vector data;
A plurality of raster conversion processing means each having a plurality of cache means for performing parallel raster conversion on the plurality of divided vector data;
A raster data combining means for combining raster data generated by the raster conversion processing means ,
The size of the processing area is the same as the memory size of the cache means,
The vector data sorting means sets the number of bits obtained by multiplying the number of bits in the X direction of the processing area by the number of raster conversion processing means as the number of bits in the X direction, and sets the number of cache means as the number of bits in the Y direction of the processing area. The area where the number of bits multiplied is the number of bits in the Y direction is used as the unit of sorting,
The drawing apparatus, wherein the vector data distribution means repeatedly distributes the plurality of divided vector data to the plurality of raster conversion processing means in order . A vector data generating means for generating a wiring pattern to be drawn on the printed circuit board as first vector data each composed of unit graphic data;
Vector data sorting means for generating the second vector data by sorting the first vector data based on the arrangement coordinates on the printed circuit board in units of areas designated in advance;
Correction parameter generation means for detecting a distortion of the printed circuit board and generating a correction parameter for correcting the wiring pattern according to the distortion;
Correction means for correcting the second vector data based on the correction parameter to generate third vector data;
Vector data distribution means for generating a plurality of fourth vector data by distributing the third vector data for each unit graphic data based on the coordinate values of the arrangement coordinates on the printed circuit board;
A plurality of raster conversion processing means for receiving the fourth vector data and generating first raster data;
Raster data combining means for combining the first raster data to generate second raster data;
A drawing apparatus comprising:
Each of the raster conversion processing means,
A processing area management means for setting a current process area in the processing areas partitioned into a preset size,
When the unit graphic data included in the fourth vector data is included in the current processing area, it is set as fifth vector data, and the unit graphic data included in the fourth vector data is different from the current processing area. A vector data dividing means that divides the part included in the current processing area into fifth vector data and the remaining part as sixth vector data;
Buffer means for temporarily storing the sixth vector data and inputting the fourth vector data to the vector data dividing means when the current processing area is changed by the processing area management means;
Raster conversion means for raster-converting the fifth vector data and generating first raster data;
A plurality of cache means for temporarily storing a part of the first raster data;
A raster memory for storing the first raster data;
Having
The size of the processing area is the same as the memory size of the cache means,
The vector data sorting means sets the number of bits obtained by multiplying the number of bits in the X direction of the processing area by the number of raster conversion processing means as the number of bits in the X direction, and sets the number of cache means as the number of bits in the Y direction of the processing area. The area where the number of bits multiplied is the number of bits in the Y direction is used as the unit of sorting,
The drawing apparatus, wherein the vector data distribution means repeatedly distributes the plurality of fourth vector data to the plurality of raster conversion processing means in order . Before Symbol vector data distributing means drawing apparatus according to claim 2, characterized in that <br/> for distributing the third vector data based on one of the coordinate values and the Y-axis direction of the coordinate values of the X-axis direction .

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