JP5395489B2 - Electronic component and manufacturing method thereof, wiring board - Google Patents

Description

  The present invention relates to an electronic component housed in a wiring board, a manufacturing method thereof, and a wiring board.

  In recent years, semiconductor integrated circuit elements (IC chips) used as computer microprocessors and the like have become increasingly faster and more functional, with an accompanying increase in the number of terminals and a tendency to narrow the pitch between terminals. . In general, a large number of terminals are densely arranged on the bottom surface of an IC chip, and such a terminal group is connected to a terminal group on the motherboard side in the form of a flip chip. However, it is difficult to connect the IC chip directly on the mother board because there is a large difference in the pitch between the terminals on the IC chip side terminal group and the mother board side terminal group. For this reason, a method is generally employed in which a package is prepared by mounting an IC chip on an IC chip mounting wiring board, and the package is mounted on a motherboard. In a wiring board for mounting an IC chip constituting this type of package, it has been proposed to provide a capacitor (also referred to as a “capacitor”) in order to reduce switching noise of the IC chip and stabilize the power supply voltage. . For example, a wiring substrate in which a capacitor is embedded in a resin core substrate (see, for example, Patent Document 1) and a wiring substrate in which a capacitor is embedded in a buildup layer formed on the front surface or the back surface of the resin core substrate have been proposed. .

  As a capacitor built in the wiring board, a via array type ceramic capacitor has been put into practical use. The ceramic capacitor includes a ceramic sintered body in which a plurality of ceramic dielectric layers and a plurality of internal electrode layers are alternately stacked. In the ceramic sintered body, a plurality of via conductors in the capacitor that are electrically connected to the internal electrode layers through the ceramic dielectric layers are arranged in an array. Furthermore, external electrodes connected to the end portions of the via conductors in the capacitors are provided on the front and back surfaces of the ceramic sintered body.

  Each external electrode in this ceramic capacitor is made of, for example, a metallized metal layer formed mainly of nickel. In order to improve the connection reliability with the wiring board, a ceramic capacitor has been developed in which a protruding conductor (copper post) made of copper is projected on an external electrode. By providing the projecting conductor, the projecting conductor bites into an insulating resin layer constituting the wiring board when incorporated in the wiring board, thereby preventing displacement of the ceramic capacitor. Moreover, since the contact area between the ceramic capacitor and the insulating resin layer is increased by forming the protruding conductor, the adhesion between the two is improved.

JP-A-2005-39243

  By the way, in the ceramic capacitor, the external electrode is formed mainly of nickel, and the protruding conductor is formed of copper. Therefore, different metals are joined to the external electrode and the protruding conductor, and there arises a problem that sufficient adhesion cannot be secured. In addition, the protruding conductor has a large volume and stress tends to remain inside, resulting in insufficient strength. For this reason, when incorporated in the wiring board, there is a problem that the protruding conductor is broken, and the reliability of the wiring board may be lowered.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a highly reliable electronic component that can sufficiently ensure the strength of the protruding conductor and a method for manufacturing the same. Another object is to provide a suitable wiring board incorporating the electronic component.

And as means (means 1A ) for solving the above-mentioned problems, a ceramic sintered body having a main surface and a back surface, and a first metal disposed on at least one of the main surface and the back surface of the ceramic sintered body. An external electrode having a metallized metal layer containing a material, a covering metal layer made of a second metal material having a higher conductivity than the first metal material and covering the surface of the metallized metal layer; and on the external electrode An electronic component comprising a plurality of protruding conductors, wherein the plurality of protruding conductors are made of the same second metal material as that of the covering metal layer, and constitute the plurality of protruding conductors. The maximum particle size of the metal particles is 5 μm or more, the maximum particle size of the metal particles constituting the coated metal layer is 3 μm or less, and the coated metal layer also covers the surfaces of the plurality of protruding conductors. Characteristic electric There is a part.
Further, as another means (means 1B) for solving the above-mentioned problem, a ceramic sintered body having a main surface and a back surface, and a first electrode disposed on at least one of the main surface and the back surface of the ceramic sintered body are arranged. An external electrode having a metallized metal layer including one metal material, and a covering metal layer made of a second metal material having higher conductivity than the first metal material and covering a surface of the metallized metal layer; An electronic component comprising a plurality of projecting conductors projecting on an electrode, wherein the plurality of projecting conductors are made of the same second metal material as the covering metal layer, and the plurality of projecting conductors The maximum particle size of the metal particles constituting the coating metal layer is 3 μm or less, and the maximum particle size of the metal particles constituting the coating metal layer is Metallized metal layer There is an electronic component characterized by being smaller than the maximum particle size of the metal particles formed.

Therefore, according to the electronic parts of means 1A and 1B , the adhesion between the coated metal layer and the metallized metal layer can be enhanced by reducing the particle size of the metal particles constituting the coated metal layer. Further, by forming the protruding conductor using the same metal material as that of the coated metal layer, sufficient adhesion between the coated metal layer and the protruding conductor can be ensured. Furthermore, since the maximum particle size of the metal particles constituting the protruding conductor is larger than the maximum particle size of the metal particles forming the coated metal layer, the residual stress inside the protruding conductor can be suppressed. As a result, the strength of the protruding conductor can be sufficiently secured, and problems such as bending of the protruding conductor can be solved. Further, by increasing the particle diameter of the metal particles constituting the protruding conductor, the grain boundary in the protruding conductor can be reduced and the resistance can be reduced.

The means 1B electronic components, a maximum particle size of the metal particles constituting the pre-Symbol coating metal layer is smaller than the maximum particle size of the metal particles constituting the metallized metal layer. Thus, when the particle size of the metal particles constituting the coated metal layer is reduced, the metal particles enter the metallized metal layer, and the coated metal layer and the metallized metal layer are securely adhered to each other. A coated metal layer can be formed. In addition, by reducing the metal particles of the coated metal layer, the smoothness of the surface of the coated metal layer is improved, and a protruding conductor having a uniform height can be formed.

The unit 1A electronic components, prior Symbol coating metal layer also covers the surface of said plurality of projecting conductors. Thus, by covering the protruding conductor with the covering metal layer having a small particle size, the grain boundary region becomes large on the surface, so that the roughening efficiency can be increased. Therefore, when an electronic component that has been subjected to the roughening treatment of the coating metal layer is built in the wiring board, sufficient adhesion with the resin insulating layer constituting the wiring board can be ensured.

The unit 1A, 1B electronic components, a maximum particle size of the metal particles constituting the pre-Symbol plurality of projecting conductors is not less 5μm or more, the maximum particle size of the metal particles constituting the coating metal layer is Ru der less 3μm . If you like this, since the metal particles of the coating metal layer with respect to metallized metal layer is reliably brought into close contact, it is possible to form the coating metal layer having excellent separation resistance. Moreover, the residual stress of the protruding conductor can be reliably suppressed, and the strength of the protruding conductor can be sufficiently ensured.

  It is preferable that the second metal material is copper, and it is more preferable to form the coated metal layer and the protruding conductor by copper plating. Thus, by forming the covering metal layer and the protruding conductor using copper, it is possible to reduce the manufacturing cost of the electronic component and easily reduce the resistance of the protruding conductor and the external electrode. .

  Examples of the ceramic sintered body include a sintered body mainly composed of a perovskite oxide. The metallized metal layer preferably includes nickel particles as metal particles as a main component and the perovskite oxide. Thus, by using nickel as a material for forming the metallized metal layer, the manufacturing cost of the ceramic sintered body can be suppressed as compared with the case of using relatively expensive palladium. Further, by adding a perovskite oxide to the metallized metal layer, the difference in thermal shrinkage of the metallized metal layer in the ceramic sintered body can be suppressed, and problems such as cracks and delamination can be avoided.

  Examples of the electronic component include a chip capacitor and a ceramic capacitor. Further, as a suitable ceramic capacitor, a ceramic sintered body having a main surface and a back surface is provided, and a plurality of internal electrodes are laminated on the ceramic sintered body via a ceramic dielectric layer, and the plurality of internal capacitors are arranged. A ceramic capacitor in which a plurality of via conductors in a capacitor connected to the electrode are provided, and the external electrode is connected to at least one of a main surface side end and a back surface side end in the plurality of capacitor via conductors, etc. Can be mentioned. The ceramic capacitor is preferably a via array type ceramic capacitor in which the plurality of capacitor via conductors are arranged in an array as a whole. With such a structure, the inductance of the capacitor can be reduced, and noise absorption and voltage stabilization can be achieved.

  Examples of the perovskite oxide include barium titanate, lead titanate, and strontium titanate. Since this kind of oxide has a high dielectric constant, it is extremely suitable as a dielectric in a capacitor, and by using it, a high-capacity capacitor can be easily realized.

  Further, as another means (means 2) for solving the above-mentioned problem, the electronic component for wiring board in which the surface of the external electrode is roughened is a resin having a core main surface and a core back surface. There is a wiring board characterized in that it is housed in a core board or in a wiring laminated part having a structure in which a resin interlayer insulating layer and a conductor layer are laminated.

  Therefore, according to the wiring board of the means 2, in the electronic component, since the coated metal layer constituting the external electrode has small metal particles, the surface of the copper plating layer can be reliably roughened. For this reason, the contact area between the external electrode and the resin interlayer insulating layer of the wiring board is increased, and the adhesion with the resin interlayer insulating layer can be sufficiently enhanced. In addition, since a protruding conductor with sufficient strength is provided on the external electrode, it is possible to improve the adhesion to the resin interlayer insulation layer and to ensure sufficient connection reliability with the conductor layer on the wiring board. can do.

  Specific examples of the resin core substrate include an EP resin (epoxy resin) substrate, a PI resin (polyimide resin) substrate, a BT resin (bismaleimide / triazine resin) substrate, and a PPE resin (polyphenylene ether resin) substrate. In addition, a substrate made of a composite material of these resins and organic fibers such as glass fibers (glass woven fabric or glass nonwoven fabric) or polyamide fibers may be used. Alternatively, a substrate made of a resin-resin composite material obtained by impregnating a thermosetting resin such as an epoxy resin with a three-dimensional network fluorine-based resin base material such as continuous porous PTFE may be used.

  The wiring laminated portion constituting the wiring board has a structure in which a resin interlayer insulating layer mainly composed of a polymer material and a conductor layer are laminated. In addition, the wiring lamination | stacking part may be formed only in any one on the said core main surface and the said core back surface, and may be formed in both on the said core main surface and the said core back surface. Is preferably formed on both the core main surface and the core back surface. With this configuration, an electric circuit can be formed in both the wiring laminated portion formed on the core main surface and the wiring laminated portion formed on the back surface of the core, thereby further enhancing the functionality of the wiring board. Can be planned.

  The resin interlayer insulation layer can be appropriately selected in consideration of insulation, heat resistance, moisture resistance and the like. Preferred examples of the material for forming the resin interlayer insulating layer include thermosetting resins such as epoxy resins, phenol resins, urethane resins, silicone resins, and polyimide resins, and thermoplastic resins such as polycarbonate resins, acrylic resins, polyacetal resins, and polypropylene resins. Etc. In addition, composite materials of these resins and organic fibers such as glass fibers (glass woven fabrics and glass nonwoven fabrics) and polyamide fibers, or three-dimensional network fluorine-based resin base materials such as continuous porous PTFE, epoxy resins, etc. A resin-resin composite material impregnated with a thermosetting resin may be used.

  The conductor layer is patterned on the resin interlayer insulating layer by a known method such as a subtractive method, a semi-additive method, or a full additive method. Examples of the metal material used for forming the conductor layer include copper, copper alloy, nickel, nickel alloy, tin, tin alloy and the like.

  Moreover, as another means (means 3) for solving the above-mentioned problem, in the method for manufacturing the electronic component, after performing the covering metal layer forming step of forming the covering metal layer by bright copper plating, There is a method of manufacturing an electronic component characterized by performing a protruding conductor forming step of forming the protruding conductor by matte copper plating.

  Therefore, according to the manufacturing method of means 3, since the bright copper plating in the coating metal layer forming step includes a brightener, the grain growth of the copper particles is suppressed, and the particle size of the copper particles in the coating metal layer can be reduced. . Further, in the matte copper plating in the protruding conductor forming step, the copper particles can be sufficiently grown and the particle diameter of the copper particles of the protruding conductor can be increased. Thus, when an electronic component is manufactured, since the copper particles of the coating metal layer are securely adhered to the metallized metal layer, a coating metal layer having excellent peeling resistance can be formed. Further, the residual stress of the protruding conductor can be reliably suppressed, and the strength of the protruding conductor can be sufficiently increased.

  In the covering metal layer forming step, the covering metal layer is preferably formed by bright copper pyrophosphate plating, and in the protruding conductor forming step, the protruding conductor is preferably formed by matte copper sulfate plating. . If it does in this way, the maximum particle diameter of the copper particle which comprises a protruding conductor can be 5 micrometers or more, and the maximum particle diameter of the copper particle which comprises a coating metal layer can be 3 micrometers or less.

1 is a schematic cross-sectional view showing a wiring board of an embodiment embodying the present invention. The schematic sectional drawing which shows a ceramic capacitor. The top view which shows a ceramic capacitor. The schematic sectional drawing which shows the principal part of a ceramic capacitor. The schematic sectional drawing which shows each metal particle size in a metallization metal layer, a copper plating layer, and a protruding conductor. Explanatory drawing of the manufacturing method of a ceramic capacitor. Explanatory drawing of the manufacturing method of a ceramic capacitor. Explanatory drawing of the manufacturing method of a ceramic capacitor. Explanatory drawing of the manufacturing method of a wiring board. Explanatory drawing of the manufacturing method of a wiring board. Explanatory drawing of the manufacturing method of a wiring board. Explanatory drawing of the manufacturing method of a wiring board. The schematic sectional drawing which shows the wiring board in another embodiment. The schematic sectional drawing which shows the principal part of the ceramic capacitor in another embodiment. The schematic sectional drawing which shows the principal part of the ceramic capacitor in another embodiment. The top view which shows the ceramic capacitor in another embodiment.

  Hereinafter, an embodiment in which the present invention is embodied in a wiring board will be described in detail with reference to the drawings.

  As shown in FIG. 1, the wiring board 10 of the present embodiment is a wiring board for mounting an IC chip. The wiring substrate 10 includes a substantially rectangular plate-shaped resin core substrate 11, a first buildup layer 31 (wiring laminated portion) formed on the core main surface 12 (upper surface in FIG. 1) of the resin core substrate 11, a resin It consists of a second buildup layer 32 (wiring laminate) formed on the core back surface 13 (the lower surface in FIG. 1) of the core substrate 11.

  The first buildup layer 31 formed on the core main surface 12 of the resin core substrate 11 includes two resin interlayer insulating layers 33 and 35 made of thermosetting resin (epoxy resin), and a conductor layer 42 made of copper. Are alternately stacked. Terminal pads 44 are formed in an array at a plurality of locations on the surface of the second resin interlayer insulation layer 35. Further, the surface of the resin interlayer insulating layer 35 is almost entirely covered with a solder resist 37. An opening 46 for exposing the terminal pad 44 is formed at a predetermined position of the solder resist 37. A plurality of solder bumps 45 are provided on the surface of the terminal pad 44. Each solder bump 45 is electrically connected to the surface connection terminal 22 of the IC chip 21 having a rectangular flat plate shape. The region where each terminal pad 44 and each solder bump 45 is formed is an IC chip mounting region 23 on which the IC chip 21 can be mounted. The IC chip mounting area 23 is set on the surface 39 of the first buildup layer 31. Also, via conductors 43 are formed at a plurality of locations in the second resin interlayer insulating layer 35. The lower end of each via conductor 43 is connected to the conductor layer 42 formed on the surface of the resin interlayer insulating layer 33, and the upper end of each via conductor 43 is the surface of the resin interlayer insulating layer 35. It is connected to the terminal pad 44 formed above. The via conductor 43 electrically connects the conductor layer 42 and the terminal pad 44 to each other.

  The second buildup layer 32 formed on the core back surface 13 of the resin core substrate 11 has substantially the same structure as the first buildup layer 31 described above. That is, the second buildup layer 32 has a structure in which two resin interlayer insulating layers 34 and 36 made of thermosetting resin (epoxy resin) and conductor layers 42 are alternately laminated. Via conductors 47 are formed at a plurality of locations in the first resin interlayer insulation layer 34. The lower end of each via conductor 47 is connected to a conductor layer 42 formed on the surface of the resin interlayer insulating layer 34. Via conductors 43 are formed at a plurality of locations in the second resin interlayer insulation layer 36, and via conductors 43 are disposed at the lower end of each via conductor 43 on the lower surface of the resin interlayer insulation layer 36. The BGA pads 48 electrically connected to the conductor layer 42 are formed in a lattice shape. The lower surface of the resin interlayer insulating layer 36 is almost entirely covered with a solder resist 38. An opening 40 for exposing the BGA pad 48 is formed at a predetermined portion of the solder resist 38. A plurality of solder bumps 49 that can be electrically connected to a mother board (not shown) are disposed on the surface of the BGA pad 48. The wiring board 10 shown in FIG. 1 is mounted on a mother board (not shown) by each solder bump 49.

  The resin core substrate 11 of the present embodiment has a substantially rectangular plate shape in plan view of 25 mm long × 25 mm wide × 0.90 mm thick. The resin core substrate 11 includes a base material 161 made of glass epoxy, a sub-base material 164 formed on an upper surface and a lower surface of the base material 161 and made of an epoxy resin to which an inorganic filler such as silica filler is added, and the base material 161. A conductor layer 163 made of copper is formed on the upper and lower surfaces. Further, a plurality of through-hole conductors 16 are formed in the resin core substrate 11 so as to penetrate the core main surface 12, the core back surface 13, and the conductor layer 163. The through-hole conductor 16 connects and conducts the core main surface 12 side and the core back surface 13 side of the resin core substrate 11 and is electrically connected to the conductor layer 163. The inside of the through-hole conductor 16 is filled with a closing body 17 such as an epoxy resin. The upper end of the through-hole conductor 16 is electrically connected to a part of the conductor layer 42 on the surface of the resin interlayer insulating layer 33, and the lower end of the through-hole conductor 16 is on the lower surface of the resin interlayer insulating layer 34. It is electrically connected to a part of a certain conductor layer 42. Further, a conductor layer 41 made of copper is patterned on the core main surface 12 and the core back surface 13 of the resin core substrate 11, and each conductor layer 41 is electrically connected to the through-hole conductor 16. Further, the resin core substrate 11 has one accommodation hole 90 that is rectangular in plan view and opens at the center of the core main surface 12 and the center of the core back surface 13. That is, the accommodation hole 90 is a through hole. The accommodating hole 90 has chamfered portions with chamfer dimensions of 0.1 mm or more and 2.0 mm or less at the four corners.

  The ceramic capacitor 101 (electronic component) shown in FIGS. 2 and 3 is housed in the housing hole 90 in an embedded state. The ceramic capacitor 101 is accommodated with the capacitor main surface 102 facing the same side as the core main surface 12 and the capacitor back surface 103 facing the same side as the core back surface 13. The ceramic capacitor 101 of the present embodiment has a substantially rectangular plate shape in plan view of 12.0 mm long × 12.0 mm wide × 1.0 mm thick. The ceramic capacitor 101 is disposed in a region immediately below the IC chip mounting region 23 in the resin core substrate 11. The area of the IC chip mounting region 23 (the area of the surface on which the surface connection terminals 22 are formed in the IC chip 21) is set to be smaller than the area of the capacitor main surface 102 of the ceramic capacitor 101. When viewed from the thickness direction of the ceramic capacitor 101, the IC chip mounting region 23 is located in the capacitor main surface 102 of the ceramic capacitor 101.

  As shown in FIG. 1, the gap between the inner surface of the accommodation hole 90 and the capacitor side surface 106 of the ceramic capacitor 101 is a resin-filled portion made of a polymer material (in this embodiment, a thermosetting resin such as epoxy). It is filled with 92. The resin filling portion 92 has a function of fixing the ceramic capacitor 101 to the resin core substrate 11. Ceramic capacitor 101 has a substantially square shape in plan view, and has chamfered portions with chamfering dimensions of 0.55 mm or more (in this embodiment, chamfering dimensions of 0.6 mm) at four corners. As a result, when the ceramic capacitor 101 is built in the wiring board 10 or when the resin filling portion 92 is deformed due to a temperature change, stress concentration on the corner portion of the ceramic capacitor 101 can be alleviated. Can be prevented.

  As shown in FIGS. 1 to 3, the ceramic capacitor 101 of the present embodiment is a so-called via array type ceramic capacitor. The ceramic sintered body 104 constituting the ceramic capacitor 101 includes one capacitor main surface 102 (upper surface in FIG. 1), one capacitor back surface 103 (lower surface in FIG. 1), and four capacitor side surfaces 106 (left surface in FIG. 1). , Right side).

  As shown in FIG. 2, the ceramic sintered body 104 is formed by alternately laminating power supply internal electrode layers 141 (internal electrodes) and ground internal electrode layers 142 (internal electrodes) via ceramic dielectric layers 105. It has the structure. The ceramic dielectric layer 105 is made of a sintered body of barium titanate, which is a kind of high dielectric constant ceramic, and functions as a dielectric (insulator) between the power internal electrode layer 141 and the ground internal electrode layer 142. To do. Each of the power supply internal electrode layer 141 and the ground internal electrode layer 142 is a layer formed mainly of nickel, and is disposed in every other layer in the ceramic sintered body 104.

  As shown in FIGS. 1 and 2, a large number of via holes 130 are formed in the ceramic sintered body 104. These via holes 130 penetrate the ceramic sintered body 104 in the thickness direction and are arranged in a lattice shape (array shape) over the entire surface of the ceramic sintered body 104. In each via hole 130, a plurality of in-capacitor via conductors 131 and 132 that communicate between the capacitor main surface 102 and the capacitor back surface 103 of the ceramic sintered body 104 are formed using nickel as a main material. In this embodiment, since the diameter of the via hole 130 is set to about 100 μm, the diameter of the via conductors 131 and 132 in the capacitor is also set to about 100 μm. Each power supply capacitor internal via conductor 131 passes through each power supply internal electrode layer 141 and electrically connects them to each other. Each ground capacitor via conductor 132 passes through each ground internal electrode layer 142 and electrically connects them to each other. Each power source capacitor via conductor 131 and each ground capacitor inner via conductor 132 are arranged in an array as a whole.

  2 and 3, a plurality of main surface side power supply external electrodes 111 and a plurality of main surface side ground external electrodes 112 are provided on the capacitor main surface 102 of the ceramic sintered body 104. It has been. Each of the external electrodes 111 and 112 has a substantially circular shape when viewed from a direction perpendicular to the capacitor main surface 102 (part thickness direction), and has a diameter of 300 μm (see FIG. 3). The main surface side power external electrode 111 is directly connected to the end surface of the plurality of power source capacitor internal via conductors 131 on the capacitor main surface 102 side, and the main surface side ground external electrode 112 is connected to a plurality of ground ground electrodes. The internal via conductor 132 is directly connected to the end surface of the capacitor main surface 102 side.

  Also, as shown in FIG. 2, a plurality of backside power supply external electrodes 121 and a plurality of backside ground external electrodes 122 are provided on the capacitor backside 103 of the ceramic sintered body 104. Each of the external electrodes 121 and 122 has a substantially circular shape when viewed from a direction perpendicular to the capacitor back surface 103, and has a diameter of 300 μm. The back-side power external electrode 121 is directly connected to the end surface on the capacitor back surface 103 side of the plurality of power-source capacitor via conductors 131, and the back-side ground external electrode 122 is a plurality of ground-capacitor vias. The conductor 132 is directly connected to the end surface on the capacitor back surface 103 side. Therefore, the power supply external electrodes 111 and 121 are electrically connected to the power supply capacitor internal via conductor 131 and the power supply internal electrode layer 141, and the ground external electrodes 112 and 122 are connected to the ground capacitor internal via conductor 132 and the ground internal electrode. Conductive to layer 142.

  As shown in FIGS. 4 and 5, the external electrodes 111, 112, 121, 122 are composed of a metallized metal layer 151 and a copper plating layer 152. The metallized metal layer 151 is disposed on the capacitor main surface 102 and the capacitor back surface 103, and is mainly composed of nickel particles 154 (first metal material). For example, 30 vol% barium titanate 155 (perovskite oxide) is added to the metallized metal layer 151 of the present embodiment as co-material particles with respect to the nickel particles 154 as the main material. The maximum particle size of the nickel particles 154 constituting the metallized metal layer 151 is about 10 μm, and the maximum particle size of the barium titanate 155 added as the co-material particles is about 5 μm.

  The copper plating layer 152 is a covering metal layer formed mainly of copper (second metal material) having higher conductivity than nickel, and entirely covers the surface of the metallized metal layer 151. In the present embodiment, the maximum particle size of the copper particles 156 constituting the copper plating layer 152 is 3 μm or less. A plurality of copper particles 156 are in contact with one of the nickel particles 154 constituting the metallized metal layer 151 at the interface between the metallized metal layer 151 and the copper plating layer 152.

  The surface of the copper plating layer 152 is roughened, and the arithmetic average roughness Ra of the surface of the copper plating layer 152 is set to 0.4 μm. The “arithmetic average roughness Ra” is an arithmetic average roughness Ra defined in JIS B0601. The measurement method of arithmetic average roughness Ra shall be in accordance with JIS B0651.

  As shown in FIGS. 1 to 5, protruding conductors 50 are provided on the external electrodes 111, 112, 121, and 122, respectively. The number of the protruding conductors 50 is equal to the number of the via conductors 131 and 132 in the capacitor, and is 50 or more in the present embodiment. Each protruding conductor 50 is a cylindrical conductor (copper post) formed by copper plating. That is, the protruding conductor 50 is formed in a cylindrical shape mainly composed of copper, which is the same metal material as the copper plating layer 152. The maximum particle size of the copper particles 157 (see FIG. 5) constituting the protruding conductor 50 is larger than the copper particles 156 constituting the copper plating layer 152 and is 5 μm or more. The diameter of each protruding conductor 50 is set smaller than the diameter (about 300 μm) of the external electrodes 111, 112, 121, 122 and larger than the diameter (about 100 μm) of the via conductors 131, 132 in the capacitor. In this embodiment, it is set to about 200 μm. Further, the height of the protruding conductor 50 is set to 50 μm or more and 200 μm or less.

  The height (thickness) of each protruding conductor 50 is substantially equal to the thickness of the resin interlayer insulating layer 33, and the surface of the top portion 52 of the protruding conductor 50 protruding on the external electrodes 111 and 112 is as follows. , At the same position as the surface of the resin interlayer insulation layer 33. Further, the surface of each protruding conductor 50 is roughened. The arithmetic average roughness Ra of the surface of the protruding conductor 50 is set to 0.4 μm, for example. The protruding conductor 50 protruding on the external electrodes 111 and 112 is connected to the conductor layer 42 formed on the surface of the resin interlayer insulating layer 33. On the other hand, the protruding conductors 50 protruding on the external electrodes 121 and 122 are connected to via conductors 47 formed at a plurality of locations in the resin interlayer insulating layer 34.

  As shown in FIG. 1, the external electrodes 111 and 112 on the capacitor main surface 102 side are the protruding conductor 50, the conductor layer 42, the via conductor 43, the terminal pad 44, the solder bump 45, and the surface connection terminals of the IC chip 21. It is electrically connected to the IC chip 21 via 22. On the other hand, the external electrodes 121 and 122 on the capacitor back surface 103 side are electrodes provided on a mother board (not shown) through the protruding conductor 50, the via conductor 47, the conductor layer 42, the via conductor 43, the BGA pad 48, and the solder bump 49. Is electrically connected.

  For example, when energization is performed from the mother board side through the external electrodes 121 and 122 and a voltage is applied between the power supply internal electrode layer 141 and the ground internal electrode layer 142, for example, positive charges accumulate in the power supply internal electrode layer 141. For example, negative charges accumulate in the ground internal electrode layer 142. As a result, the ceramic capacitor 101 functions as a capacitor. In the ceramic capacitor 101, the via-conductor 131 for power supply capacitor and the via-conductor 132 for ground capacitor are alternately arranged adjacent to each other, and the via-conductor 131 for power-supply capacitor and the via-conductor 132 for ground capacitor are connected to each other. The directions of the flowing currents are set to be opposite to each other. Thereby, the inductance component is reduced.

  Next, a method for manufacturing the ceramic capacitor 101 of the present embodiment will be described.

  First, a green sheet of a dielectric material mainly composed of barium titanate is formed, and a nickel paste for internal electrode layers is screen-printed on the green sheet and dried. As a result, a power internal electrode portion that will later become the power internal electrode layer 141 and a ground internal electrode portion that will be the ground internal electrode layer 142 are formed. Next, the green sheets with the power supply internal electrode portions and the green sheets with the ground internal electrode portions are alternately stacked, and each green sheet is integrated by applying a pressing force in the sheet stacking direction. To form a green sheet laminate.

  Further, a number of via holes 130 are formed through the green sheet laminate using a laser processing machine, and a via conductor nickel paste is filled into each via hole 130 using a paste press-fitting and filling device (not shown). Next, a nickel paste for an electrode is printed on the upper surface of the green sheet laminate, and the metallized metal layer 151 of the external electrodes 111 and 112 is formed so as to cover the upper end surfaces of the respective conductor portions on the upper surface side of the green sheet laminate. To do. Also, a nickel paste for an electrode is printed on the lower surface of the green sheet laminate, and the metallized metal layer 151 of the external electrodes 121 and 122 is formed so as to cover the lower end surfaces of the respective conductor portions on the lower surface side of the green sheet laminate. .

  Thereafter, the green sheet laminate is dried to solidify each metallized metal layer 151 to some extent. Next, the green sheet laminate is degreased and fired at a predetermined temperature for a predetermined time. As a result, barium titanate and nickel in the paste are simultaneously sintered to form a ceramic sintered body 104.

  Next, bright pyrophosphate copper plating (bright copper plating) is performed on each metallized metal layer 151 included in the obtained ceramic sintered body 104 (coated metal layer forming step). As a result, a copper plating layer 152 (thickness: 15 μm) is formed on each metallized metal layer 151, whereby each external electrode 111, 112, 121, 122 is formed.

In the present embodiment, the plating conditions are set so that the maximum particle size of the copper particles 156 constituting the copper plating layer 152 is 3 μm or less. Specifically, using a copper pyrophosphate plating bath, a temperature of about 50 ° C. to 60 ° C., a current density of about 1.0 A / dm ^{2 to} 3.0 A / dm ² , and a deposition time of about 20 minutes to 25 minutes. Electrolytic copper plating is performed under such conditions. The copper plating bath contains an additive (for example, a brightener) for suppressing the grain growth of the copper particles 156.

  And after forming the copper plating layer 152 of each external electrode 111,112,121,122, on the capacitor | condenser main surface 102 and the capacitor | condenser back surface 103 of the ceramic sintered compact 104, it is an opening part 182 (inside diameter 200 micrometers) in a predetermined location. A photoresist material 181 having a thickness of 200 μm is laminated (see FIG. 6). These openings 182 are formed by exposure and development, and part of the surfaces of the external electrodes 111, 112, 121, 122 are exposed. A metal mask (thickness: 200 μm) is laminated on the capacitor main surface 102 and the capacitor back surface 103 of the ceramic sintered body 104, and drilling using a drill is performed on the metal mask, thereby opening the opening. A metal mask having the portion 182 may be formed.

  Then, as shown in FIG. 7, matte copper sulfate plating (matte copper plating) is performed on the external electrodes 111, 112, 121, and 122 via the photoresist material 181 (protruding conductor forming step). Further, the photoresist material 181 is removed. As a result, as shown in FIG. 8, the protruding conductor 50 having a height of 50 μm or more and 200 μm or less is formed on the external electrodes 111, 112, 121, 122, and the ceramic capacitor 101 is completed. When forming the protruding conductor 50, a copper sulfate plating bath not containing a brightening agent is used, and the plating conditions are set so that the maximum particle diameter of the copper particles 157 constituting the protruding conductor 50 is 5 μm or more. Plating is performed.

  Next, a method for manufacturing the wiring board 10 of the present embodiment will be described.

  First, in the core substrate preparation step, an intermediate product of the resin core substrate 11 is prepared by a conventionally known technique and prepared in advance.

  The intermediate product of the resin core substrate 11 is manufactured as follows. First, a copper clad laminate (not shown) in which copper foil is pasted on both surfaces of a base material 161 having a length of 400 mm, a width of 400 mm, and a thickness of 0.65 mm is prepared. Next, the copper foil on both sides of the copper clad laminate is etched to pattern the conductor layer 163 by, for example, a subtractive method. Specifically, after the electroless copper plating, electrolytic copper plating is performed using the electroless copper plating layer as a common electrode. Further, the dry film is laminated, and the dry film is exposed and developed to form a dry film in a predetermined pattern. In this state, unnecessary electrolytic copper plating layer, electroless copper plating layer and copper foil are removed by etching. Thereafter, the dry film is peeled off. Next, after roughening the upper and lower surfaces of the base material 161 and the conductor layer 163, an epoxy resin film (thickness of 80 μm) to which an inorganic filler has been added is attached to the upper and lower surfaces of the base material 161 by thermocompression bonding. The sub-base material 164 is formed.

  Next, a conductor layer 41 (thickness: 50 μm) is patterned on the upper surface of the upper sub-base material 164 and the lower surface of the lower sub-base material 164. Specifically, after performing electroless copper plating on the upper surface of the upper sub-base material 164 and the lower surface of the lower sub-base material 164, an etching resist is formed, and then electrolytic copper plating is performed. Further, the etching resist is removed and soft etching is performed. Next, the laminated body composed of the base material 161 and the sub base material 164 is drilled using a router to form through holes to be the accommodation hole portions 90 at predetermined positions, and the intermediate product of the resin core substrate 11 (See FIG. 9). The intermediate product of the resin core substrate 11 is a multi-piece core substrate having a structure in which a plurality of regions to be the resin core substrate 11 are arranged vertically and horizontally along the plane direction.

  In the subsequent housing step, the mounting device is used to place the core main surface 12 and the capacitor main surface 102 on the same side, and the core back surface 13 and the capacitor back surface 103 on the same side in the housing hole 90. The ceramic capacitor 101 is accommodated (see FIG. 10). The opening on the core back surface 13 side of the accommodation hole 90 is sealed with a peelable adhesive tape 171. The adhesive tape 171 is supported by a support base (not shown). The ceramic capacitor 101 is affixed and temporarily fixed to the adhesive surface of the adhesive tape 171.

  In this state, the resin filling portion 92 made of thermosetting resin is filled into the gap between the inner surface of the accommodation hole portion 90 and the capacitor side surface 106 of the ceramic capacitor 101 using a dispenser device. Then, when heat processing are performed, the resin filling part 92 will harden | cure and the ceramic capacitor 101 will be fixed in the accommodation hole part 90 (refer FIG. 11). At this point, the adhesive tape 171 is peeled off.

  Thereafter, the surface of the copper plating layer 152 constituting the external electrodes 111 and 112 and the surface of the protruding conductor 50 are roughened (see FIG. 4). In addition, since the surface of the copper plating layer 152 and the surface of the protruding conductor 50 are roughened at the same time, a part of the surface of the copper plating layer 152 (connection portion with the protruding conductor 50) is roughened. Absent.

  Next, the first buildup layer 31 is formed on the core main surface 12 and the second buildup layer 32 is formed on the core back surface 13 based on a conventionally known method. Specifically, first, a resin epoxy insulating layer 33 is formed by depositing a photosensitive epoxy resin on the core main surface 12 and the capacitor main surface 102 and performing exposure and development (see FIG. 12). At this time, each protruding conductor 50 of the ceramic capacitor 101 is engaged with the resin interlayer insulating layer 33, whereby the ceramic capacitor 101 is positioned. Further, a photosensitive epoxy resin is applied to the core back surface 13 and the capacitor back surface 103, and the resin interlayer insulating layer 34 is formed by performing exposure and development. In place of depositing the photosensitive epoxy resin, an insulating resin or a liquid crystal polymer (LCP) may be deposited.

  Further, laser drilling is performed using a YAG laser or a carbon dioxide laser to form a via hole at a position where the via conductor 47 is to be formed. Specifically, a via hole penetrating the resin interlayer insulating layer 34 is formed, and the surface of the top portion 52 of the protruding conductor 50 protruding on the external electrodes 121 and 122 is exposed.

  Further, drilling is performed using a drill machine, and through holes (not shown) penetrating the resin core substrate 11 and the resin interlayer insulating layers 33 and 34 are formed in advance at predetermined positions. Then, after performing electroless copper plating on the surfaces of the resin interlayer insulating layers 33 and 34, the inner surfaces of the via holes, and the inner surfaces of the through holes, an etching resist is formed, and then electrolytic copper plating is performed. Further, the etching resist is removed and soft etching is performed. Thereby, the conductor layer 42 is formed on the resin interlayer insulating layer 33 and the conductor layer 42 is patterned on the resin interlayer insulating layer 34. At the same time, the through-hole conductor 16 is formed in the through hole, and the via conductor 47 is formed in each via hole. Thereafter, the cavity of the through-hole conductor 16 is filled with an insulating resin material (epoxy resin) to form the closing body 17.

  Next, a photosensitive epoxy resin is deposited on the resin interlayer insulation layers 33 and 34, and exposure and development are performed, whereby a resin interlayer insulation having via holes (not shown) at positions where the via conductors 43 are to be formed. Layers 35 and 36 are formed. Instead of depositing the photosensitive epoxy resin, an insulating resin or a liquid crystal polymer may be deposited. In this case, a via hole is formed at a position where the via conductor 43 is to be formed by a laser processing machine or the like. Next, electrolytic copper plating is performed in accordance with a conventionally known method to form a via conductor 43 inside the via hole, a terminal pad 44 is formed on the resin interlayer insulating layer 35, and a BGA is formed on the resin interlayer insulating layer 36. A pad 48 is formed.

  Next, solder resists 37 and 38 are formed by applying and curing a photosensitive epoxy resin on the resin interlayer insulation layers 35 and 36. Thereafter, exposure and development are performed with a predetermined mask placed, and the openings 40 and 46 are patterned in the solder resists 37 and 38. Further, solder bumps 45 are formed on the terminal pads 44 and solder bumps 49 are formed on the BGA pads 48. It can be understood that the product in this state is a multi-cavity wiring board in which a plurality of product regions to be the wiring board 10 are arranged vertically and horizontally along the plane direction. Furthermore, when the multi-cavity wiring board is divided, a large number of wiring boards 10 which are individual products can be obtained simultaneously.

The inventor configures the protruding conductor 50 and the copper plating layer 152 by changing the plating conditions when forming the copper plating layer 152 and the plating conditions when forming the protruding conductor 50 in the above manufacturing method. A plurality of sample products (Examples A to C in Table 1 and Comparative Example D) having different particle diameters of the copper particles 156 and 157 were produced.

  Specifically, as shown in Table 1, in the ceramic capacitor 101 of Example A, the maximum particle diameter of the copper particles 157 constituting the protruding conductor 50 is larger than 8 μm, and the copper constituting the copper plating layer 152 is formed. The maximum particle size of the particles 156 is less than 2 μm. In the ceramic capacitor 101 of Example B, the maximum particle size of the copper particles 157 constituting the protruding conductor 50 is larger than 5 μm, and the maximum particle size of the copper particles 156 constituting the copper plating layer 152 is less than 3 μm. . In the ceramic capacitor 101 of Example C, the maximum particle size of the copper particles 157 constituting the protruding conductor 50 is larger than 5 μm, and the maximum particle size of the copper particles 156 constituting the copper plating layer 152 is less than 1 μm. . In the ceramic capacitor 101 of Comparative Example D, the maximum particle diameter of the copper particles 157 constituting the protruding conductor 50 is less than 3 μm, and the maximum particle diameter of the copper particles 156 constituting the copper plating layer 152 is larger than 5 μm. It has become. That is, in each of Examples A to C, the maximum particle size of the copper particles 157 constituting the protruding conductor 50 is larger than the maximum particle size of the copper particles 156 constituting the copper plating layer 152. The maximum particle size of the copper particles 157 constituting the conductor 50 is smaller than the maximum particle size of the copper particles 156 constituting the copper plating layer 152.

  The particle diameters of the copper particles 156 and 157 are obtained by performing scanning ion (SIM) image observation using a focused ion beam (FIB) processing apparatus, and in the obtained SIM image photograph. Measured based on.

  Then, the thermal shock test (environment) in which the temperature increase from the low temperature −65 ° C. to the high temperature + 150 ° C. and the temperature decrease are repeated for 100 cycles for the wiring board 10 including the ceramic capacitors 101 of Examples A to C and Comparative Example D. Test standard MIL-STD-883D, test condition C) was carried out to evaluate its reliability. Here, the cross section of the external electrode 111 and the protruding conductor 50 in the ceramic capacitor 101 was observed for the wiring board 10 after the thermal shock test. As a result, in each of Examples A to C, it was confirmed that defects such as delamination of the resin interlayer insulating layer 33 and breakage of the protruding conductor 50 did not occur, and the reliability was sufficient. On the other hand, in Comparative Example D, the adhesion failure (delamination) of the resin interlayer insulating layer 33 due to insufficient fitting force around the copper plating layer 152 and the bending due to insufficient strength of the protruding conductor 50 were confirmed. Furthermore, in each Example AC, the planar smoothness increases by making the copper particle 156 of the copper plating layer 152 small, and the height variation of the protruding conductor 50 may be reduced as compared with the case of Comparative Example D. did it.

  Therefore, according to the present embodiment, the following effects can be obtained.

  (1) In the ceramic capacitor 101 of the present embodiment, since the protruding conductor 50 and the copper plating layer 152 are formed using copper, which is the same metal material, the adhesion between the protruding conductor 50 and the copper plating layer 152. Can be secured sufficiently. Furthermore, since the maximum particle diameter of the copper particles 157 constituting the protruding conductor 50 is larger than the maximum particle diameter of the copper particles 156 constituting the copper plating layer 152, the residual stress of the protruding conductor 50 can be suppressed. As a result, the strength of the protruding conductor 50 can be sufficiently secured, and problems such as bending of the protruding conductor 50 can be solved. Further, by increasing the particle size of the copper particles 157 constituting the protruding conductor 50, the grain boundary in the protruding conductor 50 can be reduced and its resistance can be reduced. Can increase the sex.

  (2) In the ceramic capacitor 101 of the present embodiment, the maximum particle size of the copper particles 156 constituting the copper plating layer 152 is smaller than the maximum particle size of the nickel particles 154 constituting the metallized metal layer 151. In this case, the copper particles 156 of the copper plating layer 152 enter the metallized metal layer 151, and the copper plating layer 152 and the metallized metal layer 151 are securely adhered to each other, so that the copper plating layer 152 having excellent peeling resistance is formed. Can do. Further, by reducing the copper particles 156 of the copper plating layer 152, the smoothness of the surface of the copper plating layer 152 is improved, and the protruding conductor 50 having a uniform height can be formed.

  (3) In the ceramic capacitor 101 of the present embodiment, the manufacturing cost can be reduced by forming the protruding conductor 50 and the copper plating layer 152 using copper, and the protruding conductor 50 and the external electrode 111 can be reduced. , 112, 121, 122 can be easily reduced in resistance.

  (4) In the ceramic capacitor 101 of the present embodiment, in each of the external electrodes 111, 112, 121, and 122, the metallized metal layer 151 is composed mainly of nickel particles 154, and barium titanate 155 is added as co-material particles. Has been. Thus, by using nickel as the material for forming the metallized metal layer 151, the manufacturing cost of the ceramic sintered body 104 can be reduced as compared with the case of using relatively expensive palladium. Further, by adding barium titanate 155 as a co-material particle to the metallized metal layer 151, the thermal contraction difference of the metallized metal layer 151 in the ceramic sintered body 104 can be suppressed, and problems such as cracks and delamination are avoided. can do.

  (5) In the wiring substrate 10 of the present embodiment, the via array type ceramic capacitor 101 is housed in the housing hole 90 as an electronic component. In this ceramic capacitor 101, since the plurality of via conductors 131 and 132 are arranged in an array as a whole, the inductance of the ceramic capacitor 101 can be reduced, and high-speed power supply for noise absorption and power fluctuation smoothing can be achieved. Is possible.

  (6) In the wiring substrate 10 of the present embodiment, the ceramic capacitor 101 is disposed immediately below the IC chip 21 mounted in the IC chip mounting region 23, so that the wiring connecting the ceramic capacitor 101 and the IC chip 21 is short. Thus, an increase in the inductance component of the wiring is prevented. Therefore, the switching noise of the IC chip 21 due to the ceramic capacitor 101 can be reliably reduced, and the power supply voltage can be reliably stabilized. In addition, since noise entering between the IC chip 21 and the ceramic capacitor 101 can be suppressed to a very low level, high reliability can be obtained without causing malfunction such as malfunction.

  (7) In the wiring substrate 10 of the present embodiment, since the IC chip mounting area 23 is located in the area immediately above the ceramic capacitor 101, the IC chip 21 mounted in the IC chip mounting area 23 is highly rigid. And supported by a ceramic capacitor 101 having a low coefficient of thermal expansion. Therefore, in the IC chip mounting area 23, the first buildup layer 31 is not easily deformed, so that the IC chip 21 mounted in the IC chip mounting area 23 can be supported more stably. Therefore, it is possible to prevent the IC chip 21 from cracking and poor connection due to large thermal stress. Therefore, the IC chip 21 is considered to be a large IC chip of 10 mm square or more, which has a large stress (strain) due to a difference in thermal expansion and is greatly affected by thermal stress, and has a large calorific value and severe thermal shock during use. A low-k (low dielectric constant) IC chip can be used.

  (8) In the case of this embodiment, the copper plating layer 152 covering the surface of the metallized metal layer 151 is formed by performing bright pyrophosphate copper plating in the covering metal layer forming step. Since this bright pyrophosphate copper plating contains a brightener, the growth of copper particles 156 is suppressed, and the copper plating layer 152 having a maximum particle size of 3 μm or less can be reliably formed. In the protruding conductor forming step, the protruding conductor 50 is formed by matte copper sulfate plating that does not contain a brightener. In this case, the grain growth of the copper particles 157 is promoted, and the protruding conductor 50 having the maximum particle size of the copper particles 157 of 5 μm or more can be reliably formed.

  In addition, you may change embodiment of this invention as follows.

  In the wiring substrate 10 of the above embodiment, the ceramic capacitor 101 is accommodated in the resin core substrate 11. However, a ceramic capacitor 303 (thickness 0.08 mm) thinner than the ceramic capacitor 101 of the above embodiment is formed, and the ceramic capacitor 303 is placed in the first buildup layer 310 of the wiring board 10A (see, for example, FIG. 13). May be accommodated. Also in the ceramic capacitor 303, similarly to the ceramic capacitor 101 described above, external electrodes (the external electrodes 111 and 112 on the capacitor main surface 102 and the external electrodes on the capacitor back surface 103) composed of the metallized metal layer 151 and the copper plating layer 152. 121, 122), and the protruding conductor 50 is formed on the external electrodes 111, 112, 121, 122. In addition, the maximum particle diameter of the copper particle which comprises the copper plating layer 152 of each electrode 111,112,121,122 is less than 3 micrometers, and the maximum particle diameter of the copper particle which comprises the protruding conductor 50 is 5 micrometers or more. Then, after the surface of the copper plating layer 152 of each electrode 111, 112, 121, 122 and the surface of the protruding conductor 50 are roughened, the ceramic capacitor 303 is built in the resin core substrate 11.

  Specifically, a resin sheet (uncured resin interlayer insulation layer 30) is laminated on the core main surface 12 of the resin core substrate 11, and before the resin sheet is cured, the ceramic capacitor 303 is used by using a mounting device. Is placed on the resin sheet. At this time, a part of the ceramic capacitor 303 (external electrodes 121 and 122 and the protruding conductor 50 on the capacitor back surface 103 side) is made to enter the resin sheet while being pressurized. Thereby, since the protruding conductor 50 bites into the resin sheet, the ceramic capacitor 303 is positioned. Thereafter, the resin sheet is cured to form the resin interlayer insulating layer 30. Furthermore, if the resin interlayer insulation layer 30 and the conductor layer 42 are formed alternately, the first buildup layer 310 is completed.

  In this ceramic capacitor 303 as well, by reducing the maximum particle size of the copper particles 156 constituting the copper plating layer 152, the copper plating layer 152 and the metallized metal layer 151 can be reliably adhered. Further, by increasing the maximum particle size of the copper particles 157 constituting the protruding conductor 50, the residual stress of the protruding conductor 50 can be suppressed, and the strength of the protruding conductor 50 can be sufficiently ensured. Furthermore, the conduction path (capacitor connection wiring) for electrically connecting the IC chip 21 and the ceramic capacitor 303 is shorter than when the ceramic capacitor 101 is accommodated in the resin core substrate 11. This prevents an increase in the inductance component of the wiring, so that the switching noise of the IC chip 21 can be reliably reduced by the ceramic capacitor 303 and the power supply voltage can be reliably stabilized. Furthermore, since noise entering between the IC chip 21 and the ceramic capacitor 303 can be suppressed to a very low level, high reliability can be obtained without causing malfunction such as malfunction. Even if the thin ceramic capacitor 303 is used, since the ceramic capacitor 303 itself is thick, in FIG. 13, the build-up layer is a first build-up layer made of the resin interlayer insulating layer 30 having a thickness greater than that of the above embodiment. It is embodied in 310. Further, the ceramic capacitor 101 of the above embodiment may be accommodated in the same first buildup layer 31 as that of the above embodiment.

  In the above embodiment, after the protruding conductor 50 is provided on the external electrodes 111, 112, 121, 122, the surface of the copper plating layer 152 constituting the external electrodes 111, 112, 121, 122 and the protrusions The surface of the conductor 50 was roughened at the same time. However, after the external electrodes 111, 112, 121, and 122 are formed, they may be roughened once and then roughened again when the protruding conductors 50 are formed. In this way, the connection portion between the copper plating layer 152 and the protruding conductor 50 is also roughened, so that the adhesion between the two is improved (see FIG. 14).

  In the ceramic capacitors 101 and 303 according to the above embodiments, the surface of the protruding conductor 50 may be covered with the copper plating layer 152 by further performing copper pyrophosphate plating after the protruding conductor 50 is formed. (See FIG. 15). Thus, by forming the copper plating layer 152 having a small particle size of the copper particles 156 on the surface of the protruding conductor 50, the grain boundary region on the surface becomes large, so that the efficiency of the roughening treatment can be increased. . Therefore, when the ceramic capacitors 101 and 303 subjected to the roughening treatment are incorporated in the wiring board 10, sufficient adhesion with the resin interlayer insulating layers 33 and 30 constituting the wiring board 10 can be ensured. Lamination can be reliably prevented.

In the above embodiment, the copper plated layer 152 is formed by bright copper pyrophosphate plating, and the protruding conductor 50 is formed by matte copper sulfate plating. However, the present invention is not limited to this. If the maximum particle diameter of the copper particles 157 of the protruding conductor 50 is larger than the maximum particle diameter of the copper particles 156 of the copper plating layer 152, the manufacturing method can be changed as appropriate. As a specific method, for example, the copper plating layer 152 is formed by electroless copper plating, and the protruding conductor 50 is formed by electrolytic copper plating. Also, compared to low current density plating, nucleation is promoted in high current density plating, so the particle size of the copper particles is reduced. For this reason, the copper plating layer 152 may be formed by high current density plating, and the protruding conductor 50 may be formed by low current density plating. Here, the current density of the high current density plating is, for example, 8 A / dm ² , and the low current density is, for example, 2 A / dm ² .

  In the ceramic capacitor 101 of the above embodiment, the circular external electrodes 111, 112, 121, 122 are provided, but the electrode shape may be changed to other shapes such as a substantially rectangular shape. . Further, as in the ceramic capacitor 101A shown in FIG. 16, a dummy electrode 115 may be provided on the capacitor main surface 102 so as to surround each of the external electrodes 111 and 112. The dummy electrode 115 is formed by copper plating similarly to the external electrodes 111 and 112. By providing the dummy electrode 115 in this manner, the roughened area of the copper plating layer on the capacitor main surface 102 increases, so that the adhesion with the resin interlayer insulating layer 33 is improved. Further, in the ceramic capacitor 101, the external electrode 111 is provided. , 112, 121, 122 and the protruding conductor 50 are provided on both the capacitor main surface 102 and the capacitor back surface 103, but may be provided on only one of them.

  In the above embodiment, the package form of the wiring board 10 is BGA (ball grid array). However, the package form is not limited to BGA. For example, PGA (pin grid array) or LGA (land grid array) may be used. Good.

  Next, the technical ideas grasped by the embodiment described above are listed below.

  (1) A ceramic sintered body having a main surface and a back surface, a metallized metal layer including a first metal material disposed on at least one of the main surface and the back surface of the ceramic sintered body, and the first metal An electron comprising an external electrode made of a second metal material having higher conductivity than the material and having a covering metal layer covering the surface of the metallized metal layer, and a plurality of protruding conductors protruding on the external electrode The plurality of protruding conductors are made of the same second metal material as that of the coated metal layer, and the maximum particle size of the metal particles constituting the plurality of protruding conductors is the part of the coated metal layer. An electronic component characterized in that the maximum particle size of the metal particles constituting the metallized metal layer is smaller than the maximum particle size of the metal particles constituting the metallized metal layer. .

  (2) A ceramic sintered body having a main surface and a back surface, a metallized metal layer including a first metal material disposed on at least one of the main surface and the back surface of the ceramic sintered body, and the first metal An external electrode made of a second metal material having higher conductivity than the material and having a covering metal layer covering the surface of the metallized metal layer, and a plurality of protruding conductors protruding on the external electrode, The plurality of protruding conductors are made of the same second metal material as that of the coated metal layer, and the maximum particle size of the metal particles constituting the plurality of protruding conductors is that of the metal particles constituting the coated metal layer. A method of manufacturing an electronic component having a particle size larger than the maximum particle size, wherein after performing a coated metal layer forming step of forming the coated metal layer by bright copper pyrophosphate plating, the protruding conductor is formed by matte copper sulfate plating. Protruding shape to form Method of manufacturing an electronic component which is characterized in that the body forming step.

DESCRIPTION OF SYMBOLS 10,10A ... Wiring board 11 ... Resin core board 12 ... Core main surface 13 ... Core back surface 31,310 ... 1st buildup layer as a wiring laminated part 32 ... 2nd buildup layer 30, 33 as a wiring laminated part 34, 35, 36 ... resin interlayer insulation layer 42 ... conductor layer 50 ... protruding conductors 101, 101A, 303 ... ceramic capacitor as electronic component 102 ... capacitor main surface as main surface 103 ... capacitor back surface as back surface 104 ... ceramic Sintered body 105 ... ceramic dielectric layer 111 ... main surface side power external electrode as external electrode 112 ... main surface side ground external electrode as external electrode 121 ... back side power external electrode 122 as external electrode 122 ... external External electrode for back side ground as electrode 131... Conductor via conductor in power supply as via conductor in capacitor Body 132 ... Ground capacitor via conductor as capacitor via conductor 141 ... Power supply internal electrode layer as internal electrode 142 ... Ground internal electrode layer as internal electrode 151 ... Metalized metal layer 152 ... Copper as covering metal layer Plating layer 154 ... Nickel particles 155 ... Barium titanate 156, 157 ... Copper particles as perovskite oxide

Claims (8)

A ceramic sintered body having a main surface and a back surface;
The metallized metal layer including the first metal material disposed on at least one of the main surface and the back surface of the ceramic sintered body, and the second metal material having higher conductivity than the first metal material, An external electrode having a coating metal layer covering the surface of the metallized metal layer;
An electronic component comprising a plurality of protruding conductors protruding on the external electrode,
The plurality of protruding conductors are made of the same second metal material as that of the coated metal layer, the maximum particle diameter of the metal particles constituting the plurality of protruding conductors is 5 μm or more, and constitutes the coated metal layer The maximum particle size of the metal particles is 3 μm or less,
The electronic component according to claim 1, wherein the covering metal layer also covers surfaces of the plurality of protruding conductors . A ceramic sintered body having a main surface and a back surface;
  The metallized metal layer including the first metal material disposed on at least one of the main surface and the back surface of the ceramic sintered body, and the second metal material having higher conductivity than the first metal material, An external electrode having a coating metal layer covering the surface of the metallized metal layer;
  A plurality of protruding conductors protruding on the external electrode;
An electronic component comprising:
  The plurality of protruding conductors are made of the same second metal material as that of the coated metal layer, the maximum particle diameter of the metal particles constituting the plurality of protruding conductors is 5 μm or more, and constitutes the coated metal layer The maximum particle size of the metal particles is 3 μm or less,
  The maximum particle size of the metal particles constituting the coated metal layer is smaller than the maximum particle size of the metal particles constituting the metallized metal layer.
An electronic component characterized by that. Electronic component according to claim 1, wherein the maximum particle size of the metal particles constituting the coating metal layer, characterized in that the smaller than the maximum particle size of the metal particles constituting the metallized metal layer.   The electronic component according to claim 1, wherein the second metal material is copper.   2. The ceramic sintered body is mainly composed of a perovskite oxide, and the metallized metal layer mainly includes nickel particles as metal particles and the perovskite oxide. Electronic component of any one of thru | or 4. In the ceramic sintered body, a plurality of internal electrodes are laminated and disposed via a ceramic dielectric layer, and a plurality of via conductors in a capacitor connected to the plurality of internal electrodes are provided,
The external electrode is connected to at least one of a main surface side end and a back surface side end of the plurality of via conductors in the capacitor;
6. The electronic component according to claim 1, wherein the plurality of via conductors in the capacitor are arranged in an array as a whole.   The electronic component according to any one of claims 1 to 6 is accommodated in a resin core substrate having a core main surface and a core back surface, or in a wiring laminated portion having a structure in which a resin interlayer insulating layer and a conductor layer are laminated. A wiring board characterized by being made.   The method of manufacturing an electronic component according to claim 1, wherein the protrusion is formed by matte copper plating after performing a coated metal layer forming step of forming the coated metal layer by bright copper plating. A method for manufacturing an electronic component, comprising performing a protruding conductor forming step of forming a conductor.

Images