JP5389223B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a power device, and more particularly to a semiconductor device such as an insulated gate bipolar transistor (IGBT) or a power MOSFET (insulated gate field effect transistor). More specifically, the present invention relates to a configuration for improving the drive current amount and latch-up resistance and turn-off characteristics of a power device.

  In the field of power conversion and control, power devices are used. Among these power devices, there is a MOS gate device that performs a switching operation with a voltage applied to an insulated gate. As the MOS gate device, there are an IGBT (insulated gate bipolar transistor) and a MOSFET (insulated gate field effect transistor). As characteristics of such a power device for a semiconductor switch, in addition to a high-speed operation (high-speed switching operation), a large current drive and a high breakdown voltage are required.

  Patent Document 1 (Japanese Patent Application Laid-Open No. 7-58320) discloses the following configuration aimed at shortening the turn-off time of the IGBT and increasing the operating frequency. That is, in this patent document 1, the following structures are disclosed as a conventional structure. That is, a p-type base contact layer is disposed so as to surround the n-type emitter layer, and this p-type base contact layer is in contact with the p-type base layer. Both the p-type base contact layer and the n-type emitter layer are coupled to the emitter electrode. The p-type base contact layer emits minority carriers (holes) to the emitter electrode when turned off. On the other hand, an n-type buffer layer is formed below the p-type collector layer. At turn-off, when majority carriers are emitted from the collector layer to the collector terminal, this buffer layer prevents minority carriers from being emitted to the n− type drift layer. When this n-type buffer layer is used, if the buffer effect increases, the efficiency of injection of minority carriers into the drift layer at the time of turn-on decreases, the conductivity modulation action decreases, the on-resistance increases, The voltage increases. As one configuration for avoiding this, Patent Document 1 discloses a collector short structure. In this collector short structure, an n-type collector short layer is disposed so as to surround the p-type collector layer. A p-type collector layer and an n-type collector short layer are commonly coupled to the collector electrode. In this collector short structure, majority carriers flow into the collector short layer during turn-off, but minority carriers are absorbed by the collector short layer, making it difficult for minority carriers to be generated and shortening the turn-off time.

  In the IGBT, generally, a p-type collector layer, an n-type buffer layer, an n − type drift layer, a p-type base layer, and an n-type emitter layer are formed. A parasitic thyristor is formed by this npn structure. A voltage drop in the base region of the IGBT may cause a latch-up phenomenon in which the parasitic thyristor is turned on. A configuration aimed at improving the latch-up resistance is shown in Patent Document 2 (Japanese Patent Publication No. 9-503626).

  In Patent Document 2, a high-concentration p + type region is provided below an n + type source layer in a p type base region formed in an n− type drift layer. With this high concentration p + type region, the resistance value of the p type base region is reduced, the voltage drop at the junction between the source and base regions is reduced, and the latch-up resistance is improved.

  A configuration for increasing the on-current and improving the latch-up resistance is disclosed in Patent Document 3 (Japanese Patent Laid-Open No. 2000-286416). In Patent Document 3, a collector layer, an emitter layer, and a gate electrode are formed in a ring shape. The emitter layer (source layer) has a gear-like shape having convex portions and concave portions, and a configuration in which the emitter layers are separated from each other and arranged in an island shape. In addition to reducing the base resistance under the emitter region, a hole current is emitted radially from the collector layer formed in the central portion to reduce the current density, thereby improving the latch-up resistance.

JP-A-7-58320 JP-T 9-503626 JP 2000-286416 A

  Patent Document 1 points out the following problems that occur when the collector short structure is applied to a lateral IGBT structure. That is, at the turn-off time, majority carriers pass through the lower part of the p-type collector layer and flow into the n-type collector short layer, and majority carriers also flow into the p-type collector layer. Accordingly, the injection of minority carriers into the n-type drift layer increases. In order to solve the problem of the collector short structure in the lateral IGBT structure, Patent Document 1 arranges a MOS transistor (insulated gate field effect transistor) having a sub-gate in the p-type collector layer, and this sub-gate MOS. The collector layer is coupled to the collector charge extraction layer via a transistor. A charge extraction layer is coupled to the collector terminal. In this sub-gate structure, the n-type source layer of the MOSFET is disposed adjacent to the p-type collector layer, and these are coupled by an electrode so that the n-type carrier of the n-type source layer becomes the p-type carrier of the p-type collector layer. Convert. At the turn-off time, the MOS transistor having the sub-gate structure is turned off, the p-type collector layer in the sub-gate is set in a floating state, and the p-type collector layer and the charge extraction layer are separated. Majority carriers (electrons) are extracted to the collector terminal through the charge extraction layer. On the other hand, the p-type collector layer and the lower p-well (p base) are in a floating state, and the pn junction between the well and the drift layer is maintained in a reverse bias state (below the built-in voltage) to suppress minority carrier injection. .

  However, in the configuration disclosed in Patent Document 1, a circuit for controlling the potential of the sub-gate separately from the gate (main gate) of the IGBT is required, and the scale of the control circuit increases. Also, in the IGBT element, a sub-gate and a main gate terminal are provided, and the layout area increases. In the structure disclosed in Patent Document 1, majority carriers (electrons) propagate through the lower portion of the p-type base layer and are absorbed by the charge extraction layer. However, no consideration is given to the latch-up phenomenon caused by the parasitic thyristor between the p-type collector layer, the p-well provided below, the n-type drift layer, and the n-type emitter layer.

  In the configuration disclosed in Patent Document 2, the resistance value of the p-type base region is reduced by the high-concentration p + -type region provided below the n-type source layer. However, Patent Document 2 discusses only the vertical device structure, and does not consider any application to the horizontal device structure. In addition, although consideration is given to avoiding latch-up due to parasitic thyristors in the vertical device structure, no consideration is given to the configuration for increasing the drive current.

  In the configuration shown in Patent Document 3, although the emitter region is formed in a gear shape or an island shape to avoid latch-up, the drive current is still increased and the turn-off time is shortened. There is room for improvement.

  SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a semiconductor device that can increase the amount of drive current, shorten the turn-off time, and improve the latch-up resistance of a parasitic thyristor.

A semiconductor device according to the present invention includes a semiconductor substrate, a semiconductor region formed in the semiconductor substrate, a first semiconductor layer region provided in the semiconductor region and coupled to the first electrode, and the semiconductor region The ring-shaped semiconductor region disposed so as to be separated from the first semiconductor layer region and surrounding the first semiconductor layer region, the second semiconductor layer region having a different conductivity type, and the second semiconductor layer region are separated from each other. a plurality of second semiconductor layer regions and the different conductivity type third semiconductor layer region having a unit area having a rectangular-like shape, each and are disposed at predetermined intervals having a width greater than the predetermined interval Te, this Yes an area reaching the second semiconductor layer region surface in the region between the semiconductor layer region adjacent to the second region and the third that will be disposed in the semiconductor layer region under side of the third semiconductor layer area and, the second semiconductor layer region A high-concentration semiconductor layer region having the same conductivity type as the second semiconductor layer region having a high concentration, and charge transfer between the first semiconductor layer region and the third semiconductor layer region on the surface of the second semiconductor layer region A gate electrode layer for forming a channel; and a second electrode layer in contact with the third semiconductor layer region and the high-concentration semiconductor layer .

  In a related embodiment, the third semiconductor layer region corresponding to the emitter layer region is formed in a gear shape, and the width of the third semiconductor layer region is narrowed in the recessed region. Therefore, immediately below the third semiconductor layer region in the parasitic bipolar transistor formed by the semiconductor region (drift layer) / second semiconductor layer region (base region in one embodiment) / third semiconductor layer region (emitter layer in one embodiment). The width of the second semiconductor layer region can be reduced, and the resistance of the second semiconductor layer region can be reduced accordingly. Thereby, the parasitic bipolar transistor operation is suppressed, and accordingly, the latch-up of the parasitic thyristor can be suppressed. In addition, the high concentration semiconductor layer region is disposed below the third semiconductor layer region. Similarly, the resistance of the second semiconductor layer region immediately below the third semiconductor layer region can be reduced, the parasitic bipolar transistor operation can be suppressed, and the latch Up resistance can be improved.

  Further, the main body is continuously formed, and in one embodiment, the channel width formed for the third semiconductor layer region which is an emitter is not reduced, and a constant gate-emitter or gate-source voltage is not reduced. The collector current-emitter current (ICE) characteristics or the source / drain current characteristics do not deteriorate when a collector-emitter voltage or a source-drain voltage is applied in a state where (VGE or VGS) is applied. Further, the channel region is formed in a ring shape, the channel region can be enlarged, and a large current can flow.

  Further, the pitch of the convex portions is set larger than the width of the convex portions, and the gate electrode wiring can be easily taken out.

  In the semiconductor device according to the present invention, in one embodiment, the third semiconductor layer region corresponding to the emitter layer region is composed of unit regions arranged separately from each other in an island shape, and the high concentration semiconductor layer is provided below the unit region. An area is placed. Therefore, immediately below the third semiconductor layer region in the parasitic bipolar transistor formed by the semiconductor region (drift layer) / second semiconductor layer region (base region in one embodiment) / third semiconductor layer region (emitter layer in one embodiment). The resistance of the second semiconductor layer region can be reduced. Thereby, the parasitic bipolar transistor operation is suppressed, and accordingly, the latch-up of the parasitic thyristor can be suppressed.

  Further, in the region between the unit regions, minority carriers flow through the high-concentration semiconductor layer region, and the minority carriers can be absorbed efficiently, and the turn-off time can be shortened. In addition, the high concentration semiconductor layer region is disposed below the third semiconductor layer region. Similarly, the resistance of the second semiconductor layer region immediately below the third semiconductor layer region can be reduced, the parasitic bipolar transistor operation can be suppressed, and the latch Up resistance can be improved.

  In one embodiment, although the unit regions are separately arranged in the third semiconductor layer region which is an emitter, the width of the unit regions is smaller than the distance between the unit regions. The channel width formed for the entire region is not reduced so much, and a collector-emitter voltage or a source-drain voltage is applied with a constant gate-emitter or gate-source voltage (VGE or VGS) applied. The collector current-emitter current (ICE) characteristic or the source / drain current characteristic is not deteriorated when is applied.

It is a figure which shows roughly the surface layout of the horizontal IGBT according to Embodiment 1 of this invention. It is a figure which shows schematically the cross-sectional structure along line L2-L2 shown in FIG. FIG. 2 schematically shows a cross-sectional structure along line L3-L3 shown in FIG. It is a figure which shows schematically the cross-sectional structure along line L4-L4 shown in FIG. FIG. 5 is a diagram showing an electrical equivalent circuit of a parasitic IGBT thyristor shown in FIGS. 1 to 4. (A) is a figure which expands and shows the shape of an emitter layer and an emitter contact area | region, (B) is a figure which expands and shows the structure of this emitter layer more. FIG. 7 is a diagram showing an example of the arrangement of gate electrode lead-out wirings in the emitter layer structure shown in FIG. FIG. 8 is a diagram schematically showing a planar layout of the gate electrode lead-out wiring and each electrode shown in FIG. 7. It is a figure which shows roughly the planar layout of horizontal type IGBT of the modification 1 of Embodiment 1 of this invention. FIG. 10 schematically shows a cross-sectional structure along line L10-L10 shown in FIG. FIG. 10 is a diagram schematically showing a cross-sectional structure taken along line L11-L11 shown in FIG. 9; It is a figure which shows schematically the cross-section of the horizontal IGBT of the modification 2 of Embodiment 1 of this invention. It is a figure which shows roughly the cross-section of the emitter region part of the horizontal IGBT of the modification 2 of Embodiment 1 of this invention. It is a figure which shows roughly the cross-section of the emitter region of the horizontal IGBT according to the modification 3 of Embodiment 1 of this invention. It is a figure which shows roughly the cross-section of the emitter area | region part of the horizontal IGBT of the modification 3 of Embodiment 1 of this invention. It is a figure which shows roughly the layout of the surface of the horizontal type IGBT according to Embodiment 2 of this invention. FIG. 17 schematically shows a cross-sectional structure taken along line L17-L17 shown in FIG. FIG. 17 schematically shows a cross-sectional structure taken along line L18-L18 shown in FIG. It is a figure which shows roughly the cross-section of the emitter area | region part of the horizontal IGBT of the modification 1 of Embodiment 2 of this invention. It is a figure which shows roughly the cross-section of the emitter area | region part of the horizontal IGBT of the modification 1 of Embodiment 2 of this invention. It is a figure which shows roughly the cross-section of the emitter region part of the horizontal IGBT according to the modification 2 of Embodiment 2 of this invention. It is a figure which shows roughly the cross-section of the emitter area | region part of the modification 2 of Embodiment 2 of this invention. It is a figure which shows roughly the cross-section of the emitter region part of the horizontal IGBT according to the modification 3 of Embodiment 2 of this invention. It is a figure which shows roughly the cross-section of the emitter area | region part of the modification 3 of Embodiment 2 of this invention. It is a figure which shows roughly the layout of the surface of the horizontal IGBT according to Embodiment 3 of this invention. FIG. 26 schematically shows a cross-sectional structure along line L26-L26 shown in FIG. FIG. 26 schematically shows a cross-sectional structure taken along line L27-L27 shown in FIG. It is a figure which shows roughly the cross-section of the emitter region part of the horizontal IGBT of the modification 1 of Embodiment 3 of this invention. It is a figure which shows roughly the cross-section of the emitter area | region part of horizontal IGBT in the modification 1 of Embodiment 3 of this invention. It is a figure which shows schematically the cross-section of the emitter region part of the horizontal IGBT of the modification 2 of Embodiment 3 of this invention. It is a figure which shows roughly the cross-section of the emitter area | region part of horizontal IGBT according to the modification 2 of Embodiment 3 of this invention. It is a figure which shows roughly the cross-section of the emitter area | region part of horizontal IGBT of the modification 3 of Embodiment 3 of this invention. It is a figure which shows roughly the cross-section of the emitter area | region part of the modification 3 of Embodiment 3 of this invention. It is a figure which shows roughly the layout of the surface of the horizontal IGBT according to Embodiment 4 of this invention. FIG. 35 is a diagram schematically showing a cross-sectional structure along a line L35-L35 shown in FIG. 34. FIG. 26 is a diagram schematically showing a cross-sectional structure along a line L36-L36 shown in FIG. It is a figure which shows roughly the cross-section of the emitter region part of the horizontal IGBT according to the modification 1 of Embodiment 4 of this invention. It is a figure which shows roughly the cross-section of the emitter region part of the horizontal IGBT according to the modification 1 of Embodiment 4 of this invention. It is a figure which shows roughly the cross-section of the emitter region part of horizontal type IGBT according to the modification 2 of Embodiment 4 of this invention. It is a figure which shows roughly the cross-section of horizontal IGBT according to the modification 2 of Embodiment 4 of this invention. It is a figure which shows roughly the cross-section of the emitter region part of the horizontal IGBT according to the modification 3 of Embodiment 4 of this invention. It is a figure which shows roughly the cross-section of horizontal IGBT according to the modification 3 of Embodiment 4 of this invention. It is a figure which shows roughly the layout of the surface of the lateral MOSFET according to Embodiment 5 of this invention. FIG. 44 schematically shows a cross-sectional structure taken along line L44-L44 shown in FIG. 43. It is a figure which shows an example of arrangement | positioning of the cell of IGBT according to Embodiment 6 of this invention. It is a figure which shows the other example of arrangement | positioning of IGBT cell of Embodiment 6 of this invention. It is a figure which shows roughly the layout of the surface of the conventional elliptical structure type lateral IGBT as a comparison reference. FIG. 48 shows both the channel length of the IGBT according to the sixth embodiment of the present invention and the channel region of the IGBT shown in FIG. 47. It is a figure which shows the switching characteristic of IGBT shown in FIG. It is a figure which shows the switching characteristic of IGBT shown in FIG. It is a figure which shows roughly the cross-section of the horizontal IGBT according to Embodiment 7 of this invention. FIG. 53 is a diagram showing switching characteristics of the lateral IGBT shown in FIG. 51 and the lateral IGBT shown in FIG. 2. FIG. 3 is a diagram showing holes, electron distribution, and depletion layer region boundary lines of the lateral IGBT shown in FIG. 2. It is a figure which shows distribution of the hole of junction isolation | separation structure lateral type IGBT (FIG. 2). It is a figure which shows the density | concentration distribution of the electron of the junction isolation | separation structure horizontal IGBT shown in FIG. FIG. 52 is a diagram showing a depletion layer region boundary portion of the current and potential distribution of the dielectric isolation structure lateral IGBT shown in FIG. 51. It is a figure which shows distribution of the hole of dielectric material isolation structure horizontal IGBT shown in FIG. FIG. 52 is a diagram showing collector-emitter electrons, a hole distribution, and an equilibrium hole / electron concentration distribution in the dielectric isolation structure lateral IGBT shown in FIG. 51.

[Embodiment 1]
1 schematically shows a planar layout of a lateral n-channel IGBT according to the first embodiment of the present invention. In FIG. In FIG. 1, an insulating film, wiring, electrodes, and the like are not shown, and a high-concentration semiconductor region that is one of the features of the present invention is not shown.

  In FIG. 1, the IGBT 1 includes a p-type collector layer (first semiconductor layer region) 2 formed in a circular shape in the center and an n-type buffer layer (semiconductor region) 3 formed so as to surround the collector layer 2. An n − type drift layer (semiconductor region) 4 formed in a ring shape outside the buffer layer 3, and a p type base layer (second semiconductor region) formed in a ring shape outside the n − type drift layer 4 5 and an n + emitter layer (third semiconductor region) 6 formed in the p-type base layer 5.

  The emitter layer 6 includes a main body portion 6a continuously formed in a ring shape, and a convex portion 6b that is arranged at a predetermined interval and is coupled to the main body portion 6a and protrudes in a direction away from the collector layer 2. The n + emitter layer 6 is provided with a convex region and its length in the radial direction is partially increased, thereby shortening the length of the lower portion of the emitter layer in the p-type base layer 5 and reducing the base resistance. .

  In the p-type base layer 5, a channel formation region 8 in which a channel is formed by a voltage of a gate electrode (not shown) is provided between the emitter layer 6 and the n − drift layer 4. In the emitter layer 6 region, an emitter electrode contact region 7 is provided in a ring shape at the center of the p-type base layer 5. In this emitter electrode contact region 7, an emitter electrode that is electrically coupled to the convex portion 6 b of the emitter layer 6 is provided.

  Therefore, in the emitter layer 6, the main body 6 is continuously formed in a ring shape, so that the channel is continuously formed in a ring shape in the channel formation region 8.

  An n-type layer (buffer layer) 3 formed so as to surround the p-type collector layer 2 absorbs minority carriers from the p-type collector layer 2.

  FIG. 2 schematically shows a cross-sectional structure of IGBT 1 along line L2-L2 shown in FIG. In FIG. 2, the IGBT 1 has an n − type drift layer 4 formed on the surface of a p-type semiconductor substrate (semiconductor substrate) 10. An n-type layer (well region) 3 is formed at the center portion (left end in FIG. 2) of the n − layer (drift layer) 4 surface, and a p-type collector layer 2 is formed on the surface of the n-type (buffer) layer 3. Is done. The p-type collector layer 2 is electrically connected to the collector electrode 13. Collector electrode 13 is coupled to a collector terminal (not shown) by collector electrode wiring 14.

  A first insulating film 11 is formed below the collector electrode wiring 14 and on the surface of the n − layer 4, and a second insulating film 12 functioning as a protective film is provided on the first insulating film 11. An interlayer insulating film is provided between the collector electrode 13 and the n buffer layer 3.

  On the other hand, in the emitter section shown on the right side of FIG. 2, the gate wiring 16 is formed on the first insulating film 11. The gate wiring 16 includes a gate electrode wiring portion 16 a formed on the n − layer 4 via a gate insulating film 15. The gate wiring 16 is electrically connected to the gate electrode 17. In the gate wiring 16, the gate electrode wiring portion 16 a is formed in a ring shape, thereby forming a channel according to the voltage applied to the gate electrode 17 over the entire channel formation region 8 on the surface of the p-type base layer 5.

  A p + layer 20 having a higher concentration than the p-type base layer 5 is formed deeper than the emitter layer 6 on the surface of the p-type base layer 5. An n + emitter layer 6 is formed on the p + layer 20. Emitter electrode 21 is formed in contact with both p + layer 20 and n + emitter layer 6. An interlayer insulating film 19 is provided between the gate electrode 17 and the emitter electrode 21 and is separated from each other.

  A high-concentration p + layer 20 is provided at the bottom of the n + emitter layer 6. Therefore, the resistance value of the base layer at the bottom of the n + emitter layer 6 is reduced, and the voltage drop is reduced.

  FIG. 3 schematically shows a cross-sectional structure of IGBT 1 along line L3-L3 shown in FIG. The cross-sectional structure of the IGBT 1 shown in FIG. 3 is the same as the cross-sectional structure in the vicinity of the emitter region of the IGBT shown in FIG. 2, and the corresponding parts are denoted by the same reference numerals, and detailed description thereof is omitted. . However, in FIG. 3, the first and second insulating films 11 and 12 shown in FIG.

  As shown in FIG. 3, n + emitter layer 6 extends from channel formation region 8 to the bottom of emitter electrode 21 (the convex portion is coupled to emitter electrode 21). Emitter electrode 21 is also coupled to p + layer 20 formed at the bottom of n + emitter layer 6. Therefore, the contact resistance between the emitter electrode 21 and the base layer can be reduced as compared with the case where the p-type base layer 5 is directly coupled to the emitter electrode 21. At the time of turn-off or in a steady state, holes (holes) HL flow into the emitter electrode 21 from the p base layer 5 through the p + layer 20. In this case, the resistance value in the p + layer 20 is small, and the voltage drop of the p-type base layer 5 under the n + emitter layer 6 is small. Therefore, the p-type base layer 5 and the n + emitter layer 6 can be prevented from being forward-biased, and the parasitic npn bipolar transistor can be prevented from being turned on. That is, by providing the p + layer 20, the holes HL flow into the emitter electrode 21 without stagnation just below the n + emitter layer 6, and minority carrier holes can be emitted at high speed. In other words, by reducing the contact resistance of the base layer 5 (p + layer 20) with respect to the emitter electrode 21, the base resistance of the p base region immediately below the n + emitter layer 6 is indirectly reduced.

  FIG. 4 schematically shows a cross-sectional structure of IGBT 1 along line L4-L4 shown in FIG. In the region of the IGBT 1 shown in FIG. 4, the n + emitter layer 6 is provided with the main body portion 6a and not with the convex portion 6b. Therefore, the emitter electrode 21 is in contact only with the p + layer 20. The other configuration of the cross-sectional structure shown in FIG. 4 is the same as that of the cross-sectional structure shown in FIG. 3, and corresponding portions are denoted by the same reference numerals, and detailed description thereof is omitted.

  As shown in FIG. 4, in the n + emitter layer 6, the length of the main body portion 6 a is short in a region where the convex portion 6 b is not provided. Therefore, in this region, the base resistance under the n + emitter layer 6 is smaller, and the hole HL is emitted to the emitter electrode 21 through the low resistance p + layer 20 without stagnation. Thereby, the parasitic npn bipolar transistor operation can be more effectively suppressed, and accordingly, the latch-up resistance of the parasitic thyristor when the IGBT 1 is turned off and when the steady state is turned on can be improved.

  FIG. 5 is a diagram showing an electrical equivalent circuit of the parasitic thyristor of the lateral IGBT 1 shown in FIGS. In FIG. 5, the parasitic thyristor includes a pnp bipolar transistor TR1 and an npn bipolar transistor TR2. The pnp bipolar transistor TR1 has an emitter formed by a p-type collector layer 2, a base formed by an n + layer 3 and an n− layer 4, and a collector formed by a p base layer 5 and a p + layer 20. On the other hand, npn bipolar transistor TR2 has a collector formed of n + layer 3 and n− layer 4, an emitter formed of n + emitter layer 6, and a base formed of p base layer 5 and p + layer 20. A base resistance R exists in the base layer of the bipolar transistor TR2.

  The emitter of parasitic bipolar transistor TR 1 is coupled to collector electrode 13, and the emitter and base of parasitic bipolar transistor TR 2 are coupled to emitter electrode 21.

  By providing the p + layer 20 and shortening the length of the n + emitter layer 6 in the radial direction, the base resistance R can be reduced. Accordingly, the voltage between the base and the emitter of the parasitic bipolar transistor TR2 can be suppressed from exceeding the built-in voltage, and the parasitic bipolar transistor TR2 is prevented from being turned on. Thereby, the latch-up resistance of the parasitic thyristor can be improved.

  The emitter layer 6 is formed in a gear shape having a concave portion and a convex portion, and the outer periphery thereof is formed. However, in the inner peripheral portion, the main body portion 6a is continuously formed, and the channel forming region 8 is It is formed continuously. Since the main body 6a of the emitter region 6 is formed in a ring shape, a channel is continuously formed along the circumferential direction of the emitter layer 6, and the channel width can be sufficiently increased. Therefore, the deterioration of the collector-emitter current ICE characteristic when the collector-emitter voltage VC is applied while the constant gate-emitter voltage VGE is applied is suppressed, and a large current can be driven.

  FIG. 6A is a diagram more specifically showing an emitter contact region for n + emitter layer 6 in the planar layout shown in FIG. The n + emitter layer 6 includes a main body portion 6a formed continuously in a ring shape and convex portions 6b arranged at a predetermined interval. The convex portion 6b is connected to the main body portion 6a. An emitter contact region 25 is formed along the outer periphery of the main body portion 6a so as to partially overlap the convex portion 6b. In this emitter electrode contact region 7, an emitter electrode (21) electrically connected to the convex portion 6b and p + layer 20 (not shown in FIG. 6 (A)) formed in the lower portion is formed.

  Therefore, in the emitter electrode contact region 7, the length of the p-type base layer below the n + emitter layer 6 can be reduced by using the protrusion 6 b as a region for electrical connection to the n + emitter layer 6. it can.

  FIG. 6B is an enlarged view showing a part of the structure of the n + emitter layer 6 shown in FIG. In the n + emitter layer 6, convex portions 6b having a width W2 are formed at a predetermined pitch W1 along the circumferential direction on the outer periphery of the main body portion 6a. The pitch W1 of the arrangement of the convex portions 6b is sufficiently larger than the width W2 of the convex portions 6b (W1> W2). By arranging the convex portions 6b of the n + emitter layer with a sufficient interval, an increase in the radial width of the n + emitter layer 6 can be sufficiently suppressed, and the base resistance can be reduced. Further, when the pitch W1 is sufficiently larger than the width W2 of the convex portion 6b, the following advantages are obtained.

  FIG. 7 is an enlarged view showing a planar layout of the n + emitter layer, the emitter electrode, and the gate electrode lead wiring. As shown in FIG. 7, the n + emitter layer 6 includes a main body portion 6a formed continuously in a ring shape, and convex portions 6b arranged at a predetermined pitch (W1) adjacent to the main body portion 6a. Including. Electrical contact is made with the emitter electrode 30 (21) with respect to the convex portion 6b. The emitter electrode 30 corresponds to the emitter electrode 21 shown in FIG. 2, and is arranged in a ring shape along the emitter electrode contact region 7 shown in FIG. A gate electrode lead-out wiring 32 is disposed between the protrusions 6b.

  In the region where the gate electrode lead-out wiring 32 is disposed between the convex portions 6b, the emitter electrode 30 is separated. Therefore, the main body portion 6a of the n + emitter layer 6 is continuously extended and arranged below the gate electrode lead-out wiring 32, and the emitter electrode 21 (30) is electrically connected to the n + emitter layer 6 through the convex portion 6b. Can be contacted. This eliminates the need to separate the emitter layer 6 in the region where the gate electrode lead wiring 32 is provided. By continuously extending the n + emitter layer body 6a, the channel formation region can be continuously extended, and the channel width of the IGBT can be prevented from being reduced.

  FIG. 8 is a diagram schematically showing a planar layout of the emitter electrode and the gate electrode of the IGBT 1. As shown in FIG. 8, in the IGBT, a channel forming region 8 is provided in the inner peripheral portion of the p base layer 5. A gate electrode (a gate wiring including gate electrode wirings 16 and 19) 17 is formed in a ring shape inside the channel formation region 8. Gate electrode 17 is arranged to surround n buffer layer 3 and p collector layer 2 formed therein.

  An n + emitter layer 6 having a main body portion 6a continuously formed in a ring shape and a convex portion 6b connected to the main body portion 6a is provided outside the channel forming region 8. An emitter electrode 30 (emitter electrode contact region 7) is provided on the surface of the p base layer 5 so as to partially overlap the convex portion 6b of the emitter layer 6. A part of the emitter electrode 30 is separated in a region between the convex portions 6b. In the isolation region of the emitter electrode 30, a gate electrode lead-out wiring 32 is disposed and coupled to the channel gate electrode 17 formed in a ring shape inside.

  Therefore, as shown in FIG. 8, n + emitter layer 6 is formed continuously and is electrically connected to emitter electrode 30. Therefore, a channel can be continuously formed in the n + emitter layer 6 in the channel formation region 8, and a reduction in channel width can be suppressed.

  In FIG. 8, the emitter electrode 30 is cut and separated at one place, and the gate electrode lead-out wiring 32 is disposed in this separation region. However, the emitter electrode 30 may be cut at a plurality of locations, and the gate electrode lead-out wiring 32 may be provided in each cutting region. Each divided emitter electrode 30 may be coupled to an emitter electrode lead-out line (emitter terminal) in common.

  As described above, by making the width (W1) along the circumferential direction of the convex portion 6b smaller than the pitch (W2) along the circumferential direction of the convex portion 6b, the gate electrode lead-out wiring 32 becomes , Can be disposed with a sufficient margin. This prevents the collector-emitter current ICE characteristic from deteriorating when the collector-emitter voltage VC is applied in a state where the gate-emitter voltage VGE is applied.

  In the above description, an n-channel IGBT is shown. However, the same effect can be obtained even when a lateral p-channel IGBT is used.

  If the conductivity type of each region is reversed, a lateral p-channel IGBT is obtained, and in the n base layer, a high concentration semiconductor region is formed adjacent to the p emitter region and deeper than the emitter layer.

[Modification 1]
FIG. 9 schematically shows a planar layout of the IGBT according to the first modification of the first embodiment of the present invention. Also in FIG. 9, the insulating film, electrodes, and wiring are not shown. The planar layout shown in FIG. 9 differs from the planar layout of the IGBT 1 shown in FIG. 1 in the following points. That is, in the p-type base layer 5, a high-concentration p + layer 35 is provided in a ring shape below the n + emitter layer 6 so that the tip and the outer periphery of the protrusion 6 b of the emitter layer 6 are aligned. The other configuration of the planar layout shown in FIG. 9 is the same as that of the planar layout shown in FIG. 1, and corresponding portions are denoted by the same reference numerals, and detailed description thereof is omitted.

  FIG. 10 schematically shows a cross-sectional structure along line L10-L10 shown in FIG. In FIG. 10, a p + layer 35 is formed in the p base layer 5 below the n + emitter layer 6 (6a, 6b) so that the end of the n + emitter layer is aligned. The other structure of the cross-sectional structure shown in FIG. 10 is the same as the cross-sectional structure shown in FIG. 3. Corresponding portions are denoted by the same reference numerals, and detailed description thereof is omitted. Therefore, in this region, emitter electrode 21 is electrically coupled to p-type base layer 5 and n + emitter layer 6.

  FIG. 11 schematically shows a sectional structure taken along line L11-L11 shown in FIG. In the cross-sectional structure shown in FIG. 11, the n + emitter layer 6 is formed with the main body portion 6a and not with the convex portion (6b). In this region, the high concentration p + layer 35 is coupled to the emitter electrode 21.

  As shown in FIGS. 9 to 11, in the p base layer 5, the p + layer 35 is provided below the n + emitter layer 6, and the emitter electrode 21 is formed in the concave region of the emitter layer where the convex portion 6 b is not provided. Are electrically connected to the high concentration n + region, the resistance of the p base layer 5 can be reduced, and the latch-up resistance of the parasitic thyristor can be improved. Further, the channel is continuously formed in a link shape by the main body 6a, the channel width can be sufficiently widened, and the deterioration of the collector-emitter current ICE characteristic is suppressed. Further, the p + layer 35 is electrically coupled to the emitter electrode 21, and the contact resistance of the emitter electrode 21 with respect to the base layer 5 can be reduced. Accordingly, the base resistance can be reduced, and the latch-up resistance of the parasitic thyristor can be further increased. It can be further improved.

  Further, in the n + emitter layer 6, the width of the convex portions 6b is narrower than the pitch of the convex portions 6b, and the gate electrode lead-out wiring can be arranged with a margin as in the configuration shown in FIG.

[Modification 2]
12 and 13 are diagrams schematically showing a cross-sectional structure of the emitter region portion of the IGBT according to the second modification of the first embodiment of the present invention. The cross-sectional structure shown in FIG. 12 corresponds to the cross-sectional structure along line L10-L10 shown in FIG. In the IGBT shown in FIG. 12, the n + emitter layer 6 includes a main body portion 6a formed in a circular shape and a convex portion 6b protruding in a direction away from the collector layer, as before. Under the n + emitter layer 6, a p + layer 40 having substantially the same size is provided. The cross-sectional structure shown in FIG. 12 is the same as the cross-sectional structure shown in FIG. 10, and the corresponding parts are denoted by the same reference numerals, and detailed description thereof is omitted.

  The cross-sectional structure shown in FIG. 13 corresponds to the cross-sectional structure along line L11-L11 shown in FIG. In FIG. 13, the convex part (6b) of the n + emitter layer is not provided, and the main body part 6a is arranged. A p + layer 40 is formed so as to surround the body portion 6 a of the n + emitter layer 6, and the p + layer 40 is electrically coupled to the emitter electrode 21.

  The other configuration of the cross-sectional structure shown in FIG. 13 is the same as the cross-sectional structure shown in FIG. 11, and corresponding portions are denoted by the same reference numerals, and detailed description thereof is omitted.

  As shown in FIGS. 12 and 13, the p base layer 5 is formed by forming a lower portion of the n + emitter layer 6 (6 a, 6 b) and a p + layer 40 deeper than the n + emitter layer 6 in the p base layer 5. The base resistance can be reduced, and the contact resistance with respect to the p base layer 5 can also be reduced. Thus, the same effects as those shown in FIGS. 1 to 4 can be obtained.

[Modification 3]
14 and 15 are diagrams schematically showing a cross-sectional structure of the emitter region portion of the IGBT according to the third modification of the first embodiment of the present invention. The cross-sectional structure shown in FIG. 14 corresponds to the cross-sectional structure taken along line L10-L10 in the planar layout shown in FIG. 9, and the cross-sectional structure shown in FIG. 15 taken along line L11-L11 in the planar layout shown in FIG. Corresponds to the cross-sectional structure.

  As shown in FIG. 14, a high-concentration p + layer 45 is provided in the p base layer 5 below the n + emitter layer 6 (main body portion 6a, convex portion 6b). The p + layer 45 is buried in the p base layer 5 and is separated from the emitter layer 6. Emitter electrode 21 is electrically coupled to n + emitter layer 6 and p base layer 5. On the other hand, as shown in FIG. 15, in the region where the main body portion 6 a is provided in the n + emitter layer 6 and the convex portion 6 b is not provided, the p + layer 45 is formed in the p base layer 5 in the emitter electrode. 21 extends to the bottom.

  Other configurations of the cross-sectional structures shown in FIGS. 14 and 15 are the same as the cross-sectional structures shown in FIGS. 12 and 13, and corresponding portions are denoted by the same reference numerals, and detailed description thereof is omitted.

  As shown in FIGS. 14 and 15, even when the p + layer 45 is arranged in the p base layer 5 apart from the n + emitter layer 6, the base resistance under the n + emitter layer 6 is reduced by the p + layer 45. The latch-up resistance can be improved. Further, the channel forming region 8 is continuously formed, and the deterioration of the collector-emitter current IC characteristics can be sufficiently suppressed. The shape of the emitter layer 6 is the same as that described in FIGS. 1 to 4 and Modifications 1 and 2, and has a main body portion 6a and a convex portion 6b, and the gate electrode lead-out wiring has a sufficient margin. The same effects as those of the first embodiment and the first and second modified examples described so far can be obtained.

  As described above, according to the first embodiment of the present invention, in the lateral IGBT, the emitter layer is formed in a gear shape having a concave portion and a convex portion (a shape having a main body portion and a convex portion), and more than this emitter layer. A high concentration semiconductor layer is formed in a deep portion. Accordingly, the base resistance can be reduced and the latch-up resistance of the parasitic thyristor can be improved. Further, the channel width can be sufficiently wide, and the collector-emitter current (ICE) characteristic when the collector-emitter voltage (VC) is applied in a state where a constant gate-emitter voltage (VGE) is applied. Deterioration can be suppressed. Further, the gate electrode lead-out wiring can also be arranged without affecting the contact between the emitter electrode and the emitter layer, a sufficient channel width can be secured, and a large current can be driven.

[Embodiment 2]
FIG. 16 schematically shows a planar layout of the IGBT according to the second embodiment of the present invention. Also in FIG. 16, in order to simplify the drawing, the insulating film, the electrode wiring, and the high concentration p-type layer in the base layer are not shown.

  The planar layout shown in FIG. 16 differs from the planar layout of the IGBT according to the first embodiment shown in FIG. 1 in the following points. That is, unit emitter layers (unit regions) 60 arranged separately from each other as n + emitter layers arranged in the p-type base layer 5 are arranged in a predetermined direction along the circumferential direction in the p-type base layer 5. Arranged at intervals. The other configuration of the planar layout of the IGBT shown in FIG. 16 is the same as the configuration of the planar layout shown in FIG. 1, and corresponding portions are denoted by the same reference numerals, and detailed description thereof is omitted.

  The width a along the circumferential direction of the unit emitter layer 60 is made larger than the interval b between the unit regions. The unit emitter layer 60 may have a rectangular shape having four sides. The width and interval are lengths along the circumferential direction.

  FIG. 17 schematically shows a sectional structure taken along line L17-L17 shown in FIG. As shown in FIG. 17, a high-concentration p-type semiconductor layer (p + layer) 62 is formed below the unit emitter layer 60 on the surface of the p base layer 5. Emitter electrode 21 is electrically connected to unit emitter layer 60 and p + layer 62 in emitter layer contact region 7 shown in FIG. A channel forming region 8 is formed on the surface of the p base layer 5 adjacent to the unit emitter layer. A gate wiring 16 a is provided on the channel formation region 8 with a gate insulating film 15 interposed therebetween. The gate wiring 16 a is constituted by a gate wiring that extends continuously, and constitutes a part of the gate electrode 17.

  A unit emitter layer 60 is formed in the p base layer 5 on the surface of the n − layer 4, and a high-concentration p + layer 62 is provided deeper and below the unit emitter layer.

  18 schematically shows a sectional structure taken along line L18-L18 shown in FIG. The unit emitter layer 60 is formed in an island shape. In the region shown in FIG. 18, the unit emitter layer 60 is not provided, and the p + layer 62 extends so as to be adjacent to the channel formation region 8. It is formed on the surface of the p base layer 5. A p + layer 62 is coupled to the emitter electrode 21.

  In the channel formation region 8, a channel is formed by a voltage applied to the upper gate wiring 16a. The unit emitter layer 60 is not provided in the region shown in FIG. Therefore, the holes in the turn-off state or the steady-state on-state are not in the region immediately below the n + emitter layer 60 but through the p base layer or the p + layer 62 provided between the unit emitter layers 60 to the emitter electrode 21. The tendency to flow increases. The number of holes flowing directly under the emitter layer is reduced, and the operation of the parasitic npn bipolar transistor formed by n− layer 4 / p base layer 5 / n + emitter layer 62 is suppressed. Accordingly, latch-up of the parasitic thyristor formed by p collector layer 2 / n buffer layer 3, n− drift layer 4 / p base layer 5 / n + emitter layer 60 can be suppressed.

  Further, the base resistance under the unit emitter layer 60 is reduced by the p + layer 62, and the latch-up of the parasitic thyristor can be suppressed as in the first embodiment.

  In addition, there is a region where the emitter electrode 21 is directly connected to the p + layer 62, the contact resistance between the emitter electrode 21 and the p base layer 5 can be reduced, and the p base layer 5 (p + layer 62) can be smoothly smoothed. Holes flow through the contact region between the emitter electrode 21 and the emitter electrode 21, and the latch-up resistance of the parasitic thyristors of the unit emitter layer 60 and the p + layer 62 can be further improved.

  As shown in FIG. 16, the width a along the circumferential direction of the unit emitter layer is sufficiently wider than the pitch b of the unit emitter layer 60. Therefore, the channel width can be sufficiently increased in the channel forming region 8 facing the unit emitter layer 60, and the collector-emitter current ICE characteristics can be improved.

  As shown in FIG. 16, the shape of the planar layout of the unit emitter layer 60 may be any shape such as a sector shape, a trapezoid shape, or a strip shape, and forms a closed region having four sides. It suffices if the unit emitter layer 60 is formed in an island region, and here, the shape having four sides of a strip shape, a trapezoidal shape or a fan shape is defined as a “rectangular shape”.

  The pitch b of the unit emitter layers 60 may be set to a size that allows a channel having a sufficient width to be formed in the channel formation region 8. Therefore, the unit emitter layer 60 may have a shape in which the outer peripheral portion is narrow and the portion facing the channel forming region 8 is wide.

  Further, similarly to the structure shown in FIG. 8, the gate electrode wiring extraction wiring may be arranged in a region between the island regions.

[Modification 1]
19 and 20 are diagrams schematically showing a cross-sectional structure of the emitter region portion of the IGBT according to the first modification of the second embodiment of the present invention. 19 corresponds to the cross-sectional structure along line L17-L17 shown in FIG. 16, and the cross-sectional structure shown in FIG. 20 corresponds to the cross-sectional structure along line L18-L18 shown in FIG. In the structure shown in FIG. 19, a p + layer 62 is formed below the unit n + emitter layer 60. The p + layer 62 is shorter in the radial direction than the unit emitter layer 60, and the outer peripheral portion is arranged in alignment with the outer peripheral portion of the unit emitter layer 60. Therefore, in this region, the emitter electrode 21 is electrically connected to the unit emitter layer 60 and the p-type base layer 5.

  On the other hand, in the region where the unit emitter layer 60 is not provided, the p + layer 62 is continuously formed on the surface of the p base layer 5 as shown in FIG. The p + layer 62 is formed in a part of the p base layer 5 adjacent to the channel forming region 8. In this region, emitter electrode 21 has p + layer 62 and p electrically connected to other base layer 5. In the cross-sectional structures shown in FIG. 19 and FIG. 20, the other configurations are the same as those in the cross-sectional structures shown in FIG. 17 and FIG. .

  Also in the configuration shown in FIGS. 19 and 20, the length along the radial direction of the p + layer 62 is simply shortened, and the channel forming region 8 extends to the bottom of the emitter electrode 21 in the p base layer 5. Thus, the same effect as the configuration shown in FIGS. 17 and 18 can be obtained.

[Modification 2]
21 and 22 are diagrams schematically showing a cross-sectional structure of the emitter region of the IGBT according to the second modification of the second embodiment of the present invention. Also in the configuration of Modification 2 shown in FIGS. 21 and 22, the planar layout is the same as the planar layout of the IGBT shown in FIG. 16, and the unit emitter layers 60 are spaced apart from each other along the circumferential direction. Arranged at a predetermined pitch.

  The cross-sectional structure shown in FIG. 21 corresponds to the cross-sectional structure along line L17-L17 shown in FIG. 16, and FIG. 22 corresponds to the cross-sectional structure along line L18-L18 shown in FIG. As shown in FIG. 21, the p + layer 62 is formed so as to have substantially the same radial width as the unit n + emitter layer 60 and extends to the lower part of the gate wiring 16a so as to be in contact with the channel forming region 8. Is done. A p + layer 62 is arranged in alignment with the outer peripheral portion and the inner peripheral portion of the unit emitter layer 60. Emitter electrode 21 is electrically connected to unit n + emitter layer 60 and p-type base layer 5.

  As shown in FIG. 22, in the region where the unit n + emitter layer 60 is not provided, the p + layer 62 is disposed adjacent to the channel formation region 8 and extends to the lower portion of the gate electrode wiring 16a. The emitter electrode 21 is electrically coupled.

  Also in the configurations shown in FIGS. 21 and 22, the p base layer 5 is provided with the high-concentration p + layer 62 and formed deeper than the unit n + emitter layer 60, and efficiently absorbs holes. Thus, it can be emitted to the emitter electrode 21 and the same effect as the configuration shown in FIGS. 17 and 18 can be obtained. In particular, the p + layer 62 is formed in contact with the channel formation region 8, and the base resistance under the unit emitter layer 62 can be reduced, and the channel formed in the channel formation region 8 can be efficiently removed. Can be absorbed and emitted to the emitter electrode 21.

  In the second embodiment, a lateral p-channel IGBT may be used as the IGBT. Electrons as minority carriers are emitted by the high concentration n + layer.

[Modification 3]
23 and 24 are diagrams schematically showing a cross-sectional structure in the vicinity of the emitter region of the IGBT according to the third modification of the second embodiment of the present invention. The planar layout of the IGBT of Modification 3 shown in FIG. 23 and FIG. 24 is the same as the structure shown in FIG. 16, and the unit n + emitter layer 60 is separated as the emitter layer in the p base layer 5 of the IGBT. Arranged.

  23 corresponds to the cross-sectional structure along line L17-L17 shown in FIG. 16, and the cross-sectional structure shown in FIG. 24 corresponds to the cross-sectional structure along line L18-L18 shown in FIG.

  As shown in FIGS. 23 and 24, in Modification 3, a p + layer 64 is buried in the p base layer 5 in a region deeper than the unit n + emitter layer, separated from the unit n + emitter layer 62. Formed as a layer. The p + layer 64 is disposed adjacent to the channel forming region 8 and extends to the lower part of the emitter electrode 21 in the p base layer 5. Other configurations of the IGBT shown in FIGS. 23 and 24 are the same as the configurations of the cross-sectional structures shown in FIGS. 17 to 22, and corresponding portions are denoted by the same reference numerals, and detailed description thereof is omitted.

  23 and 24, the base resistance at the bottom of the unit n + emitter layer 60 can be reduced by forming the p + layer 64 in a deep region in the p base layer 5. Further, in the region where the unit n + emitter layer 60 is not formed (see FIG. 24), the p + layer 64 can efficiently absorb holes and transfer them to the emitter electrode 21. Therefore, as shown in FIGS. 23 and 24, in the configuration in which unit n + emitter layer 60 is arranged separately, buried p + layer 64 is buried in a region deeper than unit n + emitter layer in p base layer 5. By forming the ring continuously, it is possible to improve the latch-up resistance of the parasitic thyristor. Moreover, since the channel width is sufficiently taken (the width along the circumferential direction of the unit n + emitter layer is made sufficiently larger than the pitch), the channel width can be sufficiently secured, and a large collector-emitter current flows. Can do.

  The buried p + layer 64 may have the same radial width as the unit n + emitter layer, and the buried p + layer 64 and the unit n + emitter layer 62 may be aligned.

  As described above, according to the second embodiment of the present invention, in the emitter region, the unit emitters are arranged in an island-like rectangular shape at a predetermined pitch, and the radial direction of the unit emitter layer , The minority carriers can be emitted to the emitter electrode through the high-concentration impurity layer in a state where the channel width is sufficiently wide. An improvement in the latch-up capability and an increase in driving current can be realized. Further, the turn-off time can be shortened.

[Embodiment 3]
FIG. 25 schematically shows a planar layout of the IGBT according to the third embodiment of the present invention. Also in the planar layout shown in FIG. 25, in order to simplify the drawing, insulating films, electrodes and wirings are not shown.

  The planar layout shown in FIG. 25 is the same as the planar layout of the IGBT according to the first embodiment shown in FIG. In the IGBT shown in FIG. 25, the cross-sectional structure forms a p + layer deeper than the p base layer 5 as will be described in detail below. The n + emitter layer 6 includes a main body portion 6a formed continuously in a ring shape and a protruding portion 6b protruding in the radial direction. Other configurations of the planar layout of the IGBT shown in FIG. 25 are the same as the planar layout of the IGBT shown in FIG. 1, and corresponding portions are denoted by the same reference numerals, and detailed description thereof is omitted.

  FIG. 26 schematically shows a cross-sectional structure taken along line L26-L26 shown in FIG. In FIG. 26, the base layer region 70 has a p base layer 72 formed in the channel forming region 8 deeper than the n + emitter layer 6 and a p + formed deeper than the p base layer 70 below the n + emitter layer 6. Layer 74 is included. N + emitter layer 6 and p + layer 74 are coupled to emitter electrode 21. A gate wiring 16 a (16) is provided on the channel formation region 8 via a gate insulating film 15. The gate wiring 16 is coupled to the gate electrode 17. Base region 70 is formed on the surface of n − drift layer 4.

  27 schematically shows a cross-sectional structure taken along line L27-L27 shown in FIG. In the cross-sectional structure shown in FIG. 27, in the n + emitter layer 6, the main body portion 6a is disposed and the convex portion 6b is not provided. Therefore, p + layer 74 is formed adjacent to and deeper than p base layer 72 and is entirely coupled to emitter electrode 21. Other configurations of the cross-sectional structure shown in FIG. 27 are the same as those of the cross-sectional structure shown in FIG. 26, and corresponding portions are denoted by the same reference numerals, and detailed description thereof is omitted.

  A p + layer 74 is formed deeper than the p base layer 72 and below the n + emitter layer 6 (6a). Therefore, in addition to the effects described in the first embodiment, the following effects can be further obtained.

  That is, in the parasitic npn bipolar transistor formed of n− layer 4 / p base layer 72 / n + emitter layer 6, the width of the p base region immediately below n + emitter layer 6 (6a) is narrow, and the base resistance can be reduced. And the operation of the parasitic npn bipolar transistor can be suppressed. Accordingly, the latch-up of the parasitic thyristor can be suppressed, and the latch-up resistance of the parasitic thyristor can be improved as in the first embodiment.

  Further, the base resistance is small due to the p + layer 74, and the hole HL flows through the p + layer 74 through the base resistance. In this case, the electric field strength of the curvature portion AR2 at the bottom of the p + layer 74 may be higher in the p base layer 72 than the electric field strength of the curvature portion AR1 (the impurity concentration in the p + layer 74 is higher than that in the p base layer 72). Is high). Therefore, in this case, since the hole current (the flow of the hole HL) flows in from the curvature portion AR2 at the bottom of the p + layer 74, the length of the hole current flowing immediately below the n + emitter layer 6 (6a) is shortened. Therefore, the length of the base resistance immediately below the n + emitter layer 6 (6a) is short, and accordingly, the base resistance can be reduced, operation of the parasitic bipolar transistor can be suppressed, and latch-up of the parasitic thyristor can be suppressed. .

  Further, the radial width of the p base layer 72 is shortened, and the base resistance can be further reduced.

[Modification 1]
28 and 29 are diagrams schematically showing a cross-sectional structure of the emitter region portion of the IGBT according to the first modification of the third embodiment of the present invention. The planar layout of the IGBT according to the first modification of the third embodiment is the same as that shown in FIG. The cross-sectional structure shown in FIG. 28 corresponds to the cross-sectional structure along line L26-L26 shown in FIG. 25, and the cross-sectional structure shown in FIG. 29 corresponds to the cross-sectional structure along line L27-L27 shown in FIG.

  The n + emitter layer 6 includes a main body portion 6a continuously extending in a ring shape, and a protruding portion 6b protruding in a direction away from the collector layer. In FIG. 28, the base layer region 70 includes a high-concentration p + layer 75 formed under the n + emitter layer 6 (6a, 6b) and p base layers 72 and 76 disposed on both sides of the p + layer 75. Including. N + emitter layer 6 and p base layer 76 are coupled to emitter electrode 21. The p base layer 72 is formed deeper than the emitter layer 6 below the channel forming region 8 and the emitter layer body 6a.

  On the other hand, as shown in FIG. 29, in the region where the convex portion 6b is not provided in the emitter layer 6, the p + layer 75 is lower than the p base layers 72 and 79 from the lower portion of the emitter layer body portion 6a to the lower portion of the emitter electrode 21. Deeply formed.

  Other configurations of the cross-sectional structure shown in FIGS. 28 and 29 are the same as the components of the cross-sectional structure shown in FIGS. 26 and 27, respectively, and corresponding portions are denoted by the same reference numerals. Omitted.

  Also in the configuration of the modification example 1, the p + layer 75 is formed deeper than the p base layers 72 and 76 and below the n + emitter layer 6. Therefore, as in the first embodiment, the base resistance of the p base layer below the emitter layer can be reduced, the base resistance of the parasitic npn bipolar transistor can be reduced, and the latch-up resistance of the parasitic thyristor can be improved. it can. Similarly to the configurations shown in FIGS. 26 and 27, the holes HL of minority carriers can be efficiently absorbed by the p + layer 75 and emitted to the emitter electrode 21. In addition, the same effect as the configuration shown in Embodiment 1 can be obtained.

[Modification 2]
30 and 31 are diagrams schematically showing a cross-sectional structure of the emitter region portion of the IGBT according to the second modification of the third embodiment of the present invention. Also in the configuration of the modification example 2, the n + emitter layer 6 includes the main body portion 6a and the convex portion 6b, similarly to the planar layout shown in FIG. The cross-sectional structure shown in FIG. 30 corresponds to the cross-sectional structure along L26-L26 shown in FIG. 25, and the structure shown in FIG. 31 corresponds to the cross-sectional structure along line L27-L27 shown in FIG.

  The cross-sectional structures shown in FIGS. 30 and 31 differ from the cross-sectional structures shown in FIGS. 28 and 29 in the following points. That is, the p + layer 75B formed deeper than the p base layers 72 and 76 and below the n + emitter layer 6 (6a, 6b) is aligned with the inner periphery of the n + emitter layer 6, and the inner periphery thereof is disposed. Further, the outer peripheral portion is also arranged in alignment with the outer peripheral portion of the convex portion (6b) of the n + emitter layer 6.

  Other components of the cross-sectional structure shown in FIGS. 30 and 31 are the same as those shown in FIGS. 28 and 29, and corresponding portions are denoted by the same reference numerals, and detailed description thereof is omitted.

  In the cross-sectional structures shown in FIGS. 30 and 31, the p + layer 75B is aligned with the inner periphery of the n + emitter layer 6 to form the inner periphery. Therefore, the base resistance under the n + emitter layer 6 can be further reduced, and the parasitic bipolar transistor operation can be efficiently suppressed. In addition, it is possible to obtain the same effect as the configuration shown in FIGS.

[Modification 3]
32 and 33 are diagrams schematically showing a cross-sectional structure of the emitter region portion of the IGBT according to the third modification of the third embodiment of the present invention. The cross-sectional structure shown in FIG. 32 corresponds to the cross-sectional structure along line L26-L26 in the planar layout shown in FIG. 25, and the cross-sectional structure shown in FIG. 33 is the cross-sectional structure along line L27-L27 shown in FIG. Corresponding to

  In the configuration of Modification 3, p + layer 75C is embedded in the p base layer and formed deeper than p base layers 72 and 76, as shown in FIGS. The p + layer 75C is arranged separately from the n + emitter layer 6 (6a, 6b). Therefore, p base layers 72 and 76 formed on both sides of p + layer 75C are connected at the bottom of n + emitter layer 6.

  Other configurations of the cross-sectional structure shown in FIGS. 32 and 33 are the same as those of the cross-sectional structure shown in FIGS. 28 to 31, and the corresponding portions are denoted by the same reference numerals, and the detailed description thereof will be described. Omitted.

  As shown in FIGS. 32 and 33, a width of the n + emitter layer 6 in the base region layer is similarly formed by forming a p + layer 75C deeply below the n + emitter layer 6 and away from the n + emitter layer. Can be shortened by the main body 6a, and the base resistance can be reduced. In addition, the p + layer 75C can efficiently absorb the hole HL and transmit it to the emitter electrode 21, as in the configuration shown in FIGS. That is, the electric field strength of the curvature portion of the p + layer 75C can be made larger than that of the curvature portion of the p base layer 72, holes can be efficiently absorbed by the p + layer 75C, and the lower portion of the n + emitter layer 6 can be absorbed. The resistance value of the path through which the hole current flows can be reduced.

  Further, the length of the path through which the hole current flows can be shortened by the main body 6a. Therefore, similarly to the configuration shown in FIGS. 26 to 31, the operation of the parasitic bipolar transistor can be suppressed, and the latch-up resistance of the parasitic thyristor can be improved. The channel forming region 8 is formed continuously, the channel width can be made sufficiently large, and a sufficiently large collector-emitter current can be driven.

  As described above, according to the third embodiment of the present invention, the emitter layer region is formed in a gear shape with the main body part and the convex part connected to the main body part at a predetermined interval, and is deeper than the base layer. Concentration impurity regions are formed, and minority carriers can be absorbed efficiently. Thereby, the base resistance in the lower part of the emitter layer can be reduced, the operation of the parasitic bipolar transistor can be suppressed, and the latch-up resistance of the parasitic thyristor can be improved. Further, the channel is continuously formed in a ring shape, the channel width is increased, and a sufficiently large collector-emitter current can flow.

  In the third embodiment as well, the emitter region is formed in a gear shape. By appropriately setting the width and pitch conditions of the convex portion of the emitter layer region, the gate region is formed in the region between the convex portions. The electrode lead-out wiring can be arranged, and the same effect as in the first embodiment can be obtained.

[Embodiment 4]
FIG. 34 schematically shows a planar layout of the IGBT according to the fourth embodiment of the present invention. Also in FIG. 34, electrodes, wirings, and insulating layers are not shown. The planar layout shown in FIG. 34 differs from the planar layout shown in FIG. 16 in the following points. That is, in the base layer region 80 formed in the periphery of the n − layer 4, the high concentration p + layer is formed deeper than the p base layer. The emitter layer is realized by unit emitter layers 60 separated from each other. The width a and pitch b of the unit emitter layer 60 satisfy the same relationship as in the case of the IGBT shown in the second embodiment.

  FIG. 35 schematically shows a sectional structure taken along line L35-L35 shown in FIG. As shown in FIG. 35, a p + layer 84 deeper than the p-type base layer 82 and having a higher concentration than the p-type base layer 80 is formed below the unit n + emitter layer 60. The p-type base layer 82 is arranged so as to extend to a part of the channel forming region 8 and the lower part of the n + emitter layer 60. Emitter electrode 21 is electrically connected to unit n + emitter layer 60 and p + layer 84.

  36 schematically shows a sectional structure taken along line L36-L36 shown in FIG. In the region shown in FIG. 36, no emitter layer is provided on the surface of p + layer 84. The p + layer 84 is connected to the p-type base layer 82. The emitter electrode 21 is electrically connected to the high concentration p + layer 84. Other configurations of the cross-sectional structure shown in FIGS. 35 and 36 are the same as those shown in FIGS. 17 and 18, and corresponding portions are denoted by the same reference numerals, and detailed description thereof is omitted.

  That is, as shown in FIGS. 35 and 36, when the unit emitter layers 60 are separated from each other and arranged in the emitter electrode contact region along the circumferential direction, the high concentration p + layer 84 is formed. It is formed deeper than the p base layer 82. The electric field strength of the curvature part AR2 below the p + layer 84 can be made higher than the curvature part AR1 of the p base layer 82 shown in FIG. 35, and the holes HL can be efficiently passed through the p + layer 84 to the emitter electrode 21. Can be communicated to. In particular, as shown in FIG. 36, when the n + emitter layer 60 is not provided, the hole HL can be transmitted to the emitter electrode 21 with low resistance. A p + layer 84 is provided below the n + emitter layer. The resistance value immediately below the n + emitter layer 60 is small, and the PN junction between the p + layer and the n + emitter layer 60 is less than the built-in voltage. Carrier injection is suppressed. Therefore, in addition to the configuration shown in the second embodiment, the holes HL can be absorbed and transmitted to the emitter electrode 21 in the deep p + layer 84 more efficiently.

[Modification 1]
FIGS. 37 and 38 schematically show a cross-sectional structure of the emitter region of the first modification of the IGBT according to the fourth embodiment of the present invention. The cross-sectional structure shown in FIG. 37 corresponds to the cross-sectional structure along line L35-L35 shown in FIG. 34, and the cross-sectional structure shown in FIG. 38 corresponds to the cross-sectional structure along line L36-L36 shown in FIG.

  As shown in FIGS. 37 and 38, a high-concentration deep p + layer 85A includes a p base layer 82 formed in the channel formation region 8 and a p base formed on the outer periphery of the base region 80 below the emitter electrode 21. It is formed between the layers 86. Unit n + emitter layer 60 is formed on the surface of p + layer 85A. In FIG. 37, the emitter electrode 21 is connected to the unit emitter layer 60 and the p-type base layer 86. In the region shown in FIG. 38, since unit emitter layer 60 is not provided, emitter electrode 21 is electrically connected to p + layer 85A and p-type base layer 86. Other components of the structure shown in FIGS. 37 and 38 are the same as those shown in FIGS. 35 and 36, and corresponding portions are denoted by the same reference numerals, and detailed description thereof is omitted.

  Also in the configurations shown in FIGS. 37 and 38, when the unit n + emitter layer 60 is arranged separately from each other by providing the p + layer 85A, the region between the n + emitter layers (see FIG. 38). Holes can be efficiently transmitted to the emitter electrode 21 through the p + layer 85A. Further, the deep high-concentration p + layer 85A can absorb holes and transmit them to the emitter electrode 21 more efficiently than the p base layer 82 by a high electric field. In addition, the emitter electrode 21 is electrically connected to the high-concentration p + type layer 85A, so that the contact resistance between the base layer and the emitter electrode can be reduced, and accordingly, the base resistance can be reduced.

[Modification 2]
FIGS. 39 and 40 are diagrams schematically showing a cross-sectional structure of the emitter region portion of the modification 2 of the IGBT according to the fourth embodiment of the present invention. 39 and 40 differ from the cross-sectional structure shown in FIGS. 37 and 38 in the following points. That is, the p + layer 85B is formed so as to have substantially the same width in the radial direction as the unit n + emitter layer 60, and the inner and outer peripheral portions thereof are aligned in the region shown in FIG. These other components of the structure shown in FIGS. 39 and 40 are the same as those of the structure shown in FIGS. 37 and 38, and corresponding portions are denoted by the same reference numerals, and detailed description thereof is omitted. To do.

  In the configurations shown in FIGS. 39 and 40, the high concentration p + layer 85B is formed deeper than the base layers 82 and 86 in alignment with the unit n + emitter layer 60. Therefore, the base resistance immediately below the unit n + emitter layer 60 can be reduced more effectively, and the base-emitter voltage difference can be reduced. In addition, p + layer 85B is formed longer than the structure shown in FIGS. 37 and 38, and can further reduce the base resistance. In addition to the effects of the structures shown in FIGS. Furthermore, the base resistance can be reduced, and the latch-up resistance of the parasitic thyristor can be improved.

[Modification 3]
41 and 42 schematically show a cross-sectional structure of the emitter region portion of a third modification of the IGBT according to the fourth embodiment of the present invention. The cross-sectional structures shown in FIGS. 41 and 42 differ from the cross-sectional structures shown in FIGS. 37 to 40 in the following points. That is, the p base layer p base layer 82 and the deeper p + layer 85C formed deeper than the unit n + emitter layer 60 are formed as buried layers in the p type base layers 82 and 86 and p type. It is formed deeper than the base layers 82 and 86. Therefore, p base layers 82 and 86 are connected at the surface of p + layer 85C in p base layer region 80. In particular, in a region where unit n + emitter layer 60 is not formed (see FIG. 42), p + layer 85C is simply provided as a buried impurity region under p base layers 82 and 86. The emitter electrode is electrically connected to the p-type base layers 82 and 86 in this region.

  Therefore, even if this p + layer 85C is formed as a buried region, the path through which holes under the unit n + emitter layer 60 flow is determined by the p + layer 85C, and the base resistance can be reduced. Further, the p + layer 85C is formed deeper than the p base layers 82 and 86, and holes flowing from the lower part of the p base layer due to a high electric field are efficiently absorbed by the p + layer 85C and transmitted to the emitter electrode 21. Can do.

  In the fourth embodiment, the width a along the radial direction of the unit n + emitter layer 60 is made wider than the arrangement pitch b. However, when the channel width can be sufficiently secured, the width a along the radial direction of the unit n + emitter layer 60 may be made smaller than the arrangement pitch b.

  As described above, according to the fourth embodiment of the present invention, in the emitter layer, the unit emitter layers are formed of island regions arranged separately from each other, and the high concentration impurity region is formed in the base layer. It is formed deeper and can absorb minority carriers efficiently, reduce the base resistance under the emitter layer, absorb minority carriers, and improve the latch-up resistance. Further, the turn-off time can be shortened. Furthermore, an island-shaped (rectangular shape) unit emitter layer is disposed, and a sufficient channel width can be ensured, and a sufficient collector-emitter current can be driven.

[Embodiment 5]
FIG. 43 schematically shows a planar layout of the lateral MOSFET according to the fifth embodiment of the present invention. Also in FIG. 43, the electrode, the insulating film, and the electrode wiring are not shown in order to simplify the drawing.

  In FIG. 43, a lateral n-channel MOS transistor includes a high-concentration n + type drain layer (first semiconductor layer region) 102 formed at the center and an n− drift layer (first semiconductor layer region) formed so as to surround the n + drain layer 102. Semiconductor region) 104, and p base layer (second semiconductor layer region) 105 formed so as to surround n − drift layer 104. The p base layer 105 includes a channel forming region 108 provided adjacent to the n − drift layer 14 and an n + source layer 106 formed in a gear shape along the outer periphery of the channel forming region 108. The n + source layer 106 includes a main body portion 106a that is integrally formed continuously, and a convex portion 106b that protrudes along a radial direction away from the drain layer 102. A source electrode contact region 107 is provided on the convex portion 106 b and on the outer periphery of the p base layer 105.

  44 schematically shows a sectional structure taken along line L44-L44 shown in FIG. In FIG. 44, the lateral n-channel MOSFET is formed on the surface of an n− layer (n− drift layer) 104 formed on the surface of a p-type substrate 110. An n + drain layer 102 is formed on the surface of the n− drift layer 104, and the n + drain layer 102 is electrically connected to the drain electrode 113. The drain electrode 113 is electrically connected to a drain electrode extraction wiring 114 formed on the first and second insulating films 111 and 112.

  In the vicinity of the source region, a p base layer 105 is formed on the surface of the n− drift layer 104, and an n + source layer 106 is formed on the surface of the p base layer 105. Adjacent to the n + source layer, a channel formation region 108 is provided on the inner periphery of the surface of the p base layer 105. A gate wiring 116 a is formed on the channel formation region 108 via a gate insulating film 115, and the gate wiring 116 a is connected to a portion of the conductive layer formed on the first insulating film 111 to form the gate wiring 116. Part of it. The gate wiring 116 is electrically connected to the gate electrode 117 that penetrates the second insulating film 112.

  A p + layer 120 is provided deeper than the n + source layer 106 and at a higher concentration than the p base layer 105. N + source layer 106 and p-type base layer 105 are commonly coupled to source electrode 121. In the cross-sectional structure shown in FIG. 44, n + source layer 106 includes a main body portion 106a and a convex portion 106b.

  In the region where only the main body portion 106a of the source layer 106 of the lateral MOSFET is disposed, the cross-sectional structure near the source region is the same as the cross-sectional structure shown in FIG. A source layer 106 is disposed in place of the emitter layer 6.

  As apparent from the cross-sectional structure shown in FIG. 44, in the lateral n-channel MOSFET, in the lateral n-channel IGBT structure, the drift layer and the drain layer have the same conductivity type, and the drain layer 102 is provided with a buffer layer. Except as otherwise noted, the structure of these IGBTs and MOSFETs is the same in the source and emitter regions.

  Therefore, as described in the first to fourth embodiments so far, in the lateral MOSFET, the high concentration p + layer 120 is deeper than the n + source layer 106 in the lateral MOSFET as well as the minority carrier emission in the IGBT emitter region. By providing it at 105, holes can be efficiently transferred to the source electrode 121. Further, the base resistance of the parasitic npn bipolar transistor formed by the n + source layer 106 / p + layer 120 and the p base layer 105 / n− layer 104 under the source electrode 121 can be reduced, and the latch-up resistance of the parasitic thyristor can be reduced. Can be improved. Therefore, the same effects as those of the lateral IGBT described in the first to fourth embodiments can be obtained.

  The cross-sectional structure of the source region is the same as the cross-sectional structure of the previous lateral IGBT. Therefore, even if the unit n + source layers are separated from each other in an island shape as the shape of the n + source layer 106. It is possible to apply the same shape of the n + source layer 106 as in the first to fourth embodiments described for the IGBT.

  As for the high-concentration p + layer 120, the p + layer 120 may be provided at a lower concentration than the p base layer 105 below the n + source layer 106, as in the first to fourth embodiments. 120 may be provided deeper than the p base layer 100. Since these are drawings having the same cross-sectional structure, the cross-sectional structure is not shown in order to prevent complication, but the structure of the high-concentration p + layer 120 is the configuration described in the first to fourth embodiments. Similarly, the parasitic thyristor resistance can be improved. In the channel formation region 108, channels are continuously formed in a circular shape, and a large drain-source current can be driven. In addition, turn-off time can be shortened by efficient release of minority carriers.

  In addition, the configuration of the present invention can be applied to other configurations such as a trench MOSFET having a trench structure with a gate structure as a lateral MOSFET. Similarly, the configuration of the present invention can be applied to a p-channel MOSFET by changing the conductivity type.

  As described above, according to the fifth embodiment of the present invention, in the lateral n-channel MOSFET, the p + layer 120 is provided in the source region below the n + source layer at a higher concentration than the p base layer 105. Can be efficiently discharged to the source electrode 121, the base resistance under the n + source layer can be reduced, the latch-up resistance of the parasitic thyristor can be improved, and the turn-off time can be shortened. Further, the channel is formed along the circumference in the channel formation region, and a large drain-source current can be driven.

[Embodiment 6]
FIG. 45 schematically shows a planar layout of the IGBT according to the sixth embodiment of the present invention. In the IGBT, a plurality of cells are arranged in order to drive a large current. In FIG. 45, IGBT cells 150a-150c are representatively shown. Each of these cells 150a and 150c has a circular shape, and includes a p + collector layer 2 formed in the center, an n buffer layer 3 placed so as to surround the collector layer 2, and an n buffer layer 3. N-drift layer 4 and p base layer 5 formed along the outer periphery of n-drift layer 4. An n + emitter layer 6 is formed in the p base layer 5 region. In the layout shown in FIG. 45, n + emitter layer 6 includes convex portion 6b and main body portion 6a that is continuously formed in a circular shape. A channel forming region 8 is formed in the p base layer region 5 in the inner peripheral portion of the main body 6a. A p base layer 5 is disposed adjacent to each of these cells 150a-150c. In the planar layout shown in FIG. 45, the high-concentration p + layer arranged in the electrode wiring, the insulating film, and the base layer is not shown as in the first to fifth embodiments. This high-concentration p + layer may be formed at a higher concentration than the p base layer 5 below the n + emitter layer 6 or deeper than the p base layer 5 as in the first embodiment. Good.

  The emitter layer 6 may be divided into unit emitter layers as in the second embodiment.

  In the structure shown in FIG. 45, an n + drain layer is provided in place of the p + collector layer, and the n buffer layer 3 is omitted, whereby a lateral n-channel MOSFET is realized and the same arrangement is used.

  By disposing these cells 150a to 150c, the channel width can be widened and a large current can be driven as compared with a configuration using an elliptical IGBT cell described later.

[Example of change]
FIG. 46 shows a modification of the planar layout of the IGBT according to the sixth embodiment of the present invention. The planar layout shown in FIG. 46 differs from the planar layout shown in FIG. 45 in the following points. That is, unit cells 150d to 150f are arranged in alignment, and each p base layer region 5 is shared between adjacent cells. Therefore, the arrangement area of these cells 150d to 150f can be reduced more than the arrangement area of the planar layout shown in FIG.

  The other configuration of the IGBT shown in FIG. 46 is the same as the configuration of the planar layout of the IGBT shown in FIG. 45, and corresponding portions are denoted by the same reference numerals, and detailed description thereof is omitted.

  Also in the planar layout shown in FIG. 46, the high-concentration p + layer only needs to be disposed below the emitter layer 6 and may be formed shallower than the p base layer, or deeper than the p base layer. May be. Further, the high concentration p + layer may have a buried structure. In addition, the emitter layer 6 may have a structure in which unit emitter layers are arranged separately, instead of a continuous structure having a main body portion 6a and a convex portion 6b.

  As shown in FIG. 45 and FIG. 46, when cells 150a-150c or 150d-150f are formed in a circular shape and arranged, as described below, when one elliptical cell is used. In comparison, the channel width can be made longer and a large current can be driven.

  Now, as shown in FIG. 47, consider an IGBT 200 having an elliptical structure. The IGBT 200 has an ap + collector layer 204 formed in an elliptical shape at the center, an n buffer layer 203 formed in an elliptical shape so as to surround the collector layer 204, and an elliptical shape so as to surround the n buffer layer 203. An n − drift layer 204 to be formed and a p base layer 205 formed in an elliptical shape so as to surround the drift layer 204 are included. An n + emitter layer 206 is provided in the p base layer 205, and a channel formation region 208 is provided in the n + emitter layer 206.

  The elliptical IGBT shown in FIG. 47 has a track shape with a straight portion and a circumferential portion. The cross-sectional structure in the track-shaped (elliptical) straight portion is the same as the cross-sectional structure shown in the first embodiment of the present invention (the p + emitter layer may or may not be provided). Consider, for example, that a circular cell shown in FIG. 46 is arranged with the same layout area as the elliptical IGBT shown in FIG. In this case, as shown in FIG. 48, when cells 150d-150f are arranged, the circumferential portion of channel forming region 8 of cells 150d and 150f is the circumferential portion of the channel forming region of the elliptical IGBT shown in FIG. Will be the same. Now, let CL be the distance between the central portions of the p + collector layers 2 of adjacent cells. In each of the cells 150a to 150f, r is a distance from the central portion of the p + collector layer 2 to the central portion of the channel formation region 8. The total length of the channel regions of the cells 150d and 150e corresponding to the channel length CL of the elliptical IGBT is expressed by the following equation.

2 · π · r · (1/4) · 2 = π · r
Therefore, if the distance between the centers of the p + collector layers 2 of the adjacent cells (150d and 150e) is smaller than 3 · r, the following relational expression is obtained.

CL <3 · r <π · r
The above relational expression is realized by making the distance between the channel formation regions of adjacent cells smaller than r. The channel formation region is formed in the base layer region at the outer periphery of the cell, and this condition is easily satisfied.

  Therefore, the unit cell 150d-150f (or 150a-150c) can be arranged longer than the elliptical IGBT shown in FIG. 47, so that the length along the circumference of the channel forming region 8 can be increased. Accordingly, the channel width with respect to the current flowing from the p + collector layer to the emitter layer can be increased, and a larger current can be driven.

  FIG. 49 is a diagram showing the characteristics of the collector-emitter current ICE when the collector-emitter voltage VCE is applied in a state where a constant gate-emitter voltage VGE is applied to the elliptical IGBT shown in FIG. is there. The horizontal axis indicates the collector-emitter voltage VCE in the unit V, and the vertical axis indicates the collector-emitter current ICE in the unit A. The measurement temperature is room temperature. However, a high-concentration semiconductor layer (p + layer) is not provided in the base layer in the elliptical IGBT.

  As shown in FIG. 49, in the case of an IGBT having an elliptic structure, when the collector-emitter voltage VCE is gradually increased, the collector-emitter current ICE also increases accordingly. However, when the collector-emitter voltage VCE is approximately 6 V, when the collector-emitter current ICE reaches about 0.2 A, the collector-emitter voltage VCE is increased from this region even if the collector-emitter voltage VCE is increased. The emitter current ICE is almost saturated, and even if the collector-emitter voltage VCE is increased, the collector-emitter current ICE is not sufficiently increased. Even in the region where the collector-emitter voltage VCE rises from 0V to 6V, the collector-emitter current ICE gradually rises and the on-resistance (VCE / ICE) becomes high. This is because the p + layer (p + emitter layer) is not provided in the base layer in the elliptical structure.

  FIG. 50 shows a collector when a collector-emitter voltage VCE is applied in a state where a constant gate-emitter voltage VGE is applied in a circular IGBT (see FIG. 48 or FIG. 46) structure according to the present invention. -Shows the ICE characteristics between emitters. In FIG. 50, the horizontal axis represents the collector-emitter VCE (unit V), and the vertical axis represents the collector-emitter current ICE (unit A). The measurement temperature is room temperature.

  As shown in FIG. 50, when a cell having a circular structure is arranged, when the collector-emitter voltage VCE is gradually increased, the collector-emitter current is about 0.4 A in the vicinity of voltage 6.0 V. From the beginning, the collector-emitter current shows a saturation tendency. However, in this case, the collector-emitter current ICE is about twice as large as the elliptical IGBT shown in FIG. Even in the region where the collector-emitter voltage VCE rises from 0V to 6V, the rising gradient can be increased and the on-resistance (VCE-ICE) can be reduced. These are due to the increased total channel width and reduced base resistance. Even if the amount of current increases, the p + layer is provided below the emitter layer, and the parasitic bipolar transistor in the emitter region can be prevented from conducting, and the latch-up resistance of the parasitic thyristor is improved. I can make it.

  As described above, according to the sixth embodiment of the present invention, a plurality of circular IGBTs are provided as cells, and the length of the channel region is increased compared to a configuration using one elliptical IGBT. Accordingly, the channel width can be increased accordingly, and a large amount of collector-emitter current can flow. Further, the same effects as those of the first to fourth embodiments can be obtained.

[Embodiment 7]
FIG. 51 schematically shows a cross-sectional structure of a semiconductor device (lateral n-channel IGBT) according to the seventh embodiment of the present invention. The planar (surface) layout of the IGBT shown in FIG. 51 is substantially the same as the planar layout of the IGBT shown in FIG. In the IGBT shown in FIG. 51, buried insulating film 310 is provided between n − layer 4 and semiconductor substrate 300. Since this semiconductor substrate 300 is separated from the n − layer 4, it may be either p-type or n-type conductivity type.

  The other configuration of the IGBT shown in FIG. 51 is the same as that of the IGBT shown in FIG. 2, and the corresponding parts are denoted by the same reference numerals, and detailed description thereof is omitted.

  A structure in which a buried insulating film 310 is provided on the surface of the semiconductor substrate 300 and a transistor is formed on the buried insulating film 310 is generally called an SOI (silicon-on-insulator) structure. be called. On the other hand, as shown in FIG. 2, the buried insulating film 310 is not provided, and the n-layer 4 and the p-type semiconductor substrate (10) are separated by a PN junction formed therebetween. Called structure. By using the buried insulating film 310, the n− layer 4 and the substrate 300 can be electrically separated more reliably than in the junction isolation structure, and a depletion layer is generated only in the n− layer. Can operate at high speed.

  The other configuration of the IGBT shown in FIG. 51 is the same as that of the IGBT shown in FIG. 2, and the corresponding parts are denoted by the same reference numerals, and detailed description thereof is omitted.

  FIG. 52 is a diagram showing a turn-off waveform at the time of the resistance load switching operation of the IGBT. In FIG. 52, the horizontal axis represents the turn-off time (unit: second), and the vertical axis represents the collector-emitter voltage VCE (unit × 100 V) and the collector-emitter current ICE (unit A). Curve I shows the collector-emitter voltage of the IGBT having the dielectric isolation structure (FIG. 51), and curve II shows the collector-emitter voltage VCE of the junction isolation IGBT shown in FIG. Curve III shows the collector-emitter current ICE in the dielectric isolation structure, and curve IV shows the collector-emitter current of the junction isolation structure IGBT.

  As shown in FIG. 52, the fall time tf (the time required for the collector-emitter current IGE to decrease from 90% to 10% of the maximum value) of the junction isolation type IGBT is close to 1 μs, and therefore the switching speed is slow. Accordingly, the switching loss becomes relatively large. On the other hand, in the case of the dielectric separation structure, the fall time tf is about 0.5 μs, and the switching speed is fast, and accordingly the switching speed loss can be further reduced. Further, in the turn-off waveform at the time of the resistive load switching operation, the absolute value of the increase rate of the VCE waveform (curve I) is almost the same as the absolute value of the decrease rate of the waveform (curve III) indicating the collector-emitter current ICE. It can be clearly seen that the switching operation is performed.

  Therefore, it can be clearly seen that the switching operation is performed at a higher speed when the dielectric isolation structure is used than when the junction isolation structure is used.

  However, also in the junction separation, during this switching period, at the time of turn-off, the collector-emitter voltage VCE suddenly rises and shifts to the off state (curve II), and the collector-emitter current ICE also suddenly decreases. Can be seen (curve IV). Therefore, also in the junction isolation structure, by using the p + layer and forming the emitter layer in a ring shape, as is apparent from the characteristics of the curves II and IV, the conventional elliptic structure IGBT is used to form the p + layer. 52, the p base layer is simply used, and the n emitter layer can be made faster than a structure in which the n emitter layer is formed in a ring shape (in the case of the conventional structure, the turn-off time is indicated by an arrow in FIG. 52). ).

  FIG. 53 is a diagram showing a current distribution, a voltage distribution, and a depletion layer region boundary during resistance load switching turn-off (10.6 μs) of the junction isolation structure lateral IGBT according to the first embodiment. The current distribution is indicated by a solid line, the voltage distribution is indicated by a broken line, and the depletion layer region boundary line is indicated by a one-dot chain line.

  As shown in FIG. 53, in the case of the junction isolation structure lateral IGBT, the depletion layer spreading from the emitter side is distributed not only on the collector side (region near the p-type collector layer 2) but also in the p-type substrate 10. doing. For this reason, both the potential distribution (indicated by a broken line) and the current distribution (indicated by a solid line) are distributed in the p-type substrate 10 region. Therefore, depletion on the collector side is suppressed, and the collector-emitter voltage VCE rises relatively slowly. As a result, at the time of turn-off, the decrease in the collector-emitter current ICE is also relatively gradual, and the fall time tf is accordingly delayed.

  FIG. 54 is a sectional view showing the hole distribution at the time of resistance load switching turn-off (10.6 μs) of the junction isolation structure lateral IGBT according to the first embodiment of the present invention. In this junction isolation structure lateral IGBT, as shown in FIG. 53, since depletion from the emitter side to the collector side is suppressed, many holes are distributed in the n− layer 4 and the p-type substrate 10. That is, since many holes are distributed in the n− layer 4 and the p-type substrate 10, even if a p + layer is provided, the holes distributed in the n− layer 4 and the p-type substrate 10 disappear. This means that it takes time until the falling time tf becomes relatively slow.

  FIG. 55 is a diagram showing a hole (hole) distribution, electron distribution, and hole / electron concentration distribution in an equilibrium state at the time of resistance load switching turn-off (10.6 μs) of a junction isolation structure lateral IGBT. 4 shows the distribution of each carrier from the collector side to the emitter side at a constant depth. In FIG. 55, the curve V shows the distribution of holes, the curve VI shows the distribution of electrons, and the curve VII shows the distribution of electron / hole concentration in the equilibrium state.

  As shown in FIG. 53, depletion from the emitter side to the collector side is suppressed in the junction isolation structure lateral IGBT. Therefore, in the n-layer where the depletion layer is not spread, excess holes and excess electrons that are higher than the concentration in the equilibrium state are distributed. Therefore, a large amount of these excess holes and excess electrons are distributed in the n − layer, so that it takes a long time until these excess holes and excess electrons disappear from the n − layer 4. For this reason, there is a limit to shortening the fall time tf.

  56 is a diagram showing a potential distribution, a current distribution, and a depletion layer region boundary line at the time of resistance load switching turn-off (10.6 μs) of the dielectric isolation structure lateral IGBT, and corresponds to the cross-sectional view shown in FIG. In FIG. 56, the solid line indicates the current distribution, the broken line indicates the potential distribution, and the alternate long and short dash line indicates the depletion layer region boundary line.

  As shown in FIG. 56, in the case of the dielectric isolation structure lateral IGBT, there is a buried insulating film 310 between the n− layer 4 and the p-type substrate 300. Therefore, in the buried insulating film 310, although the potential distribution exists in parallel along the surface, the depletion layer extending from the emitter side does not extend to the p-type substrate 300, and the collector side in the n− layer 4 (The insulating film originally corresponds to the depletion layer region). Therefore, in p-type substrate 300, there is no current distribution (shown by a solid line) and potential distribution (shown by a broken line). For this reason, since the depletion toward the collector side proceeds, the collector-emitter voltage also rises steeply, the corresponding collector-emitter current ICE also rises steeply, and the fall time tf becomes shorter.

  FIG. 57 is a diagram showing a hole distribution (shown by a solid line) at the time of resistance load switching turn-off (10.6 μs) of the dielectric isolation structure lateral IGBT. The cross-sectional structure corresponds to the cross-sectional structure shown in FIG. As shown in FIG. 57, in the dielectric isolation structure lateral IGBT, depletion from the emitter side to the collector side is promoted as shown in FIG. 56, so that the number of holes distributed in the n − layer 4 is small. Therefore, the time until the holes distributed in the n − layer 4 disappear is shortened, and the falling time tf is shortened.

  FIG. 58 is a diagram showing a hole distribution, an electron distribution, and a hole / electron concentration distribution in an equilibrium state at the time of resistance load switching turn-off (10.6 μs) in this dielectric isolation structure lateral IGBT. The horizontal axis indicates distance, and the vertical axis indicates density. FIG. 58 shows each distribution from the collector side to the emitter side at a constant depth in the n − layer 4. A curve X represents a hole distribution, a curve XI represents an electron distribution, and a curve XII represents an electron / hole concentration distribution in an equilibrium state.

  As shown in FIG. 56, in the dielectric isolation structure lateral IGBT, since depletion from the emitter side to the collector side is promoted, there are few regions where the depletion layer does not spread in the n − layer 4. For this reason, as shown in FIG. 58, in the n − layer 4, the amount of holes and / or electrons (excess holes, excess electrons) exceeding the concentration in the equilibrium state is small. Therefore, since the amount of excess holes and excess electrons in the n − layer 4 is small, the time until the excess holes and excess electrons disappear is shortened, and as a result, the fall time tf can be shortened.

  Therefore, by utilizing the dielectric isolation structure in the seventh embodiment of the present invention, in addition to the improvement in the collector-emitter current ICE characteristics in the IGBT and MOSFET described in the first embodiment, the fall time tf Shortening can also be realized.

  The dielectric isolation structure in the seventh embodiment can be applied to the lateral MOS in the previous fifth embodiment, and a p-channel IGBT and a p-channel lateral MOSFET can also be applied. Further, the structure of the lateral MOSFET can be similarly applied to, for example, a MOSFET having a trench gate structure.

  As described above, according to the seventh embodiment of the present invention, the transistor element has a dielectric isolation structure, and in addition to the effects of the first to sixth embodiments, the fall time is further shortened. And a high-speed switching operation can be realized.

  The present invention can be applied to a power switching element that performs power conversion / control. The power transistor may be provided as a single unit, or may be integrated with another controller as an intelligent power device.

  1 lateral IGBT, 2 p collector layer, 3 n buffer layer, 4 n− layer, 5 p base layer, 6 n + emitter layer, 6a body portion, 6b convex portion, 7 emitter contact region, 20 p + layer, 32 gate electrode extraction Wiring, 17 gate electrode, 16, 16a gate electrode wiring, 35, 40, 45 p + layer, 60 unit emitter layer, 62 p + layer, 64 p + layer, 70 base layer region, 74 p + layer, 72 p base layer, 75A, 75B, 75C p + layer, 76p base layer, 84p + layer, 82p base layer, 85A, 85B, 85C p + layer, 100 lateral MOSFET, 102 n + drain layer, 104 n− layer, 106 n + source layer, 106a body part 106b Protruding portion, 108 channel forming region, 105 p base layer, 107 source electrode contact region 120 p + layer, 10, 110 p-type substrate, 150a-150f cells, 300 semiconductor substrate 310 buried insulating film.

Claims (3)

A semiconductor substrate;
A semiconductor region formed on the surface of the semiconductor substrate;
A first semiconductor layer region provided on the surface of the semiconductor region and coupled to the first electrode;
A second semiconductor layer region having a conductivity type different from that of the ring-shaped first semiconductor layer region disposed in the semiconductor region so as to be separated from the first semiconductor layer region and to surround the first semiconductor layer region; ,
The second semiconductor layer region having a plurality of unit regions having a plurality of rectangular-like shapes, which are separated from each other in the second semiconductor layer region and arranged at predetermined intervals, each having a width larger than the predetermined interval; A third semiconductor layer region having a different conductivity type;
Before SL until the second semiconductor layer region surface in the region between the a region adjacent Ru is disposed on the second semiconductor layer region third semiconductor layer region under side of the third semiconductor layer area A high concentration semiconductor layer having the same conductivity type as the second semiconductor layer region having a higher concentration than the second semiconductor layer region,
A gate electrode layer forming a channel for charge transfer between the first semiconductor layer region and the third semiconductor layer region on the surface of the second semiconductor layer region ;
A semiconductor device comprising: the third semiconductor layer region; and a second electrode layer in contact with the high concentration semiconductor layer .   The semiconductor device according to claim 1, wherein the high-concentration semiconductor layer is deeper than the second semiconductor layer region.   The semiconductor device according to claim 1, further comprising an insulating layer formed between the semiconductor region and the semiconductor substrate.

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