JP5385967B2 - Wiring board and manufacturing method thereof - Google Patents

Description

  The present invention relates to a wiring board and a manufacturing method thereof.

  Patent Document 1 discloses a wiring board having a stack structure in which via conductors are stacked on through-hole conductors.

  Patent Document 2 discloses a wiring board having a stack structure in which a plurality of via conductors are stacked.

Japanese Patent Laid-Open No. 2001-210952 JP 2003-31952 A

  In the wiring board described in Patent Document 1 or Patent Document 2, a stack structure is formed due to the difference between the thermal expansion coefficient of the interlayer insulating layer (for example, resin) and the thermal expansion coefficient of the via conductor (for example, metal). It is considered that a large stress is likely to be generated in the via conductor (in particular, the via conductor close to the core substrate). Such stress is considered to increase as the number of floors (layers) of the stack structure increases.

  The present invention has been made in view of such circumstances, and an object thereof is to improve the reliability of electrical connection in a wiring board.

The wiring board according to the present invention is
A core substrate having a first surface and a second surface;
A first stacked portion formed on the first surface of the core substrate and including at least one pair of interlayer insulating layers and conductor layers;
A second stacked portion formed on the second surface of the core substrate and including at least one pair of interlayer insulating layers and conductor layers;
A wiring board having
The core substrate is made of a material having higher heat resistance than a material constituting any of the interlayer insulating layer of the first stacked unit and the interlayer insulating layer of the second stacked unit,
A first planar conductor pattern is formed on the first surface of the core substrate, and a second planar conductor pattern is formed on the second surface of the core substrate,
A plurality of first via conductors constituting a conductor group and a second via conductor not constituting the conductor group are formed on the core substrate, and a first interlayer insulating layer in the lowermost layer of the first stacked portion includes a first via conductor. 3 via conductors are formed, a fourth via conductor is formed in the lowermost interlayer insulating layer of the second stacked portion,
The first via conductor and the second via conductor have substantially the same thickness.
Each of the first via conductors constituting the conductor group is connected to the first planar conductor pattern having one end and the second planar conductor pattern having the other end common,
One end of the third via conductor is connected to a region of the first planar conductor pattern defined by an outer edge of one end of each first via conductor constituting the conductor group, and one end of the fourth via conductor. Is connected to a region of the second planar conductor pattern defined by the outer edge of the other end of each first via conductor constituting the conductor group.
The wiring board according to the present invention is
A core substrate having a first surface and a second surface;
A first stacked portion formed on the first surface of the core substrate and including at least one pair of interlayer insulating layers and conductor layers;
A second stacked portion formed on the second surface of the core substrate and including at least one pair of interlayer insulating layers and conductor layers;
A wiring board having
The core substrate, the lowermost interlayer insulating layer of the first stacked portion, and the lowermost interlayer insulating layer of the second stacked portion are interlayer insulating layers other than the lowermost interlayer insulating layer in the first stacked portion. And a material having higher heat resistance than a material constituting any of the interlayer insulating layers other than the lowermost interlayer insulating layer in the second stacked portion,
A first planar conductor pattern is formed on the first surface of the core substrate, and a second planar conductor pattern is formed on the second surface of the core substrate,
A plurality of first via conductors constituting a conductor group and a second via conductor not constituting the conductor group are formed on the core substrate, and a first interlayer insulating layer in the lowermost layer of the first stacked portion includes a first via conductor. 3 via conductors are formed, a fourth via conductor is formed in the lowermost interlayer insulating layer of the second stacked portion,
The first via conductor and the second via conductor have substantially the same thickness.
Each of the first via conductors constituting the conductor group is connected to the first planar conductor pattern having one end and the second planar conductor pattern having the other end common,
One end of the third via conductor is connected to a region of the first planar conductor pattern defined by an outer edge of one end of each first via conductor constituting the conductor group, and one end of the fourth via conductor. Is connected to a region of the second planar conductor pattern defined by the outer edge of the other end of each first via conductor constituting the conductor group.

  It is preferable that each of the first via conductors, the third via conductors, and the fourth via conductors constituting the conductor group have substantially the same thickness.

Each of the first stacked unit and the second stacked unit includes at least four sets of interlayer insulating layers and conductor layers,
On the third via conductor, via conductors formed in the interlayer insulating layer of the first stacked portion are stacked, whereby the first stacked portion includes first via conductors having four or more stages. A stack structure is formed,
On the fourth via conductor, a via conductor formed in the interlayer insulating layer of the second stacked unit is stacked, so that the second stacked unit includes a second layer composed of four or more stages of via conductors. It is preferred that a stack structure is formed.

  Via conductors in all layers of the first stacked portion including the third via conductor constitute a first stack structure, and via conductors in all layers of the second stacked portion including the fourth via conductor are in a second stack structure. It is preferable to constitute.

  It is preferable that all via conductors constituting the first stack structure have substantially the same thickness, and all via conductors constituting the second stack structure have substantially the same thickness.

Each of the first via conductors constituting the conductor group is composed of plating,
A first conductor layer composed of a first metal foil and a first plating is formed on the first surface of the core substrate,
A second conductor layer composed of a second metal foil and a second plating is formed on the second surface of the core substrate,
The plating that constitutes the first via conductor, the first plating, and the second plating are performed by filling an opening that penetrates the core substrate, the first metal foil, and the second metal foil. Are preferably formed integrally with each other.

The opening that penetrates the core substrate, the first metal foil, and the second metal foil includes a first opening that penetrates the first metal foil and a second opening that penetrates the second metal foil. And a third opening that penetrates the core substrate,
The third opening is tapered so as to become thinner from the first surface toward the second surface,
The width of the second opening is preferably smaller than the width of the third opening on the second surface.

  The core substrate is preferably made of a material having higher heat resistance than a material constituting any of the interlayer insulating layer of the first stacked portion and the interlayer insulating layer of the second stacked portion.

The core substrate is made of FR-5 material,
It is preferable that the interlayer insulating layer of the first stacked unit and the interlayer insulating layer of the second stacked unit are each made of FR-4 material.

Each of the core substrate, the lowermost interlayer insulating layer of the first stacked portion, and the lowermost interlayer insulating layer of the second stacked portion is made of FR-5 material,
The interlayer insulating layer other than the lowermost interlayer insulating layer in the first stacked portion and the interlayer insulating layer other than the lowermost interlayer insulating layer in the second stacked portion are each made of FR-4 material. Is preferable.

  Formed in the lowermost interlayer insulating layer of the first laminated portion, one end of the first planar conductor pattern in a region defined by the outer edge of one end of each first via conductor constituting the conductor group It is preferable to have a plurality of third via conductors to be connected.

  A region formed in the lowermost interlayer insulating layer of the second stacked portion and having one end defined by the outer edge of the other end of each first via conductor constituting the conductor group of the second planar conductor pattern It is preferable to have a plurality of the fourth via conductors connected to each other.

The wiring board according to the present invention is
A core substrate having a first surface and a second surface;
A first stacked portion formed on the first surface of the core substrate and including at least one pair of interlayer insulating layers and conductor layers;
A second stacked portion formed on the second surface of the core substrate and including at least one pair of interlayer insulating layers and conductor layers;
A wiring board having
The core substrate is made of a material having higher heat resistance than a material constituting any of the interlayer insulating layer of the first stacked unit and the interlayer insulating layer of the second stacked unit,
A first via conductor formed on the core substrate; a third via conductor formed on at least one interlayer insulating layer of the first stacked portion; and at least one interlayer insulating layer of the second stacked portion. The fourth via conductor is stacked,
A second via conductor not stacked is formed on the core substrate;
Each of the first via conductor and the second via conductor has substantially the same thickness as each other,
The first via conductor is thicker than any of the stacked third and fourth via conductors.
The wiring board according to the present invention is
A core substrate having a first surface and a second surface;
A first stacked portion formed on the first surface of the core substrate and including at least one pair of interlayer insulating layers and conductor layers;
A second stacked portion formed on the second surface of the core substrate and including at least one pair of interlayer insulating layers and conductor layers;
A wiring board having
The core substrate, the lowermost interlayer insulating layer of the first stacked portion, and the lowermost interlayer insulating layer of the second stacked portion are interlayer insulating layers other than the lowermost interlayer insulating layer in the first stacked portion. And a material having higher heat resistance than a material constituting any of the interlayer insulating layers other than the lowermost interlayer insulating layer in the second stacked portion,
A first via conductor formed on the core substrate; a third via conductor formed on at least one interlayer insulating layer of the first stacked portion; and at least one interlayer insulating layer of the second stacked portion. The fourth via conductor is stacked,
A second via conductor not stacked is formed on the core substrate;
Each of the first via conductor and the second via conductor has substantially the same thickness as each other,
The first via conductor is thicker than any of the stacked third and fourth via conductors.

Each of the first stacked unit and the second stacked unit includes at least four sets of interlayer insulating layers and conductor layers,
The first stacked portion is formed with a first stack structure composed of four or more third via conductors,
It is preferable that a second stack structure including four or more stages of fourth via conductors is formed in the second stacked portion.

  It is preferable that the third via conductors in all layers of the first stacked portion constitute a first stack structure, and the fourth via conductors in all layers of the second stacked portion constitute a second stack structure.

  All the third via conductors constituting the first stack structure have substantially the same thickness, and all the fourth via conductors constituting the second stack structure have substantially the same thickness. Is preferred.

The first via conductor is composed of plating,
A first conductor layer composed of a first metal foil and a first plating is formed on the first surface of the core substrate,
A second conductor layer composed of a second metal foil and a second plating is formed on the second surface of the core substrate,
The plating that constitutes the first via conductor, the first plating, and the second plating are performed by filling an opening that penetrates the core substrate, the first metal foil, and the second metal foil. Are preferably formed integrally with each other.

The opening that penetrates the core substrate, the first metal foil, and the second metal foil includes a first opening that penetrates the first metal foil and a second opening that penetrates the second metal foil. And a third opening that penetrates the core substrate,
The third opening is tapered so as to become thinner from the first surface toward the second surface,
The width of the second opening is preferably smaller than the width of the third opening on the second surface.

  The core substrate, the lowermost interlayer insulating layer of the first stacked portion, and the lowermost interlayer insulating layer of the second stacked portion are interlayer insulating layers other than the lowermost interlayer insulating layer in the first stacked portion. It is preferable that the second laminated portion is made of a material having higher heat resistance than a material constituting any of the interlayer insulating layers other than the lowermost interlayer insulating layer.

  It is preferable to have a plurality of third via conductors stacked on the first via conductor in the lowermost interlayer insulating layer of the first stacked portion.

  It is preferable to have a plurality of fourth via conductors stacked on the first via conductor in the lowermost interlayer insulating layer of the second stacked portion.

A method for manufacturing a wiring board according to the present invention includes:
A method of manufacturing a wiring board comprising: a core substrate; and at least one set of interlayer insulating layers and conductor layers laminated on both surfaces of the core substrate,
A core substrate made of a material having higher heat resistance than the material constituting the interlayer insulating layer and having a first surface and a second surface;
A first planar conductor pattern located on the first surface of the core substrate, a second planar conductor pattern located on the second surface of the core substrate, respectively, penetrating the core substrate, A conductor group composed of a plurality of first via conductors having one end connected to the common first planar conductor pattern and the other end connected to the common second planar conductor pattern; Forming a second via conductor having substantially the same thickness as the via conductor and not constituting the conductor group;
Forming a first interlayer insulating layer on the first surface and the first planar conductor pattern of the core substrate;
A third via that penetrates through the first interlayer insulating layer and has one end connected to a region defined by an outer edge of one end of each first via conductor constituting the conductor group of the first planar conductor pattern. Forming a conductor;
Forming a second interlayer insulating layer on the second surface and the second planar conductor pattern of the core substrate;
A fourth connected to a region penetrating the second interlayer insulating layer and having one end defined by the outer edge of the other end of each first via conductor constituting the conductor group of the second planar conductor pattern; Forming via conductors;
Forming a first upper conductor layer electrically connected to the first planar conductor pattern via the third via conductor on the first interlayer insulating layer;
Forming a second upper conductor layer electrically connected to the second planar conductor pattern via the fourth via conductor on the second interlayer insulating layer;
including.
A method for manufacturing a wiring board according to the present invention includes:
A method of manufacturing a wiring board comprising: a core substrate; and at least one set of interlayer insulating layers and conductor layers laminated on both surfaces of the core substrate,
A core substrate made of a material having higher heat resistance than a material constituting the interlayer insulating layer other than the first interlayer insulating layer and the second interlayer insulating layer included in the interlayer insulating layer, and having a first surface and a second surface. To prepare,
A first planar conductor pattern located on the first surface of the core substrate, a second planar conductor pattern located on the second surface of the core substrate, respectively, penetrating the core substrate, A conductor group composed of a plurality of first via conductors having one end connected to the common first planar conductor pattern and the other end connected to the common second planar conductor pattern; Forming a second via conductor having substantially the same thickness as the via conductor and not constituting the conductor group;
Forming the first interlayer insulating layer on the first surface and the first planar conductor pattern of the core substrate;
A third via that penetrates through the first interlayer insulating layer and has one end connected to a region defined by an outer edge of one end of each first via conductor constituting the conductor group of the first planar conductor pattern. Forming a conductor;
Forming the second interlayer insulating layer on the second surface and the second planar conductor pattern of the core substrate;
A fourth connected to a region penetrating the second interlayer insulating layer and having one end defined by the outer edge of the other end of each first via conductor constituting the conductor group of the second planar conductor pattern; Forming via conductors;
Forming a first upper conductor layer electrically connected to the first planar conductor pattern via the third via conductor on the first interlayer insulating layer;
Forming a second upper conductor layer electrically connected to the second planar conductor pattern via the fourth via conductor on the second interlayer insulating layer;
including.

A method for manufacturing a wiring board according to the present invention includes:
A method of manufacturing a wiring board comprising: a core substrate; and at least one set of interlayer insulating layers and conductor layers laminated on both surfaces of the core substrate,
A core substrate made of a material having higher heat resistance than the material constituting the interlayer insulating layer and having a first surface and a second surface;
A first planar conductor pattern located on the first surface of the core substrate; a second planar conductor pattern located on the second surface of the core substrate; and one end penetrating the core substrate. Has a first via conductor connected to the first planar conductor pattern and the other end connected to the second planar conductor pattern, respectively, and a thickness substantially the same as the first via conductor, Forming a first via conductor pattern and a second via conductor not connected to any of the second planar conductor pattern;
Forming a first interlayer insulating layer on the first surface and the first planar conductor pattern of the core substrate;
Forming a third via conductor that is narrower than the first via conductor, penetrates the first interlayer insulating layer, and is connected to the first planar conductor pattern;
Forming a second interlayer insulating layer on the second surface and the second planar conductor pattern of the core substrate;
Forming a fourth via conductor that is narrower than the first via conductor, penetrates the second interlayer insulating layer, and is connected to the second planar conductor pattern;
Forming a first upper conductor layer electrically connected to the first planar conductor pattern via the third via conductor on the first interlayer insulating layer;
Forming a second upper conductor layer electrically connected to the second planar conductor pattern via the fourth via conductor on the second interlayer insulating layer;
including.
A method for manufacturing a wiring board according to the present invention includes:
A method of manufacturing a wiring board comprising: a core substrate; and at least one set of interlayer insulating layers and conductor layers laminated on both surfaces of the core substrate,
A core substrate made of a material having higher heat resistance than a material constituting the interlayer insulating layer other than the first interlayer insulating layer and the second interlayer insulating layer included in the interlayer insulating layer, and having a first surface and a second surface. To prepare,
A first planar conductor pattern located on the first surface of the core substrate; a second planar conductor pattern located on the second surface of the core substrate; and one end penetrating the core substrate. Has a first via conductor connected to the first planar conductor pattern and the other end connected to the second planar conductor pattern, respectively, and a thickness substantially the same as the first via conductor, Forming a first via conductor pattern and a second via conductor not connected to any of the second planar conductor pattern;
Forming the first interlayer insulating layer on the first surface and the first planar conductor pattern of the core substrate;
Forming a third via conductor that is narrower than the first via conductor, penetrates the first interlayer insulating layer, and is connected to the first planar conductor pattern;
Forming the second interlayer insulating layer on the second surface and the second planar conductor pattern of the core substrate;
Forming a fourth via conductor that is narrower than the first via conductor, penetrates the second interlayer insulating layer, and is connected to the second planar conductor pattern;
Forming a first upper conductor layer electrically connected to the first planar conductor pattern via the third via conductor on the first interlayer insulating layer;
Forming a second upper conductor layer electrically connected to the second planar conductor pattern via the fourth via conductor on the second interlayer insulating layer;
including.

  According to the present invention, it is possible to improve the reliability of electrical connection in a wiring board.

It is sectional drawing which shows the wiring board which concerns on Embodiment 1 of this invention. It is a figure which shows arrangement | positioning of the through-hole and stack structure of a wiring board shown in FIG. It is sectional drawing which expands and shows a part of FIG. It is a figure which shows the positional relationship of the 1st planar conductor pattern in the wiring board shown in FIG. 1, a conductor group, and a 3rd via conductor. It is a figure which shows the positional relationship of the 2nd planar conductor pattern in the wiring board shown in FIG. 1, a conductor group, and a 4th via conductor. It is a figure which shows the via conductor of the conductor group which comprises a stack structure with the wiring board shown in FIG. It is a figure which shows the protrusion amount of a core material about the via conductor which comprises a stack structure with the wiring board shown in FIG. It is a figure which shows the wiring board (comparative example) which has a stack structure without a conductor group. It is a graph which shows the result of having simulated about the stress concerning a 6 layer, 8 layer, and 10 layer wiring board. It is a figure which shows the simulation result shown to FIG. 8A by a numerical value. It is a figure which shows the result of having simulated about the crack occupation rate in each layer of 8 layer goods and 10 layer goods. It is a figure which shows the result of having performed simulation about the wiring board which has a core board | substrate of a different material. It is a graph which shows the simulation result shown to FIG. 10A. It is a flowchart which shows the manufacturing method of the wiring board which concerns on Embodiment 1 of this invention. FIG. 12 is a diagram for explaining a step of preparing a core substrate in the method for manufacturing a wiring board shown in FIG. 11. It is a figure for demonstrating the 1st process of forming a 1st via conductor and a 2nd via conductor in the core board prepared at the process of Drawing 12A, and forming a conductor layer on a core board. It is a figure for demonstrating the 2nd process after the process of FIG. 12B. It is a figure for demonstrating the 3rd process after the process of FIG. 12C. FIG. 12 is a diagram for explaining a first step of forming a first-stage stacked portion in the method for manufacturing a wiring board shown in FIG. 11. It is a figure for demonstrating the 2nd process after the process of FIG. 13A. It is a figure for demonstrating the 3rd process after the process of FIG. 13B. It is a figure for demonstrating the 4th process after the process of FIG. 13C. FIG. 12 is a diagram for explaining a process of forming a second stacked portion in the method for manufacturing the wiring board shown in FIG. 11. FIG. 12 is a diagram for explaining a step of forming a third layered portion in the method for manufacturing the wiring board shown in FIG. 11. FIG. 12 is a diagram for explaining a first step of forming a fourth layer stack and a through hole in the method for manufacturing the wiring board shown in FIG. 11. It is a figure for demonstrating the 2nd process after the process of FIG. It is a figure for demonstrating the 3rd process after the process of FIG. It is sectional drawing which shows the wiring board which concerns on Embodiment 2 of this invention. It is sectional drawing which expands and shows a part of FIG. It is a figure which shows the positional relationship of the 1st via conductor of the core board | substrate in the wiring board shown in FIG. 19, and the 3rd via conductor stacked on it. It is a figure which shows the positional relationship of the 1st via conductor of the core board | substrate in the wiring board shown in FIG. 19, and the 4th via conductor stacked on it. In another embodiment of the present invention, an opening is formed at the boundary between the bottom surface of the via conductor constituting the conductor group of the core substrate and the conductor layer on the core substrate connected to the bottom surface to connect the two platings. It is a figure which shows a wiring board. In another embodiment of the present invention, a wiring board having an opening formed at the boundary between a bottom surface of a thick via conductor of a core substrate and a conductor layer on the core substrate connected to the bottom surface to connect the plating of the two is shown. FIG. It is a figure for demonstrating the 1st process of the manufacturing method of the wiring board shown to FIG. 22A. It is a figure for demonstrating the 2nd process after the process of FIG. 23A. It is a figure for demonstrating the 3rd process after the process of FIG. 23B. In the wiring board according to another embodiment of the present invention, the wiring board is formed at the boundary between the bottom surface of the via conductor constituting the conductor group of the core substrate and the conductor layer on the core substrate connected to the bottom surface, and connects the two platings. It is a figure which shows the example whose width | variety of an opening part is smaller than the width | variety of the bottom face of the via conductor. In the wiring board according to another embodiment of the present invention, the width of the opening formed at the boundary between the bottom surface of the thick via conductor of the core substrate and the conductor layer on the core substrate connected to the bottom surface to connect the plating of both. FIG. 5 is a diagram showing an example in which the width of the bottom surface of the thick via conductor is smaller. It is a figure which shows the 1st example of the opening part which connects metal plating in the example of FIG. 24A or FIG. 24B. It is a figure which shows the 2nd example of the opening part which connects metal plating in the example of FIG. 24A or FIG. 24B. In the wiring board which concerns on other embodiment of this invention, it is a figure which shows the positional relationship of a 1st planar conductor pattern, a conductor group, and a 3rd via conductor. In the wiring board which concerns on other embodiment of this invention, it is a figure which shows the positional relationship of a 2nd planar conductor pattern, a conductor group, and a 4th via conductor. In the wiring board which concerns on other embodiment of this invention, it is a figure which shows the example whose number of the 1st via | veer conductors which comprise a conductor group is three. In the wiring board which concerns on other embodiment of this invention, it is a figure which shows the example whose number of the 1st via | veer conductors which comprise a conductor group is four. In the wiring board which concerns on other embodiment of this invention, it is a figure which shows the example in which the number of the via conductors stacked only on one side of the conductor group of a core board | substrate is plural. In the wiring board which concerns on other embodiment of this invention, it is a figure which shows the example in which the number of the via conductors each stacked on both sides of the conductor group of a core board | substrate is plural. In the wiring board according to another embodiment of the present invention, a conductor group of the core substrate, a planar conductor pattern connected to one end of the conductor group, a plurality of via conductors connected to the planar conductor pattern, It is a figure which shows the 1st positional relationship of these. In the wiring board according to another embodiment of the present invention, a conductor group of the core substrate, a planar conductor pattern connected to one end of the conductor group, a plurality of via conductors connected to the planar conductor pattern, It is a figure which shows the 2nd positional relationship. In the wiring board according to another embodiment of the present invention, a conductor group of the core substrate, a planar conductor pattern connected to one end of the conductor group, a plurality of via conductors connected to the planar conductor pattern, It is a figure which shows the 3rd positional relationship. It is a figure which shows the positional relationship of the thick via conductor of the core board | substrate in the wiring board which concerns on other embodiment of this invention, and the 3rd via conductor stacked on it. It is a figure which shows the positional relationship of the thick via conductor of the core board | substrate in the wiring board which concerns on other embodiment of this invention, and the 4th via conductor stacked on it. In the wiring board which concerns on other embodiment of this invention, it is a figure which shows the example in which the number of the via conductors stacked on only one side of the thick via conductor of the core substrate is plural. In the wiring board which concerns on other embodiment of this invention, it is a figure which shows the example in which the number of the via conductors each stacked on both sides of the thick via conductor of the core substrate is plural. In the wiring board according to another embodiment of the present invention, a thick via conductor of the core substrate, a planar conductor pattern connected to one end of the via conductor, and a plurality of via conductors connected to the planar conductor pattern, It is a figure which shows the 1st positional relationship of these. In the wiring board according to another embodiment of the present invention, a thick via conductor of the core substrate, a planar conductor pattern connected to one end of the via conductor, and a plurality of via conductors connected to the planar conductor pattern, It is a figure which shows the 2nd positional relationship of. In the wiring board according to another embodiment of the present invention, a thick via conductor of the core substrate, a planar conductor pattern connected to one end of the via conductor, and a plurality of via conductors connected to the planar conductor pattern, It is a figure which shows the 3rd positional relationship of. In other embodiment of this invention, it is a figure which shows the 1st example of the planar shape of the through-hole which penetrates the via conductor of a core board | substrate, the via conductor of a laminated part, and the whole wiring board. In other embodiment of this invention, it is a figure which shows the 2nd example of the planar shape of the through-hole which penetrates the via conductor of a core board | substrate, the via conductor of a laminated part, and the whole wiring board. In other embodiment of this invention, it is a figure which shows the 3rd example of the planar shape of the through-hole which penetrates the via conductor of a core board | substrate, the via conductor of a laminated part, and the whole wiring board. In the wiring board according to another embodiment of the present invention, any of the core substrate, the lowermost interlayer insulating layer of the first stacked portion, and the lowermost interlayer insulating layer of the second stacked portion is any of the other interlayer insulating layers. It is a figure which shows the 1st example which consists of material with higher heat resistance than the material which comprises. In the wiring board according to another embodiment of the present invention, any of the core substrate, the lowermost interlayer insulating layer of the first stacked portion, and the lowermost interlayer insulating layer of the second stacked portion is any of the other interlayer insulating layers. It is a figure which shows the 2nd example which consists of material with higher heat resistance than the material which comprises. It is a figure which shows the wiring board with which the electronic component was mounted in the surface regarding other embodiment of this invention. In the wiring board which concerns on other embodiment of this invention, it is a figure which shows the example whose via conductor of the outermost layer is a conformal conductor.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the figure, arrows Z1 and Z2 indicate the stacking direction of the wiring boards (or the thickness direction of the wiring boards) corresponding to the normal direction of the main surface (front and back surfaces) of the wiring boards. On the other hand, arrows X1 and X2 and Y1 and Y2 respectively indicate directions orthogonal to the stacking direction (or sides of each layer). The main surface of the wiring board is an XY plane. The side surface of the wiring board is an XZ plane or a YZ plane. In the stacking direction, the side closer to the core of the wiring board is referred to as the lower layer, and the side farther from the core is referred to as the upper layer.

  The conductor layer is a layer composed of one or more conductor patterns. The conductor layer may include a conductor pattern that constitutes an electric circuit, for example, a wiring (including a ground), a pad, a land, or the like, or a planar conductor pattern that does not constitute an electric circuit.

  The opening includes notches and cuts in addition to holes and grooves.

  Of the conductors formed in the opening, the conductor formed in the via hole is referred to as the via conductor, the conductor formed in the through hole is referred to as the through-hole conductor, and is formed on the wall surface (side surface and bottom surface) of the opening. The conductive film is called a conformal conductor, and the conductor filled in the opening is called a filled conductor.

  The land is a conductor formed on or at the edge of a hole (via hole or through hole), and at least a part thereof is formed integrally with a conductor (via conductor or through hole conductor) in the hole.

  The stack means that the via conductor is formed on the land of the via conductor formed in the lower layer. That is, if the bottom surface of the via conductor does not protrude from the land of the underlying via conductor, the via conductor is stacked.

  The plating includes wet plating such as electrolytic plating or electroless plating, and dry plating such as PVD (Physical Vapor Deposition) or CVD (Chemical Vapor Deposition).

  FR is an index indicating the flame retardancy (heat resistance) of a copper clad laminate as a member of a printed wiring board, and is described as “FR-X” (X: an integer of 1 to 6). The higher the number, the higher the flame retardancy.

  Unless otherwise specified, “width (or thickness)” of a hole or column (projection) means a diameter in the case of a circle, and 2√ (cross-sectional area / π) otherwise. To do. However, this does not apply when it is clearly stated that other dimensions are indicated. When the dimensions are not uniform (when there are irregularities or when they are tapered, etc.), in principle, the average value of the dimensions (average of only effective values excluding abnormal values) is used. However, this does not apply when it is clearly stated that a value other than the average value is used, such as the maximum value.

(Embodiment 1)
The wiring board 100 according to the present embodiment is a multilayer printed wiring board as shown in FIG. The wiring board 100 of this embodiment is a double-sided rigid wiring board. However, the wiring board which concerns on this invention is not limited to a rigid wiring board, For example, a flexible wiring board or a flex rigid wiring board may be sufficient. In the wiring board 100, the dimensions and the number of layers of the conductor layer and the insulating layer can be arbitrarily changed.

  As shown in FIG. 1, the wiring board 100 includes a core insulating layer 10a (core substrate), insulating layers 20a, 30a, 40a, 50a, 60a, 70a, 80a, 90a (interlayer insulating layer), a conductor layer 11a, 11b, 21, 31, 41, 51, 61, 71, 81, 91 and via conductors 12, 22, 32, 42, 52, 62, 72, 82, 92. The core insulating layer 10a has a first surface F1 (Z1 side) and a second surface F2 (Z2 side) opposite to the first surface F1, and the via conductor 12 penetrates the core insulating layer 10a. The core insulating layer 10a, the via conductor 12, and the conductor layers 11a and 11b correspond to the core portion. Further, a buildup portion B1 (first stacked portion) is formed on the first surface F1 of the core insulating layer 10a, and a buildup portion B2 (second stacked portion) is formed on the second surface F2 of the core insulating layer 10a. Part) is formed. The build-up part B1 includes four sets of interlayer insulation layers and conductor layers (insulation layers 20a, 40a, 60a, 80a and conductor layers 21, 41, 61, 81), and the build-up part B2 includes four sets of interlayer insulations Layers and conductor layers (insulating layers 30a, 50a, 70a, 90a and conductor layers 31, 51, 71, 91).

  On the first surface F1 side of the core insulating layer 10a, five conductor layers 11a, 21, 41, 61, 81 and four insulating layers 20a, 40a, 60a, 80a are alternately stacked. The insulating layers 20a, 40a, 60a, and 80a are formed between the conductor layers 11a, 21, 41, 61, and 81, respectively.

  On the second surface F2 side of the core insulating layer 10a, five conductor layers 11b, 31, 51, 71, 91 and four insulating layers 30a, 50a, 70a, 90a are alternately stacked. The insulating layers 30a, 50a, 70a, and 90a are formed between the conductor layers 11b, 31, 51, 71, and 91, respectively.

  A hole 12a that penetrates the core insulating layer 10a is formed in the core insulating layer 10a. The via conductor 12 is a filled conductor, and is configured by filling the hole 12a with a conductor. The conductor layer 11a formed on the first surface F1 of the core insulating layer 10a and the conductor layer 11b formed on the second surface F2 of the core insulating layer 10a are electrically connected to each other through the via conductor 12. Is done.

  The core insulating layer 10a is made of, for example, FR-5 material. The core insulating layer 10a is formed, for example, by impregnating a core material with a resin. The FR-5 material can be formed, for example, by making a glass fiber cloth impregnated with an epoxy resin and performing a thermosetting treatment into a plate shape. However, it is not limited to this, The material of the core insulating layer 10a is arbitrary.

  The shape of the via conductor 12 is, for example, a tapered cylinder (conical truncated cone) that is tapered so as to be reduced in diameter from the first surface F1 to the second surface F2 of the core insulating layer 10a. -Y plane) is, for example, a perfect circle. However, it is not limited to this, and the shape of the via conductor 12 is arbitrary.

  Via conductors 22, 32, 42, 52, 62, 72, 82, and 92 are formed in the insulating layers 20a, 30a, 40a, 50a, 60a, 70a, 80a, and 90a, respectively. Each of these via conductors 22 and the like is a filled conductor, and is configured by filling the via holes 22a, 32a, 42a, 52a, 62a, 72a, 82a, and 92a with conductors. Each of the via conductors 22, 32, 42, 52, 62, 72, 82, and 92 is, for example, a tapered cylinder (conical frustum) tapered so as to be reduced in diameter toward the core insulating layer 10a. (XY plane) is, for example, a perfect circle. However, the present invention is not limited to this, and the shape of the via conductor 22 and the like is arbitrary.

  Insulating layer 20a (lowermost interlayer insulating layer of the first stacked portion), insulating layer 30a (lowermost interlayer insulating layer of the second stacked portion), and insulating layers 40a, 50a, 60a, 70a, which are higher than these, 80a and 90a are each comprised from FR-4 material, for example. Each of these insulating layers is formed by impregnating a core material with a resin, for example. The FR-4 material can be formed, for example, by making a glass fiber cloth impregnated with an epoxy resin and applying a thermosetting treatment into a plate shape. However, it is not limited to this, The material of each insulating layer is arbitrary.

  In the wiring board 100 of the present embodiment, as shown in FIG. 1, a through hole 102 a penetrating all layers of the wiring board 100 is formed. The through hole 102a penetrates the wiring board 100 in the Z direction (stacking direction). In the present embodiment, one end of the through-hole conductor 102 is connected to the outermost conductor layer 81 (specifically, a land 81a included in the conductor layer 81), and the other end of the through-hole conductor 102 is the outermost conductor layer. 91 (specifically, a land 91a included in the conductor layer 91).

  The through hole 102a is disposed on the peripheral portion of the wiring board 100, for example, as shown in FIG. The shape of the through hole 102a is, for example, a cylinder, and the opening shape of the through hole 102a is, for example, an ellipse as shown in FIG. It is considered that the strength of a wide region in the XY plane can be effectively improved by the oval shape of the through hole 102a. However, the present invention is not limited to this, and the number, the opening shape, the arrangement, and the like of the through holes 102a are arbitrary.

  In the present embodiment, the through-hole conductor 102 is formed on the wall surface of the through-hole 102a. The through-hole conductor 102 is made of a conformal conductor. Unlike the filled conductor in which the conductor is filled in the through hole 102a, the conformal conductor has a conductor only on the wall surface of the through hole 102a. Therefore, a cavity is formed in the through hole 102a, and the distortion of the wiring board 100 is reduced. It becomes easy. However, the present invention is not limited to this, and a filled conductor may be used instead of the conformal conductor.

  FIG. 3 shows an enlarged stack structure of the wiring board 100 according to the present embodiment. 4A shows the positional relationship among the first planar conductor pattern, the conductor group, and the third via conductor in the wiring board 100 of this embodiment (specifically, the positional relationship when projected onto the XY plane). 4B shows the positional relationship among the second planar conductor pattern, the conductor group, and the fourth via conductor (specifically, the positional relationship when projected onto the XY plane) in the wiring board 100 of the present embodiment. Show.

  As shown in FIGS. 3, 4A, and 4B, in the wiring board 100 of the present embodiment, a conductor group 12g is formed by a plurality of (for example, two) via conductors 12 formed in the core insulating layer 10a. The Hereinafter, the via conductors 12 constituting the conductor group 12g are referred to as via conductors 12s.

  A land 111s (first planar conductor pattern) of the via conductor 12s is formed on the first surface F1 of the core insulating layer 10a, and a land of the via conductor 12s is formed on the second surface F2 of the core insulating layer 10a. 112s (second planar conductor pattern) is formed. The land 111s is included in the conductor layer 11a, and the land 112s is included in the conductor layer 11b. The conductor layer 11a includes a wiring 11w formed integrally with the land 111s. The shape of the lands 111s and 112s is, for example, an elliptical plate shape as shown in FIG. 3, FIG. 4A, and FIG. 4B.

  Each of the via conductors 12s constituting the conductor group 12g has a land 111s (first planar conductor pattern) having a common end (upper surface F121) and a land 112s (second surface) having a common other end (bottom surface F122). To each of the conductor patterns). An upper surface F121 of the via conductor 12s corresponds to a boundary surface between the via conductor 12s and the land 111s, and a bottom surface F122 of the via conductor 12s corresponds to a boundary surface between the via conductor 12s and the land 112s. That is, in the core portion of the wiring board 100 according to the present embodiment, two flat plates (lands 111 s and 112 s) are connected to each other via a plurality of (for example, two) pillars (via conductors 12 s).

  A plurality of via conductors 22 are formed in the lowermost insulating layer 20a of the buildup portion B1, and a plurality of via conductors 32 are formed in the lowermost insulating layer 30a of the buildup portion B2. In the present embodiment, as shown in FIGS. 3 and 4A, one end (bottom surface F222) of one of the via conductors 22 (hereinafter referred to as via conductor 22s) is a land 111s (first planar conductor pattern). The two via conductors 12s constituting the conductor group 12g are connected to a region R11 defined by the outer edge of one end (upper surface F121). As shown in FIGS. 3 and 4B, one end (bottom surface F322) of one of the via conductors 32 (hereinafter referred to as via conductor 32s) is a conductor group 12g of a land 112s (second planar conductor pattern). Are connected to a region R12 defined by the outer edge of the other end (bottom surface F122) of each of the two via conductors 12s.

  Each of the regions R11 and R12 is partitioned by an auxiliary line such as a tangent line. In the present embodiment, the boundary between the regions R11 and R12 is determined by, for example, a tangent line drawn with respect to the shape (for example, a circle) of the upper surface F121 and the bottom surface F122 of the via conductor 12s. In the example shown in FIGS. 4A and 4B, the entire upper surface F121 of the via conductor 12s is included in the region R11, and the entire bottom surface F122 of the via conductor 12s is included in the region R12.

  In the present embodiment, as shown in FIGS. 4A and 4B, the via conductors 22s and 32s are located between the two via conductors 12s (for example, the middle) constituting the conductor group 12g, respectively. Further, the bottom surface F222 of the via conductor 22s on the land 111s is completely included in the region R11 defined by the outer edges of the upper surfaces F121 of the two via conductors 12s projected onto the land 111s. The bottom surface F322 of the via conductor 32s on the land 112s is completely included in the region R12 defined by the outer edges of the bottom surfaces F122 of the two via conductors 12s projected on the land 112s.

  Further, in the present embodiment, as shown in FIGS. 1 and 3, the insulating layers 40a, 60a, and 80a (each interlayer) of the buildup portion B1 (first laminated portion) are formed on the via conductor 22s (third via conductor). Each of the via conductors 42, 62, 82 formed in the insulating layer) (hereinafter referred to as via conductors 42s, 62s, 82s) is stacked, so that the build-up portion B1 has four stages of via conductors. A first stack structure S1 is formed. As shown in FIGS. 1 and 3, the insulating layers 50a, 70a, and 90a (each interlayer insulating layer) of the buildup portion B2 (second stacked portion) are formed on the via conductor 32s (fourth via conductor). Each of the via conductors 52, 72, and 92 (hereinafter referred to as via conductors 52s, 72s, and 92s, respectively) is stacked, so that the build-up portion B2 includes a four-stage via conductor. A two-stack structure S2 is formed. The via conductors 22s, 32s, 42s, 52s, 62s, 72s, 82s, and 92s are stacked on, for example, the same axis (Z axis). However, it is not essential that these via conductors 22 and the like are stacked on the same axis (Z axis).

  In the present embodiment, the via conductors 22s, 42s, 62s, and 82s of all layers of the buildup part B1 (first stacked part) constitute the first stack structure S1, and all of the buildup parts B2 (second stacked part) The via conductors 32s, 52s, 72s, 92s of the layers constitute the second stack structure S2. For this reason, it becomes easy to secure the wiring space, and the degree of freedom in designing the wiring pattern is increased. As a result, high-density wiring can be easily realized. Further, since the wiring in the X direction or the Y direction can be omitted, the wiring length can be shortened.

  In each of the first stack structure S1 and the second stack structure S2, adjacent filled conductors are in close contact (contact) and are electrically connected to each other. The first stack structure S1 and the second stack structure S2 are electrically connected to each other via the conductor group 12g and the lands 111s and 112s in the core portion. Via conductors 22s constituting the first stack structure S1 are stacked on one side of the conductor group 12g (specifically, on the land 111s), and on the other side (specifically, on the land 112s) of the conductor group 12g. Via conductors 32s constituting the two-stack structure S2 are stacked. Hereinafter, the stack structure constituted by the conductor group 12g of the core part, the first stack structure S1 of the buildup part B1, and the second stack structure S2 of the buildup part B2 is referred to as a stack structure S. The stack structure S is configured by stacking conductors (via conductors 12 s, 22 s, 32 s, 42 s, 52 s, 62 s, 72 s, 82 s, and 92 s) formed between all layers of the wiring board 100. Hereinafter, such a stack structure over all layers of the wiring board is referred to as a full stack structure. The stack structure S electrically connects the outermost conductor layers on both surfaces of the wiring board 100, that is, the conductor layer 81 and the conductor layer 91 to each other.

  In the present embodiment, one stack structure S is disposed at the center of the wiring board 100 as shown in FIG. The arrangement and number of stack structures S are arbitrary. For example, there may be a plurality of stack structures S.

  As shown in FIG. 3, the conductor layer 11a (including the land 111s and the wiring 11w) includes a metal foil 111a (for example, copper foil), an electroless plating film 111b of, for example, copper, and an electrolytic plating 111c of, for example, copper. Composed. The conductor layer 21 (including the land 211s) includes a metal foil 211a (for example, a copper foil), an electroless plating film 211b, for example, copper, and an electrolytic plating 211c, for example, copper. The conductor layer 41 (including the land 411s) includes a metal foil 411a (for example, copper foil), an electroless plating film 411b of, for example, copper, and an electrolytic plating of 411c of, for example, copper. The conductor layer 61 (including the land 611s) includes a metal foil 611a (for example, copper foil), an electroless plating film 611b of, for example, copper, and an electrolytic plating of 611c of, for example, copper. The conductor layer 81 (including the land 811s) includes a metal foil 811a (for example, copper foil), an electroless plating film 811b of, for example, copper, and an electrolytic plating of 811c of, for example, copper.

  As shown in FIG. 3, the conductor layer 11b (including the land 112s) includes a metal foil 112a (for example, copper foil), an electroless plating film 112b of copper, for example, and an electrolytic plating 112c of copper, for example. . The conductor layer 31 (including the land 311s) includes a metal foil 311a (for example, copper foil), an electroless plating film 311b of, for example, copper, and an electrolytic plating of 311c of, for example, copper. The conductor layer 51 (including the land 511s) includes a metal foil 511a (for example, a copper foil), an electroless plating film 511b of, for example, copper, and an electrolytic plating of 511c of, for example, copper. The conductor layer 71 (including the land 711s) includes a metal foil 711a (for example, copper foil), an electroless plating film 711b of, for example, copper, and an electrolytic plating of 711c of, for example, copper. The conductor layer 91 (including the land 911s) includes a metal foil 911a (for example, copper foil), an electroless plating film 911b of, for example, copper, and an electrolytic plating of 911c of, for example, copper.

  As shown in FIG. 3, each of the via conductors 12 (including the two via conductors 12s constituting the conductor group 12g) includes an electroless plating film 110b formed on the wall surface of the hole 12a, and an electroless plating in the hole 12a. Electrolytic plating 110c filled inside the plating film 110b.

  The via conductors 22, 32, 42, 52, 62, 72, 82, and 92 (including via conductors 22s, 32s, 42s, 52s, 62s, 72s, 82s, and 92s, respectively) are respectively connected to the via holes 22a, 32a, and 42a. , 52a, 62a, 72a, 82a, and 92a, the electroless plating films 211b, 311b, 411b, 511b, 611b, 711b, 811b, and 911b formed on the wall surfaces and the bottom surfaces of the electroless plating films in the via holes. Electrolytic plating 211c, 311c, 411c, 511c, 611c, 711c, 811c, and 911c filled inside is configured.

  Each of the via holes 12a, 22a, 32a, 42a, 52a, 62a, 72a, 82a, and 92a is formed by drilling with a conductor layer on one side of the insulating layer, and the conductor from the other side of the insulating layer. (For example, see FIGS. 12B, 12C, 13B, and 17 described later). Since the via conductors 12, 22, 32, 42, 52, 62, 72, 82, and 92 are each formed with a conductor layer on one side of the insulating layer, the via conductor and the conductor layer on one side of the insulating layer are formed. Is discontinuous, and an interface is formed between the two.

  Specifically, as shown in FIG. 3, for example, the electroless plating film 211b and the electrolytic plating 211c are formed continuously (without a break) over both the via conductor 22 and the conductor layer 21 on the upper layer side. . The via conductors 12, 42, 62, and 82 also have the same structure. On the other hand, between the via conductor 12 and the bottom conductor layer 11b, between the via conductor 22 and the lower conductor layer 11a, between the via conductor 42 and the lower conductor layer 21, and the via conductor 62, Interfaces (cuts) are respectively formed between the lower conductor layer 41 and between the via conductor 82 and the lower conductor layer 61, and the via conductor and the lower conductor layer are not connected. Become continuous.

  On the second surface F2 side of the core insulating layer 10a, the electroless plating film 311b and the electrolytic plating 311c are formed continuously (without a break) over both the via conductor 32 and the conductor layer 31 on the upper layer side. The via conductors 52, 72, and 92 have the same structure as this. On the other hand, between the via conductor 32 and the lower conductor layer 11b, between the via conductor 52 and the lower conductor layer 31, between the via conductor 72 and the lower conductor layer 51, and via conductors. An interface (cut) is formed between each of 92 and the lower conductive layer 71, and the via conductor and the lower conductive layer are discontinuous.

  Of the dimensions of the via conductor 12s shown in FIG. 5, the width D1 (diameter) of the upper surface F121 of the via conductor 12s is, for example, 100 μm, and the width D2 (diameter) of the bottom surface F122 of the via conductor 12s is, for example, 80 μm. .

  In the present embodiment, all the via conductors 12 (including the two via conductors 12s constituting the conductor group 12g) formed in the core insulating layer 10a have substantially the same dimensions. That is, in the present embodiment, each of the two via conductors 12s constituting the conductor group 12g and the via conductor 12 not constituting the conductor group 12g have substantially the same thickness (width). According to such a structure, it becomes easy to make electrical characteristics or manufacturing conditions uniform.

  In this embodiment, each of the via conductors 22, 32, 42, 52, 62, 72, 82, and 92 (including via conductors 22s, 32s, 42s, 52s, 62s, 72s, 82s, and 92s, respectively) has a core insulation. It has substantially the same dimensions as the via conductor 12 formed in the layer 10a. That is, each of the via conductors 12s constituting the conductor group 12g, the via conductor 22s (third via conductor), and the via conductor 32s (fourth via conductor) have substantially the same thickness. According to such a structure, it becomes easy to make electrical characteristics or manufacturing conditions uniform. However, the present invention is not limited thereto, and these via conductors may have different dimensions from the via conductors 12 of the core substrate.

  In the present embodiment, the core insulating layer 10a (core substrate), the insulating layer 20a (lowermost interlayer insulating layer of the first stacked portion), and the insulating layer 30a (lowermost interlayer insulating layer of the second stacked portion) are respectively provided. The core material is impregnated with resin. As shown in FIG. 6, the protruding amount D101 of the core material on the side surface of the via conductor 12s formed in the core insulating layer 10a (an average value when there are a plurality of core materials) is the via conductor 22s formed in the insulating layer 20a. The protruding amount D102 of the core material on the side surface of the (third via conductor) (average value when there are a plurality of core materials) and the protruding amount of the core material on the side surface of the via conductor 32s (fourth via conductor) formed in the insulating layer 30a It is larger than any of D103 (an average value when there are a plurality of D103).

  According to such a structure, since the surface area in the via hole (and hence the contact area between the via conductor and the interlayer insulating layer) is increased in the core portion, the adhesion between the via conductor and the interlayer insulating layer is improved. In addition, since the CTE (thermal expansion coefficient) of the core material is smaller than the CTE of the resin constituting the interlayer insulating layer and close to the CTE of the via conductor, it is easy to reduce the crack occurrence rate at the bottom surface of the via conductor in the core portion. It is considered to be.

  In a preferred example, the protrusions D101, D102, and D103 are each in the range of about 1 to about 3 μm.

  Hereinafter, the characteristic of the wiring board 100 of this embodiment is demonstrated using a comparative example.

  FIG. 7 shows a wiring board according to a comparative example. The wiring board shown in FIG. 7 has a full stack structure. However, the wiring board stack structure S shown in FIG. 7 is formed by stacking via conductors 10s, 22s, 32s, 42s, 52s, 62s, 72s, 82s, and 92s one by one on the same axis (Z axis). The That is, the wiring board stack structure S shown in FIG. 7 does not have a conductor group in the core portion. In this respect, the wiring board according to the comparative example shown in FIG. 7 is different from the wiring board 100 of the present embodiment shown in FIG. In FIG. 7, the same elements as those illustrated in FIG. 1 are denoted by the same reference numerals.

  The result of having performed the simulation about the wiring board which concerns on a comparative example is shown to FIG. 8A-FIG.

  FIG. 8A and FIG. 8B show the results of simulating stress (especially thermal stress due to heat cycle) applied to 6-layer, 8-layer, and 10-layer wiring boards (6-layer products, 8-layer products, and 10-layer products). FIG. The 10-layer product is a wiring board having the structure shown in FIG. 7, and the 8-layer product is a wiring board in which the outermost layers (insulating layers 80a and 90a and conductor layers 81 and 91) on both sides are eliminated from the 10-layer product. The 6-layer product is a wiring board in which the outermost two layers (insulating layers 60a, 70a, 80a, 90a and conductor layers 61, 71, 81, 91) on both sides are eliminated from the 10-layer product. In FIG. 8A, a line L1 is data related to a 6-layer product, a line L2 is data related to an 8-layer product, and a line L3 is data related to a 10-layer product.

  As shown in FIG. 8A and FIG. 8B, in any of the 6-layer product, the 8-layer product, and the 10-layer product, the stress applied to the core is the largest, and the stress decreases as the distance from the core increases. In addition, when the stress applied to each of the 6-layer product, the 8-layer product, and the 10-layer product is compared, the stress in the 10-layer product is the largest, the stress in the 8-layer product is next largest, and the stress in the 6-layer product is smallest . From this, it is surmised that the stress in the wiring board increases as the number of layers increases.

  In FIG. 9, the result of having simulated about the crack occupation rate in each layer of an 8-layer product and a 10-layer product is shown.

  As shown in FIG. 9, it is considered that most of the cracks are concentrated on the core (core substrate). As a result, there is a concern that the connection reliability in the core portion is lowered. Further, as described above, it is considered that the stress in the wiring board increases as the number of layers increases. Therefore, the occurrence of cracks around the core portion is considered to become more serious as the number of layers of the wiring board increases.

  In this regard, in the wiring board 100 of this embodiment, a conductor group 12g including a plurality of via conductors 12s penetrating the core substrate is formed on the core substrate (core insulating layer 10a). One end (upper surface F121) is connected to the common first planar conductor pattern (land 111s), and the other end (bottom surface F122) is connected to the common second planar conductor pattern (land 112s). Then, one end (bottom surface F222) of the third via conductor (via conductor 22s) formed in the insulating layer 20a (interlayer insulating layer on the first surface F1 of the core insulating layer 10a) is the first planar conductor pattern. Are connected to a region R11 defined by the outer edge of one end (upper surface F121) of each of the two via conductors 12s constituting the conductor group 12g (see FIG. 4A), and the insulating layer 30a (the second surface F2 of the core insulating layer 10a). One end (bottom surface F322) of the fourth via conductor (via conductor 32s) formed in the upper interlayer insulating layer) is the other end of each of the via conductors 12s constituting the conductor group 12g of the second planar conductor pattern. It is connected to a region R12 defined by the outer edge of (bottom surface F122) (see FIG. 4B). In such a structure, the conductor group 12g composed of a plurality of via conductors 12s is formed on the core substrate, so that the strength or heat dissipation of the core portion where large stress is likely to occur is improved. As a result, the thermal stress is reduced, and it is considered that cracks at the bottom surface F122 of the via conductor 12s or delamination between the bottom surface F122 and the conductor layer 11b hardly occur. Moreover, it is thought that the heat resistance of a wiring board improves by the heat dissipation of a core part improving. In addition, since the first planar conductor pattern (land 111s) and the second planar conductor pattern (land 112s) are connected via the plurality of via conductors 12s, they are connected via one via conductor. The conduction resistance is lower than in the case of

  In the wiring board 100 of the present embodiment, the core substrate (core insulating layer 10a) includes the interlayer insulating layer of the first stacked portion (build-up portion B1) and the interlayer insulating layer (insulating) of the second stacked portion (build-up portion B2). The layer 20a, 30a, 40a, 50a, 60a, 70a, 80a, 90a) is made of a material having higher heat resistance than the material constituting any of the layers. That is, the heat resistance of the core substrate is selectively enhanced. Specifically, the core insulating layer 10a is made of FR-5 material, and the insulating layers 20a, 30a, 40a, 50a, 60a, 70a, 80a, 90a are each made of FR-4 material. With such a structure, the heat resistance of the core portion where large stress is likely to occur is improved. As a result, it is considered that the thermal stress generated in the core portion is reduced. Hereinafter, this will be described with reference to FIGS. 10A and 10B.

  FIG. 10A and FIG. 10B are diagrams showing the results of a simulation performed on the wiring boards (sample A to sample F) having the structure shown in FIG. However, in the samples A to C, unlike the wiring board 100 of the present embodiment, the core insulating layer 10a and the insulating layers 20a, 30a, 40a, 50a, 60a, 70a, 80a, and 90a are each made of FR-4 material. Composed. On the other hand, in Sample D to Sample F, the core insulating layer 10a is made of FR-5 material, and the insulating layers 20a, 30a, 40a, 50a, 60a, 70a, 80a, 90a are the same as the wiring board 100 of the present embodiment. Are each made of FR-4 material.

  In the simulation, the stresses generated when the samples A and D were each heated from a temperature of 25 ° C. to a temperature of 150 ° C. were obtained. For samples B and E, the stress generated when the temperature was 25 ° C and the temperature was 60 ° C was determined. Moreover, about the samples C and F, the stress which arises when it heated from the state of temperature 25 degreeC and was made into temperature 45 degreeC was calculated | required, respectively.

  As shown in FIGS. 10A and 10B, the stress applied to the core substrate caused by the heating is 215 MPa for sample A, 208 MPa for sample B, 147 MPa for sample C, and 139 MPa for sample D. Sample E had 104 MPa and Sample F had 74 MPa. Thus, in any heating, the wiring board (samples D to D) in which the core substrate is made of the FR-5 material rather than the wiring boards (sample A to sample C) in which the core board is made of the FR-4 material. The stress was smaller in the sample F). From this, the heat resistance of the material of the core substrate is higher than the heat resistance of the material constituting either the interlayer insulating layer of the first stacked portion or the interlayer insulating layer of the second stacked portion laminated on both surfaces of the core substrate. By doing so, it is considered that the thermal stress generated in the core portion can be reduced.

  Further, the wiring board 100 of the present embodiment has a through-hole conductor 102. According to the through-hole conductor 102, since all the layers of the wiring board 100 are reinforced on average, it is considered that generation of cracks in the upper layer (insulating layers 20a to 90a) of the core substrate is suppressed.

  Further, the wiring board 100 of the present embodiment has a stack structure S. The stack structure S facilitates securing a wiring space and increases the degree of freedom in designing a wiring pattern. As a result, high-density wiring can be easily realized. Further, since the wiring in the X direction or the Y direction can be omitted, the wiring length can be shortened.

  As described above, according to the above structure according to the wiring board 100 of the present embodiment, a printed wiring board having highly reliable electrical connection, high heat dissipation, low conduction resistance, and high-density wiring can be obtained. Conceivable.

  In the wiring board 100 of the present embodiment, the number of conductor layers formed on the first surface F1 side of the core insulating layer 10a and the number of conductor layers formed on the second surface F2 side of the core insulating layer 10a are respectively. 5 or more layers. In the wiring board 100 of the present embodiment, the reliability of the electrical connection between layers is improved by the above structure, and thus such a multilayer wiring board can be manufactured with a high yield. However, the present invention is not limited to this, and the number of wiring boards (the number of conductor layers) to which the above structure is applied is arbitrary.

  Hereinafter, a method for manufacturing the wiring board 100 according to the present embodiment will be described. The wiring board 100 is manufactured by a procedure as shown in FIG. 11, for example.

  In step S11, a core substrate is prepared.

  Specifically, as shown in FIG. 12A, a double-sided copper-clad laminate 1000 (starting material) is prepared. The double-sided copper-clad laminate 1000 has a core insulating layer 10a (core substrate) and metal foils 111a and 112a (for example, copper foils, respectively). A metal foil 111a is formed on the first surface F1 of the core insulating layer 10a, and a metal foil 112a is formed on the second surface F2 of the core insulating layer 10a. The core insulating layer 10a is made of, for example, a completely cured FR-5 material.

  In the present embodiment, for example, without adjusting the thickness by etching, the metal foils 111a and 112a having a predetermined thickness (for example, 7.5 μm) are attached to the core insulating layer 10a from the beginning. However, it is not restricted to this, The formation method of metal foil 111a, 112a is arbitrary. For example, after a relatively thick (for example, 12 μm) metal foil is attached to the core insulating layer 10a, the metal foil is half-etched to obtain metal foils 111a and 112a having a predetermined thickness (for example, 7.5 μm). Also good.

  Moreover, in this embodiment, the thickness of the metal foil 111a and 112a of the double-sided copper clad laminated board 1000 which is a starting material is 5 micrometers or more. By setting it as such a dimension, the intensity | strength of the double-sided copper clad laminated board 1000 increases, and it is thought that the handleability improves. However, the thickness of the metal foils 111a and 112a is not limited to this range, and may be changed as appropriate.

  Subsequently, in step S12 of FIG. 11, conductor groups are formed on the core insulating layer 10a (core substrate), and conductor layers are formed on both surfaces of the core insulating layer 10a (core substrate).

  Specifically, as illustrated in FIG. 12B, an opening 110d that penetrates the metal foil 111a and the core insulating layer 10a and does not penetrate the metal foil 112a is formed by, for example, a laser. The opening 110d includes an opening 111d that penetrates the metal foil 111a and a hole 12a that penetrates the core insulating layer 10a. After the opening 110d is formed, desmearing or soft etching is performed as necessary.

  Subsequently, as shown in FIG. 12C, the plating 1001 is formed on the metal foil 111a and the opening 110d by, for example, copper panel plating, and the plating 1002 is formed on the metal foil 112a. Thereby, the opening 110d is filled with the plating 1001. As a result, a via conductor 12 (including two via conductors 12s constituting the conductor group 12g) is formed. In the core insulating layer 10a, together with the via conductor 12s (first via conductor), a via conductor 12 (second via conductor) having substantially the same thickness as the via conductor 12s and not constituting the conductor group 12g is also formed. Is done.

  The plating 1001 is formed, for example, by performing electroless plating to form an electroless plating film, and subsequently performing electroplating using the electroless plating film as a seed layer. The plating 1001 constitutes the electroless plating films 110b and 111b and the electrolytic plating 110c and 111c shown in FIG. 3, and the plating 1002 constitutes the electroless plating film 112b and the electrolytic plating 112c shown in FIG.

  As a plating solution for electroless plating, for example, a copper sulfate solution to which a reducing agent or the like is added can be used. Moreover, as a plating solution for electrolytic plating, for example, a copper sulfate solution, a copper pyrophosphate solution, a blue (cyanide) copper solution, or a copper borofluoride solution can be used.

  Subsequently, as shown in FIG. 12D, the conductor layers on both surfaces of the core insulating layer 10a are patterned by lithography, for example. Thereby, the conductor layer 11a is formed on the first surface F1 of the core insulating layer 10a, and the conductor layer 11b is formed on the second surface F2 of the core insulating layer 10a. The conductor layer 11a includes a land 111s, and the conductor layer 11b includes a land 112s. The land 111s and the land 112s are connected to each other through two via conductors 12s constituting the conductor group 12g.

  As described above, in this embodiment, plating for forming the via conductor 12 and the conductor layers 11a and 11b is performed after the opening 110d (the opening 111d and the hole 12a) is formed.

  Subsequently, in step S13 of FIG. 11, a pair of interlayer insulating layers and conductor layers (the first stacked portion and the first laminated portion and the first layer are formed on each of the first surface F1 and the second surface F2 of the core insulating layer 10a (core substrate). 1st stage of two laminated parts) is formed. A via conductor is formed in the interlayer insulating layer, and the conductor layer on the interlayer insulating layer and the conductor layer on the core substrate are electrically connected to each other through the via conductor.

  Specifically, for example, as shown in FIG. 13A, an insulating layer 20a (interlayer insulating layer) and a metal foil 1011 (for example, copper foil) are formed on the first surface F1 and the conductor layer 11a of the core insulating layer 10a. In this order, the insulating layer 30a (interlayer insulating layer) and the metal foil 1012 (for example, copper foil) are arranged in this order on the second surface F2 of the core insulating layer 10a and the conductor layer 11b. . At this stage, the insulating layers 20a and 30a are each made of FR-4 material prepreg (a semi-cured adhesive sheet). However, RCF (Resin Coated copper Foil) or the like can be used instead of the prepreg. Thereafter, the metal foils 1011 and 1012 are half-etched as necessary. Hereinafter, the wiring board shown in FIG. 13A thus obtained is referred to as a wiring board 1000a.

  Subsequently, the wiring board 1000a is heated and pressed in the Z direction. That is, pressing and heat treatment are performed simultaneously. The prepreg (insulating layers 20a and 30a) is cured by pressing and heating, and the members adhere to each other. As a result, the wiring board 1000a is integrated. Note that the pressing and heat treatment may be performed in a plurality of times. Moreover, although heat processing and a press may be performed separately, it is more efficient to perform it simultaneously. You may perform the heat processing for integration separately after a heat press.

  Subsequently, for example, as shown in FIG. 13B, via holes 22a are formed in the insulating layer 20a and via holes 32a are formed in the insulating layer 30a by, for example, a laser. The bottom surface of the via hole 22a (corresponding to the bottom surface F222 of the via conductor 22s shown in FIG. 4A) is a region defined by the outer edge of one end (upper surface F121) of each of the two via conductors 12s constituting the conductor group 12g of the land 111s. R11 (see FIG. 4A), and the bottom surface of the via hole 32a (corresponding to the bottom surface F322 of the via conductor 32s shown in FIG. 4B) is the other of each of the two via conductors 12s constituting the conductor group 12g of the land 112s. It arrange | positions in area | region R12 (refer FIG. 4B) divided by the outer edge of an edge (bottom face F122). In addition, it is preferable to perform a blackening process before drilling (laser irradiation) as needed. In addition, after drilling, desmear or soft etch is performed as necessary.

  Subsequently, as shown in FIG. 13C, plating 1013 is formed on the metal foil 1011 and in the via hole 22a by, for example, copper panel plating, and the plating 1014 is formed on the metal foil 1012 and in the via hole 32a. The platings 1013 and 1014 are formed, for example, by performing electroless plating to form an electroless plating film, and subsequently performing electroplating using the electroless plating film as a seed layer, as in the process of FIG. 12C. As a result, the via holes 22a and 32a are filled with plating 1013 and 1014, respectively. As a result, via conductors 22 and 32 are formed. The via conductor 22 has an arrangement as shown in FIG. 4A, and the via conductor 32 has an arrangement as shown in FIG. 4B. That is, the bottom surface F222 of the via conductor 22s is connected to the region R11 (see FIG. 4A) defined by the outer edge of one end (upper surface F121) of each of the two via conductors 12s constituting the conductor group 12g of the land 111s. The bottom surface F322 of the via conductor 32s is connected to a region R12 (see FIG. 4B) defined by the outer edge of each other end (bottom surface F122) of each of the two via conductors 12s constituting the conductor group 12g of the land 112s.

  Subsequently, as shown in FIG. 13D, the conductor layer on the insulating layer 20a and the conductor layer on the insulating layer 30a are respectively patterned by lithography, for example. Thereby, the conductor layer 21 is formed on the insulating layer 20a, and the conductor layer 31 is formed on the insulating layer 30a.

  Subsequently, in step S14 of FIG. 11, a pair of interlayer insulating layers and conductor layers (second stage of the first stacked portion and the second stacked portion) are formed on the conductor layer 21 and the conductor layer 31, respectively. . As in the first stage, via conductors are also formed in the second interlayer insulating layer, and the conductor layer on the first interlayer insulating layer and the conductor layer on the second interlayer insulating layer are connected to the via conductor. Are electrically connected to each other.

  Specifically, through the same process as the first stage (step S13 in FIG. 11), as shown in FIG. 14, insulating layers 40a and 50a (interlayer insulating layers, respectively), via holes 42a and 52a, via conductors 42 and 52 and conductor layers 41 and 51 are formed. The via conductors 42 constituting the first stack structure S1 (see FIG. 1) are stacked on the same axis (Z axis) as the other via conductors 22 constituting the first stack structure S1. In addition, the via conductor 52 constituting the second stack structure S2 (see FIG. 1) is stacked on the same axis (Z axis) as the other via conductor 32 constituting the second stack structure S2.

  Subsequently, in step S15 of FIG. 11, a pair of interlayer insulating layers and conductor layers (third layer of the first stacked portion and the second stacked portion) are formed on the conductor layer 41 and the conductor layer 51, respectively. . As in the second stage, via conductors are also formed in the third interlayer insulating layer, and the conductor layer on the second interlayer insulating layer and the conductor layer on the third interlayer insulating layer are connected to the via conductor. Are electrically connected to each other.

  Specifically, through the same process as the first stage (step S13 in FIG. 11), as shown in FIG. 15, insulating layers 60a and 70a (interlayer insulating layers, respectively), via holes 62a and 72a, via conductors 62 and 72 and conductor layers 61 and 71 are formed. The via conductors 62 constituting the first stack structure S1 (see FIG. 1) are stacked on the same axis (Z axis) as the other via conductors 22 constituting the first stack structure S1. Further, the via conductors 72 constituting the second stack structure S2 (see FIG. 1) are stacked on the same axis (Z axis) as the other via conductors 32 constituting the second stack structure S2.

  Subsequently, in step S <b> 16 of FIG. 11, a pair of interlayer insulating layers and conductor layers (fourth stage of the first stacked portion and the second stacked portion) are formed on the conductor layer 61 and the conductor layer 71, respectively. At the same time, a through hole penetrating all the layers of the core portion and the first to fourth stacked portions is formed.

  Specifically, for example, as shown in FIG. 16, an insulating layer 80a (interlayer insulating layer) and a metal foil 1021 (for example, copper foil) are arranged in this order on the insulating layer 60a and the conductor layer 61. The insulating layer 90a (interlayer insulating layer) and the metal foil 1022 (for example, copper foil) are disposed in this order on the insulating layer 70a and the conductor layer 71. At this stage, each of the insulating layers 80a and 90a is an FR-4 material prepreg (a semi-cured adhesive sheet). However, RCF (Resin Coated copper Foil) or the like can be used instead of the prepreg. Thereafter, the metal foils 1021 and 1022 are half-etched as necessary. Hereinafter, the wiring board shown in FIG. 16 thus obtained is referred to as a wiring board 1000b.

  Subsequently, the wiring board 1000b is heated and pressed in the Z direction. That is, pressing and heat treatment are performed simultaneously. The prepreg (insulating layers 80a and 90a) is cured by pressing and heating, and the members adhere to each other. As a result, the wiring board 1000b is integrated. Note that the pressing and heat treatment may be performed in a plurality of times. Moreover, although heat processing and a press may be performed separately, it is more efficient to perform it simultaneously. You may perform the heat processing for integration separately after a heat press.

  Subsequently, for example, as shown in FIG. 17, a via hole 82a that penetrates the insulating layer 80a, a via hole 92a that penetrates the insulating layer 90a, and a through hole 102a that penetrates all layers of the wiring board 1000b are formed by, for example, a laser. The via hole 82a is formed on the same axis (Z axis) as the via conductor 62, and the via hole 92a is formed on the same axis (Z axis) as the via conductor 72. In addition, it is preferable to perform a blackening process before drilling (laser irradiation) as needed. In addition, after drilling, desmear or soft etch is performed as necessary.

  In the laser irradiation, for example, the entire surface of the irradiated object is irradiated with laser light with a light shielding mask provided. However, the present invention is not limited to this, and the laser irradiation may be stopped in the non-irradiated portion without using the light shielding mask, and the laser beam may be irradiated only on the portion to be irradiated. Further, during the scanning of the laser beam, the via holes 82a and 92a and the through holes are increased by increasing the intensity (light quantity) of the laser beam applied to the site where the through holes 102a are formed rather than the site where the via holes 82a and 92a are formed. 102a can be formed by one scan. At this time, the laser intensity (light quantity) is preferably adjusted by pulse control. Specifically, for example, when changing the laser intensity, the number of shots (number of irradiations) is changed without changing the laser intensity per shot (one irradiation). That is, when a desired laser intensity cannot be obtained with one shot, the same irradiation position is irradiated with laser light again. For example, the hole 12a of the core part is formed by two shots, and the via holes 22a, 32a, 42a, 52a, 62a, 72a, 82a, and 92a of the buildup parts B1 and B2 are formed by one shot. In the formation of the through hole 102a, the number of shots is further increased. According to such a control method, the time for changing the irradiation condition can be omitted, so that it is considered that the throughput is improved. However, the method is not limited to this, and the laser intensity adjustment method is arbitrary. For example, the irradiation conditions may be determined for each irradiation position, and the number of irradiations may be fixed (for example, one shot for one irradiation position). The through hole 102a can be formed by irradiating laser light only from one side of the wiring board 1000b or by simultaneously irradiating laser light from both sides of the wiring board 1000b. Further, after forming a bottomed hole (non-through hole) by irradiating a laser beam from one side of the wiring board 1000b, the through hole 102a is formed by irradiating the laser beam from the other side and penetrating the bottom. May be. The through hole 102a can be formed by any method, and the through hole 102a may be formed by, for example, a drill.

  Subsequently, as shown in FIG. 18, plating 1023 is formed on the metal foil 1021, in the via hole 82a, on the metal foil 1022, in the via hole 92a, and in the through hole 102a by, for example, copper panel plating. The plating 1023 is formed, for example, by performing electroless plating to form an electroless plating film, and subsequently performing electroplating using the electroless plating film as a seed layer, as in the process of FIG. 12C. As a result, the via holes 82a and 92a are filled with the plating 1023, and the plating 1023 is formed on the wall surface of the through hole 102a. As a result, via conductors 82 and 92 and through-hole conductor 102 are formed. The via conductor 82 constituting the first stack structure S1 (see FIG. 1) is stacked on the same axis (Z axis) as the other via conductors 22 constituting the first stack structure S1. Further, the via conductors 92 constituting the second stack structure S2 (see FIG. 1) are stacked on the same axis (Z axis) as the other via conductors 32 constituting the second stack structure S2.

  In the present embodiment, the formation of the plating 1023 on the wall surface of the through hole 102a and the formation of the plating 1023 on the outermost via holes (via holes 82a and 92a) are performed simultaneously. For this reason, it is thought that reduction of the number of processes and by extension, cost reduction can be achieved.

  Subsequently, the conductive layers on both sides are patterned by lithography, for example. Thereby, the conductor layer 81 is formed on the insulating layer 80a, and the conductor layer 91 is formed on the insulating layer 90a. As a result, the wiring board 100 according to this embodiment shown in FIG. 1 is completed. After that, for example, by forming external connection terminals in the outermost layer, the wiring board 100 can be connected to other wiring boards or electronic components can be mounted on the wiring board 100 through the external connection terminals. .

  In addition, the formation method of a conductor pattern is arbitrary. For example, each conductor layer may be formed by a method of selectively plating only a pattern portion using a plating resist, that is, a so-called pattern plating method.

The manufacturing method of the wiring board according to the present embodiment is as follows:
Preparing a core insulating layer 10a (core substrate) having a first surface F1 and a second surface F2,
Lands 111s (first planar conductor pattern) located on the first surface F1 of the core insulating layer 10a and lands 112s (second planar conductor pattern) located on the second surface F2 of the core insulating layer 10a. And a plurality of via conductors 12s (first vias respectively) that penetrate the core insulating layer 10a, have one end (upper surface F121) connected to the common land 111s and the other end (bottom surface F122) connected to the common land 112s. Forming a conductor group 12g composed of a conductor) and a via conductor 12 (second via conductor) having substantially the same thickness as the via conductor 12s and not constituting the conductor group 12g;
Forming an insulating layer 20a (first interlayer insulating layer) on the first surface F1 and the land 111s of the core insulating layer 10a;
Via conductors 22s (through the insulating layer 20a, one end (bottom surface F222) is connected to a region defined by the outer edge of one end (upper surface F121) of each of the via conductors 12s constituting the conductor group 12g of the land 111s. Forming a third via conductor);
Forming an insulating layer 30a (second interlayer insulating layer) on the second surface F2 and the land 112s of the core insulating layer 10a;
Via conductor 32s penetrating insulating layer 30a and having one end (bottom surface F322) connected to a region defined by the outer edge of each other end (bottom surface F122) of via conductor 12s constituting conductor group 12g of land 112s. Forming a (fourth via conductor);
Forming a conductor layer 21 (first upper conductor layer) electrically connected to the land 111s via the via conductor 22s on the insulating layer 20a;
Forming a conductor layer 31 (second upper conductor layer) electrically connected to the land 112s via the via conductor 32s on the insulating layer 30a;
including.

  According to the manufacturing method of this embodiment, the wiring board 100 (FIG. 1) can be manufactured. The manufacturing method of this embodiment is suitable for manufacturing the wiring board 100. With such a manufacturing method, a good wiring board 100 can be obtained at low cost.

(Embodiment 2)
The second embodiment of the present invention will be described focusing on the differences from the first embodiment. Here, the same elements as those shown in FIG. 1 and the like are denoted by the same reference numerals, and the description of the already explained common parts, that is, the duplicated explanations, is omitted or simplified. .

  As shown in FIG. 19, the wiring board 100 a of the present embodiment has a full stack structure, like the wiring board 100 of the first embodiment. However, the stack structure S of the wiring board 100a is configured by stacking via conductors 12s, 22s, 32s, 42s, 52s, 62s, 72s, 82s, and 92s one by one on the same axis (Z axis). That is, the stack structure S of the wiring board 100a does not have a conductor group in the core portion.

  In the wiring board 100a of the present embodiment, as shown in FIG. 20, the via conductor 12s has a width of the via conductors 12s, 22s, 32s, 42s, 52s, 62s, 72s, 82s, and 92s that constitute the stack structure S. The via conductors 22s, 32s, 42s, 52s, 62s, 72s, 82s and 92s are larger than any width. Further, the via conductors 12 (via conductors 12 s) constituting the stack structure S are thicker than the via conductors 12 not constituting the stack structure S.

  Specifically, as shown in FIG. 21A, the width D11 of the upper surface F121 of the via conductor 12s and the width D12 of the bottom surface F122 of the via conductor 12s are each larger than the width D21 of the upper surface F221 of the via conductor 22s, and It is larger than the width D22 of the bottom surface F222 of the conductor 22s.

  As shown in FIG. 21B, the width D12 of the bottom surface F122 of the via conductor 12s is larger than the width D31 of the upper surface F321 of the via conductor 32s and larger than the width D32 of the bottom surface F322 of the via conductor 32s.

  Note that the via conductor 12s and each via conductor in the wiring board 100a have an upper surface with a width larger than the bottom surface. That is, the width D11 is larger than the width D12 (D11> D12), the width D21 is larger than the width D22 (D21> D22), and the width D31 is larger than the width D32 (D31> D32).

  In a preferred example, the width D11 is 125 μm, the width D12 is 105 μm, the widths D21 and D31 are each 100 μm, and the widths D22 and D32 are each 80 μm.

  The shapes and dimensions of the via conductors 42s, 62s, and 82s are the same as, for example, the shape and dimensions of the via conductor 22s, and the shapes and dimensions of the via conductors 52s, 72s, and 92s are, for example, the shapes and dimensions of the via conductor 32s, respectively. The same.

  The via conductors 12 (via conductors 12 other than the via conductors 12s) that do not constitute the stack structure S have the same shape and dimensions as the via conductors 12 (via conductors 12s) that constitute the stack structure S, as shown in FIG. Have substantially the same thickness. In the present embodiment, all via conductors formed in the core insulating layer 10a (core substrate) have substantially the same thickness.

  As shown in FIG. 21A, in the XY plane, the upper surface F221 and the bottom surface F222 of the via conductor 22s are respectively located in the region (projected region) immediately above the bottom surface F122 of the via conductor 12s. Further, as shown in FIG. 21B, in the XY plane, the upper surface F321 and the bottom surface F322 of the via conductor 32s are respectively located in the region (projected region) immediately above the bottom surface F122 of the via conductor 12s.

  In the wiring board 100a of the present embodiment, via conductors 12s formed in the core substrate (core insulating layer 10a) and via conductors 22s, 42s formed in the interlayer insulating layer of the build-up portion B1 (first stacked portion), 62s and 82s and via conductors 32s, 52s, 72s, and 92s formed in the interlayer insulating layer of the buildup portion B2 (second stacked portion) are stacked. The via conductor 12s is thicker than any of the stacked via conductors 22s, 32s, 42s, 52s, 62s, 72s, 82s, and 92s. That is, the width of the via conductor 12s is larger than any of the via conductors 22s, 32s, 42s, 52s, 62s, 72s, 82s, and 92s.

  In the wiring board 100a of this embodiment, the via conductor 12s (filled conductor) of the core insulating layer 10a (core substrate) that is particularly susceptible to stress in the stack structure S is thicker than the other via conductors (filled conductor). This increases the strength of the via conductor 12s and suppresses cracks or delamination in the core portion. In addition, thermal stress is less likely to occur in the core due to a decrease in electrical resistance of the via conductor 12s or an improvement in heat dissipation. As a result, connection reliability is improved.

  Also in the wiring board 100a of the present embodiment, the core insulating layer 10a (core substrate), the insulating layer 20a (the lowermost interlayer insulating layer of the first stacked portion), like the wiring board 100 (see FIG. 6) of the first embodiment, And the insulating layer 30a (the lowermost interlayer insulating layer of the second laminated portion) is formed by impregnating the core material with resin. The protruding amount of the core material on the side surface of the via conductor 12s formed in the core insulating layer 10a is the protruding amount of the core material on the side surface of the via conductor 22s formed in the insulating layer 20a and the via formed in the insulating layer 30a. It is larger than any of the protruding amount of the core material on the side surface of the conductor.

  According to such a structure, since the surface area in the via hole (and hence the contact area between the via conductor and the interlayer insulating layer) is increased in the core portion, the adhesion between the via conductor and the interlayer insulating layer is improved. In addition, since the CTE (thermal expansion coefficient) of the core material is smaller than the CTE of the resin constituting the interlayer insulating layer and close to the CTE of the via conductor, it is easy to reduce the crack occurrence rate at the bottom surface of the via conductor in the core portion. It is considered to be.

  The wiring board 100a of this embodiment can be manufactured by the method according to the manufacturing method of Embodiment 1. However, in the process for forming the via conductor 12s in the core insulating layer 10a (core substrate) (the process corresponding to the process shown in FIGS. 12B to 12D), the via conductor 12s (and its hole 12a) constituting the stack structure S. ) And the width of the via conductor 12s (and the hole 12a) is equal to the via conductors 22s, 32s, 42s, 52s, 62s, 72s, 82s, and 92s (and the via holes 22a) to be formed later. , 32a, 42a, 52a, 62a, 72a, 82a, 92a).

The manufacturing method of the wiring board according to the present embodiment is as follows:
Preparing a core insulating layer 10a (core substrate) having a first surface F1 and a second surface F2,
Lands 111s (first planar conductor pattern) located on the first surface F1 of the core insulating layer 10a and lands 112s (second planar conductor pattern) located on the second surface F2 of the core insulating layer 10a. A via conductor 12s (first via conductor) that penetrates through the core insulating layer 10a and has one end (upper surface F121) connected to the land 111s and the other end (bottom surface F122) connected to the land 112s; Forming via conductors 12 (second via conductors) having substantially the same thickness and not connected to any of the lands 111s and 112s (not constituting the stack structure S);
Forming an insulating layer 20a (first interlayer insulating layer) on the first surface F1 and the land 111s of the core insulating layer 10a;
Forming a via conductor 22s (third via conductor) that is thinner than the via conductor 12s, penetrates the insulating layer 20a, and is connected to the land 111s;
Forming an insulating layer 30a (second interlayer insulating layer) on the second surface F2 and the land 112s of the core insulating layer 10a;
Forming a via conductor 32s (fourth via conductor) that is thinner than the via conductor 12s, penetrates the insulating layer 30a, and is connected to the land 112s;
Forming a conductor layer 21 (first upper conductor layer) electrically connected to the land 111s via the via conductor 22s on the insulating layer 20a;
Forming a conductor layer 31 (second upper conductor layer) electrically connected to the land 112s via the via conductor 32s on the insulating layer 30a;
including.

  According to the manufacturing method of this embodiment, the wiring board 100a (FIG. 19) can be manufactured. The manufacturing method of this embodiment is suitable for manufacturing the wiring board 100a. With such a manufacturing method, a good wiring board 100a can be obtained at low cost.

  With regard to the same configuration and processing as in the first embodiment, an effect similar to the effect of the first embodiment described above can also be obtained in this embodiment.

(Other embodiments)
As shown in FIG. 22A or 22B, an opening 111d (first opening) that penetrates the metal foil 111a, an opening 112d (second opening) that penetrates the metal foil 112a, and the core insulating layer 10a. And the opening 111d, the opening 112d, and the hole 12a are connected to form the core insulating layer 10a, the metal foil 111a, and the opening that penetrates the metal foil 112a. May be. A conductor having a hole (for example, a small hole) formed on the bottom is also referred to as a via conductor.

  In the example of FIG. 22A or 22B, the metal foil 111a (first metal foil), the electroless plating film 111b, and the electrolytic plating 111c (first plating) are formed on the first surface F1 of the core insulating layer 10a (core substrate). ) Is formed, and the metal foil 112a (second metal foil) and the electroless layer are formed on the second surface F2 of the core insulating layer 10a (core substrate). A conductor layer 11b (second conductor layer) composed of the plating film 112b and the electrolytic plating 112c (second plating) is formed.

  The openings (opening 111d, opening 112d, and hole 12a) are formed prior to plating for forming the via conductor 12 and the conductor layers 11a and 11b, for example. For this reason, the electroless plating film 110b that constitutes the via conductor 12s, the electroless plating film 111b that constitutes the conductor layer 11a, and the electroless plating film 112b that constitutes the conductor layer 11b are integrated with each other (without a break). And the electroplating 110c constituting the via conductor 12s, the electroplating 111c constituting the conductor layer 11a, and the electroplating 112c constituting the conductor layer 11b are formed integrally (without a break). The According to such a structure, it is considered that cracks at the bottom surface F122 of the via conductor 12s or delamination between the bottom surface F122 and the conductor layer 11b is less likely to occur.

  The via conductor 12 as shown in FIG. 22A or FIG. 22B is formed in a state where both ends of the hole penetrating the insulating layer are not blocked by the conductor layer. For this reason, the via conductor and the conductor layer on both sides of the insulating layer are continuous. Hereinafter, a method for forming the core portion illustrated in FIG. 22A will be described in detail.

  After preparing the double-sided copper-clad laminate 1000 (see, for example, FIG. 12A), as shown in FIG. 23A, openings 110e that penetrate the metal foils 111a, 112a and the core insulating layer 10a are formed by, for example, a laser. The opening 110e includes an opening 111d (first opening) penetrating the metal foil 111a, an opening 112d (second opening) penetrating the metal foil 112a, and a hole 12a (first opening) penetrating the core insulating layer 10a. 3 openings). In the present embodiment, since the opening 111d, the hole 12a, and the opening 112d are formed continuously (for example, by continuous laser irradiation), the width of the opening 112d is the width of the hole 12a in the second surface F2. Is approximately the same. After the opening 110e is formed, desmear or soft etching is performed as necessary.

  For example, the entire opening 110e can be formed by irradiating laser light from one side. However, the present invention is not limited to this. After forming only the opening 111d and the hole 12a (bottomed hole) by irradiating laser light from one side, the laser beam is irradiated from the other side to penetrate the bottom, thereby opening the opening. The portion 112d may be formed.

  Subsequently, as shown in FIG. 23B, plating 1001 is formed on the metal foil 111a, the metal foil 112a, and the opening 110e by, for example, copper panel plating. Thereby, the opening 110e is filled with the plating 1001. As a result, a via conductor 12 (including two via conductors 12s constituting the conductor group 12g) is formed. The plating 1001 is formed, for example, by performing electroless plating to form an electroless plating film, and subsequently performing electroplating using the electroless plating film as a seed layer. Plating 1001 constitutes electroless plating films 110b, 111b, and 112b and electrolytic platings 110c, 111c, and 112c shown in FIG. 22A.

  By the above formation method, all via conductors formed in the core insulating layer 10a (core substrate) can be structured as shown in FIG. 22A or 22B.

  The width of the opening 112d formed in the metal foil 112a is preferably substantially the same as the width of the hole 12a in the second surface F2 (bottom surface F122), for example. However, the present invention is not limited to this. For example, as shown in FIG. 24A or FIG. 24B, the width of the opening 112d formed in the metal foil 112a may be smaller than the width of the hole 12a in the second surface F2 (bottom surface F122). . Also in this case, the electroless plating film 110b that constitutes the via conductor 12s, the electroless plating film 111b that constitutes the conductor layer 11a, and the electroless plating film 112b that constitutes the conductor layer 11b are integrally formed with each other (interval). And the electroplating 110c constituting the via conductor 12s, the electroplating 111c constituting the conductor layer 11a, and the electroplating 112c constituting the conductor layer 11b are formed integrally (without breaks). Is done. The opening 112d is formed by, for example, forming the opening 111d and the hole 12a by laser (first laser irradiation) and then irradiating the metal foil 112a with a laser having a smaller diameter than the first laser irradiation (second laser irradiation). It can be formed by laser irradiation).

  The number of openings 112d having a width D13 smaller than the width D12 of the hole 12a in the second surface F2 (bottom surface F122) may be one as shown in FIG. 25A or as shown in FIG. 25B. Multiple (for example, four) may be sufficient. The opening 112d formed in the metal foil 112a may be disposed at the center or at the end of the bottom surface F122 of the via conductor 12s in the XY plane.

  25A and 25B, the width D12 of the hole 12a on the second surface F2 (bottom surface F122) is, for example, 80 μm, and the width D13 of the opening 112d is, for example, 15 μm.

  In the wiring board (for example, see Embodiment 1) having the conductor group 12g constituting the stack structure S in the core portion, the arrangement of each of the via conductors 12s (filled conductors) constituting the conductor group 12g is shown in FIG. It is not restricted to what was shown to 4B. For example, as shown in FIGS. 26A and 26B, in the XY plane, a part of the via conductors 22s and 32s formed in the insulating layers 20a and 30a on the core insulating layer 10a (core substrate) is formed in the core insulating layer 10a. The plurality of via conductors 12s may be arranged so as to protrude from the regions R11 and R12 defined by the outer edges of the via conductors 12s. If at least a part of the via conductors 22s and 32s is in the regions R11 and R12, it is considered that effects such as improvement in electrical connection reliability are exhibited.

  In the example of FIG. 26A, in the XY plane, a part of the bottom surface F222 of the via conductor 22s is located in the region R11 defined by the outer edge of the top surface F121 of the two via conductors 12s, and the bottom surface F222 of the via conductor 22s. The other portion protrudes from the region R11. In the example of FIG. 26B, in the XY plane, a part of the bottom surface F322 of the via conductor 32s is located in the region R12 defined by the outer edge of the bottom surface F122 of the two via conductors 12s, and the bottom surface F322 of the via conductor 32s. The other part of the region protrudes from the region R12.

  In the first embodiment, the number of via conductors 12s constituting the conductor group 12g is two, but the present invention is not limited to this. For example, as shown in FIG. 27A, a conductor group 12g may be formed in the core insulating layer 10a by three via conductors 12s arranged at the vertices of an equilateral triangle. For example, as shown in FIG. 27B, a conductor group 12g may be formed in the core insulating layer 10a by four via conductors 12s arranged at the vertices of a regular square. Also in these cases, if at least a part of the via conductors 22s and 32s is connected to the region R11 (or the region R12) defined by the outer edges of the three or four via conductors 12s in the XY plane, It is considered that effects such as improvement in the connection reliability are achieved.

  In the first embodiment, the number of the via conductors 22s and 32s that are formed in the insulating layer 20a or 30a on the core insulating layer 10a (core substrate) and form the stack structure S is one, but the number is limited to this. Absent. For example, as shown in FIG. 28A, a plurality (for example, two) of via conductors 22s constituting the stack structure S may be formed in the insulating layer 20a. Alternatively, a plurality (for example, two) of via conductors 32s constituting the stack structure S may be formed in the insulating layer 30a. For example, as shown in FIG. 28B, a plurality of (for example, two) via conductors 22s constituting the stack structure S are formed in the insulating layer 20a, and a plurality (for example, constituting the stack structure S in the insulating layer 30a). For example, two via conductors 32s may be formed.

  When the number of via conductors 22s formed in the insulating layer 20a on the core insulating layer 10a (core substrate) and constituting the stack structure S is two or more, the conductor group 12g is formed as shown in FIG. 29A, for example. The via conductors 22s may be arranged on the same axis of the via conductors 12s. For example, as shown in FIG. 29B or FIG. 29C, via conductors 22s may be arranged between adjacent via conductors 12s. Such an arrangement can also be applied to the via conductor 32s.

  Of the via conductors constituting the stack structure S, a plurality of via conductors 22s and 32s above the via conductors 22s and 32s may be provided. However, in order to increase the electrical connection reliability efficiently with a small number of via conductors, it is desirable to selectively increase the number of via conductors around the core portion where the stress is particularly likely to occur in the stack structure S.

  In a wiring board having a thick via conductor (filled conductor) in the core portion constituting the stack structure S (see, for example, Embodiment 2), the relationship between the dimensions of the via conductors 12s constituting the stack structure S is shown in FIG. It is not restricted to what was shown to FIG. 21B.

  For example, as shown in FIG. 30A, the width D11 (the maximum width of the via conductor 12s) of the upper surface F121 of the via conductor 12s is made larger than the width D21 (the maximum width of the via conductor 22s) of the upper surface F221 of the via conductor 22s. The width D12 of the bottom surface F122 of the conductor 12s may be smaller than the width D21 of the top surface F221 of the via conductor 22s. For example, as shown in FIG. 30B, the width D11 of the upper surface F121 of the via conductor 12s (the maximum width of the via conductor 12s) is made larger than the width D31 of the upper surface F321 of the via conductor 32s (the maximum width of the via conductor 32s). The width D12 of the bottom surface F122 of the via conductor 12s may be smaller than the width D31 of the upper surface F321 of the via conductor 32s and larger than the width D32 of the bottom surface F322 of the via conductor 32s.

  Of the via conductor 12s and the via conductors 22s, 32s, 42s, 52s, 62s, 72s, 82s, and 92s constituting the stack structure S, the via conductor 12s formed on the core insulating layer 10a (core substrate) If the via conductors 22s, 32s, 42s, 52s, 62s, 72s, 82s, and 92s formed in B1 and B2 (the first laminated portion or the second laminated portion) are thicker, the electrical connection reliability is improved. Such effects are considered to be achieved.

  In the second embodiment, the number of via conductors 22s and 32s that are formed in the insulating layer 20a or 30a on the core insulating layer 10a (core substrate) and form the stack structure S is one, but this is not limitative. . There may be a plurality of via conductors 22s, 32s. For example, as shown in FIG. 31A, a plurality (for example, two) of via conductors 22s constituting the stack structure S may be formed in the insulating layer 20a. Alternatively, a plurality (for example, two) of via conductors 32s constituting the stack structure S may be formed in the insulating layer 30a. For example, as shown in FIG. 31B, a plurality of (for example, two) via conductors 22s constituting the stack structure S are formed in the insulating layer 20a, and a plurality (for example, constituting the stack structure S in the insulating layer 30a). For example, two via conductors 32s may be formed.

  When the number of via conductors 22s and 32s formed in the insulating layer 20a or 30a on the core insulating layer 10a (core substrate) and constituting the stack structure S is 2 or more, for example, as shown in FIG. In the −Y plane, a plurality of (for example, three) via conductors 22s are respectively provided in the region (projected region) immediately above the upper surface F121 of the via conductor 12s formed in the core insulating layer 10a (core substrate). May be included. Alternatively, for example, as shown in FIG. 32B, in the XY plane, a plurality of (for example, three) via conductors 22s are included in the region immediately above the upper surface F121 of the via conductor 12s, respectively, and a part of the bottom surface F222 is included. You may arrange | position so that another part may be contained in the area | region between the upper surface F121 of the via conductor 12s, and the land 111s. Alternatively, for example, as illustrated in FIG. 32C, the entire bottom surface F222 of the via conductor 22s may be disposed in the region between the top surface F121 of the via conductor 12s and the land 111s in the XY plane. . 32A to 32C, since the bottom surface F222 of the via conductor 22s does not protrude from the land 111s of the lower via conductor 12s, the via conductor 22s is stacked on the via conductor 12s. I can say that. The same arrangement can be applied to the via conductor 32s.

  The via conductors 12 s, 22 s, 32 s, 42 s, 52 s, 62 s, 72 s, 82 s, 92 s, the through-hole conductor 102, and the planar shape (XY plane) of their openings (holes) are circles (perfect circles or ellipses). Etc.) and is arbitrary. These planar shapes may be substantially square as shown in FIG. 33A, for example. Further, it may be a substantially regular polygon other than a substantially square, such as a substantially regular hexagon or a substantially regular octagon. In addition, the shape of the polygonal corner is arbitrary, and may be rounded, for example, substantially right angle, acute angle, obtuse angle. However, in order to prevent concentration of thermal stress, it is preferable that the corners are rounded.

  Further, each of the planar shapes may be a substantially rectangular shape or a substantially triangular shape, or a shape in which a straight line is drawn radially from the center, such as a substantially cross shape shown in FIG. 33B or a substantially regular polygonal star shape shown in FIG. 33C. (A shape in which a plurality of blades are arranged radially) may be used.

  As shown in FIG. 34A or 34B, the core substrate (core insulating layer 10a), the lowermost interlayer insulating layer (insulating layer 20a) of the first stacked portion (build-up portion B1), and the second stacked portion (build-up) The lowermost interlayer insulating layer (insulating layer 30a) of part B2) has higher heat resistance than the material constituting any of the other interlayer insulating layers (insulating layers 40a, 50a, 60a, 70a, 80a, 90a) It may consist of materials. Specifically, for example, the core insulating layer 10a and the insulating layers 20a and 30a are each made of FR-5 material, and the insulating layers 40a, 50a, 60a, 70a, 80a and 90a are each made of FR-4 material. Is done. According to such a structure, the heat resistance around the core portion where large stress is likely to occur is improved.

  Further, only the core substrate (core insulating layer 10a) includes the core material, and the other interlayer insulating layers may not include the core material. Further, only the core substrate (core insulating layer 10a) and the insulating layers 20a and 30a include the core material, and the other interlayer insulating layers may not include the core material. Moreover, as long as sufficient heat resistance can be ensured in the core part, the insulating layers of all layers may not include the core material.

  As shown in FIG. 35, solder resists 1031 and 1032 having openings 1031a and 1032a are formed in the outermost layer, and solder 1031b is respectively applied to pads (conductor layers 81 and 91) exposed in the openings 1031a and 1032a. The electronic component 200 may be mounted via 1032b. In the example of FIG. 35, the electronic component 200 is mounted on both sides, but the electronic component may be mounted only on one side.

  In the example of FIG. 35, the electronic component is mounted on the wiring board (for example, see Embodiment 1) having the conductor group 12g constituting the stack structure S in the core portion, but is not limited thereto. For example, an electronic component may be similarly mounted on a wiring board (see, for example, the second embodiment) having a thick via conductor in the core portion constituting the stack structure S. Such an electronic device can be used for a circuit board of a portable device (such as a mobile phone).

  As shown in FIG. 36, the outermost via conductors may each be a conformal conductor. In the example of FIG. 36, the via conductors 82 and 92 of the wiring board shown in FIG. 1 are each formed of a conformal conductor.

  With respect to other points as well, the configuration of the wiring boards 100 and 100a of the above-described embodiments, in particular, the type, performance, dimensions, material, shape, number of layers, or arrangement of the components do not depart from the spirit of the present invention. The range can be arbitrarily changed.

  For example, a side surface (or a wall surface of each opening) such as a via conductor may be tapered or not tapered.

  The method for manufacturing a wiring board according to the present invention is not limited to the order and contents shown in the embodiment, and the order and contents can be arbitrarily changed without departing from the gist of the present invention. Moreover, you may omit the process which is not required according to a use etc.

  The said embodiment and modification can be combined arbitrarily. It is preferable to select an appropriate combination according to the application.

  The embodiment of the present invention has been described above. However, various modifications and combinations required for design reasons and other factors are not limited to the invention described in the “claims” or the “mode for carrying out the invention”. It should be understood that it is included in the scope of the invention corresponding to the specific examples described in the above.

  The wiring board according to the present invention is suitable for a circuit board such as a mobile phone. The method for manufacturing a wiring board according to the present invention is suitable for manufacturing such a wiring board.

10a Core insulating layer 10s Via conductor 11a, 11b Conductor layer 11w Wiring 12 Via conductor 12a Hole 12a Conductor layer 12g Conductor group 12s Via conductor 20a, 40a, 60a, 80a Insulating layer 21, 41, 61, 81 Conductor layer 22, 42, 62, 82 Via conductor 22a, 42a, 62a, 82a Via hole 22s, 42s, 62s, 82s Via conductor 30a, 50a, 70a, 90a Insulating layer 31, 51, 71, 91 Conductive layer 32, 52, 72, 92 Via conductor 32a , 52a, 72a, 92a Via hole 32s, 52s, 72s, 92s Via conductor 81a, 91a Land 100, 100a Wiring board 102 Through hole conductor 102a Through hole 110b Electroless plating film 110c Electrolytic plating 110d, 110e Opening 111a, 112a Gold Foil 111b, 112b Electroless plating film 111c, 112c Electrolytic plating 111d, 112d Opening 111s, 112s Land 200 Electronic component 211a, 411a, 611a, 811a Metal foil 211b, 411b, 611b, 811b Electroless plating film 211c, 411c, 611c , 811c Electrolytic plating 211s, 411s, 611s, 811s Lands 311a, 511a, 711a, 911a Metal foils 311b, 511b, 711b, 911b Electroless plating films 311c, 511c, 711c, 911c Electrolytic plating 311s, 511s, 711s, 911s Lands Double-sided copper-clad laminate 1000a, 1000b Wiring board 1001 Plating 1011, 1012 Metal foil 1021, 1022 Metal foil 1023 Plating 1031, 10 32 Solder resist 1031a, 1032a Opening 1031b, 1032b Solder B1, B2 Build-up part F1 First surface F2 Second surface F121, F221, F321 Upper surface F122, F222, F322 Bottom surface R11, R12 Region S Stack structure S1 First stack structure S2 Second stack structure

Claims (27)

A core substrate having a first surface and a second surface;
A first stacked portion formed on the first surface of the core substrate and including at least one pair of interlayer insulating layers and conductor layers;
A second stacked portion formed on the second surface of the core substrate and including at least one pair of interlayer insulating layers and conductor layers;
A wiring board having
The core substrate is made of a material having higher heat resistance than a material constituting any of the interlayer insulating layer of the first stacked unit and the interlayer insulating layer of the second stacked unit,
A first planar conductor pattern is formed on the first surface of the core substrate, and a second planar conductor pattern is formed on the second surface of the core substrate,
A plurality of first via conductors constituting a conductor group and a second via conductor not constituting the conductor group are formed on the core substrate, and a first interlayer insulating layer in the lowermost layer of the first stacked portion includes a first via conductor. 3 via conductors are formed, a fourth via conductor is formed in the lowermost interlayer insulating layer of the second stacked portion,
The first via conductor and the second via conductor have substantially the same thickness.
Each of the first via conductors constituting the conductor group is connected to the first planar conductor pattern having one end and the second planar conductor pattern having the other end common,
One end of the third via conductor is connected to a region of the first planar conductor pattern defined by an outer edge of one end of each first via conductor constituting the conductor group, and one end of the fourth via conductor. Is connected to a region defined by the outer edge of the other end of each first via conductor constituting the conductor group of the second planar conductor pattern,
A wiring board characterized by that. A core substrate having a first surface and a second surface;
A first stacked portion formed on the first surface of the core substrate and including at least one pair of interlayer insulating layers and conductor layers;
A second stacked portion formed on the second surface of the core substrate and including at least one pair of interlayer insulating layers and conductor layers;
A wiring board having
The core substrate, the lowermost interlayer insulating layer of the first stacked portion, and the lowermost interlayer insulating layer of the second stacked portion are interlayer insulating layers other than the lowermost interlayer insulating layer in the first stacked portion. And a material having higher heat resistance than a material constituting any of the interlayer insulating layers other than the lowermost interlayer insulating layer in the second stacked portion,
A first planar conductor pattern is formed on the first surface of the core substrate, and a second planar conductor pattern is formed on the second surface of the core substrate,
A plurality of first via conductors constituting a conductor group and a second via conductor not constituting the conductor group are formed on the core substrate, and a first interlayer insulating layer in the lowermost layer of the first stacked portion includes a first via conductor. 3 via conductors are formed, a fourth via conductor is formed in the lowermost interlayer insulating layer of the second stacked portion,
The first via conductor and the second via conductor have substantially the same thickness.
Each of the first via conductors constituting the conductor group is connected to the first planar conductor pattern having one end and the second planar conductor pattern having the other end common,
One end of the third via conductor is connected to a region of the first planar conductor pattern defined by an outer edge of one end of each first via conductor constituting the conductor group, and one end of the fourth via conductor. Is connected to a region defined by the outer edge of the other end of each first via conductor constituting the conductor group of the second planar conductor pattern,
A wiring board characterized by that. Each of the first via conductors constituting the conductor group, the third via conductor, and the fourth via conductor have substantially the same thickness.
The wiring board according to claim 1 or 2 , wherein Each of the first stacked unit and the second stacked unit includes at least four sets of interlayer insulating layers and conductor layers,
On the third via conductor, via conductors formed in the interlayer insulating layer of the first stacked portion are stacked, whereby the first stacked portion includes first via conductors having four or more stages. A stack structure is formed,
On the fourth via conductor, a via conductor formed in the interlayer insulating layer of the second stacked unit is stacked, so that the second stacked unit includes a second layer composed of four or more stages of via conductors. A stack structure is formed,
The wiring board as described in any one of Claims 1 thru | or 3 characterized by the above-mentioned. Via conductors in all layers of the first stacked portion including the third via conductor constitute a first stack structure, and via conductors in all layers of the second stacked portion including the fourth via conductor are in a second stack structure. Make up,
The wiring board as described in any one of Claims 1 thru | or 4 characterized by the above-mentioned. All via conductors constituting the first stack structure have substantially the same thickness, and all via conductors constituting the second stack structure have substantially the same thickness,
The wiring board according to claim 5 . Each of the first via conductors constituting the conductor group is composed of plating,
A first conductor layer composed of a first metal foil and a first plating is formed on the first surface of the core substrate,
A second conductor layer composed of a second metal foil and a second plating is formed on the second surface of the core substrate,
The plating that constitutes the first via conductor, the first plating, and the second plating are performed by filling an opening that penetrates the core substrate, the first metal foil, and the second metal foil. Are formed integrally with each other,
Wiring board according to any one of claims 1 to 6, characterized in that. The opening that penetrates the core substrate, the first metal foil, and the second metal foil includes a first opening that penetrates the first metal foil and a second opening that penetrates the second metal foil. And a third opening that penetrates the core substrate,
The third opening is tapered so as to become thinner from the first surface toward the second surface,
A width of the second opening is smaller than a width of the third opening in the second surface;
The wiring board according to claim 7 . The core substrate is made of a material having higher heat resistance than a material constituting any of the interlayer insulating layer of the first stacked unit and the interlayer insulating layer of the second stacked unit.
The wiring board according to claim 2 . The core substrate is made of FR-5 material,
The interlayer insulating layer of the first stacked portion and the interlayer insulating layer of the second stacked portion are each made of FR-4 material.
The wiring board according to any one of claims 1 to 9, wherein: Each of the core substrate, the lowermost interlayer insulating layer of the first stacked portion, and the lowermost interlayer insulating layer of the second stacked portion is made of FR-5 material,
The interlayer insulating layer other than the lowermost interlayer insulating layer in the first stacked portion and the interlayer insulating layer other than the lowermost interlayer insulating layer in the second stacked portion are each made of FR-4 material. ,
The wiring board according to any one of claims 1 to 9, wherein: Formed in the lowermost interlayer insulating layer of the first laminated portion, one end of the first planar conductor pattern in a region defined by the outer edge of one end of each first via conductor constituting the conductor group A plurality of the third via conductors to be connected;
The wiring board according to any one of claims 1 to 11, wherein: A region formed in the lowermost interlayer insulating layer of the second stacked portion and having one end defined by the outer edge of the other end of each first via conductor constituting the conductor group of the second planar conductor pattern A plurality of the fourth via conductors connected to
The wiring board according to claim 12. A core substrate having a first surface and a second surface;
A first stacked portion formed on the first surface of the core substrate and including at least one pair of interlayer insulating layers and conductor layers;
A second stacked portion formed on the second surface of the core substrate and including at least one pair of interlayer insulating layers and conductor layers;
A wiring board having
The core substrate is made of a material having higher heat resistance than a material constituting any of the interlayer insulating layer of the first stacked unit and the interlayer insulating layer of the second stacked unit,
A first via conductor formed on the core substrate; a third via conductor formed on at least one interlayer insulating layer of the first stacked portion; and at least one interlayer insulating layer of the second stacked portion. The fourth via conductor is stacked,
A second via conductor not stacked is formed on the core substrate;
Each of the first via conductor and the second via conductor has substantially the same thickness as each other,
The first via conductor is thicker than any of the stacked third and fourth via conductors,
A wiring board characterized by that. A core substrate having a first surface and a second surface;
A first stacked portion formed on the first surface of the core substrate and including at least one pair of interlayer insulating layers and conductor layers;
A second stacked portion formed on the second surface of the core substrate and including at least one pair of interlayer insulating layers and conductor layers;
A wiring board having
The core substrate, the lowermost interlayer insulating layer of the first stacked portion, and the lowermost interlayer insulating layer of the second stacked portion are interlayer insulating layers other than the lowermost interlayer insulating layer in the first stacked portion. And a material having higher heat resistance than a material constituting any of the interlayer insulating layers other than the lowermost interlayer insulating layer in the second stacked portion,
A first via conductor formed on the core substrate; a third via conductor formed on at least one interlayer insulating layer of the first stacked portion; and at least one interlayer insulating layer of the second stacked portion. The fourth via conductor is stacked,
A second via conductor not stacked is formed on the core substrate;
Each of the first via conductor and the second via conductor has substantially the same thickness as each other,
The first via conductor is thicker than any of the stacked third and fourth via conductors,
A wiring board characterized by that. Each of the first stacked unit and the second stacked unit includes at least four sets of interlayer insulating layers and conductor layers,
The first stacked portion is formed with a first stack structure composed of four or more third via conductors,
In the second stacked portion, a second stack structure composed of four or more fourth via conductors is formed.
The wiring board according to claim 14 or 15, wherein The third via conductors in all layers of the first stacked portion constitute a first stack structure, and the fourth via conductors in all layers of the second stacked portion constitute a second stack structure.
The wiring board according to any one of claims 14 to 16, wherein the wiring board is characterized in that All third via conductors constituting the first stack structure have substantially the same thickness, and all fourth via conductors constituting the second stack structure have substantially the same thickness,
The wiring board according to claim 17. The first via conductor is composed of plating,
A first conductor layer composed of a first metal foil and a first plating is formed on the first surface of the core substrate,
A second conductor layer composed of a second metal foil and a second plating is formed on the second surface of the core substrate,
The plating that constitutes the first via conductor, the first plating, and the second plating are performed by filling an opening that penetrates the core substrate, the first metal foil, and the second metal foil. Are formed integrally with each other,
The wiring board according to any one of claims 14 to 18, characterized in that: The opening that penetrates the core substrate, the first metal foil, and the second metal foil includes a first opening that penetrates the first metal foil and a second opening that penetrates the second metal foil. And a third opening that penetrates the core substrate,
The third opening is tapered so as to become thinner from the first surface toward the second surface,
A width of the second opening is smaller than a width of the third opening in the second surface;
The wiring board according to claim 19. The core substrate, the lowermost interlayer insulating layer of the first stacked portion, and the lowermost interlayer insulating layer of the second stacked portion are interlayer insulating layers other than the lowermost interlayer insulating layer in the first stacked portion. And made of a material having higher heat resistance than the material constituting any of the interlayer insulating layers other than the lowermost interlayer insulating layer in the second stacked portion,
The wiring board according to claim 14 . A plurality of third via conductors stacked on the first via conductor in the lowermost interlayer insulating layer of the first stacked unit;
The wiring board according to any one of claims 14 to 21 , wherein the wiring board is characterized in that A plurality of fourth via conductors stacked on the first via conductor in the lowermost interlayer insulating layer of the second stacked portion;
The wiring board according to claim 22 . A method of manufacturing a wiring board comprising: a core substrate; and at least one set of interlayer insulating layers and conductor layers laminated on both surfaces of the core substrate,
A core substrate made of a material having higher heat resistance than the material constituting the interlayer insulating layer and having a first surface and a second surface;
A first planar conductor pattern located on the first surface of the core substrate, a second planar conductor pattern located on the second surface of the core substrate, respectively, penetrating the core substrate, A conductor group composed of a plurality of first via conductors having one end connected to the common first planar conductor pattern and the other end connected to the common second planar conductor pattern; Forming a second via conductor having substantially the same thickness as the via conductor and not constituting the conductor group;
Forming a first interlayer insulating layer on the first surface and the first planar conductor pattern of the core substrate;
A third via that penetrates through the first interlayer insulating layer and has one end connected to a region defined by an outer edge of one end of each first via conductor constituting the conductor group of the first planar conductor pattern. Forming a conductor;
Forming a second interlayer insulating layer on the second surface and the second planar conductor pattern of the core substrate;
A fourth connected to a region penetrating the second interlayer insulating layer and having one end defined by the outer edge of the other end of each first via conductor constituting the conductor group of the second planar conductor pattern; Forming via conductors;
Forming a first upper conductor layer electrically connected to the first planar conductor pattern via the third via conductor on the first interlayer insulating layer;
Forming a second upper conductor layer electrically connected to the second planar conductor pattern via the fourth via conductor on the second interlayer insulating layer;
including,
A method for manufacturing a wiring board. A method of manufacturing a wiring board comprising: a core substrate; and at least one set of interlayer insulating layers and conductor layers laminated on both surfaces of the core substrate,
A core substrate made of a material having higher heat resistance than a material constituting the interlayer insulating layer other than the first interlayer insulating layer and the second interlayer insulating layer included in the interlayer insulating layer, and having a first surface and a second surface. To prepare,
A first planar conductor pattern located on the first surface of the core substrate, a second planar conductor pattern located on the second surface of the core substrate, respectively, penetrating the core substrate, A conductor group composed of a plurality of first via conductors having one end connected to the common first planar conductor pattern and the other end connected to the common second planar conductor pattern; Forming a second via conductor having substantially the same thickness as the via conductor and not constituting the conductor group;
And that the core on the first surface of the substrate and the first planar conductor pattern is formed over the first interlayer insulating layer,
A third via that penetrates through the first interlayer insulating layer and has one end connected to a region defined by an outer edge of one end of each first via conductor constituting the conductor group of the first planar conductor pattern. Forming a conductor;
And that the core on the second surface of the substrate and the second planar conductor pattern is formed over the second interlayer insulating layer,
A fourth connected to a region penetrating the second interlayer insulating layer and having one end defined by the outer edge of the other end of each first via conductor constituting the conductor group of the second planar conductor pattern; Forming via conductors;
Forming a first upper conductor layer electrically connected to the first planar conductor pattern via the third via conductor on the first interlayer insulating layer;
Forming a second upper conductor layer electrically connected to the second planar conductor pattern via the fourth via conductor on the second interlayer insulating layer;
including,
A method for manufacturing a wiring board. A method of manufacturing a wiring board comprising: a core substrate; and at least one set of interlayer insulating layers and conductor layers laminated on both surfaces of the core substrate,
A core substrate made of a material having higher heat resistance than the material constituting the interlayer insulating layer and having a first surface and a second surface;
A first planar conductor pattern located on the first surface of the core substrate; a second planar conductor pattern located on the second surface of the core substrate; and one end penetrating the core substrate. Has a first via conductor connected to the first planar conductor pattern and the other end connected to the second planar conductor pattern, respectively, and a thickness substantially the same as the first via conductor, Forming a first via conductor pattern and a second via conductor not connected to any of the second planar conductor pattern;
Forming a first interlayer insulating layer on the first surface and the first planar conductor pattern of the core substrate;
Forming a third via conductor that is narrower than the first via conductor, penetrates the first interlayer insulating layer, and is connected to the first planar conductor pattern;
Forming a second interlayer insulating layer on the second surface and the second planar conductor pattern of the core substrate;
Forming a fourth via conductor that is narrower than the first via conductor, penetrates the second interlayer insulating layer, and is connected to the second planar conductor pattern;
Forming a first upper conductor layer electrically connected to the first planar conductor pattern via the third via conductor on the first interlayer insulating layer;
Forming a second upper conductor layer electrically connected to the second planar conductor pattern via the fourth via conductor on the second interlayer insulating layer;
including,
A method for manufacturing a wiring board. A method of manufacturing a wiring board comprising: a core substrate; and at least one set of interlayer insulating layers and conductor layers laminated on both surfaces of the core substrate,
A core substrate made of a material having higher heat resistance than a material constituting the interlayer insulating layer other than the first interlayer insulating layer and the second interlayer insulating layer included in the interlayer insulating layer, and having a first surface and a second surface. To prepare,
A first planar conductor pattern located on the first surface of the core substrate; a second planar conductor pattern located on the second surface of the core substrate; and one end penetrating the core substrate. Has a first via conductor connected to the first planar conductor pattern and the other end connected to the second planar conductor pattern, respectively, and a thickness substantially the same as the first via conductor, Forming a first via conductor pattern and a second via conductor not connected to any of the second planar conductor pattern;
And that the core on the first surface of the substrate and the first planar conductor pattern is formed over the first interlayer insulating layer,
Forming a third via conductor that is narrower than the first via conductor, penetrates the first interlayer insulating layer, and is connected to the first planar conductor pattern;
And that the core on the second surface of the substrate and the second planar conductor pattern is formed over the second interlayer insulating layer,
Forming a fourth via conductor that is narrower than the first via conductor, penetrates the second interlayer insulating layer, and is connected to the second planar conductor pattern;
Forming a first upper conductor layer electrically connected to the first planar conductor pattern via the third via conductor on the first interlayer insulating layer;
Forming a second upper conductor layer electrically connected to the second planar conductor pattern via the fourth via conductor on the second interlayer insulating layer;
including,
A method for manufacturing a wiring board.

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