JP5384878B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor device and a manufacturing technology thereof, and more particularly to a semiconductor device including an IGBT (Insulated Gate Bipolor Transistor) and a technology effective when applied to the manufacturing thereof.

Japanese Patent Laying-Open No. 2008-85050 (Patent Document 1) describes a technique capable of realizing an IGBT having a high breakdown voltage and excellent switching characteristics. Specifically, activation annealing of n-type impurity ions implanted to form a field stop layer (n ⁺ type semiconductor region) and ion implantation to form a collector region (p ⁺ type semiconductor region). The activation annealing of the p-type impurity ions is performed in a separate process, the activation rate of the n-type impurity ions in the field stop layer is set to 60% or more, and the activation rate of the p-type impurity ions in the collector region is 1 to 15 %, An IGBT having a high breakdown voltage and high-speed switching characteristics can be formed. Furthermore, by using a laminated film made of a nickel silicide film, a titanium film, a nickel film and a gold film for the collector electrode, ohmic contact with the collector region becomes possible, and corrosion due to moisture or the like of the collector electrode can be prevented. It is said.
JP 2008-85050 A

  An IGBT is a semiconductor element that combines high-speed switching characteristics and voltage drive characteristics of a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) and low on-voltage characteristics of a bipolar transistor. The IGBT having such characteristics is mainly used in the field of power electronics. The power electronics field is a field in which electric power is converted and controlled by controlling a large current and a high voltage (high withstand voltage) in an electric circuit. Specifically, IGBTs have been applied to industrial fields such as general-purpose inverters, AC servos, uninterruptible power supplies, and switching power supplies, as well as consumer devices such as microwave ovens and rice cookers. A general-purpose inverter of an electronic application device that controls a motor is used to control a belt conveyor, a fan control, a pump, and the like, and an AC servo is used to control a motor of a robot, a semiconductor manufacturing apparatus, and the like.

Since IGBT is used in the field of power electronics as described above, high voltage resistance is required. For this reason, the IGBT has an n ⁻ type base layer necessary for increasing the breakdown voltage. During the operation of the IGBT, a low on-voltage is secured by accumulating electrons and holes (carriers) in this n ⁻ -type base layer. Therefore, in the IGBT, the on-voltage during operation can be lowered as the accumulation amount of electrons and holes (carriers) accumulated in the n ⁻ type base layer is increased. However, the carriers accumulated in the n ⁻ -type base layer cause a phenomenon that the IGBT turn-off fall time is lengthened (hereinafter referred to as “turn-off loss”). Therefore, if a large amount of carriers are accumulated in the n ⁻ -type base layer in order to reduce the on-voltage during the operation of the IGBT, the turn-off loss of the IGBT increases. That is, in the IGBT, the reduction of the on-voltage and the turn-off loss are in a trade-off relationship. It is necessary to improve the performance of the IGBT to reduce the on-voltage and improve the turn-off loss, which are in a trade-off relationship.

  An object of the present invention is to provide a technique for realizing high performance of an IGBT by reducing the on-voltage and the turn-off loss which are in a trade-off relationship.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  A semiconductor device in a representative embodiment includes an IGBT, and the IGBT includes (a) a p-type collector layer, (b) an n-type field stop layer formed on the p-type collector layer, and (c) ) An n-type base layer formed on the n-type field stop layer; and (d) an n-type hole barrier layer formed on the n-type base layer. The IGBT includes (e) a p-type channel forming layer formed on the n-type hole barrier layer, (f) an n-type emitter layer formed on the p-type channel forming layer, and (g) the above-described An n-type emitter layer and a gate trench that penetrates the p-type channel formation layer and reaches the n-type hole barrier layer are provided. The IGBT further includes: (h) a gate insulating film formed on the inner wall of the gate trench; (i) a gate electrode formed on the gate insulating film in the gate trench; and (j) the gate electrode and And an interlayer insulating film formed on the n-type emitter layer. In addition, the IGBT includes (k) a contact hole that passes through the interlayer insulating film and the n-type emitter layer and reaches the p-type channel formation layer, and (l) is formed in the contact hole. And an emitter electrode for electrically connecting the p-type channel formation layer. Further, the IGBT is formed in (m) a p-type contact layer formed in the p-type channel formation layer and in contact with the contact hole, and (n) formed on a back surface of the p-type collector layer, a collector electrode electrically connected to the p-type collector layer; At this time, the IGBT according to the representative embodiment satisfies 4 ≦ (Qp / Qn) ≦ 16, where Qp is the carrier amount of the p-type collector layer and Qn is the carrier amount of the n-type field stop layer. It is characterized by this.

  Further, a method for manufacturing a semiconductor device in a representative embodiment includes (a) a step of preparing a semiconductor substrate made of an n-type base layer, (b) a step of forming an element isolation region in the semiconductor substrate, c) After the step (b), forming an n-type hole barrier layer on the n-type base layer in the IGBT formation region. And (d) a step of forming a gate trench reaching the n-type hole barrier layer from the main surface of the semiconductor substrate after the step (c), and (e) an inner wall of the gate trench after the step (d). And (f) a step of forming a gate electrode on the gate insulating film in the gate trench after the step (e). Next, (g) after the step (f), forming a p-type channel formation layer on the n-type hole barrier layer by forming a p-type channel formation layer inside the semiconductor substrate; (H) After the step (g), forming an n-type emitter layer on the p-type channel formation layer by forming an n-type emitter layer on the main surface of the semiconductor substrate. Subsequently, (i) after the step (h), a step of forming an interlayer insulating film on the main surface of the semiconductor substrate; (j) after the step (i), the interlayer insulating film and the n-type emitter layer Forming a contact hole that reaches the p-type channel formation layer. Then, (k) after the step (j), a step of forming a p-type contact layer in contact with the contact hole in the p-type channel formation layer, and (l) after the step (k), the contact hole Forming an emitter electrode on the interlayer insulating film including the inside, thereby electrically connecting the n-type emitter layer and the p-type channel forming layer. And (m) after the step (l), forming a n-type field stop layer on the back surface of the n-type base layer; and (n) after the step (m), on the back surface of the n-type field stop layer. a step of forming a p-type collector layer; and (o) a step of forming a collector electrode on the back surface of the p-type collector layer after the step (n). At this time, in the method of manufacturing a semiconductor device in a typical embodiment, when the carrier amount of the p-type collector layer is Qp and the carrier amount of the n-type field stop layer is Qn, 4 ≦ (Qp / Qn) The p-type collector layer and the n-type field stop layer are formed so as to satisfy ≦ 16.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  As a result of the reduction of the on-voltage and the turn-off loss that are in a trade-off relationship, the performance of the IGBT can be improved.

  In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. There are some or all of the modifications, details, supplementary explanations, and the like.

  Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

  Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say.

  Similarly, in the following embodiments, when referring to the shape, positional relationship, etc., of components, etc., unless otherwise specified, and in principle, it is considered that this is not clearly the case, it is substantially the same. Including those that are approximate or similar to the shape. The same applies to the above numerical values and ranges.

  In all the drawings for explaining the embodiments, the same members are denoted by the same reference symbols in principle, and the repeated explanation thereof is omitted. In order to make the drawings easy to understand, even a plan view may be hatched.

(Embodiment 1)
The semiconductor device according to the first embodiment is used, for example, in a drive circuit for a three-phase motor used in a hybrid vehicle or the like. FIG. 1 is a diagram showing a circuit diagram of the three-phase motor in the first embodiment. In FIG. 1, the three-phase motor circuit includes a three-phase motor 1, a power semiconductor device 2, and a control circuit 3. The three-phase motor 1 is configured to be driven by three-phase voltages having different phases. The power semiconductor device 2 is provided with an IGBT 4 and a diode (free wheel diode) 5 corresponding to three phases. That is, in each single phase, the IGBT 4 and the diode 5 are connected in antiparallel between the power supply potential (Vcc) and the input potential of the three-phase motor, and the input potential of the three-phase motor and the ground potential (GND) The IGBT 4 and the diode 5 are also connected in antiparallel between them. That is, two IGBTs 4 and two diodes 5 are provided for each single phase, and six IGBTs 4 and six diodes 5 are provided for three phases. A control circuit 3 is connected to the gate electrode of each IGBT 4, and the IGBT 4 is controlled by the control circuit 3. In the three-phase motor drive circuit configured as described above, the control circuit 3 controls the current flowing through the IGBT 4 constituting the power semiconductor device 2 to rotate the three-phase motor 1. That is, the three-phase motor 1 can be driven by controlling on / off of the IGBT 4 by the control circuit 3. When driving the three-phase motor 1 in this way, the IGBT 4 needs to be turned on / off, but the three-phase motor 1 includes an inductance. Therefore, when the IGBT 4 is turned off, a reverse current in a direction opposite to the direction in which the current of the IGBT 4 flows is generated by the inductance included in the three-phase motor 1. Since the IGBT 4 does not have the function of flowing the reverse current, the diode 5 is provided in reverse parallel to the IGBT 4 to recirculate the reverse current and release the energy accumulated in the inductance.

  The IGBT used in the above-described three-phase motor circuit is formed on a semiconductor chip, for example. Below, the structure of the semiconductor chip which formed IGBT is demonstrated. FIG. 2 is a plan view showing an upper surface of the semiconductor chip CHP on which the IGBT is formed. As shown in FIG. 2, the semiconductor chip CHP has a rectangular shape, and a guard ring GR is formed so as to surround a peripheral portion in the semiconductor chip CHP. This guard ring GR is a ring-shaped joint structure provided in order to prevent breakdown voltage deterioration in the peripheral part of the IGBT. An element formation region is formed inside the semiconductor chip CHP surrounded by the guard ring GR, and a plurality of IGBTs are formed in the element formation region. Specifically, as shown in FIG. 2, the gate electrodes G are formed in stripes along the vertical direction of the drawing. An emitter electrode (emitter pad) EE is formed on the gate electrode G via an interlayer insulating film (not shown). The gate electrode G formed in a stripe shape is connected to the gate pad GP via the gate wiring GL. Thus, the gate pad GP and the emitter electrode EE are formed on the upper surface of the semiconductor chip CHP. On the other hand, although not shown in FIG. 2, a collector electrode is formed on the back surface of the semiconductor chip CHP. Accordingly, the gate pad GP, the emitter electrode EE, and the collector electrode are formed as external connection terminals in the semiconductor chip CHP, and the IGBT is driven by applying a voltage to these external connection terminals. That is, the IGBT in the first embodiment is formed in the thickness direction of the semiconductor chip CHP, the emitter electrode EE and the gate pad GP are formed on the upper surface of the semiconductor chip CHP, and the collector electrode is formed on the back surface of the semiconductor chip CHP. It has a formed structure.

3 is a cross-sectional view taken along line AA in FIG. As shown in FIG. 3, the outer peripheral side of the semiconductor chip CHP is the left side of FIG. 3, and the inner peripheral side of the semiconductor chip CHP is the right side of FIG. Therefore, as shown in FIG. 3, a termination region, a temperature detection diode formation region, a gate wiring drawing region, and a cell region are sequentially formed from the outermost periphery to the inner region. A collector electrode CLE made of, for example, a metal film is formed on the back surface of the semiconductor chip CHP over the termination region, the temperature detection diode formation region, the gate wiring lead region, and the cell region. A nickel electrode is formed on the collector electrode CLE. A silicide film NS is formed. A p ⁺ type collector layer PCL made of a p ⁺ type semiconductor layer is formed on the nickel silicide film NS, and an n ⁺ type field stop layer NF made of an n ⁺ type semiconductor layer is formed on the p ⁺ type collector layer PCL. Has been. An n ⁻ type base layer NB made of an n ⁻ type semiconductor layer is formed on the n ⁺ type field stop layer NF. Since the structure of the upper layer than the n ⁻ type base layer NB is different in each region, the structure of each region will be described.

First, the configuration in the termination area will be described. As shown in FIG. 3, in the termination region, an element isolation region LO is formed on the surface of the n ⁻ type base layer NB. An n ⁺ type semiconductor layer NR is formed on the outermost periphery of the semiconductor chip CHP separated by the element isolation region LO. A p-type well PWL made of a p-type semiconductor layer is formed in the n ⁻ -type base layer NB inside the outermost periphery separated by the element isolation region LO. An interlayer insulating film IL1 is formed on the element isolation region LO and the n ⁺ type semiconductor layer NR and the p-type well PWL formed in the region isolated by the element isolation region LO. A plurality of contact holes C4 are formed in the interlayer insulating film IL1 so as to penetrate the interlayer insulating film IL1, and the plurality of contact holes C4 include those reaching the n ⁺ type semiconductor layer NR and p-type wells. Some reach PWL. A guard ring GR made of a metal film is formed so as to fill these contact holes C4 and to be disposed on the interlayer insulating film IL1. A surface protective film (passivation film) PV is formed so as to cover the guard ring GR. As described above, the guard ring GR is formed over and over in the termination region to suppress a decrease in breakdown voltage in the peripheral portion of the semiconductor chip CHP. For example, the impurity concentration of the p-type well PWL is determined from the viewpoint of ensuring a certain level of breakdown voltage.

Next, the configuration in the temperature detection diode formation region will be described. This temperature detection diode formation region is not shown in the plan view of the semiconductor chip CHP shown in FIG. As shown in FIG. 3, in the temperature detection diode formation region, a p-type well PWL made of a p-type semiconductor layer is formed in an n ⁻ -type base layer NB, and a gate insulating film GOX is interposed on the p-type well PWL. Thus, a temperature detection diode is formed. This temperature detection diode has a structure in which an n-type semiconductor layer N1, a p-type semiconductor layer P1, an n-type semiconductor layer N2, and a p-type semiconductor layer P2 are connected in series, and is formed of a pn junction diode. An interlayer insulating film IL1 is formed so as to cover the n-type semiconductor layer N1, the p-type semiconductor layer P1, the n-type semiconductor layer N2, and the p-type semiconductor layer P2, and a plurality of contact holes C3 are formed in the interlayer insulating film IL1. Is formed. Of the plurality of contact holes C3, one contact hole C3 penetrates the interlayer insulating film IL1 and reaches the n-type semiconductor layer N1, and another contact hole C3 penetrates the interlayer insulating film IL1 and forms a p-type semiconductor. Layer P2 has been reached. A cathode electrode CE is formed so as to fill the contact hole C3 reaching the n-type semiconductor layer N1 and to be disposed on the interlayer insulating film IL1. Similarly, an anode electrode AE is formed so as to fill the contact hole C3 reaching the p-type semiconductor layer P2 and to be disposed on the interlayer insulating film IL1. A surface protective film PV is formed so as to cover the cathode electrode CE and the anode electrode AE, and an opening is formed in the surface protective film PV so that the cathode electrode CE and the anode electrode AE are exposed.

  The temperature detection diode configured as described above is provided to detect the temperature of the IGBT formed in the cell region. That is, the temperature of the IGBT is detected by changing the forward current voltage characteristics of the temperature detection diode according to the temperature of the IGBT. This temperature detection diode has a pn junction formed by introducing impurities of different conductivity types into polysilicon, and has a cathode electrode CE and an anode electrode AE. The cathode electrode CE and the anode electrode AE are connected to a temperature detection circuit provided outside the semiconductor chip CHP. This temperature detection circuit indirectly detects the temperature of the IGBT based on the output between the cathode electrode and the anode electrode of the temperature detection diode, and when the detected temperature becomes equal to or higher than a certain temperature, it is applied to the gate electrode of the IGBT. The applied gate signal is cut off to protect the IGBT.

Next, the configuration in the gate wiring drawing region will be described. The gate wiring extraction region is a region for connecting a gate electrode formed in the cell region to the gate pad. As shown in FIG. 3, in the gate wiring lead region, a p-type well PWL is formed in the n ⁻ -type base layer NB, and a trench TR is formed so as to reach the inside from the surface of the p-type well PWL. . A gate lead-out line GH is formed on the inner wall of the trench TR via a gate insulating film GOX. That is, the gate lead-out line GH is formed so as to fill the inside of the trench TR and extend over the p-type well PWL via the gate insulating film GOX. This gate lead-out line GH is electrically connected to the gate electrode formed in the cell region. An interlayer insulating film IL1 is formed so as to cover the gate lead line GH, and a contact hole C2 that penetrates the interlayer insulating film IL1 and reaches the gate lead line GH is formed. A gate wiring GL is formed so as to fill the contact hole C2 and extend over the interlayer insulating film IL1. The gate wiring GL is electrically connected to the gate pad. Therefore, the gate electrode formed in the cell region is connected to the gate pad by the gate lead line GH and the gate line GL formed in the gate line lead region. As a result, the voltage applied to the gate pad is supplied to the gate electrode formed in the cell region via the gate wiring drawing region. A surface protective film PV is formed so as to cover the gate wiring GL formed in the gate wiring drawing region, and an opening is formed in the surface protective film PV in the gate pad connected to the gate wiring GL. That is, the gate pad is configured to be exposed from the surface protective film PV. Thereby, a voltage can be supplied to the gate pad from the outside of the semiconductor chip CHP.

Next, the configuration of the IGBT formed in the cell region will be described. Here, the configuration of the IGBT formed in the cell region will be described with reference to FIG. 4 in which the cell region in FIG. 3 is enlarged. FIG. 4 is an enlarged sectional view showing a part of the cell region. As shown in FIG. 4, in the IGBT, an n ⁺ type field stop layer NF made of an n ⁺ type semiconductor layer is formed on a p ⁺ type collector layer PCL made of a p ⁺ type semiconductor layer. An n ⁻ type base layer NB made of an n ⁻ type semiconductor layer is formed on the n ⁺ type field stop layer NF, and an n type hole barrier layer NHB made of an n type semiconductor layer is formed on the n ⁻ type base layer NB. Is formed. A p-type channel forming layer PCH made of a p-type semiconductor layer is formed on the n-type hole barrier layer NHB, and an n ⁺ -type emitter layer NE made of an n ⁺ -type semiconductor layer is formed on the p-type channel forming layer PCH. Has been.

Trench TR is formed as the surface of the n ⁺ -type emitter layer NE through the n ⁺ -type emitter layer NE and the p-type channel forming layer PCH reaches the n-type hole barrier layer NHB. A gate insulating film GOX is formed on the inner wall of the trench TR, and a gate electrode G is formed on the gate insulating film GOX so as to fill the trench TR. An interlayer insulating film IL1 is formed on the n ⁺ -type emitter layer NE including the gate electrode G, and the interlayer insulating film IL1 and the n ⁺ -type emitter layer NE penetrate between the plurality of trenches TR. A contact hole C1 reaching the p-type channel formation layer PCH is formed, and a p ⁺ -type contact layer PC made of a p ⁺ -type semiconductor layer is formed in the p-type channel formation layer PCH so as to be in contact with the bottom of the contact hole C1. Yes. A p-type latch-up prevention layer PL made of a p-type semiconductor layer is formed so as to be in contact with the p ⁺ -type contact layer PC and the n-type hole barrier layer NHB.

  A laminated film of a titanium tungsten film 12 and an aluminum film 13 as a barrier conductor film is formed on the interlayer insulating film IL1 including the inside of the contact hole C1. The laminated film made of the titanium tungsten film 12 and the aluminum film 13 becomes the emitter electrode EE.

  The IGBT configured as described above will be described by comparing the circuit configuration with the device structure. FIG. 5 is a diagram in which the circuit configuration and the device structure are associated with each other in the IGBT formed in the cell region. First, the circuit configuration of the IGBT will be described with reference to FIG. As shown in FIG. 5, the IGBT formed in the cell region has a pnp bipolar transistor Tr1, an npn bipolar transistor Tr2, and a field effect transistor Tr3. At this time, the pnp bipolar transistor Tr1 and the field effect transistor Tr3 constitute an IGBT, and the npn bipolar transistor Tr2 is a parasitic transistor formed parasitically in terms of the device structure. That is, the main configuration of the IGBT is a pnp bipolar transistor Tr1 and a field effect transistor Tr3, and the npn bipolar transistor Tr2 is a parasitic component.

The pnp bipolar transistor Tr1 includes a p ⁺ type collector layer PCL, an n ⁻ type base layer (including an n ⁺ type field stop layer NF and an n type hole barrier layer NHB), and a p type channel formation layer PCH (p ⁺ type contact). Layer PC and p-type latch-up prevention layer PL).

On the other hand, the npn bipolar transistor Tr2 which is a parasitic component includes an n ⁻ type base layer (including an n ⁺ type field stop layer NF and an n type hole barrier layer NHB) and a p type channel formation layer PCH (p ⁺ type). A contact layer PC and a p-type latch-up prevention layer PL) and an n ⁺ -type emitter layer NE.

Further, the field effect transistor Tr3 includes an n ⁺ -type emitter layer NE serving as a source region, an n ⁻ -type base layer serving as a drain region (including an n ⁺ -type field stop layer NF and an n-type hole barrier layer NHB), a p-type channel formation layer PCH provided between the n ⁺ -type emitter layer NE and the n ⁻ -type base layer NB. The gate insulating film GOX is formed on the inner wall of the trench TR, and the gate electrode G is embedded in the trench TR.

Next, the connection relationship between the pnp bipolar transistor Tr1, the npn bipolar transistor Tr2, and the field effect transistor Tr3 will be described. A pnp bipolar transistor Tr1 is connected between the collector electrode CLE of the IGBT and the emitter electrode EE of the IGBT. The base of the pnp bipolar transistor Tr1 is connected to the drain region (n ⁻ type base layer NB) of the field effect transistor Tr3, and the source region (n ⁺ type emitter layer NE) of the field effect transistor Tr3 is connected to the emitter electrode EE of the IGBT. It is connected. At this time, the collector of the npn bipolar transistor Tr2 formed parasitically is connected to the base of the pnp bipolar transistor Tr1, and the emitter of the npn bipolar transistor Tr2 is connected to the emitter electrode EE of the IGBT. The base of the npn bipolar transistor Tr2 formed in a parasitic manner is connected to the emitter electrode EE of the IGBT.

  The IGBT formed in the cell region is configured as described above, and the operation thereof will be described below with reference to FIG. First, the circuit operation will be described, and then the operation in the device structure will be described.

  With a high potential applied to the collector electrode CLE of the IGBT and a low potential applied to the emitter electrode EE of the IGBT, a gate voltage higher than the threshold is applied to the gate electrode G of the field effect transistor Tr3 via the gate wiring GL. . Then, the field effect transistor Tr3 is turned on, and the base current of the pnp bipolar transistor Tr1 flows. As a result, a current flows between the collector electrode CLE of the IGBT to which the pnp bipolar transistor Tr1 is connected and the emitter electrode EE of the IGBT. In this way, the IGBT is turned on. Subsequently, a voltage equal to or lower than the threshold voltage is applied to the gate electrode G of the field effect transistor Tr3. Then, the field effect transistor Tr3 is turned off, and the base current of the pnp bipolar transistor Tr1 does not flow. For this reason, the current flowing between the collector electrode CLE of the IGBT and the emitter electrode EE of the IGBT does not flow based on the base current. That is, as a result of turning off the pnp bipolar transistor Tr1, the IGBT is turned off. In this way, in the IGBT, the ON / OFF of the field effect transistor Tr3 is controlled to control the energization and cutoff of the base current of the pnp bipolar transistor Tr1. By energizing and interrupting the base current of the pnp bipolar transistor Tr1, the energization and interruption of the collector current of the pnp bipolar transistor Tr1 is controlled, and the on / off of the IGBT is controlled. Therefore, it can be seen that the IGBT is a semiconductor element that combines the high-speed switching characteristics and voltage driving characteristics of the field effect transistor Tr3 with the low on-voltage characteristics of the pnp bipolar transistor Tr1. The circuit operation described above is described on the assumption that the IGBT operates normally, and the parasitic npn bipolar transistor Tr2 is described as not operating.

Subsequently, the operation in the device structure will be described. A high potential is applied to the collector electrode CLE of the IGBT, and a low potential is applied to the emitter electrode EE of the IGBT. In this state, a voltage higher than the threshold is applied to the gate electrode G. Then, an inversion layer (channel) made of an n-type semiconductor layer is formed in the p-type channel formation layer in contact with the side surface of the trench TR. Therefore, the n ⁺ -type emitter layer NE and the n-type hole barrier layer NHB are electrically connected by the inversion layer, and the n ⁺ -type emitter layer NE is connected to the n ⁻ -type via the inversion layer and the n-type hole barrier layer NHB. Electrons e flow through the base layer NB. On the other hand, since a forward bias is applied between the n ⁻ type base layer NB (n ⁺ type field stop layer NF) and the p ⁺ type collector layer PCL, holes h are transferred from the p ⁺ type collector layer PCL to the n ⁻ type base layer NB. Is injected. For this reason, holes h are accumulated in the n ⁻ -type base layer NB. As a result of the electrons e being attracted by the positive charges due to the accumulated holes h, a large amount of electrons e flows into the n ⁻ -type base layer NB. As a result, the resistance of the n ⁻ type base layer NB decreases. This phenomenon is so-called conductivity modulation, and the on-voltage of the IGBT is lowered by this conductivity modulation. Then, the holes h flowing into the n ⁻ type base layer NB flow out to the emitter electrode EE through the n type hole barrier layer NHB, the p type latch-up prevention layer PL, and the p ⁺ type contact layer PC. Thus, the IGBT is turned on when a current flows from the collector electrode CLE to the emitter electrode EE. At this time, it is considered that the holes h injected from the p ⁺ type collector layer PCL into the n ⁻ type base layer NB recombine with electrons existing in the n ⁻ type base layer NB. However, a semiconductor material mainly composed of silicon has a property that recombination of electrons and holes is less likely to occur than a semiconductor material mainly composed of a compound semiconductor. Thus, n ^- most of the holes h injected into the mold base layer NB is, n ^- are accumulated without recombining with electrons e in type base layer NB. As a result, holes h are accumulated in the n ⁻ -type base layer NB, and electrons e flowing from the n ⁺ -type emitter layer NE are accumulated in the n ⁻ -type base layer NB so as to be attracted to the accumulated holes h. As a result, conductivity modulation occurs. From the above, the IGBT has a feature that the on-voltage is lowered by conductivity modulation.

Next, an operation for turning off the IGBT will be described. That is, a voltage lower than the threshold value is applied to the gate electrode G. As a result, the inversion layer formed on the side surface of the trench TR disappears, and the n ⁺ -type emitter layer NE and the n-type hole barrier layer NHB (n ⁻ -type base layer NB) are electrically disconnected. That is, the supply of electrons e from the n ⁺ type emitter layer NE to the n ⁻ type base layer NB is stopped. As a result, the IGBT is considered to be turned off, but actually, even if a voltage equal to or lower than the threshold value is applied to the gate electrode G to extinguish the inversion layer, the IGBT does not immediately turn off. That is, in the IGBT, even after the off voltage is applied to the gate electrode G, the current is not completely cut off, but it takes a certain time until the IGBT is completely turned off. This is referred to herein as turn-off loss. The cause of this turn-off loss will be described below.

The on-voltage is low when the IGBT is on, but when the IGBT is off, a potential corresponding to the power supply voltage is applied between the collector electrode CLE and the emitter electrode EE. Therefore, the reverse bias applied to the pn junction between the p-type channel formation layer PCH (p-type latch-up prevention layer PL) and the n ⁻ -type base layer NB (n-type hole barrier layer NHB) is also about the power supply potential. The depletion layer extends from the boundary of the pn junction toward the inside of the n ⁻ -type base layer NB. When the IGBT is turned off, holes h are accumulated in the n ⁻ -type base layer NB. Of the holes h which are the accumulation, n ^- intended to be within the depletion layer extending toward the inside of the mold base layer NB as soon by the electric field in the depletion layer n ^- -type base layer NB outside Swept out. On the other hand, among the holes h are accumulated, n ^- -type base layer NB which do not fall within the depletion layer extending toward the inside of, n ^- gradually difficult to flow out of the mold base layer NB tail It flows out as current. Therefore, even if the gate electrode G is set to a voltage equal to or lower than the threshold value, the IGBT does not turn off immediately, but is delayed by the time for the holes h accumulated in the n ⁻ -type base layer NB to flow out of the IGBT. . This is the mechanism of the turn-off loss in the IGBT, and the time during which the holes h accumulated in the n ⁻ -type base layer NB are swept out of the IGBT becomes the turn-off loss.

As described above, the IGBT has a feature that the on-voltage during the on-operation is lowered, and it is understood that a phenomenon called turn-off loss occurs at the time of turn-off. In the IGBT, it is desirable to increase the amount of holes h injected from the p ⁺ type collector layer PCL into the n ⁻ type base layer NB from the viewpoint of lowering the on voltage during the on operation. This is because, n ^- the more holes h are injected into the mold base layer NB, n ^- amount of holes h accumulate in the mold base layer NB is increased n ^- increased conductivity modulation in type base layer NB Because. On the other hand, from the viewpoint of reducing the turn-off loss when the IGBT is turned off, it is desirable to limit the amount of holes h injected from the p ⁺ -type collector layer PCL into the n ⁻ -type base layer NB. This is because, n ^- -type if the base layer holes h injected into the NB is greater, n ^- -type amount of holes h are accumulated in the base layer NB is increased, n ^- holes stored in type base layer NB This is because it takes a long time for h to flow out of the IGBT. Therefore, reducing the on-voltage of the IGBT and reducing the turn-off loss of the IGBT may be in a trade-off relationship in terms of the amount of holes h accumulated in the n ⁻ -type base layer NB. Recognize. The key to the high performance of the IGBT is how to balance the reduction of the on-voltage and the reduction of the turn-off loss in the trade-off relationship.

Here, in order to reduce the turn-off loss of the IGBT, it is considered that the width of the depletion layer extending to the n ⁻ -type base layer NB should be increased as described in the operation at the turn-off of the IGBT. That is, if the holes h accumulated in the n ⁻ type base layer NB enter the depletion layer, they are accelerated by the electric field in the depletion layer and swept out to the p-type channel formation layer PCH. Therefore, it is considered that the turn-off loss of the IGBT can be reduced if the entire n ⁻ -type base layer NB is set to be depleted during the off-time operation of the IGBT. An IGBT in which the entire n ⁻ type base layer NB is depleted in this way is referred to as a punch-through type IGBT. In this punch-through IGBT, the entire n ⁻ type base layer NB is configured to be depleted, but the p ⁺ type collector layer is formed below the n ⁻ type base layer NB because the depletion layer extends too much. When the depletion layer reaches the PCL, the p-type channel formation layer PCH and the p ⁺ -type collector layer PCL are connected by the depletion layer, and punch-through occurs. Therefore, an n ⁺ type field stop layer NF having an impurity concentration higher than that of the n ⁻ type base layer NB is provided between the n ⁻ type base layer NB and the p ⁺ type collector layer PCL. By providing the n ⁺ type field stop layer NF, the depletion layer extending from the n ⁻ type base layer NB stops at the n ⁺ type field stop layer NF without reaching the p ⁺ type collector layer PCL. That is, the n ⁺ type field stop layer NF has a function of preventing the depletion layer extending from the n ⁻ type base layer NB from reaching the p ⁺ type collector layer PCL. As described above, it is considered that the turn-off loss can be reduced by using a punch-through IGBT in which the entire n ⁻ -type base layer NB is depleted when the IGBT is turned off. However, even with this punch-through type IGBT, if the amount of holes accumulated in the n ⁻ type base layer NB is large, it takes time to sweep out all the accumulated holes h to the outside of the IGBT. , Turn-off loss will increase. For this reason, even in the punch-through type IGBT, it is necessary to limit the amount of holes flowing into the n ⁻ type base layer NB. In order to improve the performance of the IGBT, it is necessary to achieve both a reduction in on-voltage and a reduction in turn-off loss that are in a trade-off relationship, and it is necessary to optimize the injection efficiency of holes injected into the n ⁻ -type base layer NB I understand that there is.

Hereinafter, a configuration for optimizing the injection efficiency of holes injected into the n ⁻ type base layer NB will be described. First, in quantifying the hole injection efficiency, the injection efficiency is approximated by the following amounts. That is, it is assumed that the efficiency of hole injection from the p ⁺ type collector layer PCL to the n ⁻ type base layer NB is proportional to (Qp / Qn). At this time, Qp represents the amount of carriers (hole amount) existing in the p ⁺ -type collector layer PCL, and Qn represents the amount of carriers (electron amount) present in the n ⁺ -type field stop layer NF. .

At this time, the amount of carriers existing in the ^{p +} -type collector layer PCL (Seianaryou) Qp increases from ^{the p +} -type collector layer PCL n ^- -type base layer hole injection efficiency into the NB is increased. On the other hand, when the carrier amount (electron amount) Qn existing in the n ⁺ -type field stop layer NF increases, the efficiency of hole injection from the p ⁺ -type collector layer PCL to the n ⁻ -type base layer NB decreases. This can be said that the n ⁺ type field stop layer NF has a function of limiting the injection of holes from the p ⁺ type collector layer PCL to the n ⁻ type base layer NB. It has been found that this function of limiting hole injection increases as the amount of carriers (electron amount) present in the n ⁺ -type field stop layer NF increases. The n ⁺ -type field stop layer NF has a function of preventing a depletion layer extending from the n ⁻ -type base layer NB from reaching the p ⁺ -type collector layer PCL, and, as another function, the p ⁺ -type It can be seen that it also has a function of limiting the injection of holes from the collector layer PCL. From the above, it can be seen that the approximation that the hole injection efficiency is proportional to (Qp / Qn) is appropriate.

Next, how the carrier amount (hole amount) Qp present in the p ⁺ -type collector layer PCL and the carrier amount (electron amount) Qn present in the n ⁺ -type field stop layer NF are quantified. Will be described. FIG. 6 is a graph showing the relationship between the carrier concentration N in the p ⁺ -type collector layer PCL, the n ⁺ -type field stop layer NF, and the n ⁻ -type base layer NB and the depth from the back surface of the semiconductor chip. In FIG. 6, the vertical axis represents the carrier concentration (pieces / cm ³ ), and the horizontal axis represents the depth (μm). As shown in FIG. 6, a p ⁺ type collector layer PCL is formed in a region from the back surface of the semiconductor chip to the depth a, and an n ⁺ type field stop layer NF is formed in a region from the depth a to the depth b. Is formed. An n ⁻ type base layer NB is formed in a region deeper than the depth b. At this time, first, the amount of carriers (amount of holes) Qp existing in the p ⁺ -type collector layer PCL is quantified as shown by the equation (1) in FIG. Equation (1) is, p ⁺ -type carrier concentration of the collector layer PCL shows that integrating the (hole concentration) N depth 0 to a depth a, the integrated value p ⁺ -type collector layer PCL Is defined as the amount of carriers (amount of holes) Qp (number / cm ² ). Thus, the amount of carriers existing in the ^{p +} -type collector layer PCL (Seianaryou) Qp (pieces / cm ²⁾ is shown (the amount carrier) holes per unit area of the ^{p +} -type collector layer PCL I understand that. Similarly, the carrier amount (electron amount) Qn existing in the n ⁺ -type field stop layer NF is quantified as shown by the equation (2) in FIG. Equation (2) shows that integrating the n ⁺ carrier concentration (concentration of the electron) type field stop layer NF N depth from a depth b, and the integrated value n ⁺ -type field stop layer NF It is defined as the amount of carriers (amount of electrons) Qn (pieces / cm ² ) existing in the inside. Thus, the amount of carriers existing in the ^{n +} -type field stop layer NF (electron amount) Qn (pieces / cm ²⁾ is, ^{n +} -type field stop layer NF per unit area (the carrier amount) shows an electron amount I understand that.

Next, the relationship between (Qp / Qn) indicating the hole injection efficiency and the on-voltage of the IGBT will be described. FIG. 7 is a graph showing the relationship between (Qp / Qn) and the on-voltage of the IGBT. In FIG. 7, the vertical axis represents the on-voltage (V) of the IGBT, and the horizontal axis represents the hole injection efficiency (Qp / Qn). As shown in FIG. 7, it can be seen that the on-voltage of the IGBT decreases as (Qp / Qn) increases. Therefore, it can be seen that it is desirable to increase (Qp / Qn) from the viewpoint of reducing the on-voltage. Increasing (Qp / Qn) means increasing the value of Qp, which corresponds to an increase in hole injection efficiency. The increase in the hole injection efficiency means that the amount of holes accumulated in the n ⁻ type base layer increases, the conductivity modulation effect increases, and the resistance of the n ⁻ type base layer decreases. Yes. For this reason, it can be seen that increasing (Qp / Qn) decreases the on-voltage of the IGBT.

Next, the relationship between (Qp / Qn) indicating the hole injection efficiency and the IGBT turn-off fall time (turn-off loss) will be described. FIG. 8 is a graph showing the relationship between (Qp / Qn) and the turn-off falling time of the IGBT. In FIG. 8, the vertical axis represents the IGBT turn-off fall time (ns), and the horizontal axis represents the hole injection efficiency (Qp / Qn). As shown in FIG. 8, it can be seen that as (Qp / Qn) increases, the turn-off fall time also increases. An increase in (Qp / Qn) means an increase in the efficiency of hole injection from the p ⁺ type collector layer PCL to the n ⁻ type base layer NB, and as a result, accumulation in the n ⁻ type base layer NB. This shows that the amount of holes that are generated increases, so that the time (turn-off falling time) required to sweep out the holes accumulated in the n ⁻ -type base layer NB to the outside of the IGBT becomes longer. Then, as (Qp / Qn) becomes smaller, the turn-off falling time tends to become shorter. This is because the hole injection efficiency from the p ⁺ -type collector layer PCL to the n ⁻ -type base layer NB is reduced, and as a result, the amount of holes accumulated in the n ⁻ -type base layer NB is reduced and the holes are removed from the IGBT. This is presumably due to the shortening of the time for sweeping outside. Further, it can be seen that when (Qp / Qn) is decreased, the turn-off fall time increases rapidly. This phenomenon is because the hole injection efficiency from the p ⁺ -type collector layer PCL to the n ⁻ -type base layer NB decreases, so the amount of holes accumulated in the n ⁻ -type base layer NB decreases, and the holes This is a result contrary to the assumption that the time for sweeping out to the outside of the IGBT is shortened. The following mechanisms can be considered to explain this phenomenon. That is, that (Qp / Qn) becomes smaller means that the amount of carriers (electron amount) Qn existing in the n ⁺ -type field stop layer NF becomes larger. When the IGBT is on, a forward bias is applied between the p ⁺ -type collector layer PCL and the n ⁺ -type field stop layer NF, so that a positive bias is applied from the p ⁺ -type collector layer PCL to the n ⁻ -type base layer NB. It is considered that electrons flow from the n ⁺ type field stop layer NF to the p ⁺ type collector layer PCL at the same time as the holes flow. In the present case, the carrier of the n ⁺ -type field stop layer NF (electron amount) is large, the amount of carriers flowing from the n ⁺ -type field stop layer NF to the p ⁺ -type collector layer PCL (electron amount) is also considered to be greater . In this state, when the IGBT is turned off, electrons flowing into the p ⁺ type collector layer PCL are swept out of the IGBT, but since the amount of electrons flowing into the p ⁺ type collector layer PCL is large, It can be considered that the time for sweeping out the outside of the IGBT becomes longer and the turn-off fall time of the IGBT becomes longer. That is, in the region where (Qp / Qn) is very small, the sweep time of electrons flowing into the p ⁺ -type collector layer PCL is more apparent than the sweep time of holes accumulated in the n ⁻ -type base layer NB. It is presumed that it will be transformed. In this way, the characteristics of the graph shown in FIG. 8 can be described.

  From the relationship between (Qp / Qn) and on-voltage shown in FIG. 7 and (Qp / Qn) and turn-off fall time (turn-off loss) shown in FIG. 8, the on-voltage is reduced and the turn-off fall time is shortened. The inventors have found that there is an optimal (Qp / Qn) value that can be achieved. The method for obtaining the range of (Qp / Qn) will be described below. From the relationship shown in FIG. 8, it can be seen that the value of (Qp / Qn) is desirably about 5 to 8 in order to shorten the turn-off fall time. On the other hand, FIG. 7 shows that the on-voltage is smaller as (Qp / Qn) is larger. From these relationships, the present inventors have found that the value of (Qp / Qn) may be set to about 8 in order to shorten the turn-off fall time and reduce the on-voltage. However, even if the value of (Qp / Qn) is set to about 8, in actuality, variation occurs for the following reason. Therefore, it is actually necessary to give a width to the value of (Qp / Qn). In the first embodiment, the range is 4 ≦ (Qp / Qn) ≦ 16. If (Qp / Qn) is within this range, the on-voltage can be sufficiently reduced and the turn-off fall time can be shortened.

Hereinafter, the reason why the range of (Qp / Qn) indicating the hole injection efficiency is set to 4 or more and 16 or less will be described. Qp is the amount of carriers (amount of holes) present in the p ⁺ type collector layer PCL, and Qn is the amount of carriers (amount of electrons) present in the n ⁺ type field stop layer NF. At this time, the p ⁺ -type collector layer PCL and the n ⁺ -type field stop layer NF are formed by introducing an impurity into the semiconductor substrate using an ion implantation method and then performing activation annealing. For example, the n ⁺ -type field stop layer NF is formed by introducing an n-type impurity such as phosphorus into the semiconductor substrate and then activating the n-type impurity by laser annealing. Here, when the activated n-type impurity increases, the amount of carriers (electrons) existing in the n ⁺ -type field stop layer NF also increases. In other words, even if a large amount of n-type impurity is introduced, the amount of carriers (electrons) existing in the n ⁺ -type field stop layer NF decreases if the activation amount of the n-type impurity is small.

FIG. 9 is a graph showing the relationship between the dose amount and the carrier amount Qn when forming the n ⁺ -type field stop layer NF. In FIG. 9, the vertical axis represents the carrier amount (pieces / cm ² ), and the horizontal axis represents the Lindose amount (pieces / cm ² ). As shown in FIG. 9, it can be seen that the carrier amount Qn increases as the Lindose amount increases. In FIG. 9, there are a plurality of types of plots (for example, triangle mark, circle mark, and x mark), which correspond to changing the laser annealing conditions. As can be seen from FIG. 9, even when the laser annealing conditions are changed, the activation rate of phosphorus is small. That is, when the n ⁺ -type field stop layer NF is formed, it can be considered that the carrier amount Qn does not depend on the laser annealing conditions if the Lindose amount is almost determined. Therefore, the desired carrier amount Qn can be obtained by accurately controlling the Lindose amount.

On the other hand, the p ⁺ -type collector layer PCL is formed by introducing a p-type impurity such as boron into the semiconductor substrate and then activating the p-type impurity by laser annealing. Here, as the number of activated p-type impurities increases, the amount of carriers (holes) present in the p ⁺ -type collector layer PCL also increases. In other words, even if a large amount of p-type impurity is introduced, the amount of carriers (holes) present in the p ⁺ -type collector layer PCL is small if the activation amount of the p-type impurity is small.

FIG. 10 is a graph showing the relationship between the boron dose and the carrier amount Qp when the p ⁺ -type collector layer PCL is formed. In FIG. 10, the vertical axis represents the carrier amount (pieces / cm ² ), and the horizontal axis represents the boron dose amount (pieces / cm ² ). As shown in FIG. 10, it can be seen that the carrier amount Qp increases as the borondose amount increases. In FIG. 10, there are a plurality of types of plots (for example, triangle mark, circle mark, and x mark), which correspond to changing the laser annealing conditions. It can be seen from FIG. 10 that the activation rate of boron varies when the laser annealing conditions are changed. That is, when the p ⁺ -type collector layer PCL is formed, the carrier amount Qp can be considered to vary if the laser annealing conditions are changed even if the boron dose is determined. Therefore, it can be seen that when the p ⁺ -type collector layer PCL is formed, even if the boron dose is accurately controlled to obtain a desired carrier amount Qp, it varies depending on the activation annealing conditions.

  From the above, when Qp and Qn are controlled so that (Qp / Qn) is set to a desired value, Qn can be accurately controlled by the dose amount, while Qp can be accurately controlled only by the dose amount. However, the variation becomes large. Therefore, it is desirable to set (Qp / Qn) to 8 from FIG. 7 and FIG. 8 from the viewpoint of achieving both a reduction in on-voltage and a reduction in turn-off loss, but as shown in FIG. Considering that the carrier amount Qp varies from half to double even with the same borondose amount, it can be seen that the range of (Qp / Qn) needs to be widened to be 4 or more and 16 or less. In this case, even if the range of (Qp / Qn) is 4 or more and 16 or less, the ON voltage can be sufficiently reduced and the turn-off loss can be reduced, and the performance of the IGBT can be improved. In other words, in order to improve simultaneously the reduction of the on-voltage and the reduction of the turn-off loss that are in a trade-off relationship, the range of (Qp / Qn) indicating the hole injection efficiency should be optimized to 4 or more and 16 or less. It turns out that it is necessary. As described above, the first feature point in the first embodiment is that the range of (Qp / Qn) indicating the hole injection efficiency is set to 4 or more and 16 or less. With this first feature point, it is possible to realize a high-performance IGBT as a result of reducing the turn-on loss and reducing the on-voltage of the IGBT in a trade-off relationship.

For the above reasons, in the first embodiment, the range of (Qp / Qn) is 4 or more and 16 or less. Specifically, when the value range of (Qp / Qn) is 4 or more and 16 or less, for example, the carrier amount Qp of the p-type collector layer PCL is 4.0 × 10 ^{13 to} 8.0 × 10 ¹³ (pieces). / Cm ² ), and the carrier region Qn of the n-type field stop layer NF is 5 × 10 ^{12 to} 1.0 × 10 ¹³ (pieces / cm ² ).

The first characteristic point of the first embodiment is that the range of (Qp / Qn) indicating the hole injection efficiency is set to 4 or more and 16 or less, but the value of (Qp / Qn) is actually measured. A method will be described. First, the first measurement method is SPR. SPR (Spreading Resistance Profiling method) is a measurement method called spread resistance measurement. This spreading resistance measurement method is an analysis method in which a sample is polished obliquely, a probe (probe) on the polished surface is brought into contact, and the carrier concentration is obtained from the electrically measured resistance. In the first embodiment, the carrier concentration distribution in the depth direction of the p ⁺ -type collector layer PCL and the n ⁺ -type field stop layer NF can be obtained by the spreading resistance measurement method. Then, the carrier amount Qp of the p ⁺ -type collector layer PCL and the carrier amount Qn of the n ⁺ -type field stop layer NF can be obtained by integrating the obtained carrier concentration distribution with the depth. Finally, the hole injection efficiency can be obtained by taking the ratio of the carrier amount Qp of the p ⁺ -type collector layer PCL and the carrier amount Qn of the n ⁺ -type field stop layer NF.

  Subsequently, the second measurement method is a measurement method using a spreading resistance microscope. A measuring method using a spreading resistance microscope is called SSRM (Scanning Spread Resistance Microscope). FIG. 11 is a diagram for explaining the measurement principle using a spreading resistance microscope. As shown in FIG. 11, a bias voltage is applied to the sample S by the power source E, and the conductive probe P formed on the cantilever KL is brought into contact with the sample S. The resistance distribution can be obtained by measuring the current flowing through the conductive probe P by the wide range logarithmic amplifier AMP. And it is the analysis method which calculates | requires carrier concentration from this resistance distribution.

  According to the measuring method using the spreading resistance microscope, the applied voltage is concentrated immediately below the conductive probe P, and therefore a current (spreading resistance) in which the impurity concentration just below the probe is dominant can be detected. Since a wide range logarithmic amplifier AMP having a measurement range of 10 pA to 0.1 mA is used, a wide carrier concentration can be measured. Furthermore, in order to reduce the contact resistance of the conductive probe P, measurement is performed with a high load with the cantilever KL having a large spring constant, so that there is an advantage that a resistance value depending on the carrier concentration can be measured.

Next, the second feature point in the first embodiment will be described. The first feature point in the first embodiment is that the carrier amount (hole amount) existing in the p ⁺ -type collector layer PCL is Qp and the carrier amount (electron amount) present in the n ⁺ -type field stop layer NF. Is assumed that the hole injection efficiency is (Qp / Qn), and the value of (Qp / Qn) is 4 or more and 16 or less. By adjusting the hole injection efficiency in this way, it is possible to improve the balance between the reduction of the on-voltage and the reduction of the turn-off loss that are in a trade-off relationship.

However, considering only the reduction of the on-voltage, as shown in FIG. 7, the on-voltage can be reduced as the hole injection efficiency (Qp / Qn) is increased. In this mechanism, if the efficiency of hole injection from the p ⁺ -type collector layer PCL to the n ⁻ -type base layer NB is increased, the amount of holes accumulated in the n ⁻ -type base layer NB increases. The on-voltage is reduced by conductivity modulation in which electrons gather in the n ⁻ -type base layer NB so as to be attracted to the positive charge. Therefore, the point for reducing the on-voltage is to increase the amount of holes accumulated in the n ⁻ -type base layer NB. For this reason, in addition to increasing the hole injection efficiency, it is considered that the ON voltage can be reduced by suppressing the outflow of holes from the n ⁻ -type base layer NB.

Therefore, the second feature point of the first embodiment is realized by paying attention to suppressing the outflow of holes from the n ⁻ type base layer NB. Specifically, the second feature of the first embodiment is that, as shown in FIGS. 4 and 5, an n-type hole made of an n-type semiconductor layer is provided between the n ⁻ -type base layer NB and the p-type channel formation layer PCH. The barrier layer NHB is provided. The n-type hole barrier layer NHB is formed as a region where the n-type impurity concentration is higher than that of the n ⁻ -type base layer NB. Accordingly, it is possible to suppress the holes accumulated in the n ⁻ type base layer NB from flowing out to the p type channel formation layer PCH. As a result, many holes are accumulated in the n ⁻ -type base layer NB, and the conductivity modulation during the ON operation of the IGBT can be enhanced. Therefore, the second embodiment of the first embodiment in which an n-type hole barrier layer NHB having a higher impurity concentration than the n ⁻ -type base layer NB is provided between the n ⁻ -type base layer NB and the p-type channel formation layer PCH. The on-voltage of the IGBT can be further reduced due to the feature point.

Here, n ^- by providing a high n-type hole barrier layer NHB impurity concentration than type base layer NB, n ^- holes stored in type base layer NB is the flow out to the p-type channel forming layer PCH What can be suppressed can be inferred from the function of the n ⁺ -type field stop layer NF. That is, if the carrier amount Qn of the n ⁺ -type field stop layer NF is increased, the efficiency of hole injection from the p ⁺ -type collector layer PCL can be limited. It can be seen that the passage of can be suppressed. Thus, n ^- between the mold base layer NB and p-type channel forming layer PCH, n ^- the type base layer NB providing high n-type hole barrier layer NHB impurity concentration than, n ^- p -type base layer NB It is considered that the amount of holes flowing out to the mold channel forming layer PCH can be limited. That is, the second aspect of the present embodiment 1, n ^- has been made in view of reducing the amount of holes flowing out of the mold base layer NB, n ^- -type base layer NB of n-type impurity than An n-type hole barrier layer NHB having a high impurity concentration is provided.

Next, the third feature point of the first embodiment will be described. As described above, the second feature of the first embodiment is that the n-type hole barrier having an impurity concentration higher than that of the n ⁻ -type base layer NB is between the n ⁻ -type base layer NB and the p-type channel formation layer PCH. The layer NHB is provided, but a side effect of providing the n-type hole barrier layer NHB is that a latch-up phenomenon is likely to occur in the IGBT.

  First, the latch-up phenomenon of the IGBT will be described with reference to FIG. In FIG. 5, with a high potential applied to the collector electrode CLE and a low potential applied to the emitter electrode EE of the IGBT, a gate voltage higher than the threshold value is applied to the gate electrode G of the field effect transistor Tr3 via the gate wiring GL. Apply. Then, the field effect transistor Tr3 is turned on, and the base current of the pnp bipolar transistor Tr1 flows. As a result, a current flows between the collector electrode CLE of the IGBT to which the pnp bipolar transistor Tr1 is connected and the emitter electrode EE of the IGBT. In this way, the IGBT is turned on.

At this time, the current flowing from the collector electrode CLE of the IGBT to the emitter electrode EE of the IGBT flows from the collector electrode CLE through the p-type channel formation layer PCH to the emitter electrode EE formed so as to be embedded in the contact hole C1. . Therefore, the current that flows from the collector electrode CLE of the IGBT to the emitter electrode EE of the IGBT passes through the resistance of the p-type channel formation layer PCH. The p-type channel formation layer PCH is an npn bipolar transistor Tr2 formed parasitically from the n ⁺ -type emitter layer NE, the p-type channel formation layer PCH, and the n ⁻ -type base layer NB (including the n-type hole barrier layer NHB). To serve as a base for Therefore, when the resistance of the p-type channel formation layer PCH (base resistance of the npn bipolar transistor Tr2) increases, the voltage drop due to the current flowing through this resistance increases, and the base of the npn bipolar transistor Tr2 (p-type channel formation layer PCH) The emitter (n ⁺ -type emitter layer NE) is forward-biased and the npn bipolar transistor Tr2 is turned on. Then, the collector current of the npn bipolar transistor Tr2 flows from the n ⁻ type base layer NB (n type hole barrier layer NHB) to the n ⁺ type emitter layer NE through the p type channel formation layer PCH. Since the collector current of the npn bipolar transistor Tr2 becomes the base current of the pnp bipolar transistor Tr1, the current flowing from the collector electrode CLE of the IGBT to the emitter electrode EE of the IGBT is further increased.

  The collector current of the npn bipolar transistor Tr2 becomes the base current of the pnp bipolar transistor Tr1, and the base current of the pnp bipolar transistor Tr1 continues to flow even when the field effect transistor Tr3 is turned off. That is, when the parasitic npn bipolar transistor Tr2 is turned on, a current that cannot be controlled by the field effect transistor Tr3 flows as a base current of the pnp bipolar transistor Tr1. As a result, even if the field effect transistor Tr3 is turned off, current continues to flow between the IGBT collector electrode CLE and the IGBT emitter electrode EE until the IGBT is destroyed. This phenomenon is a latch-up phenomenon.

The cause of the latch-up phenomenon is that the parasitic npn bipolar transistor Tr2 is turned on. The parasitic npn bipolar transistor Tr2 is easily turned on because the resistance of the p-type channel formation layer PCH (npn bipolar transistor Tr2). This is a case where the base resistance of the Therefore, in order to prevent the latch-up phenomenon, in the IGBT, it is necessary to reduce the resistance of the p-type channel formation layer PCH to make it difficult for the npn bipolar transistor Tr2 to be turned on. From this, in order to make ohmic connection between the contact hole C1 reaching the p-type channel formation layer PCH and the p-type channel formation layer PCH and reduce the resistance, the inside of the p-type channel formation layer PCH below the bottom of the contact hole C1 Is provided with a p ⁺ -type contact layer PC. That is, the p ⁺ -type contact layer PC has a function of reducing the resistance of the p-type channel formation layer PCH so as to prevent the latch-up phenomenon, and the impurity concentration of the p-type impurity is higher than that of the p-type channel formation layer PCH. Is formed to be large.

Even in this case, the p-type channel formation layer PCH exists between the p ⁺ -type contact layer PC and the n-type hole barrier layer NHB. At this time, if an n-type hole barrier layer NHB having an n-type impurity concentration higher than that of the n ⁻ -type base layer NB is formed, the resistance of the p-type channel formation layer PCH in contact with the n-type hole barrier layer NHB increases. It is. This mechanism will be described. Since the p-type channel formation layer PCH is a p-type semiconductor layer and the n-type hole barrier layer NHB is an n-type semiconductor layer, a pn junction is formed at the boundary between the p-type channel formation layer PCH and the n-type hole barrier layer NHB. It is formed. When the n-type hole barrier layer NHB is formed in this pn junction, the electron concentration of the n-type semiconductor layer becomes higher than that of the pn junction between the n ⁻ -type base layer NB and the p-type channel formation layer PCH. In the pn junction, for example, diffusion due to a concentration difference between the electron concentration (majority carrier) of the n-type semiconductor layer forming the pn junction and the electron concentration (minority carrier) of the p-type semiconductor layer tends to occur. That is, diffusion tends to occur in a direction in which the difference in electron concentration between the n-type semiconductor layer and the p-type semiconductor layer is to be relaxed. On the other hand, in the pn junction, a depletion layer is generated, and an electric field is also generated by this depletion layer. In the pn junction, the diffusion due to the concentration difference and the electric field due to the depletion layer work in opposite directions, and the diffusion due to the concentration difference and the electric field due to the depletion layer are balanced. The width of the depletion layer is determined so as to realize this equilibrium state. From this, the formation of the n-type hole barrier layer NHB means that the electron concentration of the n-type semiconductor layer in the pn junction becomes high, and the diffusion tendency due to the concentration difference becomes strong. Therefore, the depletion layer electric field for balancing with the diffusion due to the concentration difference is increased. Increasing the electric field in the depletion layer means increasing the width of the depletion layer. That is, the depletion layer formed in the p-type channel formation layer PCH extends. Since the depletion layer functions as an electrically insulating region, an increase in the width of the depletion layer means an increase in the resistance of the p-type channel formation layer PCH. Therefore, when the n-type hole barrier layer NHB is formed, the resistance of the p-type channel formation layer PCH is increased, and the parasitic npn bipolar transistor Tr2 is easily turned on.

Therefore, in the first embodiment, as shown in FIG. 5, a p-type latch-up prevention layer PL is provided between the p ⁺ -type contact layer PC and the n-type hole barrier layer NHB. The provision of the p-type latch-up prevention layer PL is a third feature point of the first embodiment. That is, in the first embodiment, the p-type latch-up prevention layer PL having a higher p-type impurity concentration than the p-type channel formation layer PCH between the p ⁺ -type contact layer PC and the n-type hole barrier layer NHB. Is provided. Thus, by providing the p-type latch-up prevention layer PL having an impurity concentration higher than that of the p-type channel formation layer PCH, the base resistance of the parasitic npn bipolar transistor Tr2 can be reduced. That is, the p-type latch-up prevention layer PL has a function of suppressing the latch-up phenomenon that occurs in the IGBT, and in particular, even if the n-type hole barrier layer NHB is provided, the latch-up does not occur in the IGBT. it can. The impurity concentration of the p-type latch-up prevention layer PL is set to be higher than that of the p-type channel formation layer PCH and lower than that of the p ⁺ -type contact layer PC.

Next, the fourth feature point of the first embodiment will be described. FIG. 12 is a diagram illustrating the fourth feature point in the first embodiment. As shown in FIG. 12, the fourth feature point of the first embodiment is that the trench TR in which the gate electrode G is embedded passes through the n-type hole barrier layer NHB and reaches the n ⁻ -type base layer NB. It is a point that is deeply formed. Specifically, for example, the trench TR is formed so that the bottom thereof exists at a position deeper than twice the depth of the p-type channel formation layer PCH. In the description so far, the configuration of the IGBT not having the fourth feature point has been described, but here, by configuring the IGBT to have the fourth feature point of the first embodiment, there is a further advantage. Explain that.

Below, the advantage of the 4th feature point in this Embodiment 1 is explained. First, as described above, the n-type hole barrier layer NHB is provided between the n ⁻ -type base layer NB and the p-type channel formation layer PCH. This n-type hole barrier layer NHB has a function of suppressing the outflow of holes from the n ⁻ type base layer NB. From the viewpoint of suppressing the outflow of holes, the impurities of the n-type hole barrier layer NHB It is desirable that the concentration be high.

However, if the impurity concentration of the n-type hole barrier layer NHB is too high, a latch-up phenomenon is likely to occur, and when the IGBT is turned off, the n-type hole barrier layer NHB and the p-type channel formation layer PCH (p-type latch-up) The width of the depletion layer extending from the pn junction formed at the boundary with the prevention layer PL) to the n ⁻ type base layer NB is reduced. That is, when the impurity concentration of the n-type hole barrier layer NHB becomes high, the extension of the depletion layer is suppressed. As a result, the width of the depletion layer that passes through the n-type hole barrier layer NHB and extends to the n ⁻ -type base layer becomes small. . This means that the entire n ⁻ -type base layer NB is not depleted, and among the holes remaining in the n ⁻ -type base layer NB, the amount of holes remaining outside the depletion layer is increased. It takes a long time to be swept out of the IGBT. That is, if the impurity concentration of the n-type hole barrier layer NHB is too high, there is a side effect of increasing turn-off loss. From the above, the impurity concentration of the n-type hole barrier layer NHB cannot be made too high.

Therefore, the first embodiment further employs a structure that suppresses the outflow of holes from the n ⁻ -type base layer NB. This structure is the fourth characteristic point of the first embodiment, and the trench TR in which the gate electrode G is embedded is formed deeply so as to penetrate the n-type hole barrier layer NHB and reach the n ⁻ -type base layer NB. It is what you want to do. FIG. 12 is a diagram illustrating the fourth feature point in the first embodiment. First, a positive voltage is applied to the gate electrode G to turn on the IGBT. In this case, as shown in FIG. 12, since a positive voltage is applied to the gate electrode G, electrons are transferred from the n ⁻ type base layer NB in contact with the bottom of the trench TR to the peripheral region at the bottom of the trench TR. Accumulate to form a storage region. Since this accumulation region has a high n-type impurity concentration, it has a function of suppressing the outflow of holes from the n ⁻ -type base layer NB. In particular, when the n-type impurity concentration of the accumulation region is higher than the impurity concentration of the n-type hole barrier layer NHB, the function of suppressing the outflow of holes becomes larger than that of the n-type hole barrier layer NHB. This means that the amount of holes accumulated in the n ⁻ -type base layer NB increases, and as a result, the on-voltage of the IGBT can be reduced.

Further, considering the case where the IGBT is turned off, for example, a GND voltage is applied to the gate electrode G. Therefore, since the gate electrode G is not at a positive voltage, the accumulation region formed when the IGBT is turned on disappears. That is, when the IGBT is turned off, the accumulation region formed in the peripheral region at the bottom of the trench TR disappears. This means that when the IGBT is turned off, the extension of the depletion layer formed in the n ⁻ -type base layer NB is not inhibited by the accumulation region having a high impurity concentration. For this reason, when the IGBT is turned off, the depletion layer extends over the entire n ⁻ -type base layer NB, so that the turn-off loss can be reduced. From the above, according to the fourth feature point, the trench TR in which the gate electrode G is buried is formed deeply so as to penetrate the n-type hole barrier layer NHB and reach the n ⁻ -type base layer NB. The on-voltage of the IGBT can be reduced without increasing.

  In the first embodiment, as described above, the first feature point to the fourth feature point are provided, but it is not necessary to have all of the first feature point to the fourth feature point. However, according to the IGBT including all of the first to fourth feature points, it is possible to achieve both the reduction of the on-voltage and the reduction of the turn-off loss, and to provide the highest performance IGBT. Hereinafter, it will be described that an IGBT including all of the first to fourth feature points has the highest performance.

  FIG. 13 is a graph plotting the relationship between the ON voltage and the turn-off fall time (turn-off loss) by changing the structure of the IGBT. In FIG. 13, the vertical axis indicates the on-voltage (V), and the horizontal axis indicates the turn-off fall time (ns). At this time, since the IGBT having a low ON voltage and a short turn-off fall time has high performance, the region closer to the origin in FIG. 13 means that higher performance of the IGBT can be realized.

  In FIG. 13, first, the conditions A to D will be described. Condition A shows the condition that (Qp / Qn) indicating the hole injection efficiency is (Qp / Qn) ≈1, and Condition B is that the hole injection efficiency is (Qp / Qn) ≈2. It shows the condition to do. Similarly, Condition C shows a condition in which (Qp / Qn) indicating hole injection efficiency is (Qp / Qn) ≈20, and Condition D is a hole injection efficiency (Qp / Qn). The condition of ≈10 is shown. Of these conditions A to D, it can be seen that condition D is closest to the origin of the graph as shown in FIG. In other words, if the condition D is (Qp / Qn) ≈10, the reduction of the ON voltage and the reduction of the turn-off fall time can be most compatible. First, it can be seen that by setting 4 ≦ (Qp / Qn) ≦ 16, which is the first feature point of the first embodiment, high performance of the IGBT can be realized.

Subsequently, the conditions (1) to (4) will be described. Condition (1) is that, in the IGBT structure, the n-type hole barrier layer NHB, which is the second feature point, is formed (with HB), and the depth of the trench TR, which is the fourth feature point, is the n ⁻ -type base layer The case where it forms deeply so that NB may be reached is shown. Condition (2) is that the n-type hole barrier layer NHB, which is the second feature point, is formed in the IGBT structure (with HB), but the depth of the trench TR is a normal depth. Condition (3) is that the n-type hole barrier layer NHB is not formed (no HB) in the IGBT structure, the depth of the trench TR is set to a normal depth, and a thinned-out structure is provided. Condition (4) shows a case where the n-type hole barrier layer NHB is not formed (no HB) and the depth of the trench TR is also normal in the IGBT structure.

Here, the thinning structure shown in the condition (3) is a structure shown in FIG. That is, the contact hole C1, the p ⁺ -type contact layer PC and the n ⁺ -type emitter layer NE connected to the emitter electrode EE are not formed so as to be thinned between the plurality of trenches TR. That is, this is a structure in which cells constituting the IGBT are thinned out. According to this structure, since the path through which holes pass from the n ⁻ type base layer NB to the emitter electrode EE is reduced, the amount of holes accumulated in the n ⁻ type base layer NB increases when the IGBT is turned on. In addition, the ON voltage can be reduced by conductivity modulation. That is, the IGBT thinning-out structure is one structure for realizing a reduction in on-voltage.

  As shown in FIG. 13, let us consider a condition D that can achieve the highest performance of the IGBT among the conditions A to D. Consider a case where conditions (1) to (3) are further added in the structure of the IGBT satisfying the condition D. Then, as shown in FIG. 13, the condition (1) is plotted at a position closest to the origin of the graph, and it can be seen that the IGBT can have high performance. That is, when the structure of the IGBT is formed so as to satisfy the condition D and the condition (1), the performance of the IGBT can be enhanced most. That is, the IGBT structure having the first feature point, the second feature point, and the fourth feature point in the first embodiment can achieve a high performance that can reduce the on-voltage and the turn-off fall time. An IGBT can be provided. At this time, by providing the third feature point in the first embodiment, it is possible to provide a highly reliable IGBT that can prevent latch-up.

  In the above, the case where priority is given to the reduction of the ON voltage and the reduction of the turn-off fall time has been described. However, when it is desired to further secure the load short-circuit withstand capability, it is desirable to use a thinning structure as in the condition (3). The thinning structure has an effect of reducing the large current (saturation current) determined by the saturation current of the MOSFET (corresponding to the field effect transistor Tr3 in FIG. 5) when the load is short-circuited when the IGBT is turned on. For this reason, it is possible to lengthen the time (short-circuit resistance) until the IGBT that has reached the saturation current is destroyed.

  The semiconductor device according to the first embodiment is configured as described above, and the manufacturing method thereof will be described below with reference to the drawings.

First, a semiconductor substrate made of an n ⁻ type base layer NB is prepared. The semiconductor substrate made of the n ⁻ type base layer NB can be formed by, for example, the FZ method (Floating zone method). The FZ method is a kind of method for growing a silicon single crystal. Specifically, in an argon gas atmosphere, one of the polycrystalline silicon ingots is brought into contact with a seed crystal (single crystal piece), and the polycrystalline silicon ingot is heated and melted in a strip shape with a coil to which a high frequency voltage is applied, and the strip region is seeded. In this method, the entire ingot is gradually single-crystallized by moving from the crystal region.

Next, as shown in FIG. 15, the silicon oxide film 10 is formed on the main surface (front surface) of the n ⁻ -type base layer NB (semiconductor substrate), and then the silicon nitride film 11 is formed on the silicon oxide film 10. . The silicon oxide film 10 can be formed by using, for example, a thermal oxidation method, and the silicon nitride film 11 can be formed by, for example, a CVD (Chemical Vapor Deposition) method. Then, the silicon nitride film 11 is patterned by using a photolithography technique and an etching technique. The patterning of the silicon nitride film 11 is performed so as to open a region for forming an element isolation region.

Subsequently, a resist film R1 is applied on the patterned silicon nitride film 11. Then, the resist film R1 is patterned by a photolithography technique. The patterning of the resist film R1 is performed so as to open a region for forming the n-type hole barrier layer NHB. Thereafter, an n-type hole barrier layer NHB is formed in the cell region by ion implantation using the patterned resist film R1 as a mask. The n-type hole barrier layer NHB is performed by introducing an n-type impurity such as phosphorus into the n ⁻ -type base layer NB by an ion implantation method. The n-type hole barrier layer NHB is formed as a region having a higher impurity concentration of n-type impurities than the n ⁻ -type base layer NB.

Next, as shown in FIG. 16, after removing the patterned resist film R1, a resist film R2 is further applied on the semiconductor substrate. Then, the resist film R2 is patterned by exposing and developing the resist film R2. The patterning of the resist film R2 is performed so as to open a region for forming a p-type well. Thereafter, a p-type well PWL is formed by ion implantation using the patterned resist film R2 as a mask. The p-type well PWL is performed by introducing a p-type impurity such as boron into the n ⁻ -type base layer NB.

  Subsequently, as shown in FIG. 17, after removing the patterned resist film R2, an element isolation region LO is formed using the silicon oxide film 10 and the patterned silicon nitride film 11. The element isolation region LO is formed by, for example, a selective oxidation method, but may be formed by using an STI method as another method.

Next, as shown in FIG. 18, a trench (gate trench) TR is formed by using a photolithography technique and an etching technique. At this time, the bottom of the trench TR may be formed so as to exist in the n-type hole barrier layer NHB, and in order to realize the fourth feature point in the first embodiment, the trench TR has an n-type hole. The barrier layer NHB may be formed so as to reach the n ⁻ type base layer NB. The following description will be made on the assumption that the bottom of the trench TR is formed so as to exist in the n-type hole barrier layer NHB.

Thereafter, as shown in FIG. 19, a gate insulating film GOX is formed on the surface of the semiconductor substrate in which the trench TR is formed. The gate insulating film GOX is formed of, for example, a silicon oxide film, and can be formed using, for example, a thermal oxidation method. However, the gate insulating film GOX is not limited to the silicon oxide film and can be variously changed. For example, the gate insulating film GOX may be a silicon oxynitride film (SiON). That is, a structure in which nitrogen is segregated at the interface between the gate insulating film GOX and the semiconductor substrate may be employed. The silicon oxynitride film has a higher effect of suppressing generation of interface states in the film and reducing electron traps than the silicon oxide film. Therefore, the hot carrier resistance of the gate insulating film GOX can be improved, and the insulation resistance can be improved. In addition, the silicon oxynitride film is less likely to penetrate impurities than the silicon oxide film. For this reason, by using a silicon oxynitride film for the gate insulating film GOX, it is possible to suppress fluctuations in the threshold voltage caused by diffusion of impurities in the gate electrode toward the semiconductor substrate. For example, the silicon oxynitride film may be formed by heat-treating the semiconductor substrate in an atmosphere containing nitrogen such as NO, NO _2, or NH ₃ . Further, after forming a gate insulating film GOX made of a silicon oxide film on the surface of the semiconductor substrate, the semiconductor substrate is heat-treated in an atmosphere containing nitrogen, and nitrogen is segregated at the interface between the gate insulating film GOX and the semiconductor substrate. The same effect can be obtained.

  Further, the gate insulating film GOX may be formed of a high dielectric constant film having a dielectric constant higher than that of a silicon oxide film, for example. Conventionally, a silicon oxide film has been used as the gate insulating film GOX from the viewpoint of high insulation resistance and excellent electrical and physical stability at the silicon-silicon oxide interface. However, with the miniaturization of elements, the thickness of the gate insulating film GOX is required to be extremely thin. When such a thin silicon oxide film is used as the gate insulating film GOX, a so-called tunnel current is generated in which electrons flowing through the IGBT channel tunnel through the barrier formed by the silicon oxide film and flow to the gate electrode.

  Therefore, by using a material having a dielectric constant higher than that of the silicon oxide film, a high dielectric constant film capable of increasing the physical film thickness even when the capacitance is the same has been used. According to the high dielectric constant film, since the physical film thickness can be increased even if the capacitance is the same, the leakage current can be reduced. In particular, the silicon nitride film is also a film having a higher dielectric constant than the silicon oxide film, but in the first embodiment, it is desirable to use a high dielectric constant film having a higher dielectric constant than the silicon nitride film.

For example, a hafnium oxide film (HfO ₂ film), which is one of hafnium oxides, is used as a high dielectric constant film having a dielectric constant higher than that of a silicon nitride film, but instead of a hafnium oxide film, a hafnium aluminate film is used. Other hafnium-based insulating films such as HfON film (hafnium oxynitride film), HfSiO film (hafnium silicate film), HfSiON film (hafnium silicon oxynitride film), and HfAlO film can also be used. Further, a hafnium-based insulating film in which an oxide such as tantalum oxide, niobium oxide, titanium oxide, zirconium oxide, lanthanum oxide, or yttrium oxide is introduced into these hafnium-based insulating films can also be used. Since the hafnium-based insulating film has a dielectric constant higher than that of the silicon oxide film or the silicon oxynitride film, like the hafnium oxide film, the same effect as that obtained when the hafnium oxide film is used can be obtained.

  Subsequently, as shown in FIG. 20, a polysilicon film is formed on the semiconductor substrate including the inside of the trench TR. An n-type impurity such as phosphorus is introduced into the polysilicon film, and can be formed by, for example, a CVD method. The polysilicon film into which this phosphorus has been introduced fills the trench TR and is formed on the semiconductor substrate. Thereafter, the polysilicon film into which phosphorus is introduced is patterned by using a photolithography technique and an etching technique. By this patterning, the gate electrode G is formed so as to fill the trench TR formed in the cell region, and the gate lead line GH extending from the trench TR onto the semiconductor substrate is formed in the gate wiring lead region.

  Next, as shown in FIG. 21, a polysilicon film is formed on the semiconductor substrate on which the gate electrode G is formed. Conductive impurities are not introduced into this polysilicon film. Then, the polysilicon film is patterned by using a photolithography technique and an etching technique. Thereby, the conductor film CF can be formed in the temperature detection diode formation region.

Subsequently, as shown in FIG. 22, a p-type channel formation layer PCH is formed in the cell region by using a photolithography technique and an ion implantation method. The p-type channel formation layer PCH can be formed by introducing a p-type impurity such as boron into the n-type hole barrier layer NHB. After that, by using again the photolithography technique and the ion implantation method, the n ⁺ type emitter layer NE is formed in the cell region, and the n ⁺ type semiconductor layer NR is formed in the termination region. That is, in the cell region, an n ⁺ -type emitter layer NE is formed by introducing an n-type impurity such as phosphorus into the surface of the semiconductor substrate above the p-type channel formation layer PCH. Similarly, in the temperature detection diode formation region, the n-type semiconductor layer N1 and the n-type semiconductor layer N2 are formed by introducing an n-type impurity into the conductor film.

  Next, the p-type semiconductor layer P1 and the p-type semiconductor layer P2 are formed in the temperature detection diode formation region by using a photolithography technique and an ion implantation method. Specifically, the p-type semiconductor layer P1 and the p-type semiconductor layer P2 are formed by introducing a p-type impurity such as boron into the conductor film. As a result, a pn junction diode serving as a temperature detection diode is formed in the temperature detection diode formation region.

  Then, as shown in FIG. 23, an interlayer insulating film IL1 is formed on the surface of the semiconductor substrate. The interlayer insulating film IL1 is formed of, for example, a laminated film of a PSG (phospho silicate glass) film and an SOG (spin on glass) film. Thereafter, a trench penetrating the interlayer insulating film IL1 is formed in the cell region by using a photolithography technique and an etching technique. Then, the contact hole C1 is formed between the trenches TR by etching the semiconductor substrate exposed from the groove. The contact hole C1 is formed so as to penetrate the interlayer insulating film IL1 and reach the p-type channel formation layer PCH.

Next, by using a photolithography technique and an ion implantation method, a p ⁺ type contact layer PC is formed in the p type channel formation layer PCH immediately below the bottom of the contact hole C1. The p ⁺ -type contact layer PC is formed by introducing a p-type impurity such as boron into the p-type channel formation layer, and the impurity concentration of the p ⁺ -type contact layer PC is higher than the impurity concentration of the p-type channel formation layer. It is high.

Thereafter, as shown in FIG. 24, the p-type latch-up prevention layer PL is formed below the p ⁺ -type contact layer PC by using the photolithography technique and the ion implantation method again. The p-type latch-up prevention layer PL is formed by introducing a p-type impurity such as boron into the p-type channel formation layer PCH, and the impurity concentration of the p-type latch-up prevention layer PL is that of the p-type channel formation layer PCH. The impurity concentration is higher than the impurity concentration and lower than the impurity concentration of the p ⁺ -type contact layer PC. This p-type latch-up prevention layer PL is formed between the p ⁺ -type contact layer PC and the n-type hole barrier layer NHB. The p-type latch-up prevention layer PL is formed so as to be in contact with the p ⁺ -type contact layer PC and also in contact with the n-type hole barrier layer NHB.

Subsequently, as shown in FIG. 25, contact holes C2 to C4 are formed in the interlayer insulating film IL1 by using a photolithography technique and an etching technique. Specifically, a contact hole C2 is formed in the gate wiring lead region, and the gate lead line GH is exposed at the bottom of the contact hole C2. Similarly, a contact hole C3 is formed in the temperature detection diode formation region, the n-type semiconductor layer N1 is exposed at the bottom of the contact hole C3, and the p-type semiconductor layer P2 is exposed at the bottom of the contact hole C3. Form. Further, a contact hole C4 in the termination region, and that p-type well PWL in the bottom of the contact hole C4 is exposed, to form what n ⁺ -type semiconductor layer NR is exposed at the bottom of the contact hole C4.

  Thereafter, a titanium tungsten film 12 is formed on the interlayer insulating film IL1 including the insides of the contact holes C1 to C4. The titanium tungsten film 12 is a film that functions as a barrier conductor film, and can be formed by using, for example, a sputtering method. Then, an aluminum film 13 is formed on the titanium tungsten film 12. The aluminum film 13 can be formed using, for example, a sputtering method, and may be formed from an aluminum silicon (AlSi) film instead of the aluminum film 13. The barrier conductor film is not limited to the titanium tungsten film, and may be formed from a titanium film or a molybdenum silicide film.

  Next, the laminated film of the titanium tungsten film 12 and the aluminum film 13 is patterned by using a photolithography technique and an etching technique. Thereby, in the cell region, an emitter electrode EE composed of a laminated film of the titanium tungsten film 12 and the aluminum film 13 is formed. A gate wiring GL made of a titanium tungsten film 12 and an aluminum film 13 is formed in the gate wiring drawing region, and a cathode electrode CE and an anode electrode AE made of the titanium tungsten film 12 and the aluminum film 13 are formed in the temperature detection diode forming region. It is formed. Similarly, a guard ring GR composed of a titanium tungsten film 12 and an aluminum film 13 is formed in the termination region.

  Subsequently, as shown in FIG. 26, a surface protective film (passivation film) PV is formed on the semiconductor substrate. This surface protective film can be formed from a polyimide resin, for example. Then, an opening is provided in the surface protective film PV. Specifically, a part of the emitter electrode EE is exposed in the cell region, and a part of the gate wiring (including the gate pad) GL is exposed in the gate wiring drawing region. Similarly, the anode electrode AE and the cathode electrode CE are exposed in the temperature detection diode formation region.

Next, as shown in FIG. 27, a reinforcing plate SH is affixed on the surface protective film PV formed on the semiconductor substrate. This reinforcement board SH is comprised from the glass substrate, for example. Then, the back surface of the semiconductor substrate (the surface on which the n ⁻ type base layer NB is exposed) is ground. Thereafter, as shown in FIG. 28, an n ⁺ -type field stop layer NF is formed on the back surface of the semiconductor substrate. The n ⁺ type field stop layer NF is formed by introducing an n-type impurity such as phosphorus into the back surface of the semiconductor substrate using an ion implantation method. Thereafter, laser annealing is performed to activate the introduced n-type impurity. According to laser annealing, since it can be locally heated, the structure formed on the surface (main surface) of the semiconductor substrate is introduced into the n ⁺ -type field stop layer NF without causing damage due to heat treatment. N-type impurities can be activated.

Subsequently, as shown in FIG. 29, a p ⁺ -type collector layer PCL is formed on the back surface of the semiconductor substrate. The p ⁺ -type collector layer PCL is formed by introducing a p-type impurity such as boron into the back surface of the semiconductor substrate using an ion implantation method. Thereafter, laser annealing is performed to activate the introduced p-type impurity. Since laser annealing can be locally heated, the structure formed on the surface (main surface) of the semiconductor substrate is introduced into the p ⁺ -type collector layer PCL without causing damage due to heat treatment. The p-type impurity can be activated.

In the first embodiment, the introduction of n-type impurities and laser annealing for forming the n ⁺ -type field stop layer NF and the introduction of p-type impurities and laser annealing for forming the p ⁺ -type collector layer PCL are adjusted. To do. Thus, the ratio of the carrier amount (hole amount) Qp present in the p ⁺ -type collector layer PCL and the carrier amount (electron amount) Qn present in the n ⁺ -type field stop layer NF (Qp / Qn) Is formed to be 4 or more and 16 or less.

  Next, as shown in FIG. 30, a nickel silicide film NS is formed on the back surface of the semiconductor substrate. The nickel silicide film NS is formed by forming a nickel film on the back surface of the semiconductor substrate, for example, by sputtering, and then performing laser annealing on the nickel film. The nickel silicide film NS is formed for improving moisture resistance. In the first embodiment, the nickel silicide film NS is formed, but the nickel silicide film NS may not be formed.

  Subsequently, as shown in FIG. 31, a collector electrode CLE is formed on the back surface of the semiconductor substrate. The collector electrode CLE is, for example, a laminated film of titanium (Ti) film / nickel (Ni) film / gold (Au) film, aluminum (Al) film / titanium (Ti) film / nickel (Ni) film / gold ( (Au) film. Then, the semiconductor device according to the first embodiment can be manufactured by finally removing the reinforcing plate SH.

(Embodiment 2)
In the first embodiment, the p ⁺ -type collector layer PCL and the n ⁺ -type field stop layer NF are introduced into the semiconductor substrate by ion implantation, and then the introduced conductive impurities are activated by laser annealing. The example to be formed has been described. In the second embodiment, an example will be described in which the p ⁺ type collector layer PCL is formed as a semiconductor substrate, and the n ⁺ type field stop layer NF is formed as an epitaxial layer on the semiconductor substrate.

FIG. 32 is a cross-sectional view showing the configuration of the IGBT according to the second embodiment. The configuration of the IGBT in the second embodiment is, for example, substantially the same as the configuration of the IGBT in the first embodiment shown in FIG. 32, in the IGBT according to the second embodiment, an n ⁺ type field stop layer NF made of an n ⁺ type semiconductor layer is formed on a p ⁺ type collector layer PCL made of a p ⁺ type semiconductor layer. An n ⁻ type base layer NB made of an n ⁻ type semiconductor layer is formed on the n ⁺ type field stop layer NF, and an n type hole barrier layer NHB made of an n type semiconductor layer is formed on the n ⁻ type base layer NB. Is formed. A p-type channel forming layer PCH made of a p-type semiconductor layer is formed on the n-type hole barrier layer NHB, and an n ⁺ -type emitter layer NE made of an n ⁺ -type semiconductor layer is formed on the p-type channel forming layer PCH. Has been.

Trench TR is formed as the surface of the n ⁺ -type emitter layer NE through the n ⁺ -type emitter layer NE and the p-type channel forming layer PCH reaches the n-type hole barrier layer NHB. A gate insulating film GOX is formed on the inner wall of the trench TR, and a gate electrode G is formed on the gate insulating film GOX so as to fill the trench TR. An interlayer insulating film IL1 is formed on the n ⁺ -type emitter layer NE including the gate electrode G, and the interlayer insulating film IL1 and the n ⁺ -type emitter layer NE penetrate between the plurality of trenches TR. A contact hole C1 reaching the p-type channel formation layer PCH is formed, and a p ⁺ -type contact layer PC made of a p ⁺ -type semiconductor layer is formed in the p-type channel formation layer PCH so as to be in contact with the bottom of the contact hole C1. Yes. A p-type latch-up prevention layer PL made of a p-type semiconductor layer is formed so as to be in contact with the p ⁺ -type contact layer PC and the n-type hole barrier layer NHB.

  A laminated film of a titanium tungsten film 12 and an aluminum film 13 as a barrier conductor film is formed on the interlayer insulating film IL1 including the inside of the contact hole C1. The laminated film made of the titanium tungsten film 12 and the aluminum film 13 becomes the emitter electrode EE.

The difference between the IGBT according to the second embodiment configured as described above and the IGBT according to the first embodiment is the method for forming the p ⁺ -type collector layer PCL. In the first embodiment, the p ⁺ type collector layer PCL is formed by introducing conductive impurities into the semiconductor substrate by ion implantation and then activating the introduced conductive impurities by laser annealing. On the other hand, in the second embodiment, the p ⁺ type collector layer PCL is formed as a semiconductor substrate. That is, the p ⁺ type collector layer PCL is formed as a p ⁺ type semiconductor substrate. Therefore, the p ⁺ -type collector layer PCL in the second embodiment is thicker than the p ⁺ -type collector layer PCL in the first embodiment. Further, in the first embodiment, the n ⁺ type field stop layer NF is formed by introducing conductive impurities into the semiconductor substrate by ion implantation and then activating the introduced conductive impurities by laser annealing. ing. In contrast, in the second embodiment, the n ⁺ type field stop layer NF is formed as an epitaxial layer on the semiconductor substrate.

The second embodiment can also be configured to have the second feature point and the third feature point described in the first embodiment. That, n ^- by forming the n-type hole barrier layer NHB suppressing outflow of holes from the mold base layer NB, n ^- -type base layer can increase the conductivity modulation in the NB, the on-voltage of the IGBT Can be reduced. By providing the p-type latch-up prevention layer PL, the parasitic npn bipolar transistor can be prevented from being turned on and the IGBT latch-up breakdown can be suppressed. Furthermore, the IGBT according to the second embodiment can have the fourth feature point described in the first embodiment. In other words, the trench TR in which the gate electrode G is buried is formed deeply so as to penetrate the n-type hole barrier layer NHB and reach the n ⁻ -type base layer NB, thereby further increasing the turn-off loss. The on-voltage can be reduced. From the above, even in the IGBT according to the second embodiment, high performance of the IGBT can be realized.

The IGBT in the second embodiment is configured as described above, and the manufacturing method thereof is substantially the same as the manufacturing method of the IGBT in the first embodiment. First, a p-type semiconductor substrate to be a p ⁺ -type collector layer PCL is prepared, and an n ⁺ -type field stop layer NF is formed on the p-type semiconductor substrate by using an epitaxial growth technique. Then, an n ⁻ type base layer NB is formed on the n ⁺ type field stop layer NF using an epitaxial growth technique. Subsequent steps are the same as those in the first embodiment. However, in the first embodiment, the p ⁺ -type collector layer PCL and the n ⁺ -type field stop layer NF are formed by ion implantation from the back surface of the semiconductor substrate. However, in the second embodiment, as described above, the epitaxial growth technique is used. Therefore, the ion implantation process for forming the p ⁺ type collector layer PCL and the n ⁺ type field stop layer NF is not performed. In this manner, the semiconductor device according to the second embodiment can be formed.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  In the above-described embodiment, the case where the technical idea of the present invention is applied to a trench IGBT has been described. However, the present invention is not limited to this, and the technical idea of the present invention can also be applied to, for example, a planar IGBT.

  The present invention can be widely used in the manufacturing industry for manufacturing semiconductor devices.

It is a figure which shows the circuit diagram of the three-phase motor in Embodiment 1 of this invention. It is a top view of the semiconductor chip which formed IGBT. It is sectional drawing cut | disconnected by the AA line of FIG. It is the figure which expanded the cell area | region which forms IGBT. It is the figure which matched the circuit structure and device structure about IGBT currently formed in the cell area | region. The figure showing the relationship between the depth from the back surface of the semiconductor chip and the carrier concentration defines the carrier amount of the p ⁺ -type collector layer and the carrier amount of the n ⁺ -type field stop layer. It is a graph which shows the relationship between (Qp / Qn) and ON voltage. It is a graph which shows the relationship between (Qp / Qn) and turn-off fall time. It is a graph which shows the relationship between the amount of Lindos and the amount of carriers of an n ⁺ type field stop layer. It is a graph which shows the relationship between the amount of borondes and the amount of carriers of a p ⁺ type collector layer. It is a figure explaining the measurement principle of carrier concentration distribution by a spreading resistance microscope. FIG. 6 is a diagram for explaining one of feature points in the first embodiment. It is a figure which shows the relationship between turn-off fall time and ON voltage. It is a figure explaining the thinning-out structure of IGBT. 7 is a cross-sectional view showing a manufacturing step of the semiconductor device in the first embodiment. FIG. FIG. 16 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 15; FIG. 17 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 16; FIG. 18 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 17; FIG. 19 is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 18; FIG. 20 is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 19; FIG. 21 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 20; FIG. 22 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 21; FIG. 23 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 22; FIG. 24 is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 23; FIG. 25 is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 24; FIG. 26 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 25; FIG. 27 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 26; FIG. 28 is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 27; FIG. 29 is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 28; FIG. 30 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 29; FIG. 31 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 30; FIG. 6 is a cross-sectional view showing a structure of an IGBT in a second embodiment.

Explanation of symbols

1 Three-phase motor 2 Power semiconductor device 3 Control circuit 4 IGBT
5 Diode 10 Silicon oxide film 11 Silicon nitride film 12 Titanium tungsten film 13 Aluminum film AE Anode electrode AMP Wide range logarithmic amplifier C1 Contact hole C2 Contact hole C3 Contact hole C4 Contact hole CE Cathode electrode CF Conductor film CHP Semiconductor chip CLE Collector electrode E Power supply EE Emitter electrode e Electron G Gate electrode GH Gate lead line GL Gate wiring GOX Gate insulating film GP Gate pad GR Guard ring h Hole IL1 Interlayer insulating film KL Cantilever LO Element isolation region N1 n-type semiconductor layer N2 n-type semiconductor layer NB n ^- -type base layer NE n ⁺ -type emitter layer NF n ⁺ -type field stop layer NHB n-type hole barrier layer NR n ⁺ -type semiconductor layer NS nickel Siri Sai Film P conductive probe P1 p-type semiconductor layer P2 p-type semiconductor layer PC p ⁺ -type contact layer PCH p-type channel forming layer PCL p ⁺ -type collector layer protective PL p-type latch-up prevention layer PV surface membrane PWL p-type well Qp Carrier amount Qn Carrier amount R1 Resist film R2 Resist film S Sample SH Reinforcing plate TR Trench Tr1 pnp bipolar transistor Tr2 npn bipolar transistor Tr3 Field effect transistor

Claims (20)

A semiconductor device including an IGBT,
The IGBT is
(A) a p-type collector layer;
(B) an n-type field stop layer formed on the p-type collector layer;
(C) an n-type base layer formed on the n-type field stop layer;
(D) an n-type hole barrier layer formed on the n-type base layer;
(E) a p-type channel forming layer formed on the n-type hole barrier layer;
(F) an n-type emitter layer formed on the p-type channel forming layer;
(G) through the n-type emitter layer and the p-type channel forming layer, a gate trench reaching the n-type hole barrier layer,
(H) a gate insulating film formed on the inner wall of the gate trench;
(I) a gate electrode formed on the gate insulating film in the gate trench;
(J) an interlayer insulating film formed on the gate electrode and the n-type emitter layer;
(K) a contact hole reaching the p-type channel formation layer through the interlayer insulating film and the n-type emitter layer;
(L) an emitter electrode formed in the contact hole and electrically connecting the n-type emitter layer and the p-type channel forming layer;
(M) a p-type contact layer formed in the p-type channel formation layer and in contact with the contact hole;
(N) a collector electrode formed on the back surface of the p-type collector layer and electrically connected to the p-type collector layer;
The carrier amount of the p-type collector layer Qp, when the carrier amount Qn of the n-type field stop layer, meets the 4 ≦ (Qp / Qn) ≦ 16,
The semiconductor device according to claim 1, wherein a bottom portion of the gate trench penetrates the n-type hole barrier layer and reaches the n-type base layer . The semiconductor device according to claim 1,
And a p-type latch-up preventing layer formed in contact with the p-type contact layer and the n-type hole barrier layer. The semiconductor device according to claim 2,
The p-type contact layer has a higher impurity concentration than the p-type channel formation layer. The semiconductor device according to claim 3,
The p-type latch-up prevention layer has a higher impurity concentration than the p-type channel formation layer and a lower impurity concentration than the p-type contact layer. The semiconductor device according to claim 1,
The n-type hole barrier layer has a higher impurity concentration than the n-type base layer. The semiconductor device according to claim 5,
The n-type field stop layer has a higher impurity concentration than the n-type base layer. The semiconductor device according to claim 1 ,
The semiconductor device according to claim 1, wherein the bottom of the gate trench is present at a position deeper than twice the depth of the p-type channel formation layer. The semiconductor device according to claim 1,
The carrier amount Qp of the p-type collector layer is 4.0 × 10 ^{13 to} 8.0 × 10 ¹³ (pieces / cm ² ), and the carrier region Qn of the n-type field stop layer is 5 × 10 ¹² to 1.0 × 10 ¹³ (pieces / cm ² ) The semiconductor device according to claim 1,
The semiconductor device according to claim 1, wherein the emitter electrode is formed of a laminated film of a barrier conductor film and a metal film. The semiconductor device according to claim 9 ,
2. The semiconductor device according to claim 1, wherein the barrier conductor film is formed of any one of a titanium film, a titanium tungsten film, and a molybdenum silicide film, and the metal film is formed of a film mainly composed of aluminum. The semiconductor device according to claim 10 ,
The collector device includes a laminated film of titanium film / nickel film / gold film or a laminated film of aluminum film / titanium film / nickel film / gold film. A method for manufacturing a semiconductor device including an IGBT, comprising:
The step of forming the IGBT includes:
(A) preparing a semiconductor substrate comprising an n-type base layer;
(B) forming an element isolation region in the semiconductor substrate;
(C) After the step (b), forming an n-type hole barrier layer on the n-type base layer in the IGBT formation region;
(D) after the step (c), forming a gate trench reaching the n-type hole barrier layer from the main surface of the semiconductor substrate;
(E) after the step (d), forming a gate insulating film on the inner wall of the gate trench;
(F) after the step (e), forming a gate electrode on the gate insulating film in the gate trench;
(G) after the step (f), forming a p-type channel formation layer on the n-type hole barrier layer by forming a p-type channel formation layer inside the semiconductor substrate;
(H) after the step (g), forming an n-type emitter layer on the p-type channel formation layer by forming an n-type emitter layer on the main surface of the semiconductor substrate;
(I) After the step (h), forming an interlayer insulating film on the main surface of the semiconductor substrate;
(J) after the step (i), forming a contact hole that reaches the p-type channel formation layer through the interlayer insulating film and the n-type emitter layer;
(K) after the step (j), forming a p-type contact layer in contact with the contact hole in the p-type channel formation layer;
(L) a step of electrically connecting the n-type emitter layer and the p-type channel forming layer by forming an emitter electrode on the interlayer insulating film including the inside of the contact hole after the step (k); ,
(M) After the step (l), forming an n-type field stop layer on the back surface of the n-type base layer;
(N) After the step (m), forming a p-type collector layer on the back surface of the n-type field stop layer;
(O) after the step (n), forming a collector electrode on the back surface of the p-type collector layer,
When the carrier amount of the p-type collector layer is Qp and the carrier amount of the n-type field stop layer is Qn, the p-type collector layer and the n-type field stop are set so as to satisfy 4 ≦ (Qp / Qn) ≦ 16. Forming a layer ,
The method of manufacturing a semiconductor device, wherein the gate trench formed in the step (d) is formed so as to penetrate the n-type hole barrier layer and reach the n-type base layer . A method of manufacturing a semiconductor device according to claim 12 ,
After the step (k), a p-type latch-up prevention layer is formed so as to be in contact with the p-type contact layer and the n-type hole barrier layer. A method for manufacturing a semiconductor device according to claim 13 , comprising:
A semiconductor device, wherein the impurity concentration of the p-type latch-up prevention layer is formed to be lower than the impurity concentration of the p-type contact layer and higher than the impurity concentration of the p-type channel formation layer. Manufacturing method. A method for manufacturing a semiconductor device according to claim 14 , comprising:
A method of manufacturing a semiconductor device, wherein an impurity concentration of the n-type hole barrier layer is higher than an impurity concentration of the n-type base layer. A method of manufacturing a semiconductor device according to claim 12 ,
The n-type field stop layer is formed by activating the introduced n-type impurities by laser annealing after injecting n-type impurities into the semiconductor substrate by ion implantation. Device manufacturing method. A method of manufacturing a semiconductor device according to claim 16 ,
The method of manufacturing a semiconductor device, wherein the n-type impurity is phosphorus. A method of manufacturing a semiconductor device according to claim 12 ,
The p-type collector layer is formed by activating the introduced p-type impurity by laser annealing after injecting a p-type impurity into the semiconductor substrate by an ion implantation method. Manufacturing method. A method of manufacturing a semiconductor device according to claim 18 ,
The method of manufacturing a semiconductor device, wherein the p-type impurity is boron. A method of manufacturing a semiconductor device according to claim 12 ,
The method of manufacturing a semiconductor device, wherein a bottom portion of the gate trench exists at a position deeper than twice the depth of the p-type channel formation layer.

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