JP2004079878A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device capable of preventing negative resistance, softer dielectric strength, and increase in a leak current when a MOS bipolar element is turnd on. <P>SOLUTION: The semiconductor device has a 2nd conductivity base layer 102 formed on a 1st main surface of a 1st conductivity semiconductor substrate 101, a gate electrode 105 formed in the 2nd conductivity base layer 102, a 1st conductivity emitter layer 107 formed on the surface of the 2nd conductivity base layer 102, a 1st conductivity field stop layer 109 and a 1st conductivity leak stop layer 110 formed in the 1st conductivity semiconductor substrate 101, a 2nd conductivity collector layer 111 formed in contact with the 1st conductivity leak stop layer 110, a 1st main electrode 108 formed on the 1st conductivity emitter layer 107 and 2nd conductivity base layer 102, and a 2nd main electrode 112 formed on the 2nd conductivity collector layer. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a power semiconductor device, and more particularly to a power device such as an IGBT.
[0002]
[Prior art]
In response to the recent demand for smaller and higher performance power supply equipment in the field of power electronics, power semiconductor devices have been required to have higher withstand voltage and higher current, as well as lower loss, higher breakdown strength, and higher speed. Focus is on improvement. In particular, in terms of high breakdown voltage and high current, an IGBT (Insulated Gate Bipolar Transistor) is used as an insulated gate semiconductor device having a breakdown voltage of about 300 V or more. IGBTs have both the high-speed switching characteristics of power MOSFETs and the high-output characteristics of bipolar transistors, and are widely used in power converters such as inverters and switching power supplies. As the gate structure of the IGBT, there are a planar structure formed in a flat plate shape and a trench structure formed buried.
[0003]
FIG. 20 shows an IGBT having a trench structure as a conventional power semiconductor device. A P-type base layer 2002 is formed on a first main surface of an N-type semiconductor substrate 2001, and a groove 2003 extending from the P-type base layer 2002 to the N-type semiconductor substrate is formed. A gate insulating film 2004 is formed in the trench 2003, and a gate electrode 2005 is buried in contact with the gate insulating film 2004. On the gate electrode 2005, an interlayer insulating film 2006 is formed. In the surface region of the P-type base layer 2002, an N-type emitter layer 2007 having a high impurity concentration is formed so as to be in contact with the side wall of the groove 2003.
[0004]
An emitter electrode 2008 is formed on the P-type base layer 2002 and the N-type emitter layer 2007 so as to contact the P-type base layer 2002 and the N-type emitter layer 2007. The gate electrode 2005 is not in contact with the emitter electrode 2008 because the interlayer insulating film 2006 is formed thereon. The N-type semiconductor substrate 2001, the P-type base layer 2002, the gate insulating film 2004, the gate electrode 2005, and the N-type emitter layer 2007 form a MOSFET. That is, a channel is formed on the sidewall of the groove 2003 of the P-type base layer 2002, and electrons are injected from the N-type emitter layer 2007 into the N-type semiconductor substrate 2001.
[0005]
On the other hand, an N-type buffer layer (field stop layer) 2009 is formed on the second main surface of the N-type semiconductor substrate 2001. On the second main surface side of the N-type semiconductor substrate 2001, a P-type collector layer 2010 and a collector electrode 2011 are formed. Here, the P-type collector layer is formed with a relatively high impurity concentration, and the P-type collector layer and the field stop layer are formed with a thickness of about 2 μm or less.
[0006]
FIG. 21 is a schematic diagram showing the impurity concentration distribution of the P-type collector layer 2010, the N-type field stop layer 2009, and the N-type semiconductor substrate 2001, which is the impurity concentration on the second main surface side. The vertical axis represents the concentration, and the horizontal axis represents the depth (the direction of the arrow is on the first main surface side).
[0007]
The operation of the IGBT will be described. When a positive voltage is applied to the collector electrode 2011 and a negative voltage is applied to the emitter electrode 2008, when a positive voltage that is more positive than the emitter electrode 2008 is applied to the gate electrode 2005, The surface of the P-type base layer 2002 in contact with the gate electrode 2005 is inverted to N-type, and an inversion layer is formed. Electrons are injected from the N-type emitter layer 2006 to the N-type semiconductor substrate 2001 through the inversion layer and reach the P-type collector layer 2010. Accordingly, the N-type semiconductor substrate 2001 and the P-type collector layer 2010 are forward-biased via the N-type field stop layer 2009, and holes are injected from the P-type collector layer 2010 into the N-type semiconductor substrate 2001. As described above, both electrons and holes are injected into the N-type semiconductor substrate 2001, and conductivity modulation occurs in the N-type semiconductor substrate 2001, so that the ON voltage is reduced. That is, the element becomes conductive.
[0008]
On the other hand, to turn off, a negative voltage is applied to the gate electrode 2005 with respect to the emitter electrode 2008. Accordingly, the inversion layer formed on the P-type base layer 2002 in contact with the gate electrode 2005 disappears, and electron injection stops.
On the other hand, a part of the holes accumulated in the N-type semiconductor substrate 2001 is discharged to the emitter electrode through the P-type base layer 2002, and the remaining holes recombine with the electrons and disappear. The device turns off.
[0009]
When a positive voltage is applied to the collector electrode 2011 and 0 V is applied to the emitter electrode 2006 and the gate electrode 2005, a depletion layer extends from a junction between the P-type base layer 2002 and the N-type semiconductor substrate 2001. , The element enters the reverse blocking state. In an IGBT called a punch-through type, the N-type field stop layer 2009 is formed, and the electric field is reduced to prevent the depletion layer from reaching the P-type collector layer and maintain the breakdown voltage. (In a non-punch-through IGBT, a thick N-type semiconductor substrate is used to prevent the depletion layer from reaching the P-type collector layer and maintain the withstand voltage.) 2. Description of the Related Art A semiconductor device described in -501382 (publicly known document) is known.
[0010]
[Problems to be solved by the invention]
When a field stop layer is formed in contact with the P-type collector layer, injection of holes at the time of turn-off can be suppressed, and turn-off loss can be reduced.
However, on the other hand, there is a problem that the leak current increases at a voltage lower than the desired withstand voltage and that the withstand voltage becomes soft. Here, the softening of the breakdown voltage is a phenomenon in which the rise of the breakdown voltage becomes gentle and the breakdown voltage decreases.
Further, if the concentration of the field stop layer is increased to suppress the leakage current, there is a problem that a negative resistance is generated at the time of turn-on, and the on-voltage increases.
[0011]
SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has as its object to provide a semiconductor device capable of preventing a negative resistance, a soft breakdown voltage, and an increase in leakage current from occurring at the time of turn-on.
[0012]
[Means for Solving the Problems]
In order to achieve the above object, a semiconductor device according to the present invention includes a first conductivity type semiconductor substrate,
A second conductivity type base layer formed on a first main surface of the first conductivity type semiconductor substrate;
A first conductivity type emitter layer formed in a surface region of the second conductivity type base layer;
A gate insulating film formed to be in contact with the second conductivity type base layer;
A gate electrode formed to be in contact with the gate insulating film;
A first conductivity type field stop layer formed in the first conductivity type semiconductor substrate; a second conductivity type collector layer formed on a second main surface of the first conductivity type semiconductor substrate;
A first conductivity type leak stop layer provided between the first conductivity type field stop layer and the second conductivity type collector layer and formed so as to be in contact with at least the second conductivity type collector layer;
A first main electrode formed on the first conductivity type emitter layer and the second conductivity type base layer;
A second main electrode formed on the second conductivity type collector layer;
It is characterized by having.
[0013]
According to another aspect of the present invention, there is provided a semiconductor device comprising: a first conductivity type semiconductor substrate;
A second conductivity type base layer formed on a first main surface of the first conductivity type semiconductor substrate;
A first conductivity type emitter layer formed in a surface region of the second conductivity type base layer;
A gate insulating film formed to be in contact with the second conductivity type base layer;
A gate electrode formed to be in contact with the gate insulating film;
A first conductivity type field stop layer formed in the first conductivity type semiconductor substrate; a second conductivity type collector layer formed on a second main surface of the first conductivity type semiconductor substrate;
A first conductivity type leak stop layer provided between the first conductivity type field stop layer and the second conductivity type collector layer, and formed to be in contact with both layers;
A first main electrode formed on the first conductivity type emitter layer and the second conductivity type base layer;
A second main electrode formed on the second conductivity type collector layer;
It is characterized by having.
[0014]
In addition, a method of manufacturing a semiconductor device according to the present invention for achieving the above object includes a step of forming a second conductivity type base layer on a first main surface of a first conductivity type semiconductor substrate;
Forming a gate insulating film in contact with the second conductivity type base layer;
Forming a gate electrode in contact with the gate insulating film;
Forming an interlayer insulating film on the gate electrode;
Forming a first conductivity type emitter layer by introducing a first conductivity type impurity into a surface region of the second conductivity type base layer;
Forming a field stop layer in the first conductivity type semiconductor substrate by introducing a first conductivity type impurity into a second main surface of the first conductivity type semiconductor substrate; Forming a first conductivity type leak stop layer closer to the second main surface than the first conductivity type field stop layer by introducing a first conductivity type impurity into the second main surface of
Forming a second conductivity type collector layer in contact with the first conductivity type leak stop layer by introducing a second conductivity type impurity into a second main surface of the first conductivity type semiconductor substrate;
Forming a first main electrode on the first conductivity type emitter layer and the second conductivity type base layer;
Forming a second main electrode on the second conductivity type collector layer;
It is characterized by having.
[0015]
In addition, a method of manufacturing a semiconductor device according to the present invention for achieving the above object includes a step of forming a second conductivity type base layer on a first main surface of a first conductivity type semiconductor substrate;
Forming a gate insulating film in contact with the second conductivity type base layer;
Forming a gate electrode in contact with the gate insulating film;
Forming an interlayer insulating film on the gate electrode;
Forming a first conductivity type emitter layer by introducing a first conductivity type impurity into a surface region of the second conductivity type base layer;
By introducing an impurity of the first conductivity type into the second main surface of the first conductivity type semiconductor substrate, the first conductivity type leak stop layer and the first conductivity type semiconductor substrate are sequentially arranged in the first conductivity type semiconductor substrate from the second main surface side. Forming a first conductivity type field stop layer;
Forming a second conductivity type collector layer in contact with the first conductivity type leak stop layer by introducing a second conductivity type impurity into a second main surface of the first conductivity type semiconductor substrate;
Forming a first main electrode on the first conductivity type emitter layer and the second conductivity type base layer;
Forming a second main electrode on the second conductivity type collector layer;
It is characterized by having.
[0016]
According to the semiconductor device and the method of manufacturing the same of the present invention, the first conductivity type field stop layer for reducing the extension of the depletion layer in the reverse blocking state and the first conductivity type for reducing the increase in leakage current are provided on the second conductivity type collector layer side. By forming the conductive type leak stop layer, it is possible to prevent a negative resistance, a soft breakdown voltage, and an increase in leak current which occur at the time of turn-on.
[0017]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of a semiconductor device of the present invention will be described in detail with reference to the drawings.
(First Embodiment)
FIG. 1 is a sectional view of a main part of a trench IGBT according to the first embodiment of the present invention.
[0018]
As shown in FIG. 1, a P-type base layer 102 is formed on a first main surface of an N-type semiconductor substrate 101, and a groove 103 extending from the P-type base layer 102 to the N-type semiconductor substrate is formed. I have. A gate insulating film 104 is formed in the groove 103, and a gate electrode 105 is buried in contact with the gate insulating film 104. On the gate electrode 105, an interlayer insulating film 106 is formed. In the surface region of the P-type base layer 102, an N-type emitter layer 107 having a high impurity concentration is formed so as to be in contact with the side wall of the groove 103.
[0019]
An emitter electrode 108 is formed on the P-type base layer 102 and the N-type emitter layer 107 so as to contact the P-type base layer 102 and the N-type emitter layer 107. The gate electrode 105 is not in contact with the emitter electrode 108 because the interlayer insulating film 106 is formed thereon. Here, the interlayer insulating film 106 formed on the gate electrode 105 may be buried in the trench 103. By forming in this manner, it is not necessary to form a contact hole for contacting the P-type base layer 102 and the N-type emitter layer 107 when the emitter electrode 108 is formed. Even when the distance is short, the emitter electrode 108 can be easily formed.
[0020]
The N-type semiconductor substrate 101, the P-type base layer 102, the gate insulating film 104, the gate electrode 105, and the N-type emitter layer 107 form a MOSFET. That is, a channel is formed on the side wall of the groove 103 of the P-type base layer 102, and electrons are injected from the N-type emitter layer 107 into the N-type semiconductor substrate 101.
[0021]
On the other hand, an N-type field stop layer 109 and an N-type leak stop layer 110 are formed on the second main surface of the N-type semiconductor substrate 101. The N-type leak stop layer 110 is formed closer to the second main surface than the N-type field stop layer 109 is. On the second main surface side of the N-type semiconductor substrate 101, a P-type collector layer 111 and a collector electrode 112 are formed so as to be in contact with the N-type leak stop layer 110.
[0022]
The operation of the IGBT will be described. When a positive voltage is applied to the collector electrode 112 and a negative voltage is applied to the emitter electrode 108, when a positive voltage that is more positive than the emitter electrode 108 is applied to the gate electrode 105, The surface of the P-type base layer 102 in contact with the gate electrode 105 is inverted to N-type, and an inversion layer is formed. Electrons are injected from the N-type emitter layer 106 into the N-type semiconductor substrate 101 through the inversion layer and reach the P-type collector layer 111. As a result, the N-type semiconductor substrate 101 and the P-type collector layer 111 are forward-biased via the N-type leak stop layer 110 and the N-type field stop layer 109, and holes are released from the P-type collector layer 111 to the N-type semiconductor. It is injected into the substrate 101. As described above, both electrons and holes are injected into the N-type semiconductor substrate 101, and conductivity modulation occurs in the N-type semiconductor substrate 101, so that the ON voltage is reduced. That is, the element becomes conductive.
[0023]
On the other hand, to turn off, a negative voltage is applied to the gate electrode 105 with respect to the emitter electrode 108. Accordingly, the inversion layer formed on the P-type base layer 102 in contact with the gate electrode 105 disappears, and the electron injection stops. On the other hand, a part of the holes accumulated in the N-type semiconductor substrate 101 is discharged to the emitter electrode through the P-type base layer 102, and the remaining holes recombine with the electrons and disappear. The device turns off.
[0024]
When a positive voltage is applied to the collector electrode 112 and a ground potential is applied to the emitter electrode 108 and the gate electrode 105, a depletion layer is formed from the junction between the P-type base layer 102 and the N-type semiconductor substrate 101. Elongates, and the element enters the reverse blocking state.
[0025]
FIG. 2 shows an impurity concentration distribution of the P-type collector layer 111, the N-type leak stop layer 110, the N-type field stop layer 109, and the impurity concentration distribution on the second main surface side. FIG. The vertical axis represents the concentration, and the horizontal axis represents the depth (the direction of the arrow is on the first main surface side). The value obtained by integrating the density with respect to the depth is the dose amount. The N-type leak stop layer 110 and the N-type field stop layer 109 have respective peaks and are formed with independent distributions. Here, as shown in FIGS. 3 and 4, the N-type leak stop layer 110 and the N-type field stop layer 109 may be formed separately. The N-type semiconductor substrate 101 is formed at a lower concentration than the N-type leak stop layer 110 and the N-type field stop layer 109.
[0026]
A method for obtaining the dose of the N-type field stop layer 109 will be described below. The dose of the N-type field stop layer 109 is mainly determined by the concentration of the N-type semiconductor substrate 101 and the like. Here, the dose is an effective dose, and can be estimated from, for example, a spreading resistance (Spreading Resistance) measuring method or a Hall measuring method using the Hall effect. Also, from the experimental results, the effective dose obtained in the activation method using thermal annealing at a relatively low temperature (about 400 ° C. to 500 ° C.) is determined by secondary ion mass spectrometry (SIMS); Secondary Ion Mass Mass Spectroscopy). It has been found that the dose is about 30% of the dose obtained by the method.
[0027]
First, the thickness and concentration (resistivity) of the N-type semiconductor substrate 101 are selected. The required thickness (lower limit) generally requires a thickness of about 10 μm in order to secure a withstand voltage of about 100 V, and preferably a thickness of about 10% to 30%. It is. For example, in order to ensure a withstand voltage of 600 V, a thickness of about 60 μm is required, and preferably about 65 μm to 80 μm with a thickness of about 10% to 30%. Further, for a certain voltage, the total charge amount of the N-type layer required to neutralize the charge of the P-type base layer 102 is obtained, and when an N-type semiconductor substrate having a certain thickness is selected, The concentration (upper limit) limited by the critical electric field is determined. That is, the thickness and concentration (resistivity) of the N-type semiconductor substrate 101 are determined by the range of the lower limit of the thickness and the upper limit of the concentration, which are limited according to a desired breakdown voltage.
[0028]
Subsequently, when the thickness and the concentration of the N-type semiconductor substrate 101 are determined, the total charge amount of the N-type semiconductor substrate 101 is obtained. Since the charge obtained by subtracting the total charge of the N-type semiconductor substrate 101 from the total charge of the N-type layer necessary to maintain the breakdown voltage is the charge required for the field stop layer, this charge is dosed. By converting to the amount, the dose amount of the field stop layer can be obtained. Specifically, it can be obtained as follows.
[0029]
When a voltage V is applied, the charge amount q per unit length of the N-type layer_V[Cm^-1] Indicates the depletion layer width as W assuming a non-punch-through device._dl[Cm] and the concentration of the N-type semiconductor substrate is set to N [cm].^-3], Q_V= NW_dl ²Is represented by Depletion layer width W_dlIs calculated by considering the breakdown voltage V and the concentration N of the N-type semiconductor substrate, and can be expressed by the following equation (1).
W_dl= (2kεV / qN)^1/2(1)
(K: Boltzmann constant, ε: dielectric constant of silicon, V: voltage, q: elementary charge, N: concentration of N-type semiconductor substrate)
The N-type semiconductor substrate is an I layer. The I layer is a drift layer and is a region of the N-type semiconductor substrate between the N-type field stop layer and the N-type base layer. Here, an N-type semiconductor substrate on the N-type field stop layer is shown. Charge amount q per unit length of I layer_VI[Cm^-1] Indicates that the thickness of the I layer is W_I[Cm], q_VI= NW_I ²Is represented by Charge q per unit length required for field stop layer_FS[Cm^-1] Is q_V-Q_VIAnd q_FS= N (W_dl-W_I) (W_dl+ W_I). Therefore, the dose Q of the field stop layer_FSIs represented by the following equation (2).
Q_FS= Q_FS/ (W_dl+ W_I) = N (W_dl-W_I) (2)
(Q_FS: Charge amount per unit length of field stop layer, W_dl: Depletion layer width, W
_I: Thickness of I layer, N: concentration of N-type semiconductor substrate)
FIG. 5 shows the concentration N (horizontal axis) of the N-type semiconductor substrate 101 and the dose Q of the N-type field stop layer 109._FS(Ordinate) is shown. 4 is a graph theoretically calculated and obtained so as to satisfy a charge neutral condition required to neutralize the charge of the P-type base layer 102. Here, the thickness W of the N-type semiconductor substrate 101_IIs about 60 μm, and the withstand voltage V is about 600 V. The dose on the curve of the graph is the minimum dose required to maintain a desired breakdown voltage, and in a hatched region, when a reverse bias is applied, the N-type semiconductor substrate 101 and the The depletion layer extending from the junction with the P-type base layer 102 can be reduced by the N-type field stop layer 109.
[0030]
For example, the impurity concentration of the N-type semiconductor substrate 101 is 4 × 10^Thirteencm^-3(Specific resistance 100Ω · cm), the dose of the N-type field stop layer 109 is 4 × 10¹¹cm^-2With the above, the breakdown voltage can be maintained. Here, it is sufficient that the field stop layer has a function of blocking an electric field, and 1 × 10¹²cm^-2Below, preferably 6 × 10¹¹cm^-2The following dose is good. As described above, when the dose amount of the field stop layer is large, there arises a problem that a negative resistance is generated at the time of turn-on and it is difficult to turn on. The thickness of the N-type field stop layer 109 is not particularly limited.
[0031]
Next, how to determine the dose and the thickness of the N-type leak stop layer 110 will be described below. The dose and the thickness of the N-type leak stop layer 110 are mainly determined by the dose of the P-type collector layer and the like.
[0032]
The dose and the thickness of the N-type leak stop layer can be obtained by the following equation (3) by applying the theory of the current gain of the bipolar transistor to the IGBT as follows.
Q_LS/ Q_C= [481-480 cosh (W_LS/ 60)] / [2194 sinh (W_LS/ 60)] (3)
(Q_LS: Dose amount of the N-type leak stop layer 110, Q_C: Dose of the P-type collector layer 111, W_LS[Μm]: thickness of the N-type leak stop layer 110)
The parameters in equation (3) are values obtained from experiments and simulations. If the dose ratio between the N-type leak stop layer 110 and the P-type collector layer 111 is determined, the required thickness of the N-type leak stop layer 110 is determined. If the ratio of the dose of the N-type leak stop layer 110 to the dose of the P-type collector layer 111 is 1 or less, the problem of negative resistance does not occur. The P-type collector layer 111 can be formed as thin as about 0.1 μm to 2 μm. By adjusting the impurity concentration to secure a predetermined dose, the thickness can be reduced to 1 μm or less, and the size can be further reduced.
[0033]
FIG. 6 shows the dose Q of the N-type leak stop layer 110._LSAnd the dose Q of the P-type collector layer 111_C(Horizontal axis) and the thickness W of the N-type leak stop layer 110_LS(Ordinate) is shown. On the graph curve, when the dose ratio between the N-type leak stop layer 110 and the P-type collector layer 111 has a certain value, it is necessary to prevent an increase in leak current at a desired voltage (withstand voltage). The thickness of the N-type leak stop layer 110 is shown. In the shaded region, no increase in leakage current occurs. A dose ratio Q between the N-type leak stop layer 110 and the P-type collector layer 111_LS/ Q_CIt can be seen that the smaller the thickness of the N-type leak stop layer 110 becomes, the more the thickness becomes smaller.
[0034]
When the dose ratio between the N-type leak stop layer 110 and the P-type collector layer 111 is 0.01 ≦ Q_LS/ Q_CThe device of ≦ 0.2 has good performance in electrical characteristics such as switching, is excellent in practicality such as a manufacturing process, and is particularly effective.
When the minimum required thickness of the N-type leak stop layer 110 determined from the dose ratio is about 0.3 μm or more and 4 μm or less (0.01 ≦ Q_LS/ Q_C≦ 0.2), it is more preferable to form the layer with the minimum required thickness.
[0035]
For example, the dose of the P-type collector layer 111 is 1 × 10¹⁴cm^-2The N-type leak stop layer is 2 × 10^Thirteencm^-2Then, the dose ratio is 0.2. Therefore, if the thickness of the N-type leak stop layer 110 is about 0.3 μm, an increase in leak current can be prevented.
[0036]
As described above, the effective doses of the N-type field stop layer 109, the N-type leak stop layer 110, and the P-type collector layer 111 formed on the second main surface side of the N-type semiconductor substrate 101 are as follows. By determining the thickness, it is possible to prevent an increase in negative resistance and leak current generated at the time of turn-on.
[0037]
FIG. 7 shows a device simulation result. Assuming a withstand voltage of 600 V, the N-type semiconductor substrate has a thickness of 50 μm and an impurity concentration of 1 × 10^Thirteencm^-3It is. A curve A in the graph is a device having a structure of a P-type collector layer / leak stop layer / field stop layer / N-type semiconductor substrate from the second main surface side. The thickness of the P-type collector layer is 1 μm, and the effective dose is 1 × 10^Thirteencm^-2The thickness of the leak stop layer is 0.5 μm, and the effective dose is 1.05 × 10¹²cm^-2It is. The thickness of the field stop layer is 1 μm, and the effective dose is 2.31 × 10¹¹cm^-2It is. Curve B in the graph is a device having a structure of a P-type collector layer / field stop layer / N-type semiconductor substrate from the second main surface side, except that no leak stop layer is formed. This is the same structure as the device of the curve A. The thickness of the P-type collector layer is 1 μm, and the effective dose is 1 × 10^Thirteencm^-2Where the thickness of the field stop layer is 1 μm and the effective dose is 2.31 × 10¹¹cm^-2It is. Curve C in the graph is a device having a structure of a field stop layer / N-type semiconductor substrate from the second main surface side, except that no P-type collector layer is formed. It has the same structure as the device. The thickness of the field stop layer is 1 μm, and the effective dose is 2.31 × 10¹¹cm^-2It is.
[0038]
As shown in FIG. 7, it can be seen that the device indicated by curve A in the graph functions as a field stop layer and a leak stop layer, and can maintain a withstand voltage of 600 V. It can be seen that, in the device indicated by the curve B in the graph, since the leak stop layer is not formed, the leak current increases and the breakdown voltage cannot be maintained. Further, the device of the curve C in the graph has the same result as the device of the curve A in the graph, and it can be seen that the withstand voltage of 600 V can be maintained without punch-through.
In the device indicated by the curve C in the graph, the P-type collector layer is not formed, and it can be seen from the simulation result whether the extension of the depletion layer can be reduced by the field stop layer. Therefore, it can be seen that a device having good characteristics cannot be manufactured only with the field stop layer that reduces the elongation of the depletion layer, so that it is necessary to form two layers, the field stop layer and the leak stop layer.
[0039]
Hereinafter, an example of a method for manufacturing the semiconductor device described in this embodiment will be described. The withstand voltage is, for example, 600V.
[0040]
As shown in FIG. 8, a P-type base layer 802 is formed on a first main surface of an N-type semiconductor substrate 801 having a specific resistance of about 40 Ω · cm and a thickness of, for example, 600 μm. The concentration of the N-type semiconductor substrate 801 is about 1 × 10¹⁴cm^-3It is. Next, a groove 803 extending from the P-type base layer 802 to the N-type semiconductor substrate 801 is formed. A gate insulating film 804 is formed in the groove 803, and a gate electrode 805 is buried so as to be in contact with the gate insulating film 804. A patterned interlayer insulating film 806 is formed on the gate electrode 805, and a high impurity concentration N-type emitter layer 807 is selectively formed on the surface region of the P-type base layer 802 so as to be in contact with the side wall of the groove 803. Form. An emitter electrode 808 is formed on the P-type base layer 802 and the N-type emitter layer 807 so as to contact the P-type base layer 802 and the N-type emitter layer 807. The gate electrode 805 is not in contact with the emitter electrode 808 because the interlayer insulating film 806 is formed thereon.
[0041]
Next, as shown in FIG. 9, the N-type semiconductor substrate 801 is ground from the second main surface, which is the back surface of the first main surface, to a thickness of about 60 μm required to maintain a withstand voltage of 600 V. Grinding is performed with a grindstone or the like.
[0042]
Next, as shown in FIG. 10, N-type impurities such as phosphorus, arsenic, and antimony are ion-implanted from the second main surface of the N-type semiconductor substrate 801 at an acceleration energy of, for example, about 500 keV, and an effective dose amount is 5 × 10¹¹cm^-2An N-type field stop layer 809 is formed to a degree. The thickness of the N-type field stop layer 809 is, for example, 0.4 μm.
[0043]
Next, as shown in FIG. 11, N-type impurities such as phosphorus, arsenic, and antimony are ion-implanted at an acceleration energy of, for example, about 300 keV, and an effective dose amount is 1 × 10 4.¹²cm^-2An N-type leak stop layer 810 having a thickness of about 0.6 μm is formed. At this time, it is also possible to obtain the device structure and the impurity concentration distribution in FIGS. 3 and 4 by appropriately selecting conditions such as acceleration energy. For example, by increasing the acceleration energy at the time of ion implantation of the field stop layer 809, the field stop layer 809 can be formed deep in the N-type semiconductor substrate 801 and such a structure can be obtained. Here, the dose of the P-type collector layer 811 is 1 × 10^Thirteencm^-2And
[0044]
Next, as shown in FIG. 12, a P-type impurity such as boron or indium is ion-implanted with an acceleration energy of, for example, about 30 keV, and an effective dose amount is 1 × 10 4.^Thirteencm^-2A P-type collector layer 811 having a thickness of about 1 μm is formed. Subsequently, annealing is performed at 350 ° C. to 550 ° C. The P-type collector layer 811 and the leak stop layer 810 are formed in contact with each other. A collector electrode 812 is formed on the P-type collector layer 811.
[0045]
As described above, the field stop layer for reducing the extension of the depletion layer and the leak stop layer for reducing the increase in the leak current in the reverse blocking state are formed, and the effective dose of the field stop layer and the P-type collector layer, By determining the dose and the thickness of the mold leak stop layer, it is possible to prevent an increase in negative resistance and leak current generated at the time of turn-on.
[0046]
In the present embodiment, the vertical trench IGBT has been described as an example. However, the present invention is not limited to this, and similar effects can be obtained by applying the invention to a planar device or a horizontal device. Also, the conductivity types of the N type and the P type may be reversed.
(Second embodiment)
FIG. 13 is a cross-sectional view of a main part of a trench IGBT according to the second embodiment of the present invention. The difference from the first embodiment is that as shown in FIG. 14, the impurity concentration distributions of the field stop layer and the leak stop layer do not form independent distributions but form continuous distributions. is there.
[0047]
As shown in FIG. 13, a P-type base layer 1302 is formed on a first main surface of an N-type semiconductor substrate 1301, and a groove 1303 extending from the P-type base layer 1302 to the N-type semiconductor substrate is formed. I have. A gate insulating film 1304 is formed in the groove 1303, and a gate electrode 1305 is buried in contact with the gate insulating film 1304. On the gate electrode 1305, an interlayer insulating film 1306 is formed. In the surface region of the P-type base layer 1302, an N-type emitter layer 1307 having a high impurity concentration is formed so as to be in contact with the side wall of the groove 1303.
[0048]
An emitter electrode 1308 is formed on the P-type base layer 1302 and the N-type emitter layer 1307 so as to contact the P-type base layer 1302 and the N-type emitter layer 1307. The gate electrode 1305 is not in contact with the emitter electrode 1308 because the interlayer insulating film 1306 is formed thereon. Here, the interlayer insulating film 1306 formed on the gate electrode 1305 may be buried in the groove 1303. By forming in this manner, when forming the emitter electrode 1308, it is not necessary to form a contact hole for contacting the P-type base layer 3102 and the N-type emitter layer 1307, and the gap between the gate electrode 1305 is eliminated. Even when the distance is short, the emitter electrode 1308 can be easily formed.
[0049]
The N-type semiconductor substrate 1301, the P-type base layer 1302, the gate insulating film 1304, the gate electrode 1305, and the N-type emitter layer 1307 form a MOSFET. That is, a channel is formed on the sidewall of the groove 1303 of the P-type base layer 1302, and electrons are injected from the N-type emitter layer 1307 into the N-type semiconductor substrate 1301.
[0050]
On the other hand, an N-type field stop layer 1309 and an N-type leak stop layer 1310 are formed on the second main surface of the N-type semiconductor substrate 1301. The N-type leak stop layer 1310 is formed on the second main surface side of the N-type field stop layer 1309 so as to be in contact with and overlap the N-type leak stop layer 1309.
[0051]
On the second main surface side of the N-type semiconductor substrate 1301, a P-type collector layer 1311 and a collector electrode 1312 are formed so as to be in contact with the N-type leak stop layer 1310.
[0052]
FIG. 14 shows the impurity concentration distribution of the P-type collector layer 1311, the N-type leak stop layer 1310, the N-type field stop layer 1309, and the N-type semiconductor substrate 1301, which is the impurity concentration distribution on the second main surface side. FIG. The vertical axis represents the concentration, and the horizontal axis represents the depth (the direction of the arrow is on the first main surface side). The value obtained by integrating the density with respect to the depth is the dose amount. The N-type semiconductor substrate 1301 is formed at a lower concentration than the N-type leak stop layer 1310 and the N-type field stop layer 1309.
[0053]
Here, as shown in FIG. 14, the N-type leak stop layer 1310 and the N-type field stop layer 1309 are formed with a continuous impurity concentration distribution.
[0054]
Next, an example of a method for manufacturing the semiconductor device described in this embodiment will be described. The withstand voltage is, for example, 1000V.
[0055]
As shown in FIG. 15, a P-type base layer 1502 is formed on a first main surface of an N-type semiconductor substrate 1501 having a specific resistance of about 50 Ω · cm and a thickness of, for example, 500 μm. The concentration of the N-type semiconductor substrate 1501 is about 8 × 10^Thirteencm^-3It is.
[0056]
Next, a groove 1503 extending from the P-type base layer 1502 to the N-type semiconductor substrate 1501 is formed. A gate insulating film 1504 is formed in the groove 1503, and a gate electrode 1505 is buried so as to be in contact with the gate insulating film 1504. A patterned interlayer insulating film 1506 is formed on the gate electrode 1505, and a high impurity concentration N-type emitter layer 1507 is selectively formed on the surface region of the P-type base layer 1502 so as to be in contact with the side wall of the groove 1503. Form. An emitter electrode 1508 is formed on the P-type base layer 1502 and the N-type emitter layer 1507 so as to contact the P-type base layer 1502 and the N-type emitter layer 1507. The gate electrode 1505 is not in contact with the emitter electrode 1508 because the interlayer insulating film 1506 is formed thereon.
[0057]
Next, as shown in FIG. 16, the N-type semiconductor substrate 1501 is ground from the second main surface, which is the back surface of the first main surface, to a thickness of about 100 μm necessary to maintain a withstand voltage of 1000 V. Grinding is performed with a grindstone or the like.
[0058]
Next, as shown in FIG. 17, N-type impurities such as phosphorus, arsenic, and antimony are ion-implanted from the second main surface of the N-type semiconductor substrate 1501 at an acceleration energy of, for example, about 700 keV. The minimum effective dose required to reduce the depletion layer elongation, 5 × 10¹¹cm^-2An N-type field stop layer 1509 and an N-type leak stop layer 1510 are formed. The thickness of the N-type field stop layer 1509 is, for example, 0.5 μm. Under the N-type field stop layer 1509 having the minimum necessary dose, an effective dose is 8 × 10¹¹cm^-3An N-type leak stop layer 1510 having a thickness of at least about 0.7 μm is formed. By appropriately selecting conditions such as acceleration energy, the concentration profile of FIG. 16 can be obtained. Here, the dose of the P-type collector layer is 1 × 10^Thirteencm^-3And
[0059]
Next, as shown in FIG. 18, a P-type impurity such as boron or indium is ion-implanted at an acceleration energy of, for example, about 30 keV, and an effective dose amount is 1 × 10 4.^Thirteencm^-3A P-type collector layer 1511 having a thickness of about 1 μm is formed.
The P-type collector layer 1511 is formed in contact with the N-type leak stop layer. Subsequently, annealing is performed at 350 ° C. to 550 ° C. Forming a collector electrode 1512 on the P-type collector layer 1511;
Although the field stop layer and the leak stop layer are continuously distributed, in the present embodiment, a field stop layer having a minimum dose required to perform its function and a field stop layer formed thereunder are formed. It is assumed that there are two layers of leak stop layers. That is, a field stop layer having a necessary and sufficient concentration and a leak stop layer having at least a necessary and sufficient thickness. These can be obtained with reference to equations (1) to (3) (FIGS. 6 and 19).
[0060]
Thus, the effective dose of the N-type field stop layer and the P-type collector layer formed on the second main surface side of the N-type semiconductor substrate and the dose and thickness of the N-type leak stop layer are selected. Thus, by forming in the same process as in the related art, it is possible to prevent an increase in negative resistance and leak current generated at the time of turn-on.
[0061]
In the present embodiment, the vertical trench IGBT has been described as an example, but the present invention is not limited to this, and the same effect can be obtained even with a planar device or a horizontal device. Also, the conductivity types of the N type and the P type may be reversed.
[0062]
In the first and second embodiments, the case where the withstand voltage V is 600 V or 1000 V has been described as an example, but is not limited. However, it is particularly effective when applied to a device having a withstand voltage of 300 V or more. The concentration ratio between the N-type leak stop layer and the P-type collector layer (Q_LS/ Q_C) Has been described as an example of 0.08 or 0.1, but is not limited. However, 0.01 ≦ Q_LS/ Q_CA device of ≦ 0.2 has good performance in electrical characteristics such as switching, is excellent in practicality such as a manufacturing process, and is particularly effective.
[0063]
【The invention's effect】
As described above in detail, according to the present invention, on the second conductivity type collector layer side, the first conductivity type field stop layer for reducing the extension of the depletion layer in the reverse blocking state and the first conductivity type field stop layer for reducing the increase in the leak current are provided. By forming the one-conductivity-type leak stop layer, it is possible to prevent a negative resistance, a soft breakdown voltage, and an increase in leak current that occur at the time of turn-on.
[Brief description of the drawings]
FIG. 1 is a fragmentary cross-sectional view showing a semiconductor device according to a first embodiment of the present invention.
FIG. 2 is a diagram schematically showing an example of a second main surface side impurity concentration distribution of the semiconductor device according to the first embodiment of the present invention;
FIG. 3 is a fragmentary cross-sectional view showing another semiconductor device according to the first embodiment of the present invention.
FIG. 4 is a diagram schematically showing another example of the impurity concentration distribution on the second main surface side of the semiconductor device according to the first embodiment of the present invention.
FIG. 5 is a diagram showing NQ of the semiconductor device according to the first embodiment of the present invention;_FSFIG.
FIG. 6 is a graph showing Q of the semiconductor device according to the first embodiment of the present invention;_LS/ Q_C-W_LSFIG.
FIG. 7 is a diagram showing a device simulation result showing the effect of the leak stop layer.
FIG. 8 is a fragmentary cross-sectional view showing one step of a method for manufacturing a semiconductor device according to the first embodiment of the present invention.
FIG. 9 is a fragmentary cross-sectional view showing one step of a method for manufacturing the semiconductor device according to the first embodiment of the present invention.
FIG. 10 is a fragmentary cross-sectional view showing one step of a method for manufacturing the semiconductor device according to the first embodiment of the present invention.
FIG. 11 is a fragmentary cross-sectional view showing a step of the method for manufacturing the semiconductor device according to the first embodiment of the present invention.
FIG. 12 is an essential part cross sectional view showing one step of a method of manufacturing a semiconductor device according to the first embodiment of the present invention.
FIG. 13 is a fragmentary cross-sectional view showing a semiconductor device according to a second embodiment of the present invention.
FIG. 14 is a diagram schematically showing an example of a second main surface side impurity concentration distribution of the semiconductor device according to the second embodiment of the present invention;
FIG. 15 is a fragmentary cross-sectional view showing one step of a method for manufacturing a semiconductor device according to the second embodiment of the present invention.
FIG. 16 is a fragmentary cross-sectional view showing one step of a method for manufacturing a semiconductor device according to the second embodiment of the present invention.
FIG. 17 is a fragmentary cross-sectional view showing one step of a method for manufacturing a semiconductor device according to the second embodiment of the present invention.
FIG. 18 is a fragmentary cross-sectional view showing one step of a method for manufacturing a semiconductor device according to the second embodiment of the present invention.
FIG. 19 is a diagram showing NQ of a semiconductor device according to a second embodiment of the present invention;_FSFIG.
FIG. 20 is a cross-sectional view of a main part showing a conventional semiconductor device.
FIG. 21 is a diagram schematically showing an example of a second main surface side impurity concentration distribution of a conventional semiconductor device.
[Explanation of symbols]
101,801,1301,1501 ... N-type semiconductor substrate
102,802,1302,1502 ... P-type base layer
103, 803, 1303, 1503 ... groove
104, 804, 1304, 1504 ... gate insulating film
105,805,1305,1505 ... gate electrode
106,806,1306,1506 ... interlayer insulating film
107, 807, 1307, 1507 ... N-type emitter layer
108, 808, 1308, 1508 ... Emitter electrode
109, 809, 1309, 1509 ... N-type field stop layer
110, 810, 1310, 1510 ... N-type leak stop layer
111, 811, 1311, 1511... P-type collector layer
112, 812, 1312, 1512 ... Collector electrode
2001: N-type semiconductor substrate
2002: P-type base layer
2003 ... groove
2004: Gate insulating film
2005 ... Gate electrode
2006 ... interlayer insulating film
2007 ... N-type emitter layer
2008: Emitter electrode
2009 ... N-type field stop layer
2010: P-type collector layer
2011: Collector electrode

Claims (14)

A first conductivity type semiconductor substrate;
A second conductivity type base layer formed on a first main surface of the first conductivity type semiconductor substrate;
A first conductivity type emitter layer formed in a surface region of the second conductivity type base layer;
A gate insulating film formed to be in contact with the second conductivity type base layer;
A gate electrode formed to be in contact with the gate insulating film;
A first conductivity type field stop layer formed in the first conductivity type semiconductor substrate; a second conductivity type collector layer formed on a second main surface of the first conductivity type semiconductor substrate;
A first conductivity type leak stop layer provided between the first conductivity type field stop layer and the second conductivity type collector layer and formed so as to be in contact with at least the second conductivity type collector layer;
A first main electrode formed on the first conductivity type emitter layer and the second conductivity type base layer;
A second main electrode formed on the second conductivity type collector layer;
A semiconductor device comprising: In the first conductivity type field stop layer, 1 × 10 ¹² [cm ⁻² ] ≧ Q _FS ≧ N (W _dl −W _I )
(However, Q _FS [cm ⁻² ] is the effective dose of the field stop layer, N [cm ⁻³ ] is the impurity concentration of the first conductivity type semiconductor substrate, and W _dl [cm] is the first conductivity type semiconductor.) The depletion layer width of the substrate, W _I [cm], satisfies the thickness of the first conductivity type semiconductor substrate on the first conductivity type field stop layer),
In the first conductivity type leak stop layer,
1 ≧ Q _LS / Q _C ≧ [481-480 cosh (W _LS / 60)] / [2194 sinh (W _LS / 60)]
_(However, Q LS ^{[cm -2]} is an effective dose of the leakage stop _layer, Q C ^{[cm -2]} is an effective dose of the second conductivity type collector _{layer, W LS [μm]} is 2. The semiconductor device according to claim 1, wherein a thickness of the leak stop layer is satisfied. A first conductivity type semiconductor substrate;
A second conductivity type base layer formed on a first main surface of the first conductivity type semiconductor substrate;
A first conductivity type emitter layer formed in a surface region of the second conductivity type base layer;
A gate insulating film formed to be in contact with the second conductivity type base layer;
A gate electrode formed to be in contact with the gate insulating film;
A first conductivity type field stop layer formed in the first conductivity type semiconductor substrate; a second conductivity type collector layer formed on a second main surface of the first conductivity type semiconductor substrate;
A first conductivity type leak stop layer provided between the first conductivity type field stop layer and the second conductivity type collector layer, and formed to be in contact with both layers;
A first main electrode formed on the first conductivity type emitter layer and the second conductivity type base layer;
A second main electrode formed on the second conductivity type collector layer;
A semiconductor device comprising: In the first conductivity type field stop layer, 1 × 10 ¹² [cm ⁻² ] ≧ Q _FS ≧ N (W _dl −W _I )
(However, Q _FS [cm ⁻² ] is the effective dose of the field stop layer, N [cm ⁻³ ] is the impurity concentration of the first conductivity type semiconductor substrate, and W _dl [cm] is the first conductivity type semiconductor.) The depletion layer width of the substrate, W _I [cm], satisfies the thickness of the first conductivity type semiconductor substrate on the first conductivity type field stop layer),
In the first conductivity type leak stop layer,
1 ≧ Q _LS / Q _C ≧ [481-480 cosh (W _LS / 60)] / [2194 sinh (W _LS / 60)]
_(However, Q LS ^{[cm -2]} is an effective dose of the leakage stop _layer, Q C ^{[cm -2]} is an effective dose of the second conductivity type collector _{layer, W LS [μm]} is 4. The semiconductor device according to claim 3, wherein a thickness of the leak stop layer is satisfied. 5. The semiconductor device according to claim 1, wherein said second conductivity type collector layer has a thickness of 0.1 to 2 [mu] m. The gate electrode is characterized in that a gate insulating film is formed in a groove formed in the second conductivity type base layer, and a conductive material is embedded so as to be in contact with the gate insulating film. The semiconductor device according to claim 1, wherein: The semiconductor device according to claim 1, wherein the first conductivity type is N-type, and the second conductivity type is P-type. Forming a second conductivity type base layer on a first main surface of the first conductivity type semiconductor substrate;
Forming a gate insulating film in contact with the second conductivity type base layer;
Forming a gate electrode in contact with the gate insulating film;
Forming an interlayer insulating film on the gate electrode;
Forming a first conductivity type emitter layer by introducing a first conductivity type impurity into a surface region of the second conductivity type base layer;
Forming a field stop layer in the first conductivity type semiconductor substrate by introducing a first conductivity type impurity into a second main surface of the first conductivity type semiconductor substrate; Forming a first conductivity type leak stop layer closer to the second main surface than the first conductivity type field stop layer by introducing a first conductivity type impurity into the second main surface of
Forming a second conductivity type collector layer in contact with the first conductivity type leak stop layer by introducing a second conductivity type impurity into a second main surface of the first conductivity type semiconductor substrate;
Forming a first main electrode on the first conductivity type emitter layer and the second conductivity type base layer;
Forming a second main electrode on the second conductivity type collector layer;
A method for manufacturing a semiconductor device, comprising: In the step of forming the first conductivity type field stop layer, 1 × 10 ¹² [cm ⁻² ] ≧ Q _FS ≧ N (W _dl −W _I )
(However, Q _FS [cm ⁻² ] is the effective dose of the field stop layer, N [cm ⁻³ ] is the impurity concentration of the first conductivity type semiconductor substrate, and W _dl [cm] is the first conductivity type semiconductor.) The depletion layer width of the substrate, W _I [cm], is formed so as to satisfy the thickness of the first conductivity type semiconductor substrate on the first conductivity type field stop layer).
In the step of forming the first conductivity type leak stop layer,
1 ≧ Q _LS / Q _C ≧ [481-480 cosh (W _LS / 60)] / [2194 sinh (W _LS / 60)]
_(However, Q LS ^{[cm -2]} is an effective dose of the leakage stop _layer, Q C ^{[cm -2]} is an effective dose of the second conductivity type collector _{layer, W LS [μm]} is 9. The method for manufacturing a semiconductor device according to claim 8, wherein the semiconductor device is formed so as to satisfy a thickness of the leak stop layer. Forming a second conductivity type base layer by the first main surface of the first conductivity type semiconductor substrate;
Forming a gate insulating film in contact with the second conductivity type base layer;
Forming a gate electrode in contact with the gate insulating film;
Forming an interlayer insulating film on the gate electrode;
Forming a first conductivity type emitter layer by introducing a first conductivity type impurity into a surface region of the second conductivity type base layer;
By introducing an impurity of the first conductivity type into the second main surface of the first conductivity type semiconductor substrate, the first conductivity type leak stop layer and the first conductivity type semiconductor substrate are sequentially arranged in the first conductivity type semiconductor substrate from the second main surface side. Forming a first conductivity type field stop layer;
Forming a second conductivity type collector layer in contact with the first conductivity type leak stop layer by introducing a second conductivity type impurity into a second main surface of the first conductivity type semiconductor substrate;
Forming a first main electrode on the first conductivity type emitter layer and the second conductivity type base layer;
Forming a second main electrode on the second conductivity type collector layer;
A method for manufacturing a semiconductor device, comprising: In the step of forming the first conductivity type field stop layer, 1 × 10 ¹² [cm ⁻² ] ≧ Q _FS ≧ N (W _dl −W _I )
(However, Q _FS [cm ⁻² ] is the effective dose of the field stop layer, N [cm ⁻³ ] is the impurity concentration of the first conductivity type semiconductor substrate, and W _dl [cm] is the first conductivity type semiconductor.) The depletion layer width of the substrate, W _I [cm], is formed so as to satisfy the thickness of the first conductivity type semiconductor substrate on the first conductivity type field stop layer).
In the step of forming the first conductivity type leak stop layer,
1 ≧ Q _LS / Q _C ≧ [481-480 cosh (W _LS / 60)] / [2194 sinh (W _LS / 60)]
_(However, Q LS ^{[cm -2]} is an effective dose of the leakage stop _layer, Q C ^{[cm -2]} is an effective dose of the second conductivity type collector _{layer, W LS [μm]} is The semiconductor device according to claim 10, wherein the semiconductor device is formed so as to satisfy (thickness of a leak stop layer). 12. The method according to claim 8, wherein the second conductive type collector layer has a thickness of 0.1 to 2 [mu] m. The step of forming the gate electrode,
Forming a groove in the second conductivity type base layer;
Forming a gate insulating film in the trench;
12. The method of manufacturing a semiconductor device according to claim 8, further comprising: embedding a gate electrode in the groove so as to be in contact with the gate insulating film formed in the groove. The method according to claim 8, wherein the first conductivity type is N-type, and the second conductivity type is P-type.

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