JP5383874B2 - Integrated circuit device with three-dimensional laminated structure - Google Patents

Description

  The present invention relates to a method for manufacturing an integrated circuit device (three-dimensional stacked integrated circuit device) having a three-dimensional stacked structure formed by stacking a plurality of semiconductor circuit layers having various functions, and more specifically, the stacked semiconductors. The present invention relates to a method for manufacturing a three-dimensional stacked integrated circuit device, which includes an adhesive placement step for mechanical / electrical connection between circuit layers in the vertical direction (stacking direction) and a mechanical connection step for embedded wiring. Here, “buried interconnections” refer to wirings (conductors) for electrical connection in the stacking direction embedded in each of the semiconductor circuit layers.

  In recent years, semiconductor devices having a three-dimensional structure formed by stacking a plurality of semiconductor chips have been proposed. For example, Kurino et al. Proposed an “intelligent image sensor chip having a three-dimensional structure” in “1999 IDM Technical Digest” published in 1999 (see Non-Patent Document 1). ).

  This image sensor chip has a four-layer structure, a processor array and an output circuit are arranged in a first semiconductor circuit layer, a data latch and a masking circuit are arranged in a second semiconductor circuit layer, and a third semiconductor circuit An amplifier and an analog / digital converter are arranged in the layer, and an image sensor array is arranged in the fourth semiconductor circuit layer. The uppermost surface of the image sensor array is covered with a quartz glass layer including the microlens array, and the microlens array is formed on the surface of the quartz glass layer. Each image sensor in the image sensor array is formed with a photodiode as a semiconductor light receiving element. The semiconductor circuit layers constituting the four-layer structure are mechanically connected using an adhesive, and embedded wirings using conductive plugs and microbump electrodes brought into contact with the embedded wirings And are electrically connected.

  This image sensor chip does not use bonding wires for electrical connection between the semiconductor circuit layers. Accordingly, a three-dimensional structure in which a plurality of semiconductor chips are stacked and integrated on a support substrate and bonding wires are arranged around the semiconductor chips, and electrical connection between the semiconductor chips is realized by the bonding wires. It is different from a semiconductor device (this is conventionally known as disclosed in Patent Document 1).

  Also, Lee et al. In the “Journal of the Japan Society of Applied Physics” published in April 2000 titled “Development of three-dimensional integration technology for highly parallel image processing chips” proposed by Kurino et al. An image processing chip including an image sensor similar to the image sensor has been proposed (Non-Patent Document 2).

  Lee's image processing chip has almost the same structure as the solid-state image sensor proposed by Kurino et al.

  Both the conventional image sensor chip and the image processing chip having the above-described three-dimensional stacked structure are formed by laminating a plurality of semiconductor wafers (hereinafter also simply referred to as wafers) containing desired semiconductor circuits and fixing them together. Thereafter, the obtained wafer laminate is cut (diced) and divided into a plurality of chip groups. That is, a semiconductor wafer having a semiconductor circuit formed therein is laminated and integrated at a wafer level to form a three-dimensional laminated structure, which is divided to obtain an image sensor chip or an image processing chip.

  In these conventional image sensor chips and image processing chips, each of a plurality of stacked semiconductor circuits in the chip constitutes a “semiconductor circuit layer”.

Kurino et al., “Intelligent Image Sensor Chip with Three-Dimensional Structure”, 1999 IDM Technical Digest p. 36.4.1-36.4.4 (H. Kurino et al., "Intelligent Image Sensor Chip with Three Dimensional Structure", 1999 IEDM Technical Digest, pp. 36.4.1-36.4.4, 1999) Li et al., “Development of three-dimensional integration technology for highly parallel image processing chips”, “The Journal of Japan Society of Applied Physics”, Volume 39, p. 2473-2477, Part 1B, April 2000, (K. Lee et al., "Development of Three-Dimensional Integration Technology for Highly Parallel Image-Processing Chip", Jpn. J. Appl. Phys. Vol. 39 , pp. 2474-2477, April 2000)

Japanese Patent Laid-Open No. 2002-110902 (FIGS. 1 and 4)

  In the manufacturing process of the image sensor chip and the image processing chip having the conventional three-dimensional stacked structure described above, the semiconductor circuit layer (which is configured by stacking and integrating a plurality of semiconductor wafers) inside the wafer stack ( Here, the electrical connection in the vertical direction (stacking direction) between the semiconductor wafers is made by fine embedded wirings (or conductive plugs) formed through the semiconductor circuit layers in the stacking direction, and these embedded wirings. This is done using a micro-bump electrode fixed to the end. However, a specific method for forming the embedded wiring and the microbump electrode is not specified. The embedded wiring and the micro bump electrode are not only very fine and have a size of about several μm, but a large number of them are arranged close to each other, so that it is not easy to realize them. Therefore, there is a demand for a method for realizing a highly reliable electrical connection in the stacking direction using such embedded wiring and microbump electrodes.

  There is also a demand for a method of mechanically connecting semiconductor circuit layers (here, semiconductor wafers) constituting the wafer laminate with high reliability inside the wafer laminate. This can also be realized by the above-described electrical connection using microbump electrodes. However, in order to increase the strength and reliability of the mechanical connection, an electrically insulating adhesive is provided in the gap between adjacent semiconductor circuit layers. It is preferable to dispose an agent and bond the semiconductor circuit layers to each other with the adhesive. In this case, a method of injecting liquid or fluidized adhesive into the gap can be considered, but in that case, in order to completely fill the gap, it is necessary to inject the adhesive more than the volume of the gap. There is. As a result, there arises a problem that post-treatment is required to remove excess adhesive protruding from the gap after injection. In this post-processing, since a chemical is used to remove excess adhesive, troublesome work such as the need to prevent the influence of the chemical on each semiconductor circuit layer is increased. . Therefore, there is a demand for a method that can eliminate such difficulties and reduce the number of manufacturing steps.

  These two requests are made by stacking and integrating a plurality of semiconductor chips in place of the “wafer stack” in the manufacturing process of the image sensor chip and the image processing chip having the conventional three-dimensional stacked structure described above. This is also true when using a “chip stack”.

  The present invention has been made in consideration of these points, and the object of the present invention is to use embedded wiring for mechanical connection and electrical connection in the stacking direction between stacked semiconductor circuit layers. Another object of the present invention is to provide a method for manufacturing an integrated circuit device having a three-dimensional stacked structure, which can be realized easily and with high reliability.

  Another object of the present invention is to perform post-processing of ensuring that an electrically insulating adhesive can be disposed in the gap between the stacked semiconductor circuit layers and removing excess adhesive protruding from the gap. An object of the present invention is to provide a method of manufacturing an integrated circuit device having a three-dimensional stacked structure, which can be omitted.

  Other objects of the present invention which are not specified here will become apparent from the following description and the accompanying drawings.

(1) A method of manufacturing an integrated circuit device according to the present invention includes:
A method of manufacturing an integrated circuit device having a three-dimensional stacked structure in which a plurality of semiconductor circuit layers are stacked on a support substrate,
Forming a plurality of embedded wirings, one end of which is exposed from the back surface of the semiconductor circuit layer, inside one semiconductor circuit layer constituting the three-dimensional stacked structure;
Forming a plurality of bump electrodes on the back surface of the semiconductor circuit layer, or on the surface of another semiconductor circuit layer constituting the three-dimensional stacked structure, or both of them;
An electrically insulating adhesive film having a shape that does not overlap the exposed end of the embedded wiring or the bump electrode on the back surface of the semiconductor circuit layer, the surface of the other semiconductor circuit layer, or both of them. Forming, and
Making the back surface of the semiconductor circuit layer and the surface of the other semiconductor circuit layer face each other while interposing the adhesive film therebetween,
By narrowing the distance between the back surface of the semiconductor circuit layer and the surface of the other semiconductor circuit layer opposed to each other, the adhesive film is placed between the back surface of the semiconductor circuit layer and the surface of the other semiconductor circuit layer. A step of deforming at least one of the exposed end of the embedded wiring and the bump electrode while being deformed in a gap remaining therebetween, and mechanically connecting to each other directly or via another conductive member; Prepared,
The adhesive film is filled in the entire gap at the end of the mechanical connection step between the exposed end of the embedded wiring and the bump electrode.

  (2) In the method of manufacturing an integrated circuit device according to the present invention, as described above, a plurality of buried portions in which one end is exposed from the back surface of the semiconductor circuit layer inside one semiconductor circuit layer constituting the three-dimensional stacked structure. While forming the embedded wiring, a plurality of bump electrodes are formed on the back surface of the semiconductor circuit layer, the surface of the other semiconductor circuit layer constituting the three-dimensional stacked structure, or both of them. Thereafter, an electrically insulating adhesive having a shape that does not overlap the exposed end of the embedded wiring or the bump electrode on the back surface of the semiconductor circuit layer, the surface of the other semiconductor circuit layer, or both of them. A film is formed. Further, after the back surface of the semiconductor circuit layer and the surface of the other semiconductor circuit layer are opposed to each other with the adhesive film interposed therebetween, the back surface of the semiconductor circuit layer and the other semiconductor circuit layer The distance between the surfaces is narrowed, so that at least one of the exposed end and the bump electrode of the embedded wiring is deformed and mechanically connected to each other directly or via another conductive member. At this time, the adhesive film is deformed in a gap remaining between the back surface of the semiconductor circuit layer and the surface of the other semiconductor circuit layer, and the exposed end of the embedded wiring and the bump electrode The entire gap is filled at the end of the mechanical connection process.

  Therefore, the entire volume of the adhesive film remains in the gap between the semiconductor circuit layer and the other semiconductor circuit layer at the end of the mechanical connection process between the exposed end of the embedded wiring and the bump electrode. By adjusting the total volume of the adhesive film so as to be substantially equal to the volume of the gap, it becomes possible to arrange a necessary amount of adhesive in the gap, and the adhesive does not protrude from the gap. Can be. Therefore, it is possible to reliably dispose the electrically insulating adhesive in the gap between the laminated semiconductor circuit layers constituting the three-dimensional laminated structure, and to remove the excess adhesive protruding from the gap The effect that can be omitted is obtained.

  Further, the mechanical connection between the exposed end of the embedded wiring and the bump electrode may be performed directly or through another conductive member by deforming at least one of the exposed end of the embedded wiring and the bump electrode. Therefore, the mechanical connection between the exposed end of the embedded wiring and the bump electrode is strengthened. In addition, since the adhesive film fills the gaps by deformation, the bonding between the semiconductor circuit layer and the other semiconductor circuit layer is ensured. As described above, high reliability can be obtained in mechanical connection and electrical connection between the semiconductor circuit layer and the other semiconductor circuit layer by a combination of the easy processes as described above. In other words, the mechanical connection and electrical connection in the stacking direction between the stacked semiconductor circuit layers constituting the three-dimensional stacked structure can be realized easily and with high reliability using the embedded wiring. An effect is obtained.

  (3) In the method for manufacturing an integrated circuit device of the present invention, the “support substrate” may be any material as long as it has sufficient rigidity to support a plurality of semiconductor circuit layers, and the material thereof is arbitrary. It may be a semiconductor, glass, or other material. A semiconductor substrate having a circuit formed therein, that is, a so-called LSI wafer may be used.

  The “semiconductor circuit layer” and the “other semiconductor circuit layer” mean a semiconductor circuit layer, in other words, a semiconductor circuit formed in a layer shape. Therefore, the “semiconductor circuit layer” may include a “semiconductor substrate” and “elements” or “circuits” formed inside or on the surface of the semiconductor substrate, and other configurations are arbitrary.

  Usually, some “circuit” (for example, an amplifier circuit, a signal processing circuit, or an integrated circuit providing a predetermined function) is formed inside or on the surface of the “semiconductor substrate”. Only an “element” (for example, a light receiving element) may be formed. For example, only a large number of “light receiving elements” arranged in an array may be formed inside or on the surface of the “semiconductor substrate”. “Elements” include active elements such as transistors and passive elements such as resistors. As the “active element”, a MOS field effect transistor (Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET, hereinafter referred to as “MOS transistor”) is typically used in consideration of a small occupied area and the like. However, a transistor other than a MOS transistor, a diode, or the like may be used. As the “passive element”, for example, a resistor, a capacitive element or the like is used.

  The “semiconductor substrate” may be formed of a single semiconductor member (for example, a semiconductor wafer or a semiconductor chip), or may be formed of a plurality of semiconductor members (for example, a semiconductor wafer or a semiconductor chip). The physical dimensions of the “semiconductor substrate” are not limited, and may be the size of a semiconductor wafer (wafer size), the size of a chip obtained by dividing a semiconductor wafer (chip size), or the wafer size. It may be an intermediate size of the chip size or a size larger than the wafer size. The material of the “semiconductor substrate” is arbitrary, and may be silicon, a compound semiconductor, or other semiconductors as long as a desired semiconductor element or circuit can be formed. The structure of the “semiconductor substrate” is also arbitrary, and may be a simple plate made of a semiconductor or a so-called SOI (Silicon On Insulator) substrate.

  “Built-in wiring” refers to a wiring or conductor for electrical connection in the stacking direction embedded in each semiconductor circuit layer. The “embedded wiring” is usually an “insulating film” that covers the entire inner wall surface of the “trench” formed in the semiconductor substrate, and a “conductive material” that is filled (embedded) in the space inside the insulating film. "(Often referred to as" conductive plug "). However, it is not necessarily limited to this configuration.

  Here, the “trench” may have any desired depth as long as it has a desired depth and accommodates a conductive material that becomes an embedded wiring. The depth, opening shape, opening size, cross-sectional shape, etc. of the “trench” can be arbitrarily set as required. As a method for forming the “trench”, any method can be used as long as it can be formed by selectively removing the semiconductor substrate from the surface side. For example, an anisotropic etching method using a mask can be suitably used.

As the “insulating film” covering the inner wall surface of the “trench”, any insulating film can be used as long as it can electrically insulate the semiconductor substrate and the “conductive material” filled in the “trench”. . For example, silicon dioxide (SiO ₂ ), silicon nitride (SiN _x ), or the like can be suitably used. A method of forming the “insulating film” is arbitrary.

  The “conductive material” filled in the “trench” may be any material that can be used for electrical connection between the semiconductor circuit layers, and any material can be used. For example, a semiconductor such as polysilicon or a metal such as tungsten (W), copper (Cu), or aluminum (Al) can be preferably used. As the filling method of the “conductive material”, any method can be used as long as the “conductive material” can be filled into the “trench” from one side of the semiconductor substrate.

  The “bump electrode” may have any configuration as long as it is a bump-like electrode that can be used for electrical connection in the stacking direction between semiconductor circuit layers. As the material of the “bump electrode”, any material can be used as long as it has conductivity that can be used for electrical connection in the stacking direction between the semiconductor circuit layers.

  At least one of the exposed end of the “embedded wiring” and the “bump electrode” is formed by allowing the two semiconductor circuit layers to face each other while interposing the adhesive film therebetween, and then reducing the distance between the two. It is necessary that at least one of the exposed end of the embedded wiring and the bump electrode is deformed and mechanically connected to each other directly or via another bump electrode. By deforming the “bump electrode” in this way, the contact area with the mating member (embedded wiring, other bump electrode, etc.) is expanded, and as a result, the reliability of the mechanical and electrical connection between the two is improved. “Deformation” of at least one of the exposed end of the embedded wiring and the bump electrode may be plastic deformation, or may be deformation due to softening or fluidization of at least a part thereof.

  The material of the “bump electrode” is a material in which the “bump electrode” and the embedded wiring are brought into contact with each other while being heated and pressed (for example, a laminate of indium (In) and gold (Au), In / Au), the two may be brought into direct contact and mechanically connected. However, if the material of the bump electrode is not bonded to each other even if the bump electrode and the embedded wiring are brought into contact with each other while being heated and pressed (for example, tungsten (W)), an appropriate bonding metal is sandwiched between them. It is necessary to make a mechanical connection between them. As the bonding metal, for example, an In—Au alloy, a tin (Sn) -gold (Ag) alloy, an In simple substance, an Sn simple substance, or the like can be used. In this case, the joining metal becomes “another conductive member”.

  Since the configuration and formation method of the “bump electrode” are arbitrary, a separately formed bump-shaped conductive material piece is attached to the back surface of the semiconductor circuit layer, the surface of the other semiconductor circuit layer, or both of them. It may be formed by being fixed at a predetermined position, or formed by directly depositing a conductive material on the back surface of the semiconductor circuit layer, the surface of the other semiconductor circuit layer, or a predetermined position on both of them by a plating method or the like. May be. Moreover, you may form using the wiring formed in the back surface of the said semiconductor circuit layer, or the surface of the said other semiconductor circuit layer.

  As the “other conductive member”, any member can be used as long as it can be used for electrical connection between the semiconductor circuit layers. Typically, a bump electrode similar to the “bump electrode” described above is used, but is not limited thereto. The “joining metal” described above can also be used as “other conductive member”.

  The “electrically insulating adhesive film” is an electrically insulating adhesive film capable of bonding and integrating the semiconductor circuit layer and the other semiconductor circuit layer. It remains viscous even after patterning into a shape that does not overlap the exposed end of the wiring or the bump electrode, and at least part of the wiring is softened or fluidized under a predetermined condition. For example, polyimide resin, SOG (Spin On Glass) material, etc. can be used. Among these adhesives, polyimide resin is particularly preferable. This is because the polyimide resin is easy to handle and has high chemical stability.

  “By narrowing the distance between the back surface of the semiconductor circuit layer and the surface of the other semiconductor circuit layer opposed to each other, the adhesive film is formed between the back surface of the semiconductor circuit layer and the surface of the other semiconductor circuit layer. A process of deforming at least one of the exposed end of the embedded wiring and the bump electrode while being deformed in a gap remaining between the two, and mechanically connecting to each other directly or via another conductive member. The method of implementing is not particularly limited. Typically, the exposed end portion of the embedded wiring and the corresponding bump electrode are mechanically connected directly or through another conductive member by “welding” or “pressure welding”. The method may be used. In the case where “welding” or “pressure welding” cannot be performed directly, mechanical connection may be performed with an appropriate bonding metal interposed therebetween.

  This step can be performed using, for example, a known semiconductor wafer laminating apparatus (for example, see “three-dimensional LSI laminating apparatus” described in Japanese Patent Laid-Open No. 5-160340 (Japanese Patent No. 2984441)). Similar devices are also disclosed in the following articles:

Matsumoto et al., “New 3D Wafer Bonding Technology Using Adhesive Injection Method”, 1998, Journal of Applied Physics, 1 (3B), p. 1217-1221 (Takuji Matsumoto, Masakazu Satoh, Katsuyuki Sakuma, Hiroyuki Kurino, Nobuaki Miyakawa, Hikotaro Itani and Mitsumasa Koyanagi, "New three-dimensional wafer bonding technology using the adhesive injection method," Jpn. J. Appl. Phys., 1 (3B), pp.1217-1221, 1998)
“At least one of the exposed end of the embedded wiring and the bump electrode is deformed while the adhesive film is deformed in a gap remaining between the back surface of the semiconductor circuit layer and the surface of the other semiconductor circuit layer. It is preferable to heat the embedded wiring and the bump electrode to a predetermined temperature in order to be deformed and mechanically connected to each other directly or via another conductive member. The reason is that at least one of the exposed end of the embedded wiring and the bump electrode is partially melted and deformed by heating, or at least the exposed end of the embedded wiring and the bump electrode This is because one side is softened and can be deformed under pressure, so that a desired mechanical connection can be easily realized. Similarly, since at least a part of the adhesive film is softened or fluidized by heating, the adhesive film can be deformed by reducing the distance between the back surface of the semiconductor circuit layer and the surface of the other semiconductor circuit layer. This is because the entire gap can be filled.

  “The adhesive film filled in the entire gap at the end of the mechanical connection step between the exposed end of the embedded wiring and the bump electrode” is performed during or after the mechanical connection step. In the curing step to be performed, curing is performed by an appropriate method. As a method for curing the adhesive film, in view of ease of implementation, heating to a predetermined temperature (and subsequent heat radiation cooling) is preferable, but is not limited thereto. For example, if ultraviolet rays can be transmitted, they can be cured by ultraviolet irradiation or the like, or can be cured by adding an appropriate drug.

  (4) In a preferred example of the method for manufacturing an integrated circuit device according to the present invention, the adhesive film has a configuration in which the adhesive film is divided into a plurality of island-shaped adhesive elements. In this case, the gap between the back surface of the semiconductor circuit layer and the surface of the other semiconductor circuit layer is narrowed by the gas remaining between the back surface of the semiconductor circuit layer and the surface of the other semiconductor circuit layer. Even after being applied, there is an advantage that it is easy to escape outside through the island-like adhesive elements.

  In another preferred example of the method for manufacturing an integrated circuit device of the present invention, the exposed end of the embedded wiring or a region overlapping the bump electrode, and mechanical connection between the exposed end of the embedded wiring and the bump electrode Except for the region for absorbing deformation caused by deformation of at least one of the exposed end of the embedded wiring, the bump electrode, and the other conductive member at the end of the process, the adhesive film , Having a structure formed continuously without being divided into a plurality of adhesive elements. In this case, there is an advantage that patterning of the adhesive film is easier than the case where the adhesive film is divided into a plurality of island-shaped adhesive elements.

  In this example, when the gap between the back surface of the semiconductor circuit layer and the surface of the other semiconductor circuit layer that are opposed to each other is reduced, the adhesive film forms the back surface of the semiconductor circuit layer and the other semiconductor circuit. It is preferable to have a gap (such as a slit) that allows gas existing in the gap between the layers to escape to the outside. This is because the gas is more efficiently eliminated through the gap.

  In still another preferable example of the method for manufacturing an integrated circuit device of the present invention, another electrically insulating adhesive film patterned in a shape that does not overlap with the embedded wiring or the bump electrode is formed on the other circuit. A step of forming on the surface of the semiconductor circuit layer, and when the exposed end of the embedded wiring and the bump electrode are mechanically connected, the adhesive film and the other adhesive film are Bonded to each other. In this example, since two adhesive films are used, even when the gap between the back surface of the semiconductor circuit layer and the surface of the other semiconductor circuit layer is relatively large, the adhesive is surely applied to the entire gap. There is an advantage that can be filled.

  In this example, various combinations are possible. For example, (a) both the adhesive film formed on the back surface of the semiconductor circuit layer and the other adhesive film formed on the surface of the other semiconductor circuit layer have a plurality of island-shaped bonds. It has a structure divided into agent elements. Alternatively, (b) the exposure of the embedded wiring at the end of the mechanical connection step between the exposed end of the embedded wiring or the bump electrode and the exposed end of the embedded wiring and the bump electrode. The adhesive film formed on the back surface of the semiconductor circuit layer, except for an end, a region for absorbing deformation caused by deformation of at least one of the bump electrode and the other conductive member, Both the other adhesive film formed on the surface of the other semiconductor circuit layer have a configuration formed continuously without being divided into a plurality of adhesive elements. Or (c) any one of the adhesive film formed on the back surface of the semiconductor circuit layer and the other adhesive film formed on the surface of the other semiconductor circuit layer has a plurality of island shapes A mechanical connection step between the exposed end of the embedded wiring or the bump electrode and the exposed end of the embedded wiring and the bump electrode. At the end of the plurality of adhesive elements, except for an area for absorbing deformation caused by deformation of at least one of the exposed end of the embedded wiring, the bump electrode, and the other conductive member. It has a structure formed continuously without being divided.

  In still another preferred example of the method of manufacturing an integrated circuit device according to the present invention, the bump electrode is bonded directly to each of the exposed ends of the plurality of embedded wirings. In this case, there is an advantage that the number of steps is reduced because a step of forming a conductive member such as a bump electrode on the side of the embedded wiring becomes unnecessary.

  In this example, it is preferable that the exposed end of the embedded wiring protrudes from the back surface of the semiconductor circuit layer. In this case, not only is a step of forming a conductive member such as a bump electrode on the side of the embedded wiring unnecessary, but there is an advantage that mechanical connection between the embedded wiring and the bump electrode is easier. is there.

  According to still another preferred example of the method for manufacturing an integrated circuit device of the present invention, the method includes a step of forming another bump electrode as the other conductive member at each of the exposed ends of the plurality of embedded wirings. The exposed end of the embedded wiring and the bump electrode are mechanically connected to each other through the other bump electrode. In this case, although the step of forming the other bump electrode is required, the height (thickness) of the bump electrode can be reduced by the amount of the other bump electrode. There is an advantage that formation becomes easy.

  In still another preferred example of the method for manufacturing an integrated circuit device according to the present invention, a mechanical connection step between the exposed end of the embedded wiring and the bump electrode is performed under heating, and the adhesive film is formed at that time. The heating temperature is set so that at least a part of the material is softened or fluidized. In this example, there exists an advantage that the said mechanical connection process can be performed easily.

  In still another preferred example of the method of manufacturing an integrated circuit device according to the present invention, a mechanical connection step between the exposed end of the embedded wiring and the bump electrode is performed under heating, and at that time, the embedded wiring The heating temperature is set so that at least one of the exposed end and the bump electrode is plastically deformed and mechanically connected to each other directly or via the other conductive member. In this example, there exists an advantage that the said mechanical connection process can be performed easily.

  In still another preferred example of the method of manufacturing an integrated circuit device according to the present invention, a mechanical connection step between the exposed end of the embedded wiring and the bump electrode is performed under heating, and at that time, the embedded wiring A heating temperature is set such that at least a part of the exposed end of the bump and the bump electrode are deformed by being softened or fluidized and mechanically connected to each other directly or via the other conductive member. . In this example, there exists an advantage that the said mechanical connection process can be performed easily.

  In still another preferred example of the method of manufacturing an integrated circuit device according to the present invention, the back surface of the semiconductor circuit layer and the other semiconductor circuit layer are mechanically connected in the mechanical connection step between the exposed end of the embedded wiring and the bump electrode. When the gap between the surface and the surface of the adhesive film is reduced, before the exposed end of the embedded wiring and the bump electrode come into contact directly or via the other conductive member, That is, the protruding height of the embedded wiring, the height of the bump electrode, and the adhesive so as to contact the back surface of the semiconductor circuit layer, the surface of the other semiconductor circuit layer, or the surface of another adhesive film) The thickness of the film is set. In this case, since the adhesive film contacts the opposite surface before the exposed end of the embedded wiring and the bump electrode are directly or indirectly contacted, the deformation amount of the adhesive film is large. Become. Therefore, in this example, the amount of deformation of the adhesive film must be increased due to the layout of the embedded wiring and the bump electrode (for example, using a material that is difficult to deform as the material of the bump electrode). In such a case).

  In still another preferred example of the method of manufacturing an integrated circuit device according to the present invention, the back surface of the semiconductor circuit layer and the other semiconductor circuit layer are mechanically connected in the mechanical connection step between the exposed end of the embedded wiring and the bump electrode. Before the adhesive film comes into contact with the opposing surface (that is, the back surface of the semiconductor circuit layer, the surface of the other semiconductor circuit layer, or the surface of another adhesive film) when the distance from the front surface is narrowed Further, the protruding height of the embedded wiring, the height of the bump electrode, and the adhesive so that the exposed end of the embedded wiring and the bump electrode are in direct contact with each other or through the other conductive member. The thickness of the film is set. In this case, since the exposed end of the embedded wiring and the bump electrode come into direct or indirect contact before the adhesive film contacts the opposite surface, the exposed end of the embedded wiring and The deformation amount of at least one of the bump electrodes is increased. Therefore, in this example, when the deformation amount of the adhesive film cannot be increased due to the layout of the embedded wiring and the bump electrode (for example, when the deformation amount of the adhesive film is increased, the adhesive film faces the opposite direction). In the case of entering the gap between the two bump electrodes or the case where a material that is difficult to deform is used as the material of the adhesive film).

  In still another preferred example of the method of manufacturing an integrated circuit device according to the present invention, the back surface of the semiconductor circuit layer and the other semiconductor circuit layer are mechanically connected in the mechanical connection step between the exposed end of the embedded wiring and the bump electrode. When the distance from the surface is narrowed, the adhesive film faces the exposed end of the embedded wiring and the bump electrode directly or almost simultaneously with the other conductive member. The protruding height of the embedded wiring, the height of the bump electrode, and the adhesion so as to come into contact with the surface (that is, the back surface of the semiconductor circuit layer, the surface of the other semiconductor circuit layer, or the surface of another adhesive film) The thickness of the agent film is set. In this case, since the exposed end of the embedded wiring and the bump electrode are in direct or indirect contact with each other and the adhesive film is in contact with the opposing surface, this example is The amount of deformation of the adhesive film cannot be increased due to the layout of the embedded wiring and the bump electrode, and the amount of deformation of at least one of the exposed end of the embedded wiring and the bump electrode cannot be increased ( For example, it can be suitably used for a case where a material that hardly deforms is used for both the bump electrode and the adhesive film.

  (5) The method for manufacturing an integrated circuit device of the present invention described above can be applied to any integrated circuit device having a three-dimensional stacked structure, and the size thereof is not limited. The three-dimensional stacked integrated circuit device may be a wafer size (in this case, each of the semiconductor circuit layers constituting the three-dimensional stacked structure is a wafer size) or a chip size (in this case, each of the semiconductor circuit layers). May be an intermediate size between the wafer size and the chip size (in this case, each of the semiconductor circuit layers constituting the three-dimensional stacked structure is an intermediate size between the wafer size and the chip size). Or a size larger than the wafer size (in this case, each of the semiconductor circuit layers constituting the three-dimensional stacked structure is larger than the wafer size). Here, “wafer size” means substantially the same size as a semiconductor wafer (for example, 8 inches in diameter). In the present invention, since the number of stacked semiconductor circuit layers is arbitrary, the height of the three-dimensional stacked integrated circuit device is also arbitrary.

  Each of the semiconductor circuit layers may be formed of one semiconductor wafer or a plurality of semiconductor wafers arranged two-dimensionally, or one semiconductor chip (or a semiconductor member) or a plurality of two-dimensionally arranged semiconductor wafers. You may form from the semiconductor chip (or semiconductor member).

  In the method of manufacturing an integrated circuit device according to the present invention, (i) an electrically insulating adhesive can be reliably disposed in a gap between stacked semiconductor circuit layers, and an excess adhesive protruding from the gap is removed. The post-processing of removing can be omitted. (Ii) The mechanical connection and the electrical connection in the stacking direction between the stacked semiconductor circuit layers are easily and highly reliable using the embedded wiring. The effect that it can be obtained.

It is a fragmentary sectional view which shows the manufacturing method of the integrated circuit device which has a three-dimensional laminated structure which concerns on 1st Embodiment of this invention for every process. FIG. 3 is a partial cross-sectional view illustrating the method for manufacturing the integrated circuit device having the three-dimensional stacked structure according to the first embodiment of the present invention for each process, and is a continuation of FIG. 1. FIG. 3 is a partial cross-sectional view illustrating the method for manufacturing the integrated circuit device having the three-dimensional stacked structure according to the first embodiment of the present invention for each process, and is a continuation of FIG. 2. FIG. 4 is a partial cross-sectional view illustrating the method for manufacturing the integrated circuit device having the three-dimensional stacked structure according to the first embodiment of the present invention for each step, and is a continuation of FIG. 3. FIG. 5 is a partial cross-sectional view illustrating the method for manufacturing the integrated circuit device having the three-dimensional stacked structure according to the first embodiment of the present invention for each process, and is a continuation of FIG. 4. FIG. 6 is a partial cross-sectional view illustrating the method for manufacturing the integrated circuit device having the three-dimensional stacked structure according to the first embodiment of the present invention for each step, and is a continuation of FIG. 5. FIG. 7 is a partial cross-sectional view illustrating the method for manufacturing the integrated circuit device having the three-dimensional stacked structure according to the first embodiment of the present invention for each process, and is a continuation of FIG. 6. FIG. 9 is a partial cross-sectional view showing the method for manufacturing the integrated circuit device having the three-dimensional stacked structure according to the first embodiment of the present invention for each step, and is a continuation of FIG. 7. (A), (b) is the elements on larger scale which each show the detail of the process of FIG. 5 of the manufacturing method of the integrated circuit device with the three-dimensional laminated structure which concerns on 1st Embodiment of this invention, and the process of FIG. is there. FIG. 8 is a partial enlarged cross-sectional view showing details of the step of FIG. 7L of the method for manufacturing the integrated circuit device having a three-dimensional laminated structure according to the first embodiment of the present invention. FIG. 7 is a partial cross-sectional view showing a method for manufacturing an integrated circuit device having a three-dimensional laminated structure according to a second embodiment of the present invention for each step, and corresponds to FIG. 5. FIG. 12 is a partial cross-sectional view illustrating a method for manufacturing an integrated circuit device having a three-dimensional stacked structure according to a second embodiment of the present invention for each step, which is a continuation of FIG. 11 and corresponds to FIG. 6. FIG. 13 is a partial cross-sectional view illustrating a method of manufacturing an integrated circuit device having a three-dimensional stacked structure according to a second embodiment of the present invention for each step, which is a continuation of FIG. 12 and corresponds to FIG. (A), (b) is a partial expanded sectional view which shows the detail of the process of FIG. 11 and FIG. 12 of the manufacturing method of the integrated circuit device which has a three-dimensional laminated structure which concerns on 2nd Embodiment of this invention, respectively. FIG. 14 is a partial enlarged cross-sectional view showing details of the step of FIG. 13 in the method of manufacturing an integrated circuit device having a three-dimensional laminated structure according to the second embodiment of the present invention. FIG. 5 is a partial cross-sectional view showing a method for manufacturing an integrated circuit device having a three-dimensional stacked structure according to a third embodiment of the present invention for each step, and corresponds to FIG. 5. FIG. 17 is a partial cross-sectional view illustrating a method of manufacturing an integrated circuit device having a three-dimensional stacked structure according to a third embodiment of the present invention for each process, and is a continuation of FIG. 16 and corresponds to FIG. FIG. 18 is a partial cross-sectional view illustrating the method for manufacturing the integrated circuit device having a three-dimensional stacked structure according to the third embodiment of the present invention for each process, and is a continuation of FIG. 17 and corresponds to FIG. (A), (b) is a partial expanded sectional view which respectively shows the detail of the process of FIG. 16 and FIG. 17 of the manufacturing method of the integrated circuit device which has a three-dimensional laminated structure concerning 3rd Embodiment of this invention. FIG. 19 is a partial enlarged cross-sectional view illustrating details of the process of FIG. 18 of the method for manufacturing the integrated circuit device having a three-dimensional stacked structure according to the third embodiment of the present invention. FIG. 9 is a partial cross-sectional view showing a method of manufacturing an integrated circuit device having a three-dimensional laminated structure according to a fourth embodiment of the present invention for each step, corresponding to FIG. 5. FIG. 22 is a partial cross-sectional view illustrating a method for manufacturing an integrated circuit device having a three-dimensional stacked structure according to a fourth embodiment of the present invention for each step, which is a continuation of FIG. 21 and corresponds to FIG. 6. FIG. 24 is a partial cross-sectional view illustrating the method for manufacturing the integrated circuit device having a three-dimensional stacked structure according to the fourth embodiment of the present invention for each step, which is a continuation of FIG. 22 and corresponds to FIG. 7; (A), (b) is a partial expanded sectional view which shows the detail of the process of FIG. 21 and FIG. 22 of the manufacturing method of the integrated circuit device which has a three-dimensional laminated structure concerning 4th Embodiment of this invention, respectively. FIG. 24 is a partial enlarged cross-sectional view showing details of the step of FIG. 23 in the method for manufacturing an integrated circuit device having a three-dimensional stacked structure according to the fourth embodiment of the present invention. FIGS. 3A and 4B are partial cross-sectional views showing a method for manufacturing an integrated circuit device having a three-dimensional stacked structure according to the fifth embodiment of the present invention for each step, and FIGS. ) Respectively. FIG. 27 is a partial cross-sectional view illustrating the method for manufacturing the integrated circuit device having a three-dimensional stacked structure according to the fifth embodiment of the present invention for each process, and is a continuation of FIG. 26 and corresponds to FIG. 5. FIG. 28 is a partial cross-sectional view illustrating a method for manufacturing an integrated circuit device having a three-dimensional stacked structure according to a fifth embodiment of the present invention for each step, which is a continuation of FIG. 27 and corresponds to FIG. 6. FIG. 29 is a partial cross-sectional view showing the method of manufacturing the integrated circuit device having a three-dimensional stacked structure according to the fifth embodiment of the present invention for each process, and is a continuation of FIG. 28 and corresponds to FIG. (A), (b) is a partial expanded sectional view which shows the detail of the process of FIG. 27 and FIG. 28 of the manufacturing method of the integrated circuit device which has a three-dimensional laminated structure concerning 5th Embodiment of this invention, respectively. FIG. 30 is a partial enlarged cross-sectional view showing details of the step of FIG. 29 in the method of manufacturing the integrated circuit device having a three-dimensional stacked structure according to the fifth embodiment of the present invention. (A) is a schematic top view which shows the relationship between the position and magnitude | size of an upper and lower micro bump electrode used with the manufacturing method of the integrated circuit device which has the three-dimensional laminated structure which concerns on 1st Embodiment of this invention, (b) ) Is a conceptual diagram showing an example of a layout of a micro-bump electrode group and an adhesive element group disposed on the surface of the multilayer wiring structure of the second semiconductor circuit layer in the manufacturing method. It is a partial expanded sectional view which shows the manufacturing method of the integrated circuit device which has a three-dimensional laminated structure concerning 6th Embodiment of this invention. It is a partial expanded sectional view which shows the manufacturing method of the integrated circuit device which has a three-dimensional laminated structure concerning 7th Embodiment of this invention. It is a partial expanded sectional view which shows the manufacturing method of the integrated circuit device which has a three-dimensional laminated structure concerning 8th Embodiment of this invention. It is a partial expanded sectional view which shows the manufacturing method of the integrated circuit device which has a three-dimensional laminated structure concerning 9th Embodiment of this invention. It is a partial expanded sectional view which shows the manufacturing method of the integrated circuit device which has a three-dimensional laminated structure concerning 10th Embodiment of this invention. It is a partial expanded sectional view which shows the manufacturing method of the integrated circuit device which has a three-dimensional laminated structure concerning 11th Embodiment of this invention. It is a partial expanded sectional view which shows the manufacturing method of the integrated circuit device which has a three-dimensional laminated structure concerning 12th Embodiment of this invention. It is a partial expanded sectional view which shows the manufacturing method of the integrated circuit device which has a three-dimensional laminated structure concerning 13th Embodiment of this invention. It is a partial expanded sectional view which shows the manufacturing method of the integrated circuit device which has a three-dimensional laminated structure concerning 14th Embodiment of this invention. It is a partial expanded sectional view which shows the manufacturing method of the integrated circuit device which has a three-dimensional laminated structure concerning 15th Embodiment of this invention. It is a partial expanded sectional view which shows the manufacturing method of the integrated circuit device which has a three-dimensional laminated structure concerning 16th Embodiment of this invention. It is a partial expanded sectional view which shows the manufacturing method of the integrated circuit device which has a three-dimensional laminated structure concerning 17th Embodiment of this invention. It is a partial expanded sectional view which shows the manufacturing method of the integrated circuit device which has a three-dimensional laminated structure concerning 18th Embodiment of this invention. It is a partial expanded sectional view which shows the manufacturing method of the integrated circuit device which has a three-dimensional laminated structure concerning 19th Embodiment of this invention. It is a partial expanded sectional view which shows the manufacturing method of the integrated circuit device which has a three-dimensional laminated structure concerning 20th Embodiment of this invention. It is a partial expanded sectional view which shows the manufacturing method of the integrated circuit device which has a three-dimensional laminated structure concerning 21st Embodiment of this invention. It is the elements on larger scale which show the layout of the electrode used by the manufacturing method of the integrated circuit device which has a three-dimensional laminated structure concerning 22nd Embodiment of this invention, and the pattern of an adhesive film. It is a partial enlarged plan view which shows the layout of the electrode used by the manufacturing method of the integrated circuit device which has a three-dimensional laminated structure concerning 23rd Embodiment of this invention, and the pattern of an adhesive film. It is a partial enlarged plan view which shows the layout of the electrode used by the manufacturing method of the integrated circuit device which has a three-dimensional laminated structure concerning 24th Embodiment of this invention, and the pattern of an adhesive film. It is a partial enlarged plan view which shows the layout of the electrode used by the manufacturing method of the integrated circuit device which has a three-dimensional laminated structure concerning 25th Embodiment of this invention, and the pattern of an adhesive film.

  DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, preferred embodiments of the invention will be described in detail with reference to the accompanying drawings.

(First embodiment)
FIG. 1A to FIG. 8M are partial cross-sectional views showing, for each step, a method for manufacturing an integrated circuit device having a three-dimensional stacked structure according to the first embodiment of the present invention. FIGS. 9A and 9B are partial enlarged sectional views showing details of the process of FIG. 5, and FIGS. 10C and 10D are parts showing details of the processes of FIGS. It is an expanded sectional view. The first embodiment is an example of manufacturing an integrated circuit device having a three-dimensional stacked structure by stacking semiconductor wafers.

First, as shown in FIG. 1A, a wafer (Si wafer) 11 made of single crystal silicon (Si) is prepared as a semiconductor substrate. Next, a silicon dioxide (SiO ₂ ) film 12 (thickness of about 10 nm) is formed on the surface (first main surface) of the wafer (semiconductor substrate) 11, and the entire surface is covered with the SiO ₂ film 12. Subsequently, on the SiO ₂ film 12, a silicon nitride _(Si 3 _{N 4)} film 12a (a thickness of about 50 nm), it covers the entire surface of the SiO ₂ film 12 with _{the Si} 3 _{N 4} film 12a. Further, a photoresist film 17 patterned so as to obtain a desired trench 13 is formed on the Si ₃ N ₄ film 12a.

Thereafter, using the photoresist film 17 as a mask, the underlying Si ₃ N ₄ film 12a is selectively removed, and an opening is formed at a location where the trench 13 is to be formed. Subsequently, using the Si ₃ N ₄ film 12a thus formed with the opening as a mask, the underlying SiO ₂ film 12 and the Si substrate (wafer) 11 are selectively removed sequentially. Here, a known anisotropic etching method (dry etching method) is used. In this way, a plurality of trenches 13 having a desired depth are formed from a surface side at a predetermined position inside the substrate (wafer) 11. The trenches 13 are respectively arranged at positions where embedded wiring (here, conductor plugs) for electrical connection in the stacking direction of the Si substrate (wafer) 11 is to be formed. The state at this time is as shown in FIG.

After the etching is completed, the photoresist film 17 used as a mask is removed. The photoresist film 17 used as a mask may be removed after the etching of the Si ₃ N ₄ film 12a and before the SiO ₂ film 12 is etched.

Thereafter, with the Si ₃ N ₄ film 12a left on the surface of the Si substrate (wafer) 11, the SiO ₂ film 14 (thickness of about 500 nm) is selected on the exposed surface (inner wall surface) of these trenches 13 by thermal oxidation. Form. The SiO ₂ film 14 covers the entire inner wall surface of the trench 13 and is connected to and integrated with the SiO ₂ film 12 covering the surface of the substrate 11. The state at this time is as shown in FIG. After the thermal oxidation, the Si ₃ N ₄ film 12a is removed by a known method.

Next, an appropriate conductive material is selectively embedded from the surface side of the substrate 11 into each trench 13 whose exposed surface is covered with the SiO ₂ film 14 by a known method to form the conductive plug 15. . For example, after a conductive material film is deposited over the entire surface of the Si substrate (wafer) 11 by a CVD (Chemical Vapor Deposition) method, the conductivity is obtained by an etch back method or a CMP (Chemical Mechanical Polishing) method. By selectively removing the portion of the material film on the SiO ₂ film 12 and leaving the portion inside the trench 13, the conductive plug 15 is obtained inside each trench 13. Examples of the conductive material used here include semiconductors such as polysilicon and metals such as tungsten (W), copper (Cu), and aluminum (Al), but are not limited thereto.

Then, a necessary number of MOS transistors are formed by a known method at a position where the trench 13 on the surface of the substrate 11 is not formed, in other words, at a position not overlapping with the trench 13 on the surface of the substrate 11. Accordingly, elements other than MOS transistors (not shown) are also formed to obtain a desired circuit. Each MOS transistor includes a pair of source / drain regions 16 formed in the substrate 11 at intervals, a gate insulating film 12b formed between the source / drain regions 16, and a gate insulating film 12b. And the gate electrode 18 formed on the substrate. The gate insulating film 12 b is formed of a SiO ₂ film formed in a separate process from the SiO ₂ film 12. That is, it is formed by selectively removing the SiO ₂ film 12 at a place where the gate insulating film 12b is to be formed, and then forming a SiO ₂ film again at the same place. The state at this time is as shown in FIG.

  Next, as shown in FIG. 2D, an interlayer insulating film 19 is formed on the entire surface of the Si substrate (wafer) 11 on the insulating film 12, and the interlayer insulating film 19 forms the MOS transistor and the surface exposed from them. Cover the whole. As the interlayer insulating film 19, a known organic or inorganic insulating film is arbitrarily used. Then, the interlayer insulating film 19 is selectively etched to form through holes reaching the desired source / drain regions 16 and the conductive plugs 15 in the respective trenches 13. Next, the conductive material 21 is filled into the through holes corresponding to the source / drain regions 16 of the insulating film 19 by a known method. Thereafter, a conductive metal film (not shown) is formed on the insulating film 19 and then the metal film is selectively etched to obtain the metal wiring film 20. The metal wiring film 20 is in contact with each conductive plug 15 through a corresponding through-hole in the interlayer insulating film 19, whereby the metal wiring film 20 and the conductive plug 15 are electrically connected. The metal wiring film 20 is also electrically connected to the source / drain region 16 via a conductive material 21 filled in the corresponding through hole of the interlayer insulating film 19.

  Subsequently, a multilayer wiring structure 30 is formed on the metal wiring film 20 by a known method. The multilayer wiring structure 30 includes an insulating material 31, three wiring layers 32, 33, and 34 embedded in the insulating material 31, and a conductor 35 that is mainly used for interlayer connection between the wiring layers 32, 33, and 34. , 36. Since the configuration / materials used and the formation method of the multilayer wiring structure 30 are known, a detailed description thereof will be omitted. In the present invention, it is needless to say that the wiring structure is not limited to such a multilayer wiring structure 30 and may be a single-layer wiring structure having only one wiring layer.

  Then, a plurality of micro bump electrodes (small bump electrodes) 37 are formed on the surface (flattened) of the multilayer wiring structure 30 (that is, the insulating material 31) by a known method. The state at this time is as shown in FIG. These micro bump electrodes 37 are electrically connected to the corresponding conductive plugs 15 in the trench 13 via the wiring layers 32, 33 or 34 and the conductors 35 or 36 in the multilayer wiring structure 30, respectively. Connected. In this way, the micro bump electrodes 37 on the surface of the multilayer wiring structure 30 and the conductive plugs 15 below the multilayer wiring structure 30 are electrically interconnected, and through this, the vertical direction (stacking direction) of the Si substrate 11 Can be electrically interconnected. On the other hand, the MOS transistor (that is, the circuit) formed on the Si substrate 11 is electrically connected to the multilayer wiring structure 30 and the conductive plug 15 via the metal wiring film 20 as necessary. It is also possible to input and output electric signals to the MOS transistor (circuit) via the electrode 37 and the conductive plug 15.

  The micro bump electrode 37 is formed by any known method. A piece of conductive material formed separately may be fixed to the surface of the multilayer wiring structure 30 or may be formed by directly depositing a conductive material on the surface of the multilayer wiring structure 30 by a plating method or the like. Good. Further, the micro bump electrode 37 may be formed using the conductor 36 of the multilayer wiring structure 30 or the like.

  The Si substrate (Si wafer) 11 having the MOS transistor (circuit) and the multilayer wiring structure 30 formed on the substrate 11 constitute the first semiconductor circuit layer 1.

  Subsequently, the first semiconductor circuit layer 1 is fixed to an appropriate support substrate 40 using the micro bump electrodes 37 formed on the surface of the multilayer wiring structure 30. In other words, the first semiconductor circuit layer 1 and the support substrate 40 are mechanically connected using the micro bump electrode 37. As the support substrate 40, for example, a glass, a single crystal Si wafer or the like can be suitably used, but here, a Si wafer (LSI wafer incorporating a semiconductor circuit) is used. The first semiconductor circuit layer 1 is mechanically and electrically connected to the semiconductor circuit (not shown) formed in the support substrate 40 made of Si wafer by the microbump electrode 37. The Si wafer may be a simple wafer that does not contain a semiconductor circuit.

  In this state, there is a gap corresponding to the thickness of the microbump electrode 37 between the multilayer wiring structure 30 and the support substrate 40. Therefore, the gap 39 is filled with an electrically insulating adhesive 39 and cured. As the adhesive 39, polyimide resin, epoxy resin, or the like can be suitably used. Thus, the first semiconductor circuit layer 1 is electrically and mechanically connected to the support substrate 40 by the adhesive 39 and the microbump electrode 37.

  When the support substrate 40 is formed of glass or formed of a semiconductor wafer that does not incorporate a semiconductor circuit, the microbump electrode 37 is located between the first semiconductor circuit layer 1 and the support substrate 40. It will be used only for mechanical connection. However, in this case, the micro bump electrode 37 may be omitted, and the first semiconductor circuit layer 1 may be directly bonded to the support substrate 40 with an adhesive, which is more efficient. Further, the adhesive 39 is formed as a patterned film on the surface of the multilayer wiring structure 30 or the opposite surface of the support substrate 40 in the same manner as a patterned adhesive film 44a described later. The multilayer wiring structure 30 and the support substrate 40 may be electrically and mechanically interconnected using the electrode 37.

  Thereafter, while holding the first semiconductor circuit layer 1 using the support substrate 40, the back surface (second main surface of the first semiconductor circuit layer 1) side of the Si substrate 11 is placed inside each of the inside by mechanical polishing and CMP. Polishing is performed until the distance from the lower end of the trench 13 is about 1 μm, for example, to reduce the thickness of the entire substrate 11. The first semiconductor circuit layer 1 thus polished and thinned is denoted by 1a hereinafter. The state at this time is as shown in FIG.

Next, the back surface side of the thinned first semiconductor circuit layer 1a (that is, the Si substrate 11) is selectively removed by isotropic etching such as wet etching or plasma etching, as shown in FIG. Thus, the SiO ₂ film 14 covering the inner wall surface of the trench 13 is exposed on the back surface side of the first semiconductor circuit layer 1a. The etching amount at this time is adjusted so that the lower end of the conductive plug 15 protrudes from the back surface of the substrate 11 by a predetermined distance at the end of etching.

Subsequently, as shown in FIG. 3G, a SiO ₂ film 41 is formed on the back surface of the substrate 11 and the exposed SiO ₂ film 14 by a known method such as a CVD method. The thickness of the SiO ₂ film 41 is about 0.2 μm, for example. The SiO ₂ film 41 by polishing by CMP thus formed, together with the SiO ₂ film 41 an end portion of the rear surface side of the SiO ₂ film 14 and conductive plug 15 is selectively removed, in FIG. 4 (h) As shown, the lower end of the conductive plug 15 inside the trench 13 is exposed. The remaining SiO ₂ film 41 covers a portion other than the conductive plug 15 on the back surface of the semiconductor substrate 11, and the entire back surface of the substrate 11 is flat, in other words, the back surface of the first semiconductor circuit layer 1a. The whole is flat.

  Thereafter, as shown in FIG. 4I, a micro bump electrode 42 is formed on each exposed lower end of each conductive plug 15 by a known method. These electrodes 42 are formed, for example, by forming a conductive film (not shown) on the entire back surface of the substrate 11 (first semiconductor circuit layer 1a) in the state shown in FIG. It can be formed by selective removal by etching, or can be formed using a lift-off method or a plating method. When using the lift-off method, first, a resist film (not shown) having through holes is formed on the entire back surface of the substrate 1a in the state shown in FIG. Then, after forming a conductive layer (not shown) on the resist film, the resist film is peeled off. Then, only the portion of the conductive film that is in contact with the back surface of the semiconductor circuit layer 1a through the through hole of the resist film selectively remains and becomes the electrode 42. Each electrode 42 is fixed to the lower end of the corresponding conductive plug 15 as shown in FIG. The plating method can be formed in the same manner as the lift-off method.

  The height of the micro bump electrode 42 with respect to the back surface of the substrate 11 is Hc as shown in FIG. The height Hc of the electrode 42 is, for example, 1 μm.

  Next, the second semiconductor circuit layer 2 is fixed to the back surface of the first semiconductor circuit layer 1a as follows. Here, for simplicity of explanation, the second semiconductor circuit layer 2 has substantially the same configuration as the first semiconductor circuit layer 1 and is manufactured by the same method as the first semiconductor circuit layer 1. It is assumed that the corresponding elements are denoted by the same reference numerals as those of the first semiconductor circuit layer 1 and description thereof is omitted. Needless to say, the second semiconductor circuit layer 2 may be configured differently from the first semiconductor circuit layer 1 as necessary.

  On the planarized surface (the first main surface of the second semiconductor circuit layer 2) of the multilayer wiring structure 30 (that is, the insulating material 31) of the second semiconductor circuit layer 2, FIG. 5 (j) and FIG. 9 (a). As shown in FIG. 4, a plurality of micro bump electrodes 43a are formed. These electrodes 43a are formed by the same method as the micro bump electrodes 42 of the first semiconductor circuit layer 1a. Here, four electrodes 43a correspond to each of the electrodes 42 provided on the back surface of the first semiconductor circuit layer 1a (Si wafer 11). In other words, four electrodes 43a (each positioned at each vertex of a rectangle) are joined to one electrode 42. Details will be described later with reference to FIG.

  As shown in FIG. 9A, the height of the electrode 43a with respect to the surface of the multilayer wiring structure 30 is Hb, and is set to 2 μm, for example.

  Further, when the electrodes 42 and 43a are brought into pressure contact with each other, only the electrode 43a is selectively crushed (plastic deformation), so that the electrode 43a is made of a conductive material whose hardness is sufficiently lower than that of the electrode 42. Yes. For example, when the electrode 42 is formed of tungsten (W), the electrode 43a is preferably formed of a laminate (In / Au) of indium (In) and gold (Au). Moreover, when the electrode 42 is formed of copper (Cu), the electrode 43a is preferably formed of a laminate (Sn / Ag) of tin (Sn) and silver (Ag).

  Next, as shown in FIGS. 5 (j) and 9 (a), a patterned electrically insulating adhesive is adhered to the surface of the multilayer wiring structure 30 (that is, the insulating material 31) of the second semiconductor circuit layer 2. An agent film 44a is formed. The adhesive film 44a is formed by patterning an electrically insulating adhesive such as polyimide resin or SOG (Spin On Glass) material at room temperature, and is patterned (cured) into a predetermined shape. The surface (exposed surface) can be softened or fluidized by heating to a predetermined temperature (in other words, heat softening property or It has heat fluidity).

  The adhesive film 44a includes a plurality of portions (hereinafter referred to as “adhesive elements”) 44aa formed in a bump shape (island shape), and these portions (adhesive elements). 44aa is regularly distributed on the surface of the multilayer wiring structure 30. The adhesive film 44a has a shape that does not overlap any of the electrodes 43a, and is disposed except for the portion where the electrode 43a is formed and the vicinity thereof. Therefore, the adhesive film 44a (that is, all the adhesive elements 44aa) does not overlap with the electrode 42 (conductive plug 15) of the first semiconductor circuit layer 1a.

  As shown in FIG. 9A, the height Ha of the adhesive element 44aa on the basis of the surface of the multilayer wiring structure 30 is, for example, 4 μm.

  The total volume of the adhesive film 44a (more precisely, the total volume after curing) is a mechanical and electrical connection between the second semiconductor circuit layer 2 and the first semiconductor circuit layer 1a using the electrodes 42 and 43a. In this case, the entire gap formed between the two circuit layers 1a and 2 is filled with the adhesive film 44a, and the value is set so that the excess adhesive film 44a does not protrude from the gap. This is to avoid the operation of removing the excess adhesive film 44a protruding from the gap after the circuit layers 1a and 2 are connected.

  Since the adhesive film 44a does not exist in the vicinity of the electrode 42 and 43a and there is a gap between the island-shaped adhesive elements 44aa, as shown in FIG. The height Ha of each adhesive element 44aa (which is equal to the thickness of the adhesive film 44a) is set larger than the height Hb of the electrode 43a (Ha> Hb), and each adhesive element The height Ha of 44aa is set to be larger than the sum of the height Hc of the electrode 42 and the height Hb of the electrode 43a (Ha> (Hb + Hc)). This is because, when the second semiconductor circuit layer 2 and the first semiconductor circuit layer 1a are connected, each adhesive element 44aa is crushed by pressurization and spreads around the electrodes 42 and 43a, so that the circuit layer 1a This is to fill the entire gap remaining between 2 and 2.

  As will be described later, when the second semiconductor circuit layer 2 and the first semiconductor circuit layer 1a are connected, the respective electrodes 43a are also crushed and plastically deformed and spread around them. As a result, the four electrodes 43a corresponding to each electrode 42 are mutually connected and integrated.

  The adhesive film 44a is divided into a large number of adhesive elements 44aa because the air existing between the circuit layers 2 and 1a when the second semiconductor circuit layer 2 and the first semiconductor circuit layer 1a are connected to each other. This is to make it easier to escape to the outside (that is, to facilitate degassing). That is, even when the circuit layers 2 and 1a are almost connected, the gas (air) remaining between the layers 2 and 1a is pushed out through the gap between the adjacent adhesive elements 44aa. Because.

  The adhesive film 44a is formed by the following method, for example. After an electrically insulating adhesive film is formed and cured on the entire surface of the second semiconductor circuit layer 2 by a coating method or the like, a patterned resist film is formed thereon by a known method. Then, the adhesive film is selectively removed by a known lithography method. Thus, a patterned adhesive film 44a having a thickness Ha is obtained. As another method, there is a method of selectively removing the adhesive film by a known lithography method using a photosensitive adhesive.

  Here, the adhesive film 44a is formed after the microbump electrode 43a is formed, but the microbump electrode 43a may be formed after the adhesive film 44a is formed.

  Subsequently, as shown in FIGS. 5J and 9A, the surface of the second semiconductor circuit layer 2 is opposed to the back surface of the first semiconductor circuit layer 1a fixed via the support substrate 40 from below. Let (Conversely, the second semiconductor circuit layer 2 may be fixed and the first semiconductor circuit layer 1a fixed to the support substrate 40 may be opposed from above.) Thereafter, the second semiconductor circuit layer 2 is pushed between the circuit layers 2 and 1a. When pressure is applied to bring the circuit layers 2 and 1a close to each other, the height of each adhesive element 44aa (that is, the thickness of the adhesive film 44a) Ha is larger than the height Hb of the electrode 43a (Ha> Hb), and the height Ha of each adhesive element 44aa is larger than the sum of the height Hc of the electrode 42 and the height Hb of the electrode 43a (Ha> (Hb + Hc)). ), The tip (top) of the adhesive film 44a (adhesive element 44aa) of the second semiconductor circuit layer 2 is brought into contact with the back surface of the first semiconductor circuit layer 1a.

  After that, by applying a pressing force between the circuit layers 2 and 1a to reduce the distance between the two, as shown in FIGS. 6 (k) and 10 (c), each electrode 43a of the second semiconductor circuit layer 2 is obtained. Is brought into contact with the electrode 42 of the corresponding first semiconductor circuit layer 1a. When the distance between the back surface of the first semiconductor circuit layer 1a and the surface of the second semiconductor circuit layer 2 at this time, that is, the interlayer gap is G1, the interlayer gap G1 is equal to the sum of the thickness of the electrode 42 and the thickness of the electrode 43a. That is, G1 = Hc + Hb. At this time, the adhesive film 44a is crushed and deformed, and is spread over almost the entire gap between the circuit layers 1 and 2, but the adhesive film 44a is divided into island-shaped adhesive elements 44aa. Therefore, the adhesive film 44a spreads almost uniformly in the gap. Further, since a gap 45 is easily formed between the deformed adhesive film 44a and the back surface of the first semiconductor circuit layer 1a (and between the adjacent adhesive elements 44aa), it remains in the gap. The air to be discharged can be surely discharged to the outside through the gap 45, and the risk of bubbles being generated in the finally cured adhesive film 44a can be eliminated.

  The step of bringing the electrodes 42 and 43a into contact with each other after the first semiconductor circuit layer 1a and the second semiconductor circuit layer 2 are opposed to each other is performed at room temperature. The value of the distance G1 between the first semiconductor circuit layer 1a and the second semiconductor circuit layer 2 is appropriately determined within a range of 2 μm to 10 μm, for example, but is typically 4 μm. However, the heights Hc and Hb of the electrodes 42 and 43a can be further reduced to 2 μm or less. In this case, the value of the distance G1 is appropriately determined within a range of 0.1 μm to 2 μm, for example.

  Thereafter, the electrodes 43a and 42 brought into contact with each other are connected to each other as follows.

  That is, the second semiconductor circuit layer 2 and the first semiconductor circuit layer 1a in the states of FIGS. 6K and 10C are heated from room temperature to a predetermined temperature. The temperature is set to a temperature at which the surface (exposed surface) of the adhesive film 44a in a pressure-deformed state is slightly softened or the surface is slightly fluidized. The temperature varies depending on the type of adhesive used for the adhesive film 44a, but is arbitrarily set within a range of 100 to 400 ° C., for example, in consideration of the temperature at which the electrode 42 and the electrode 43a are “press-contacted”. . At this time, depending on the heating temperature to be set, at least one of the electrode 42 and the electrode 43a may be partially melted and the surface thereof may be curved.

  Subsequently, by applying a pressing force, the second semiconductor circuit layer 2 is made closer to the first semiconductor circuit layer 1a from below, or the first semiconductor circuit layer 1a is viewed from above with respect to the second semiconductor circuit layer 2. Is lowered, the gap between the circuit layers 1a and 2 is narrowed as shown in FIG. 8 (m) and FIG. 10 (d). In other words, the interlayer gap between the circuit layers 1a and 2 is set to G2 (G2 <G1) smaller than G1. At this time, a compressive force acts between the electrode 43a of the second semiconductor circuit layer 2 and the electrode 42 of the first semiconductor circuit layer 1a. As a result, only the electrode 43a having a mechanical strength lower than that of the electrode 42 is selectively crushed so that the electrode 42 and the electrode 43 are joined to each other by “pressure contact”, and the adhesive element 44aa is further expanded. And completely connected and integrated within the gap. At this time, the four electrodes 43a corresponding to one electrode 42 are crushed and integrated, and as a result, the electrodes 42 and the electrodes 43a have a one-to-one correspondence. In this way, the entire gap between the circuit layers 2 and 1a is filled with the adhesive film 44a except for the electrode 43a and the electrode 42 which are in pressure contact with each other, and the extra adhesive film 44a may protrude from the gap. Absent. The state at this time is as shown in FIG. 8 (m) and FIG. 10 (d).

  When at least one of the electrode 42 and the electrode 43a is partially melted during heating, the electrode 42 and the electrode 43a are joined by “re-solidification” of the melted electrodes 42 and 43a or “pressure welding”. And “re-solidification” are performed in a mixed form.

  In this heating and pressure welding process, when the interlayer gap is reduced from G1 to G2, air (atmosphere) existing in the gap between the circuit layers 1a and 2 is surely removed, and the circuit layer 1a and the circuit It is important that the layers 2 are glued together. In the first embodiment, since the adhesive film 44a is divided into a large number of adhesive elements 44aa, the air present in the gaps is separated from the back surface of the first semiconductor circuit layer 1a and the adhesive film 44a (this is heated). The surface is softened or fluidized) and the minute space remaining between the adjacent adhesive elements 44aa can be reliably discharged to the outside. Further, since the surface of the adhesive film 44a is softened or fluidized, the circuit layers 1a and 2 can be reliably bonded to each other when the interlayer gap becomes G2.

  The value of the interlayer gap G2 is appropriately determined within a range of 1 μm to 9 μm, for example, but is typically 3 μm. However, the heights Hc and Hb of the electrodes 42 and 43a can be further reduced to 1 μm or less. In this case, the value of the distance G2 is appropriately determined in the range of 0.05 μm to 1 μm, for example.

  As described above, the second semiconductor circuit layer 2 is fixed (that is, mechanically connected) to the back surface side of the first semiconductor circuit layer 1a using the electrode 42 and the electrode 43a, and both the circuit layers 1a and 2 are connected. The electrical connection between is also made simultaneously. At the same time, the circuit layers 1a and 2 are bonded to each other by the adhesive film 44a filled in the entire gap between the circuit layers 1a and 2 except for the portions of the electrodes 43a and 42 connected to each other. Is done.

  When the mechanical and electrical connection between the electrode 42 and the electrode 43a and the bonding of the adhesive film 44a are completed as described above, the circuit layers 1 and 2a bonded to each other are naturally cooled to room temperature. Therefore, the adhesive film 44a is finally cured by heating, ultraviolet irradiation, chemical addition, or the like. Since treatment is easy, it is preferable to cure by heating. The heating temperature is appropriately set within a range of 120 to 500 ° C., for example, depending on the properties of the adhesive used as the adhesive film 44a. Thus, the mechanical connection and the electrical connection between the two semiconductor circuit layers 1a and 2 are completed.

  The subsequent steps are the same as those for the first semiconductor circuit layer 1a. That is, with respect to the second semiconductor circuit layer 2 bonded to the first semiconductor circuit layer 1a, the rear surface side of the Si substrate (wafer) 11 is formed on each trench 13 by CMP, as in the case of the first semiconductor circuit layer 1a. Polishing is performed until the distance from the lower end of the metal becomes about 1 μm, for example. The second semiconductor circuit layer 2 thus reduced in thickness is hereinafter referred to as 2a.

Next, the lower part of the substrate (wafer) 11 of the second semiconductor circuit layer 2a is selectively removed by the same method as that for the first semiconductor circuit layer 1a to expose the SiO ₂ film 14 inside the trench 13, An SiO ₂ film 41 is formed on the back surface of the substrate 11 and the exposed SiO ₂ film 14, and the SiO ₂ film 41 and the SiO ₂ film 14 are selectively removed to expose the lower end of the conductive plug 15. Further, the microbump electrodes 42 are respectively formed on the lower ends of the exposed conductive plugs 15. Thus, the configuration of the semiconductor circuit layer 2a is as shown in FIG. The second semiconductor circuit layer 2a in FIG. 8 (m) is substantially in the same state as the first semiconductor circuit layer 1a shown in FIG. 4 (i).

  In the case where the integrated circuit device is a three-dimensional stacked integrated circuit device having a two-layer structure composed of the first and second semiconductor circuit layers 1a and 2a, micro bumps formed on the back surface of the second semiconductor circuit layer 2a The electrode 42 is used as a micro bump electrode for external circuit connection. When the integrated circuit device has third or more semiconductor circuit layers, the third, fourth, fifth, fifth,... Are stacked on the second semiconductor circuit layer 2a by the same method as described above, if necessary. The semiconductor circuit layers (not shown) are stacked and fixed to produce an integrated circuit device having a three-dimensional stacked structure.

  At this stage, as is apparent from FIGS. 7 (l) and 10 (d), the circuit inside the first semiconductor circuit layer 1a, on the other hand, is in the multilayer wiring structure 30 in the first semiconductor circuit layer 1a. It is electrically connected to the circuit in the upper support substrate 40 via the wiring and the electrode 37, and on the other hand, the conductive plug 15, the electrodes 42 and 43 in the first semiconductor circuit layer 1a, and the second semiconductor. It is electrically connected to the circuit in the second semiconductor circuit layer 2a via the wiring in the multilayer wiring structure 30 in the circuit layer 2a. Similarly, the circuit in the second semiconductor circuit layer 2a is connected to the lower external circuit or third semiconductor circuit layer via the conductive plug 15 and the electrode 42 (and 43) in the second semiconductor circuit layer 2a. The circuit is electrically connected.

  Here, with reference to FIG. 32, the positional relationship between the electrode 42 of the first semiconductor circuit layer 1a and the electrode 43a of the second semiconductor circuit layer 2 and the surface of the second semiconductor circuit layer 2 were formed. The configuration of the patterned adhesive film 44a will be described in detail. FIG. 32A is an enlarged plan view showing the positional relationship between the electrodes 42 and 43a, and FIG. 32B is an enlarged plan view showing the configuration of the adhesive film 44a.

  As shown in FIG. 32A, each of the micro bump electrodes 42 provided on the back surface of the first semiconductor circuit layer 1a (the end surface of the conductive plug 15) has a length of two sides Lc1 and Lc2 (X direction). Has a rectangular planar shape with Lc1 as the length and Lc2) as the length in the Y direction. The two sides of the electrode 42 are parallel to the X direction, and the other two sides are parallel to the Y direction. The planar shape and size of the electrode 42 are equal to the planar shape and size of the end face of the corresponding conductive plug 15, respectively.

  Four microbump electrodes 43a formed on the surface of the second semiconductor circuit layer 2 form a set and correspond to one microbump electrode. Each of the four electrodes 43a has a rectangular planar shape in which the lengths of two sides are Lb1 and Lb2 (the length in the X direction is Lb1 and the length in the Y direction is Lb2). The four electrodes 43a have the same planar shape and size. Two sides of each electrode 43a are parallel to the X direction, and the other two sides are parallel to the Y direction.

  The four electrodes 43a are arranged corresponding to the four corners of the corresponding one electrode 42, respectively. Two electrodes 43a adjacent in the X direction are arranged with a gap P1 therebetween. The two electrodes 43a adjacent in the Y direction are arranged with a gap P2. Therefore, L1 = Lb1 + P1 + Lb1 and L2 = Lb2 + P2 + Lb2 hold.

  In FIG. 32A, for simplicity of illustration, the electrodes 42 and 43a are both square. For example, L1 = L2 = 5 μm, Lb1 = Lb2 = 2 μm, P1 = P2 = 1 μm, and Lc1 = Lc2 = 3 μm. In this case, the four electrodes 43a are arranged symmetrically with respect to the center of each electrode 42 at each corner.

  As shown in FIG. 32 (b), the adhesive film 44a has a shape (pattern) that does not overlap with the electrode 43a, and includes a large number of adhesive elements 44aa. The planar shape of each adhesive element 44aa is a rectangle in which the length of two sides is La1 and La2 (the length in the X direction is La1 and the length in the Y direction is La2). The size and layout of each adhesive element 44aa are appropriately adjusted according to the position where the adhesive element 44aa is disposed and how many electrodes 43a there are around. This is because the first semiconductor circuit layer 1a and the second semiconductor circuit except for the positions of the electrodes 42 and 43a when the interlayer gap is decreased from G1 to G2 while the surface of the adhesive element 44aa is softened or fluidized. This is because the entire gap between the layers 2 is filled with the adhesive film 44a. Thus, the size and layout of the adhesive element 44aa are arbitrarily set according to the necessity of filling the gap.

  Gaps d1, d2, d3, and d4 are provided between the adhesive element 44aa and the plurality of electrodes 43a surrounding it. The gap between adjacent adhesive elements 44aa is d11 in the X direction and d12 in the Y direction.

  In FIG. 32 (b), in order to simplify the illustration, the planar shape of the adhesive element 44aa is a square. To illustrate typical numerical values, d1 = d2 = d3 = d4 = 2 μm and d11 = d12 = 1.5 μm.

  The planar shape of the adhesive element 44aa is rectangular here, but the present invention is not limited to this. Any shape other than a rectangle can be used. The values of d1, d2, d3, d4, d11, and d12 are determined in consideration of the degree of spread of the adhesive element 44aa due to pressurization and softening or fluidization.

  As described above, in the method of manufacturing an integrated circuit device according to the first embodiment of the present invention, one end is inside the first semiconductor circuit layer 1a constituting the three-dimensional laminated structure, and the back surface of the semiconductor circuit layer 1a ( A plurality of conductive plugs 15 (that is, embedded wirings) exposed from the back surface of the substrate 11 are formed, and micro bump electrodes 42 are formed on the exposed end surfaces of the plugs 15. On the other hand, a plurality of micro bump electrodes 43a are formed at predetermined positions on the surface of the second semiconductor circuit layer 2 constituting the three-dimensional stacked structure (the surface of the multilayer wiring structure 30). Thereafter, a patterned electrically insulating adhesive film 44a having a shape that does not overlap the conductive plug 15 and the electrodes 42 and 43a is formed on the surface of the second semiconductor circuit layer 2, and then the first semiconductor. The back surface of the circuit layer 1a and the surface of the second semiconductor circuit layer 2 are opposed to each other. Then, by narrowing the distance between the two circuit layers 1a and 2, the electrode 42 and the electrode 43a are brought into contact with each other while spreading the adhesive film 44a, so that the gap between the first semiconductor circuit layer 1a and the second semiconductor circuit layer 2 is increased. Let G1 be the interlayer gap. Further, by applying a pressing force under heating, the gap between the first semiconductor circuit layer 1a and the second semiconductor circuit layer 2 is narrowed until the interlayer gap becomes G2. As a result, the electrode 43a is deformed and the circuit layers 1a and 2 are mechanically and electrically connected to each other. At this time, the adhesive film 44a is deformed (spreaded) in the gap remaining between the circuit layers 1a and 2 and filled in the gap at the end of the mechanical connection process of the electrodes 42 and 43a. I'm damned. The circuit layers 1a and 2 are bonded to each other by the adhesive film 44a.

  For this reason, when the interlayer gap between the first semiconductor circuit layer 1a and the second semiconductor circuit layer 2 is set to a predetermined value G2, it becomes substantially equal to the total volume of the space remaining between the layers 1a and 2. By adjusting the total amount of the adhesive film 44a, it becomes possible to reliably dispose the electrically insulating adhesive in the entire gap between the two layers 1a and 2, and the extra adhesive protruding beyond the gap. Need not be removed. This is the same for the connection between the second semiconductor circuit layer 2a and the third semiconductor circuit layer or between other semiconductor circuit layers.

  Therefore, it is possible to reliably arrange an electrically insulating adhesive in a gap between any stacked semiconductor circuit layers constituting a three-dimensional laminated structure, and to remove excess adhesive protruding from the gap. Post-processing can be omitted. As a result, the mechanical connection and electrical connection in the stacking direction between the stacked arbitrary semiconductor circuit layers constituting the three-dimensional stacked structure can be performed using the conductive plug 15 (that is, the embedded wiring) and the electrodes 42 and 43a. It can be realized easily and with high reliability.

In the first embodiment described above, the patterned adhesive film 44a is formed on the surface of the second semiconductor circuit layer 2 (the surface of the multilayer wiring structure 30), but the back surface of the first semiconductor circuit layer 2 is formed. it may be formed on (the surface of the SiO ₂ film 41). Further, the adhesive film 44a may not be divided into island-shaped adhesive elements 44aa, and may be formed continuously like an adhesive film 44c of a third embodiment described later. Even in this case, the gap 45 is surely formed between the adhesive film 44a whose surface is softened or fluidized and the back surface of the first semiconductor circuit layer 1a. The air remaining in the gap can be reliably discharged to the outside through the gap 45. Therefore, an effect similar to that of the adhesive film 44a divided into island-shaped adhesive elements 44aa can be obtained.

  In the first embodiment described above, the first semiconductor circuit layer 1a and the second semiconductor circuit layer 2a are sequentially stacked and fixed under the support substrate 40, but the support substrate 40 is turned upside down. Thus, it goes without saying that the first semiconductor circuit layer 1a and the second semiconductor circuit layer 2a may be laminated and fixed in order on the support substrate 40.

  Furthermore, in the first embodiment described above, after the first semiconductor circuit layer 1 having the structure shown in FIG. 2D is formed, the first substrate 37 is immediately connected to the support substrate 40 using the electrode 37, and then, FIG. The second semiconductor circuit layer 2 having the structure shown in j) is formed and then immediately connected to the first semiconductor circuit layer 1 using the electrodes 42 and 43. However, the manufacturing method of the present embodiment is not limited to this. . For example, it may be as follows. That is, first, the first semiconductor circuit layer 1 having the structure shown in FIG. 2D and the second semiconductor circuit layer 2 having the structure shown in FIG. Thereafter, the first semiconductor circuit layer 1 is fixed to the support substrate 40 and then the back surface of the first semiconductor circuit layer 1 is processed to form the first semiconductor circuit layer 1a having the structure shown in FIG. Subsequently, after the second semiconductor circuit layer 2 having the structure shown in FIG. 5J is fixed to the first semiconductor circuit layer 1a, the back surface of the second semiconductor circuit layer 2 is processed, and the structure shown in FIG. The second semiconductor circuit layer 2a having the above is formed.

  The above-described first embodiment is an example of manufacturing an integrated circuit device having a three-dimensional stacked structure by stacking semiconductor wafers, but in the same process as this, three-dimensional stacking is performed by stacking semiconductor chips instead of the semiconductor wafer. It is also possible to manufacture an integrated circuit device having a structure.

  Further, the wafer-size three-dimensional stacked integrated circuit device having the above-described configuration can be used as it is as a wafer-size three-dimensional stacked integrated circuit device without dividing a wafer stack composed of a plurality of stacked wafers. However, it goes without saying that it can be divided into a plurality of parts by dicing in a direction orthogonal to the support substrate 40 (stacking direction) and used as a three-dimensional stacked integrated circuit device smaller than the wafer size.

(Second Embodiment)
11 (a) to 13 (c) and FIGS. 14 (a) to 15 (d) show a method of manufacturing an integrated circuit device having a three-dimensional stacked structure according to the second embodiment of the present invention for each process. It is a fragmentary sectional view shown. This second embodiment is also an example of manufacturing an integrated circuit device having a three-dimensional stacked structure by stacking semiconductor wafers.

  The manufacturing method of the integrated circuit device according to the second embodiment includes a back surface (second main surface) of the first semiconductor circuit layer 1a and a front surface (first main surface) of the second semiconductor circuit layer 2 constituting a three-dimensional stacked structure. The method is the same as that of the integrated circuit device according to the first embodiment except that electrically insulating adhesive films 44b1 and 44b2 are formed on both sides. The adhesive film 44b1 has a shape that does not overlap with the conductive plug 15 and the microbump electrode 42, and includes a plurality of island-shaped adhesive elements 44bb1. The adhesive film 44b2 has a shape that does not overlap with the micro-bump electrode 43a, and includes a large number of island-shaped adhesive elements 44bb2. Therefore, below, only the outline is demonstrated about the process same as 1st Embodiment, and a different process is demonstrated in detail.

  FIGS. 11A to 13C correspond to FIGS. 5J to 7L in the first embodiment, respectively. FIGS. 14A to 15D correspond to FIGS. 9A to 10D in the first embodiment, respectively.

  First, the first semiconductor circuit layer 1a having the configuration shown in FIG. 4H is formed by the same process as in the first embodiment. Thereafter, using the same material as in the first embodiment and by the same method, as shown in FIG. 4I, a microbump electrode 42 is formed at the lower end of each exposed conductive plug 15, respectively.

  The height Hc of the electrode 42 with respect to the back surface of the first semiconductor circuit layer 1a is, for example, 1 μm.

Next, similarly to the adhesive film 44a in the first embodiment, as shown in FIG. 11A and FIG. 14A, the back surface (second main surface) of the first semiconductor circuit layer 1a, that is, SiO _2. On the exposed surface of the film 41, a patterned electrically insulating adhesive film 44b1 is formed. This adhesive film 44b1 is formed by patterning (curing) an electrically insulating adhesive such as polyimide resin or SOG material at room temperature, and its surface (exposed) is heated to a predetermined temperature. Surface) can be softened or fluidized. (In other words, it has heat softening property or heat fluidity.)
The adhesive film 44b1 is composed of a number of adhesive elements 44bb1 formed in a bump shape (island shape), they adhesives element 44bb1 is a layout as shown in FIG. 32 (b), SiO ₂ film 41 are regularly distributed on the exposed surface. The adhesive film 44b1 has a shape that does not overlap any of the electrodes 42, and is disposed except for the portion where the electrode 42 is formed and the vicinity thereof. Therefore, the adhesive film 44b1 (that is, all the adhesive elements 44bb1) does not overlap the conductive plug 15.

  As shown in FIG. 14A, the height of the adhesive element 44bb1 with respect to the back surface of the first semiconductor circuit layer 1a is Hd, and is set to 3 μm, for example.

  On the other hand, on the surface (flattened) of the multilayer wiring structure 30 (that is, the insulating material 31) of the second semiconductor circuit layer 2 manufactured by the same method as the first semiconductor circuit layer 1, FIG. As shown in FIG. 14A, a plurality of micro bump electrodes 43a (height is Hb) are formed. The electrode 43a is formed by the same method as the electrode 42 of the first semiconductor circuit layer 1a. Here, as in the first embodiment, four electrodes 43a correspond to each of the electrodes 42 provided on the back surface of the first semiconductor circuit layer 1a (Si wafer 11). In other words, four electrodes 43 a are bonded to one electrode 42. Further, when the electrodes 42 and 43a are brought into contact with each other and pressed, only the electrode 43a is selectively crushed (plastically deformed), so that the electrode 43a is more mechanical than the electrode 42 as in the first embodiment. It is formed from a conductive material having low strength.

  The height Ha of the electrode 43a with respect to the surface of the second semiconductor circuit layer 2 is set to 2 μm, for example.

  Next, in the same manner as the adhesive film 44a in the first embodiment, on the surface of the multilayer wiring structure 30 (that is, the insulating material 31) of the second semiconductor circuit layer 2, FIG. 11 (a) and FIG. 14 (a). As shown, a patterned electrically insulating adhesive film 44b2 is formed. This adhesive film 44b2 is formed using the same electrically insulating adhesive as the adhesive film 44b1, and has a viscosity (adhesiveness) after being patterned (cured) into a predetermined shape. In addition, the surface can be softened or fluidized by heating to a predetermined temperature.

  The adhesive film 44b2 is composed of a large number of adhesive elements 44bb2 formed in a bump shape (island shape). These adhesive elements 44bb2 have a layout as shown in FIG. It is distributed regularly on the surface of the structure 30. The adhesive film 44b2 has a shape that does not overlap with the electrode 43a, and is disposed except for a portion where the electrode 43a is formed and its vicinity. Therefore, the adhesive film 44b2 (that is, all the adhesive elements 44bb2) does not overlap with the electrode 42 (conductive plug 15).

  The height Ha of the adhesive element 44bb2 with respect to the surface of the second semiconductor circuit layer 2 is set to 3 μm, for example.

  The sum of the total volume of the adhesive films 44b1 and 44b2 (total volume after curing) is obtained by mechanically and electrically connecting the second semiconductor circuit layer 2 and the first semiconductor circuit layer 1a using the electrodes 42 and 43a. At this time, the entire gap formed between the two circuit layers 1a and 2 is filled with the adhesive films 44b1 and 44b2, and the value is set so that the extra adhesive films 44b1 and 44b2 do not protrude from the gap. . This is to avoid the operation of removing the excess adhesive films 44b1 and 44b2 protruding from the gap after the circuit layers 1a and 2 are connected.

  Since the adhesive films 44b1 and 44b2 do not exist in the vicinity of the place where the electrodes 42 and 43a are present, there is a gap between the island-shaped adhesive element 44bb1 and the island-shaped adhesive element 44bb2, respectively. 14A, the height Hd of each adhesive element 44bb1 (which is equal to the thickness of the adhesive film 44b1) is set larger than the height Hc of the electrode 42. (Hd> Hc), and the height Ha of each adhesive element 44bb2 is set larger than the height Hb of the electrode 43a (Ha> Hb). This is because, when the second semiconductor circuit layer 2 and the first semiconductor circuit layer 1a are connected, the adhesive elements 44bb1 and 44bb2 are crushed by pressurization, and around the electrode 42 and the electrode 43a and each adhesive element. This is to fill the entire gap remaining between the circuit layers 1a and 2 by spreading to the gap between 44bb1 and 44bb2, respectively.

  As will be described later, when the second semiconductor circuit layer 2 and the first semiconductor circuit layer 1a are connected, the respective electrodes 43a are also crushed and plastically deformed and spread around them. As a result, the four electrodes 43a corresponding to each electrode 42 are mutually connected and integrated.

  The adhesive films 44b1 and 44b2 are divided into a plurality of adhesive elements 44bb1 and 44bb2, respectively, when the second semiconductor circuit layer 2 and the first semiconductor circuit layer 1a are connected to each other. This is to facilitate the escape of air existing between 1a to the outside (that is, to facilitate degassing). That is, even when the circuit layers 2 and 1a are almost connected, the air existing between the layers 2 and 1a is pushed out through the gap between the adjacent adhesive elements 44b1 and 44b2. It is. Each of the adhesive elements 44bb1 has a one-to-one correspondence with the adhesive element 44bb2.

  Here, the adhesive film 44b1 is formed after the microbump electrode 42 is formed, and the adhesive film 44b2 is formed after the microbump electrode 43a is formed. However, after the adhesive film 44b1 is formed, the microbump electrode 42a is formed. The bump electrode 42 may be formed, or the microbump electrode 43a may be formed after the adhesive film 44b2 is formed.

  Subsequently, as shown in FIGS. 11A and 14A, the surface of the second semiconductor circuit layer 2 is opposed to the back surface of the first semiconductor circuit layer 1a fixed via the support substrate 40 from below. Let (Conversely, the second semiconductor circuit layer 2 may be fixed and the first semiconductor circuit layer 1a fixed to the support substrate 40 may be opposed from above.) Thereafter, the second semiconductor circuit layer 2 is pushed between the circuit layers 2 and 1a. When pressure is applied to bring the circuit layers 2 and 1a close to each other, the height of each adhesive element 44bb1 (the thickness of the adhesive film 44a) Hd is larger than the height Hc of the electrode 42 (Hd> Hc). Further, since the height of each adhesive element 44bb2 (the thickness of the adhesive film 44b2) Ha is larger than the height Hb of the electrode 43a (Ha> Hb), first, as shown in FIG. Further, the tip (top) of the adhesive film 44b2 (adhesive element 44bb2) of the second semiconductor circuit layer 2 is brought into contact with the tip (top) of the adhesive film 44b1 (adhesive element 44bb1) of the first semiconductor circuit layer 1a. It is done.

  Thereafter, a pressing force is applied between the circuit layers 2 and 1a to reduce the distance between the two, and as shown in FIGS. 12B and 15C, each electrode 43a of the second semiconductor circuit layer 2 is obtained. Is brought into contact with the electrode 42 of the corresponding first semiconductor circuit layer 1a. When the distance between the back surface of the first semiconductor circuit layer 1a and the surface of the second semiconductor circuit layer 2 at this time, that is, the interlayer gap is G1, the interlayer gap G1 is equal to the sum of the thickness of the electrode 42 and the thickness of the electrode 43a. That is, G1 = Hc + Hb. At this time, the adhesive films 44b1 and 44b2 are both crushed and deformed, and are spread over almost the entire gap between the circuit layers 1 and 2, but the adhesive films 44b1 and 44b2 are island-shaped adhesive elements. Since it is divided into 44bb1 and 44bb2, respectively, the adhesive films 44b1 and 44b2a spread almost uniformly in the gap. Further, since a gap 45 is easily formed between the deformed adhesive film 44b1 and the adhesive film 44b2 (and between the adjacent adhesive elements 44bb1 and 44bb2), the air remaining in the gap Can be reliably discharged to the outside through the gap 45, and the possibility of bubbles being generated in the finally integrated and cured adhesive film 44b1b2 can be eliminated.

  The step of bringing the electrodes 42 and 43a into contact with each other after the first semiconductor circuit layer 1a and the second semiconductor circuit layer 2 are opposed to each other is performed at room temperature, as in the first embodiment. The value of the distance G1 between the first semiconductor circuit layer 1a and the second semiconductor circuit layer 2 is appropriately determined within a range of 2 μm to 10 μm, for example, but is typically 4 μm. However, the heights Hc and Hb of the electrodes 42 and 43a can be further reduced to 2 μm or less. In this case, the value of the distance G1 is appropriately determined within a range of 0.1 μm to 2 μm, for example. This is also the same as in the first embodiment.

  Thereafter, the electrodes 43a and 42 brought into contact with each other are connected to each other as follows.

  That is, the second semiconductor circuit layer 2 and the first semiconductor circuit layer 1a in the states of FIGS. 12B and 15C are heated from room temperature to a predetermined temperature. The temperature is set to a temperature at which the surfaces (exposed surfaces) of the adhesive films 44b1 and 44b2 in the pressure-deformed state are slightly softened or the surfaces are slightly fluidized. The temperature varies depending on the type of adhesive used for the adhesive films 44b1 and 44b2, but is arbitrarily set within a range of, for example, 100 to 400 ° C. in consideration of the temperature at which the electrode 42 and the electrode 43a are “press-contacted”. Is done. At this time, depending on the heating temperature to be set, at least one of the electrode 42 and the electrode 43a may be partially melted and the surface thereof may be curved.

  Subsequently, by applying a pressing force, the second semiconductor circuit layer 2 is made closer to the first semiconductor circuit layer 1a from below, or the first semiconductor circuit layer 1a is viewed from above with respect to the second semiconductor circuit layer 2. As shown in FIG. 13 (c) and FIG. 15 (d), the gap between the circuit layers 1a and 2 is reduced from G1 by narrowing the gap between the circuit layers 1a and 2 as shown in FIGS. A smaller G2 (G2 <G1) is assumed. At this time, a compressive force acts between the electrode 43a of the second semiconductor circuit layer 2 and the electrode 42 of the first semiconductor circuit layer 1a. As a result, only the electrode 43a having a mechanical strength lower than that of the electrode 42 is selectively crushed so that the electrode 42 and the electrode 43 are joined to each other by “pressure contact”, and the adhesive elements 44bb1 and 44bb2 are further provided. They are spread and connected and integrated with each other. At this time, the four electrodes 43a corresponding to one electrode 42 are crushed and integrated, and as a result, the electrodes 42 and the electrodes 43a have a one-to-one correspondence. In this way, the entire gap between the circuit layers 2 and 1a is filled with the adhesive film 44a except for the electrode 43a and the electrode 42 that are in pressure contact with each other, and the extra adhesive film 44b1 or 44b2 is removed from the gap. It does not protrude. The state at this time is as shown in FIGS. 13 (c) and 15 (d).

  When at least one of the electrode 42 and the electrode 43a is partially melted during heating, the electrode 42 and the electrode 43a are joined by “re-solidification” of the melted electrodes 42 and 43a or “pressure welding”. And “re-solidification” are performed in a mixed form. This is the same as in the first embodiment.

  In this heating and pressure welding process, when the interlayer gap is reduced from G1 to G2, air (atmosphere) existing in the gap between the circuit layers 1a and 2 is surely removed, and the circuit layer 1a and the circuit It is important that the layers 2 are glued together. In this second embodiment, the adhesive films 44b1 and 44b2 are divided into a large number of adhesive elements 44bb1 and 44bb2, respectively, so that the air present in the gaps becomes the adhesive films 44b1 and 44b2 (both are heated). The surface is softened or fluidized) and the minute space remaining between the adjacent adhesive elements 44bb1 and 44bb2 can be reliably discharged to the outside. In addition, since the surface of the adhesive film 44bb1 and the surface of the adhesive film 44bb2 are both softened or fluidized, when the interlayer gap becomes G2, the adhesive film 44bb1 and the adhesive film 44bb2 are easily bonded. As a result, the circuit layers 1a and 2 can be securely bonded to each other.

  The value of the interlayer gap G2 is appropriately determined within a range of 1 μm to 9 μm, for example, but is typically 3 μm. However, the heights Hc and Hb of the electrodes 42 and 43a can be further reduced to 1 μm or less. In this case, the value of the distance G2 is appropriately determined in the range of 0.05 μm to 1 μm, for example.

  As described above, the second semiconductor circuit layer 2 is fixed (that is, mechanically connected) to the back surface side of the first semiconductor circuit layer 1a using the electrode 42 and the electrode 43a, and both the circuit layers 1a and 2 are connected. The electrical connection between is also made simultaneously. At the same time, both circuit layers 1a and 2 are mutually connected by adhesive films 44b1 and 44b2 filled in the entire gap between the circuit layers 1a and 2 except for the portions of the electrodes 43a and 42 connected to each other. Glued to.

  When the mechanical / electrical connection between the electrode 42 and the electrode 43a and the bonding of the adhesive films 44b1 and 44b2 are finished as described above, the circuit layers 1 and 2a bonded to each other are naturally cooled to room temperature. Therefore, the adhesive films 44b1 and 44b2 integrated by heating, ultraviolet irradiation, chemical addition, etc. are finally cured. Since treatment is easy, it is preferable to cure by heating. The heating temperature is appropriately set within a range of 120 to 500 ° C., for example, depending on the properties of the adhesive used as the adhesive films 44b1 and 44b2. Thus, the mechanical connection and the electrical connection between the two semiconductor circuit layers 1a and 2 are completed.

  Since the subsequent steps are the same as those in the first embodiment, the description thereof is omitted.

  As described above, the method for manufacturing an integrated circuit device according to the second embodiment of the present invention has an electrically insulating adhesive on both the back surface of the first semiconductor circuit layer 1a and the surface of the second semiconductor circuit layer 2. Since the manufacturing method of the integrated circuit device according to the first embodiment is the same as that of the first embodiment except that the films 44b1 and 44b2 are formed, the same effect as that obtained in the first embodiment can be obtained. it is obvious. However, in the second embodiment, since the two adhesive films 44b1 and 44b2 are used, the adhesive force between the second semiconductor circuit layer 2 and the first semiconductor circuit layer 1a is increased as compared with the first embodiment. There is.

(Third embodiment)
FIGS. 16A to 18C and FIGS. 19A to 20D show a method of manufacturing an integrated circuit device having a three-dimensional stacked structure according to the third embodiment of the present invention for each process. It is a fragmentary sectional view shown. This third embodiment is also an example of manufacturing an integrated circuit device having a three-dimensional stacked structure by stacking semiconductor wafers.

  The method for manufacturing an integrated circuit device according to the third embodiment includes a back surface (second main surface) of the first semiconductor circuit layer 1a and a front surface (first main surface) of the second semiconductor circuit layer 2 constituting a three-dimensional stacked structure. The manufacturing method of the integrated circuit device of the first embodiment is the same as that of the first embodiment, except that electrically insulating adhesive films 44c and 44b2 are formed on both sides. The adhesive film 44c has a shape that does not overlap with the conductive plug 15 and the microbump electrode 42, but is formed continuously and is not divided into a large number of adhesive elements as in the second embodiment. Is different. A gap is formed between the adhesive film 44c and each electrode 42 as a region for absorbing a volume increase caused by the electrode 43a being crushed during connection. Similar to the second embodiment, the adhesive film 44b2 has a shape that does not overlap with the microbump electrode 43a, and includes a large number of adhesive elements 44bb2. Therefore, below, only the outline is demonstrated about the process same as 1st Embodiment, and a different process is demonstrated in detail.

  FIGS. 16A to 18C correspond to FIGS. 5J to 7L in the first embodiment, respectively. FIGS. 19A to 20D correspond to FIGS. 9A to 10D in the first embodiment, respectively.

  First, the first semiconductor circuit layer 1a having the configuration shown in FIG. 4H is formed by the same process as in the first embodiment. Thereafter, using the same material as in the first embodiment and by the same method, as shown in FIG. 4I, a microbump electrode 42 is formed at the lower end of each exposed conductive plug 15, respectively.

  The height Hc of the electrode 42 with respect to the back surface of the first semiconductor circuit layer 1a is, for example, 2.5 μm.

Next, in the same manner as the adhesive film 44a in the first embodiment and the adhesive film 44b1 in the second embodiment, as shown in FIGS. 16A and 19A, the first semiconductor circuit layer 1a is formed. A patterned electrically insulating adhesive film 44 c is formed on the back surface (second main surface), that is, the exposed surface of the SiO ₂ film 41. The adhesive film 44c is formed by patterning (curing) an electrically insulating adhesive such as polyimide resin or SOG material at room temperature, and its surface (exposed) is heated to a predetermined temperature. Surface) can be softened or fluidized.

The adhesive film 44 c has a shape that does not overlap with the electrode 42 (and the conductive plug 15), but is not divided into adhesive elements, and the SiO ₂ film 41 except for a portion where the electrode 42 is located and its vicinity. Covers the entire exposed surface. Therefore, the adhesive film 44 c does not overlap with the conductive plug 15.

  As shown in FIG. 19A, the height of the adhesive film 44c with reference to the back surface of the first semiconductor circuit layer 1a is Hd, and is set to 2 μm, for example.

  On the other hand, on the surface (flattened) of the multilayer wiring structure 30 (that is, the insulating material 31) of the second semiconductor circuit layer 2 manufactured by the same method as the first semiconductor circuit layer 1, FIG. As shown in FIG. 19A, a plurality of micro bump electrodes 43a (height is Hb) are formed. The electrode 43a is formed by the same method as the electrode 42 of the first semiconductor circuit layer 1a. Here, as in the first embodiment, four electrodes 43a correspond to each of the electrodes 42 provided on the back surface of the first semiconductor circuit layer 1a (Si wafer 11). In other words, four electrodes 43 a are bonded to one electrode 42. Further, when the electrodes 42 and 43a are brought into contact with each other and pressed, only the electrode 43a is selectively crushed (plastically deformed), so that the electrode 43a is more mechanical than the electrode 42 as in the first embodiment. It is formed from a conductive material having low strength.

  The height Hb of the electrode 43a with respect to the surface of the second semiconductor circuit layer 2 is set to 2 μm, for example.

  Next, in the same manner as the adhesive film 44a in the first embodiment, on the surface of the multilayer wiring structure 30 (that is, the insulating material 31) of the second semiconductor circuit layer 2, FIG. 16 (a) and FIG. As shown, a patterned electrically insulating adhesive film 44b2 is formed. This adhesive film 44b2 is formed using the same electrically insulating adhesive as the adhesive film 44b1, and has a viscosity (adhesiveness) after being patterned (cured) into a predetermined shape. In addition, the surface can be softened or fluidized by heating to a predetermined temperature.

  The adhesive film 44b2 is composed of a large number of adhesive elements 44bb2 formed in a bump shape (island shape). These adhesive elements 44bb2 have a layout as shown in FIG. It is distributed regularly on the surface of the structure 30. The adhesive film 44b2 has a shape that does not overlap with the electrode 43a, and is disposed except for a portion where the electrode 43a is formed and its vicinity. Therefore, the adhesive film 44b2 (that is, all the adhesive elements 44bb2) does not overlap with the electrode 42 (conductive plug 15).

  The height Ha of the adhesive element 44bb2 with respect to the surface of the second semiconductor circuit layer 2 is set to 3 μm, for example.

  The sum of the total volume (total volume after curing) of the adhesive films 44c and 44b2 is obtained by mechanically and electrically connecting the second semiconductor circuit layer 2 and the first semiconductor circuit layer 1a using the electrodes 42 and 43a. At this time, the entire gap formed between the two circuit layers 1a and 2 is filled with the adhesive films 44c and 44b2, and the value is set so that the excess adhesive films 44c and 44b2 do not protrude from the gap. Yes. This is to avoid the operation of removing the excess adhesive films 44c and 44b2 protruding from the gap after the circuit layers 1a and 2 are fixed.

  As shown in FIG. 19A, the thickness Hd of the adhesive film 44c is smaller than the height Hc of the electrode 42 (Hd <Hc), but each adhesive element 44bb2 of the adhesive film 44b2 has a thickness Hd. The height Ha (which is equal to the thickness of the adhesive film 44b2) is larger than the height Hb of the electrode 43a (Ha> Hb). For this reason, when the second semiconductor circuit layer 2 and the first semiconductor circuit layer 1a are connected, each adhesive element 44bb2 is crushed by pressurization, and the periphery of the electrode 42 and the electrode 43a and between each adhesive element 44bb2. Each of the gaps between the circuit layers 1a and 2 is easily filled.

  As will be described later, when the second semiconductor circuit layer 2 and the first semiconductor circuit layer 1a are connected, the respective electrodes 43a are also crushed and plastically deformed and spread around them. As a result, the four electrodes 43a corresponding to each electrode 42 are mutually connected and integrated.

  The adhesive film 44b2 is divided into a plurality of adhesive elements 44bb2 when the second semiconductor circuit layer 2 and the first semiconductor circuit layer 1a are connected to each other between the circuit layers 2 and 1a. This is to facilitate the escape of air to the outside (that is, to facilitate degassing). That is, even when the circuit layers 2 and 1a are almost connected, the air existing between the layers 2 and 1a is pushed out through the gap between the adjacent adhesive elements 44bb2. .

  Here, the adhesive film 44c is formed after the microbump electrode 42 is formed, and the adhesive film 44b2 is formed after the microbump electrode 43a is formed. However, after the adhesive film 44c is formed, the microbump electrode 42a is formed. The bump electrode 42 may be formed, or the microbump electrode 43a may be formed after the adhesive film 44b2 is formed.

  Subsequently, as shown in FIGS. 16A and 19A, the surface of the second semiconductor circuit layer 2 is opposed to the back surface of the first semiconductor circuit layer 1a fixed via the support substrate 40 from below. Let (Conversely, the second semiconductor circuit layer 2 may be fixed and the first semiconductor circuit layer 1a fixed to the support substrate 40 may be opposed from above.) Thereafter, the second semiconductor circuit layer 2 is pushed between the circuit layers 2 and 1a. When pressure is applied to bring the circuit layers 2 and 1a close to each other, the height of each adhesive element 44bb2 (the thickness of the adhesive film 44b2) Ha is larger than the height Hb of the electrode 43a (Ha> Hb). Since the thickness Hd of the adhesive film 44c is smaller than the height Hc of the electrode 42 (Hd <Hc) and Ha + Hd> Hb + Hc, first, as shown in FIG. The tip (top) of the adhesive film 44b2 (adhesive element 44bb2) of the semiconductor circuit layer 2 is brought into contact with the surface of the adhesive film 44c of the first semiconductor circuit layer 1a.

  Thereafter, a pressing force is applied between the circuit layers 2 and 1a to reduce the distance between the two, and as shown in FIGS. 16B and 20C, each electrode 43a of the second semiconductor circuit layer 2 is obtained. Is brought into contact with the electrode 42 of the corresponding first semiconductor circuit layer 1a. When the distance between the back surface of the first semiconductor circuit layer 1a and the surface of the second semiconductor circuit layer 2 at this time, that is, the interlayer gap is G1, the interlayer gap G1 is equal to the sum of the thickness of the electrode 42 and the thickness of the electrode 43a. That is, G1 = Hc + Hb. At this time, the adhesive films 44c and 44b2 are both crushed and deformed, and are spread over almost the entire gap between the circuit layers 1 and 2, but the adhesive film 44b2 is formed on the island-shaped adhesive element 44bb2. Since it is divided, the adhesive film 44b2 spreads almost uniformly in the gap. Further, since the gap 45 is easily formed between the deformed adhesive film 44c and the adhesive film 44b2 (and between the adjacent adhesive elements 44bb2), the air remaining in the gap is void. It can be reliably discharged to the outside through 45, and the risk of bubbles being generated in the finally integrated and cured adhesive film 44b2c can be eliminated.

  The step of bringing the electrodes 42 and 43a into contact with each other after the first semiconductor circuit layer 1a and the second semiconductor circuit layer 2 are opposed to each other is performed at room temperature, as in the first embodiment. The value of the distance G1 between the first semiconductor circuit layer 1a and the second semiconductor circuit layer 2 is appropriately determined within a range of 2 μm to 10 μm, for example, but is typically 4 μm. However, the heights Hc and Hb of the electrodes 42 and 43a can be further reduced to 2 μm or less. In this case, the value of the distance G1 is appropriately determined within a range of 0.1 μm to 2 μm, for example. This is also the same as in the first embodiment.

  Thereafter, the electrode 43a and the electrode 42 brought into contact with each other are bonded to each other as follows.

  That is, the second semiconductor circuit layer 2 and the first semiconductor circuit layer 1a in the states of FIGS. 17B and 20C are heated from room temperature to a predetermined temperature. The temperature is set to a temperature at which the surfaces (exposed surfaces) of the adhesive films 44c and 44b2 in the pressure-deformed state are slightly softened or the surfaces are slightly fluidized. The temperature varies depending on the type of adhesive used for the adhesive films 44 c and 44 b 2, but is arbitrarily set within a range of, for example, 100 to 400 ° C. in consideration of the temperature at which the electrode 42 and the electrode 43 a “pressure contact”. Is done. At this time, depending on the heating temperature to be set, at least one of the electrode 42 and the electrode 43a may be partially melted and the surface thereof may be curved.

  Subsequently, as in the first embodiment, as shown in FIGS. 18C and 20D, the gap between the circuit layers 1a and 2 is reduced by narrowing the gap between the circuit layers 1a and 2. The interlayer gap is set to G2 smaller than G1 (G2 <G1). At this time, only the electrode 43a of the second semiconductor circuit layer 2 whose mechanical strength is lower than that of the electrode 42 of the first semiconductor circuit layer 1a is selectively crushed, and the electrode 42 and the electrode 43 are mutually pressed by “pressure contact”. At the same time, the adhesive element 44bb2 is further spread and connected to and integrated with each other, and further connected to and integrated with the adhesive film 44c. At this time, the four electrodes 43a corresponding to one electrode 42 are crushed and integrated, and as a result, the electrodes 42 and the electrodes 43a have a one-to-one correspondence. Thus, the entire gap between the circuit layers 2 and 1a is filled with the adhesive film 44b2c except for the portions of the electrode 43a and the electrode 42 that are in pressure contact with each other, and the extra adhesive film 44b1 or 44b2 is removed from the gap. It does not protrude. The state at this time is as shown in FIG. 18 (c) and FIG. 20 (c).

  When at least one of the electrode 42 and the electrode 43a is partially melted during heating, the electrode 42 and the electrode 43a are joined by “re-solidification” of the melted electrodes 42 and 43a or “pressure welding”. And “re-solidification” are performed in a mixed form. This is the same as in the first embodiment.

  In this heating and pressing process, when the interlayer gap is reduced from G1 to G2, the adhesive film 44b2 is divided into a large number of adhesive elements 44bb2, so that air existing in the gap between the circuit layers 1a and 2 is present. Passes through the gap 45 between the adhesive films 44c and 44b2 (both of which are softened or fluidized by heating) and the minute space remaining between the adjacent adhesive elements 44bb2, Can be reliably discharged. In addition, since both the surface of the adhesive film 44c and the surface of the adhesive film 44bb2 are softened or fluidized, when the interlayer gap becomes G2, the adhesive film 44c and the adhesive film 44bb2 are easily bonded. As a result, the circuit layers 1a and 2 can be securely bonded to each other.

  The value of the interlayer gap G2 is appropriately determined within a range of 1 μm to 9 μm, for example, but is typically 3 μm. However, the heights Hc and Hb of the electrodes 42 and 43a can be further reduced to 1 μm or less. In this case, the value of the distance G2 is appropriately determined in the range of 0.05 μm to 1 μm, for example.

  As described above, the second semiconductor circuit layer 2 is fixed (that is, mechanically connected) to the back surface side of the first semiconductor circuit layer 1a using the electrode 42 and the electrode 43a, and both the circuit layers 1a and 2 are connected. The electrical connection between is also made simultaneously. At the same time, the circuit layers 1a and 2 are bonded to each other by the adhesive films 44c and 44b2 filled in the entire gap between the circuit layers 1a and 2 except for the portions of the electrodes 43a and 42 that are pressed against each other. Bonded to each other.

  When the mechanical and electrical connection between the electrode 42 and the electrode 43a and the bonding of the adhesive films 44c and 44b2 are completed as described above, the circuit layers 1 and 2a bonded to each other are naturally cooled to room temperature. Therefore, the adhesive films 44b1 and 44b2 integrated by heating, ultraviolet irradiation, chemical addition, etc. are finally cured. Since treatment is easy, it is preferable to cure by heating. The heating temperature is appropriately set within a range of 120 to 500 ° C., for example, depending on the properties of the adhesive used as the adhesive films 44b1 and 44b2. Thus, the mechanical connection and the electrical connection between the two semiconductor circuit layers 1a and 2 are completed.

  Since the subsequent steps are the same as those in the first embodiment, the description thereof is omitted.

  As described above, the manufacturing method of the integrated circuit device according to the third embodiment of the present invention is an electrically insulating adhesive on both the back surface of the first semiconductor circuit layer 1a and the surface of the second semiconductor circuit layer 2. Since the manufacturing method of the integrated circuit device according to the first embodiment is the same as that of the first embodiment except that the films 44c and 44b2 are formed, the same effect as that obtained in the first embodiment can be obtained. it is obvious. However, in the third embodiment, since the two adhesive films 44c and 44b2 are used, as in the second embodiment, the second semiconductor circuit layer 2 and the first semiconductor circuit layer than in the first embodiment are used. There is an advantage that the adhesive force of 1a is increased.

  In the third embodiment, the adhesive film 44b2 is divided into adhesive elements, but since the adhesive film 44c is not divided into adhesive elements, the air in the gap 45 between the circuit layers 1 and 2a Ease of discharging is inferior to that of the second embodiment. However, since it is not necessary to divide the adhesive film 44c into adhesive elements, the process of forming the adhesive film 44c is that much easier.

(Fourth embodiment)
21 (a) to 23 (c) and FIGS. 24 (a) to 25 (c) show a method of manufacturing an integrated circuit device having a three-dimensional stacked structure according to the fourth embodiment of the present invention for each step. It is a fragmentary sectional view shown. The fourth embodiment is also an example of manufacturing an integrated circuit device having a three-dimensional stacked structure by stacking semiconductor wafers.

  The manufacturing method of the integrated circuit device of 4th Embodiment is the back surface (2nd main surface) of the 1st semiconductor circuit layer 1a and the surface (1st main surface) of the 2nd semiconductor circuit layer 2 which comprise a three-dimensional laminated structure. The method is the same as the method of manufacturing the integrated circuit device of the first embodiment except that electrically insulating adhesive films 44c1 and 44c2 are formed on both sides. The adhesive film 44c1 has a shape that does not overlap the conductive plug 15 and the microbump electrode 42, but is formed continuously and is not divided into a large number of adhesive elements. Similarly, the adhesive film 44c2 has a shape that does not overlap the microbump electrode 43a, but is formed continuously and is not divided into a large number of adhesive elements. Therefore, below, only the outline is demonstrated about the process same as 1st Embodiment, and a different process is demonstrated in detail.

  FIG. 21A to FIG. 23C correspond to FIG. 5J to FIG. 7L in the first embodiment, respectively. FIGS. 24A to 25C correspond to FIGS. 9A to 10C in the first embodiment, respectively.

  First, the first semiconductor circuit layer 1a having the configuration shown in FIG. 4H is formed by the same process as in the first embodiment. Thereafter, using the same material as in the first embodiment and by the same method, as shown in FIG. 4I, a microbump electrode 42 is formed at the lower end of each exposed conductive plug 15, respectively.

  The height Hc of the electrode 42 with respect to the back surface of the first semiconductor circuit layer 1a is, for example, 2.5 μm.

Next, similarly to the adhesive film 44a in the first embodiment and the adhesive film 44b1 in the second embodiment, as shown in FIGS. 21A and 24A, the first semiconductor circuit layer 1a is formed. An unpatterned electrically insulating adhesive film 44 c 1 is formed on the back surface (second main surface), that is, the exposed surface of the SiO ₂ film 41. The adhesive film 44c1 is formed by patterning (curing) an electrically insulating adhesive such as polyimide resin or SOG material at room temperature, and its surface (exposed) is heated to a predetermined temperature. Surface) can be softened or fluidized.

The adhesive film 44 c 1 has a shape that does not overlap the electrode 42 (and the conductive plug 15), but is not divided into adhesive elements, and the SiO ₂ film 41 except for a portion where the electrode 42 is present and its vicinity. Covers the entire exposed surface. Therefore, the adhesive film 44 c 1 does not overlap with the conductive plug 15.

  As shown in FIG. 24A, the height of the adhesive element 44c1 with respect to the back surface of the first semiconductor circuit layer 1a is Hd, and is set to 2 μm, for example.

  On the other hand, on the surface (flattened) of the multilayer wiring structure 30 (that is, the insulating material 31) of the second semiconductor circuit layer 2 manufactured by the same method as the first semiconductor circuit layer 1, FIG. As shown in FIG. 24A, a plurality of micro bump electrodes 43a (height is Hb) are formed. The electrode 43a is formed by the same method as the electrode 42 of the first semiconductor circuit layer 1a. Here, as in the first embodiment, four electrodes 43a correspond to each of the electrodes 42 provided on the back surface of the first semiconductor circuit layer 1a (Si wafer 11). In other words, four electrodes 43 a are bonded to one electrode 42. Further, when the electrodes 42 and 43a are brought into contact with each other and pressed, only the electrode 43a is selectively crushed (plastically deformed), so that the electrode 43a is more mechanical than the electrode 42 as in the first embodiment. It is formed from a conductive material having low strength.

  The height Hb of the electrode 43a with respect to the surface of the second semiconductor circuit layer 2 is set to 2.5 μm, for example.

  Next, in the same manner as the adhesive film 44a in the first embodiment, on the surface of the multilayer wiring structure 30 (that is, the insulating material 31) of the second semiconductor circuit layer 2, FIG. 21 (a) and FIG. 24 (a). As shown, a patterned electrically insulating adhesive film 44c2 is formed. The adhesive film 44c2 is formed using the same electrically insulating adhesive as the adhesive film 44c1, and has a viscosity (adhesiveness) after being cured into a predetermined shape. The surface can be softened or fluidized by heating to temperature.

  Similarly to the adhesive film 44c1, the adhesive film 44c2 has a shape that does not overlap the electrode 43a, but is not divided into adhesive elements, and the multilayer wiring structure 30 except for a portion where the electrode 43a is located and its vicinity. Covers the entire surface of the.

  A thickness Ha of the adhesive film 44c2 with respect to the surface of the second semiconductor circuit layer 2 is set to 2 μm, for example.

  The sum of the total volume (total volume after curing) of the adhesive films 44c1 and 44c2 is obtained by mechanically and electrically connecting the second semiconductor circuit layer 2 and the first semiconductor circuit layer 1a using the electrodes 42 and 43a. At this time, the entire gap formed between the two circuit layers 1a and 2 is filled with the adhesive films 44c1 and 44c2, and the adhesive film 44c1 and 44c2 are set so as not to protrude from the gap. Yes. This is to avoid the operation of removing the excess adhesive films 44c1 and 44c2 protruding from the gap after the circuit layers 1a and 2 are connected.

  Since the adhesive films 44c1 and 44c2 do not exist in the vicinity of the positions where the electrodes 42 and 43a are present, the thickness Hd of the adhesive film 44c1 is equal to the height Hc of the electrode 42 as shown in FIG. Is set smaller (Hd <Hc), and the thickness Ha of the adhesive film 44c2 is set smaller than the height Hb of the electrode 43a (Ha <Hb). This is because when the second semiconductor circuit layer 2 and the first semiconductor circuit layer 1a are connected, the adhesive films 44c1 and 44c2 are crushed by the pressure and spread around the electrodes 42 and 43a, This is because the entire gap remaining between the circuit layers 1a and 2 is filled.

  As will be described later, when the second semiconductor circuit layer 2 and the first semiconductor circuit layer 1a are connected, the respective electrodes 43a are also crushed and plastically deformed and spread around them. As a result, the four electrodes 43a corresponding to each electrode 42 are mutually connected and integrated.

  Here, the adhesive film 44c1 is formed after the microbump electrode 42 is formed, and the adhesive film 44c2 is formed after the microbump electrode 43a is formed. However, the microbump electrode 42a is formed after the adhesive film 44c1 is formed. The bump electrode 42 may be formed, or the microbump electrode 43a may be formed after the adhesive film 44c2 is formed.

  Subsequently, as shown in FIGS. 21A and 24A, the surface of the second semiconductor circuit layer 2 is opposed to the back surface of the first semiconductor circuit layer 1a fixed via the support substrate 40 from below. Let (Conversely, the second semiconductor circuit layer 2 may be fixed and the first semiconductor circuit layer 1a fixed to the support substrate 40 may be opposed from above.) Thereafter, the second semiconductor circuit layer 2 is pushed between the circuit layers 2 and 1a. When the circuit layers 2 and 1a are brought close to each other by applying pressure, the thickness Hd of the adhesive film 44c1 is set to be smaller than the height Hc of the electrode 42 (Hd <Hc), and the thickness Ha of the adhesive film 44c2 is set. Is set to be smaller than the height Hb of the electrode 43a (Ha <Hb). First, as shown in FIGS. 22B and 24B, the electrode 42 of the second semiconductor circuit layer 2 The tip (top) is brought into contact with the tip (top) of the electrode 43a of the first semiconductor circuit layer 1a. The interlayer gap between the circuit layers 1 and 2 at this time is G1 (G1 = Hc + Hb).

  At this time, the adhesive films 44c1 and 44c2 are not joined and integrated, and a gap 45 is formed between the opposing surfaces of the adhesive films 44c1 and 44c2. For this reason, air can be easily discharged outside through the gap 45.

  The step of bringing the electrodes 42 and 43a into contact with each other after the first semiconductor circuit layer 1a and the second semiconductor circuit layer 2 are opposed to each other is performed at room temperature, as in the first embodiment. The value of the distance G1 between the first semiconductor circuit layer 1a and the second semiconductor circuit layer 2 is appropriately determined within a range of 2 μm to 10 μm, for example, but is typically 4 μm. However, the heights Hc and Hb of the electrodes 42 and 43a can be further reduced to 2 μm or less. In this case, the value of the distance G1 is appropriately determined within a range of 0.1 μm to 2 μm, for example. This is also the same as in the first embodiment.

  Thereafter, the electrode 43a and the electrode 42 brought into contact with each other are bonded to each other as follows.

  That is, the second semiconductor circuit layer 2 and the first semiconductor circuit layer 1a in the states of FIGS. 22B and 24B are heated from room temperature to a predetermined temperature. The temperature is set to a temperature at which the surfaces (exposed surfaces) of the adhesive films 44c1 and 44c2 are slightly softened or the surfaces thereof are slightly fluidized. The temperature differs depending on the type of adhesive used for the adhesive films 44c1 and 44c2, but is arbitrarily set within a range of, for example, 100 to 400 ° C. in consideration of the temperature at which the electrode 42 and the electrode 43a are “pressed”. Is done. At this time, depending on the heating temperature to be set, at least one of the electrode 42 and the electrode 43a may be partially melted and the surface thereof may be curved.

  Subsequently, by applying a pressing force, as in the first embodiment, as shown in FIGS. 23 (c) and 25 (c), by narrowing the gap between the circuit layers 1a and 2, The interlayer gap between the circuit layers 1a and 2 is G2 and smaller G2 (G2 <G1). At this time, a compressive force acts between the electrode 43a of the second semiconductor circuit layer 2 and the electrode 42 of the first semiconductor circuit layer 1a. As a result, only the electrode 43a having a mechanical strength lower than that of the electrode 42 is selectively crushed so that the electrode 42 and the electrode 43 are joined to each other by “pressure contact”, and the adhesive films 44c1 and 44c2 are mutually connected. It is connected and integrated with each other while being pushed and spread. At this time, the four electrodes 43a corresponding to one electrode 42 are crushed and integrated, and as a result, the electrodes 42 and the electrodes 43a have a one-to-one correspondence. In this way, the entire gap between the circuit layers 2 and 1a is filled with the adhesive film 44c1c2 except for the portions of the electrodes 43a and 42 that are in pressure contact with each other, and the extra adhesive film 44c1 or 44c2 is removed from the gap. It does not protrude. The The state at this time is as shown in FIG. 23 (c) and FIG. 25 (c).

  When at least one of the electrode 42 and the electrode 43a is partially melted during heating, the electrode 42 and the electrode 43a are joined by “re-solidification” of the melted electrodes 42 and 43a or “pressure welding”. And “re-solidification” are performed in a mixed form. This is the same as in the first embodiment.

  In the fourth embodiment, since both of the adhesive films 44c1 and 44c2 are not divided into adhesive elements, the air existing between the opposing surfaces of the adhesive films 44c1 and 44c2 is not heated between Before the gap is narrowed to G2, it is discharged to the outside through the gap 45. Since both the surface of the adhesive film 44c1 and the surface of the adhesive film 44c2 are softened or fluidized, the adhesive film 44c1 and the adhesive film 44c2 are easily bonded when the interlayer gap becomes G2, and as a result, The circuit layers 1a and 2 can be securely bonded to each other. This is the same as in the first embodiment.

  The value of the interlayer gap G2 is appropriately determined within a range of 1 μm to 9 μm, for example, but is typically 3 μm. However, the heights Hc and Hb of the electrodes 42 and 43a can be further reduced to 1 μm or less. In this case, the value of the distance G2 is appropriately determined in the range of 0.05 μm to 1 μm, for example.

  As described above, the second semiconductor circuit layer 2 is fixed (that is, mechanically connected) to the back surface side of the first semiconductor circuit layer 1a using the electrode 42 and the electrode 43a, and both the circuit layers 1a and 2 are connected. The electrical connection between is also made simultaneously. At the same time, both circuit layers 1a and 2 are mutually connected by adhesive films 44b1 and 44b2 filled in the entire gap between the circuit layers 1a and 2 except for the portions of the electrodes 43a and 42 connected to each other. Glued to.

  When the mechanical / electrical connection between the electrode 42 and the electrode 43a and the bonding of the adhesive films 44c1 and 44c2 are completed as described above, the circuit layers 1 and 2a bonded to each other are naturally cooled to room temperature. Therefore, the adhesive films 44c1 and 44c2 integrated by heating, ultraviolet irradiation, chemical addition, etc. are finally cured. Since treatment is easy, it is preferable to cure by heating. The heating temperature is appropriately set within a range of 120 to 500 ° C., for example, depending on the properties of the adhesive used as the adhesive films 44c1 and 44c. Thus, the mechanical connection and the electrical connection between the two semiconductor circuit layers 1a and 2 are completed.

  Since the subsequent steps are the same as those in the first embodiment, the description thereof is omitted.

  As described above, the method for manufacturing an integrated circuit device according to the fourth embodiment of the present invention has an electrically insulating adhesive on both the back surface of the first semiconductor circuit layer 1a and the surface of the second semiconductor circuit layer 2. Except for forming the films 44c1 and 44c2, respectively, it is the same as the manufacturing method of the integrated circuit device according to the first embodiment described above, and therefore the same effect as that obtained in the first embodiment can be obtained. it is obvious. However, in the fourth embodiment, since the two adhesive films 44c1 and 44c2 are used, as in the second embodiment, the second semiconductor circuit layer 2 and the first semiconductor circuit layer than in the first embodiment are used. There is an advantage that the adhesive force of 1a is increased.

  In the fourth embodiment, since both of the adhesive films 44c1 and 44c2 are not divided into adhesive elements, the air in the gap 45 between the circuit layers 1 and 2a is easily discharged as much as the second embodiment. Inferior to. However, since it is not necessary to divide the adhesive films 44c1 and 44c2 into adhesive elements, the process of forming the adhesive films 44c1 and 44c2 is much easier.

(Fifth embodiment)
26 (a) to 29 (e) and FIGS. 30 (a) to 31 (d) show a method of manufacturing an integrated circuit device having a three-dimensional stacked structure according to the fifth embodiment of the present invention for each step. It is a fragmentary sectional view shown. The fifth embodiment is also an example of manufacturing an integrated circuit device having a three-dimensional stacked structure by stacking semiconductor wafers.

  In the manufacturing method of the integrated circuit device of the fifth embodiment, the microbump electrode is not formed on the back surface (second main surface) of the first semiconductor circuit layer 1a constituting the three-dimensional stacked structure, and the end of the conductive plug 15 is formed. Is directly in contact with the micro bump electrode 43a on the surface (first main surface) of the second semiconductor circuit layer 2, and is the same as the manufacturing method of the integrated circuit device of the first embodiment. Therefore, below, only the outline is demonstrated about the process same as 1st Embodiment, and a different process is demonstrated in detail.

First, the first semiconductor circuit layer 1a having the configuration shown in FIG. 3F is formed by the same process as in the first embodiment. Thereafter, similarly to the first embodiment, the SiO ₂ film 41 is formed on the back surface of the substrate 11 and the exposed SiO ₂ film 14 to obtain the configuration shown in FIG. The configuration thus obtained is again shown in FIG. The subsequent steps are different from those in the first embodiment.

That is, in the configuration shown in FIGS. 3G and 26A, the portion of the SiO ₂ film 41 covering the end of the conductive plug 15 is selectively removed by a known etching method, and the conductive plug 15 is removed. The edge part 15a of this is exposed. As a result, the end 15a of the conductive plug 15 protrudes from the SiO ₂ film 41 as shown in FIG. The remaining SiO ₂ film 41 covers portions other than the conductive plug 15 on the back surface of the semiconductor substrate 11. Hereinafter, the first semiconductor circuit layer having such a structure is referred to as 1b. Unlike the first embodiment, the entire back surface of the first semiconductor circuit layer 1b is not flat. Further, the micro bump electrode 42 is not formed at the lower end of each exposed conductive plug 15.

As shown in FIG. 30A, the height of the protruding portion of each conductive plug 15 with respect to the back surface of the first semiconductor circuit layer 1b (the surface of the SiO ₂ film 41) is He, for example, 1 μm. Is done.

  Next, the second semiconductor circuit layer 2 is fixed to the back surface of the first semiconductor circuit layer 1b as follows. Here, it is assumed that the second semiconductor circuit layer 2 has substantially the same configuration as that of the first semiconductor circuit layer 1 and is manufactured by the same method as that of the first semiconductor circuit layer 1. Are denoted by the same reference numerals as those of the first semiconductor circuit layer 1 and description thereof is omitted. Needless to say, the second semiconductor circuit layer 2 may be configured differently from the first semiconductor circuit layer 1 as necessary.

  As shown in FIGS. 27 (c) and 30 (a), a plurality of micro bump electrodes are formed on the surface (flattened) of the multilayer wiring structure 30 (that is, the insulating material 31) of the second semiconductor circuit layer 2. 43a is formed. These electrodes 43a are formed by the same method as the micro bump electrodes 42 of the first semiconductor circuit layer 1b in the first embodiment. Here, four electrodes 43a correspond to each of the conductive plugs 15 provided on the first semiconductor circuit layer 1b (Si wafer 11). In other words, four electrodes 43 a are bonded to one conductive plug 15.

  Further, when the conductive plug 15 and the electrode 43a are brought into pressure contact with each other, only the electrode 43a is selectively crushed (plastically deformed), so that the electrode 43a has a conductivity sufficiently lower than that of the conductive plug 15. It is formed from a functional material. For example, as in the first embodiment, when the electrode 42 is formed of tungsten (W), the electrode 43a is preferably formed of a laminate (In / Au) of indium (In) and gold (Au). Moreover, when the electrode 42 is formed of copper (Cu), the electrode 43a is preferably formed of a laminate (Sn / Ag) of tin (Sn) and silver (Ag).

  Next, as shown in FIGS. 27 (c) and 30 (a), a patterned electrically insulating adhesive is adhered to the surface of the multilayer wiring structure 30 (that is, the insulating material 31) of the second semiconductor circuit layer 2. The agent film 44a is formed by the same method as in the first embodiment. This adhesive film 44a is the same as that used in the first embodiment, and is composed of a number of adhesive elements 44aa (height Ha) formed in a bump shape (island shape). These adhesive elements 44aa are regularly distributed on the surface of the multilayer wiring structure 30. The adhesive film 44a has a shape that does not overlap any of the electrodes 43a, and is disposed except for the portion where the electrode 43a is formed and the vicinity thereof. Accordingly, the adhesive film 44a (that is, all the adhesive elements 44aa) does not overlap with the conductive plug 15 of the first semiconductor circuit layer 1b.

  As shown in FIG. 30A, the height of the adhesive element 44aa on the basis of the surface of the second semiconductor circuit layer 2 is Ha, and is set to 4 μm, for example.

  The total volume of the adhesive film 44a (the total volume after curing) is determined when the second semiconductor circuit layer 2 and the first semiconductor circuit layer 1b are connected using the conductive plug 15 and the electrode 43a. The entire gap formed between the layers 1b and 2 is filled with the adhesive film 44a, and the value is set so that the excess adhesive film 44a does not protrude from the gap. Since the adhesive film 44a does not exist in the vicinity of the conductive plug 15 and the electrode 43a and in the vicinity thereof, as shown in FIG. 30A, the height Ha of each adhesive element 44aa (this is the adhesive film 44a is equal to the height Hb of the electrode 43a (Ha> Hb), and each adhesive element is bonded to the second semiconductor circuit layer 2 and the first semiconductor circuit layer 1b. 44aa is crushed and spreads around the place where the conductive plug 15 and the electrode 43a are present, so that the entire gap formed between the circuit layers 1b and 2 can be easily filled.

  A typical example of the height Hb of the electrode 43a with respect to the surface of the second semiconductor circuit layer 2 is 2 μm, for example.

  The adhesive film 44a is divided into a large number of adhesive elements 44aa when the second semiconductor circuit layer 2 and the first semiconductor circuit layer 1b are bonded to each other between the circuit layers 2 and 1b. This is to facilitate the escape of air to the outside (that is, to facilitate degassing). That is, even when the circuit layers 2 and 1b are almost connected, the air existing between the layers 2 and 1b is pushed out through the gap between the adjacent adhesive elements 44aa. .

  Here, the adhesive film 44a is formed after the microbump electrode 43a is formed, but the microbump electrode 43a may be formed after the adhesive film 44a is formed.

  Subsequently, as shown in FIGS. 27A and 30A, the surface of the second semiconductor circuit layer 2 is opposed to the back surface of the first semiconductor circuit layer 1b fixed through the support substrate 40 from below. Let (Conversely, the second semiconductor circuit layer 2 may be fixed and the first semiconductor circuit layer 1b fixed to the support substrate 40 may be opposed from above.) Thereafter, the second semiconductor circuit layer 2 is pushed between the circuit layers 2 and 1b. When pressure is applied to bring the circuit layers 2 and 1b close to each other, the height of each adhesive element 44aa (the thickness of the adhesive film 44a) Ha is larger than the height Hb of the electrode 43a (Ha> Hb). And larger than the sum of the protruding height He of the conductive plug 15 and the height Hb of the electrode 43a (Ha> Hb + He), first, as shown in FIG. 30B, the second semiconductor circuit layer 2 is bonded. The tip (top) of the agent film 44a (adhesive element 44aa) is brought into contact with the back surface of the first semiconductor circuit layer 1b.

  Thereafter, a pressing force is applied between the circuit layers 2 and 1b to reduce the distance between the two, and as shown in FIGS. 28D and 31C, each electrode 43a of the second semiconductor circuit layer 2 is obtained. Is brought into contact with the electrode 42 of the corresponding first semiconductor circuit layer 1b. At this time, the distance between the back surface of the first semiconductor circuit layer 1b and the surface of the second semiconductor circuit layer 2, that is, the interlayer gap G1, is equal to the sum of the protruding height of the conductive plug 15 and the height of the electrode 43a, that is, G1 = He + Hb. At this time, the adhesive film 44a is crushed and deformed to be spread over almost the entire gap between the circuit layers 1b and 2, but the adhesive film 44a is divided into island-shaped adhesive elements 44aa. Therefore, the adhesive film 44a spreads almost uniformly in the gap. Further, since a gap 45 is easily formed between the back surface of the first semiconductor circuit layer 1b and the deformed adhesive film 44a (and between the adjacent adhesive elements 44aa), it remains in the gap. The air to be discharged can be surely discharged to the outside through the gap 45, and the risk of bubbles being generated in the finally integrated and cured adhesive film 44a can be eliminated.

  The step of making the conductive plug 15 and the electrode 43a contact each other after the first semiconductor circuit layer 1b and the second semiconductor circuit layer 2 are opposed to each other is performed at room temperature, as in the first embodiment. The value of the distance G1 between the first semiconductor circuit layer 1b and the second semiconductor circuit layer 2 is appropriately determined within a range of 2 μm to 10 μm, for example, and is typically 4 μm. However, the heights Hc and Hb of the electrodes 42 and 43a can be further reduced to 2 μm or less. In this case, the value of the distance G1 is appropriately determined within a range of 0.1 μm to 2 μm, for example. This is also the same as in the first embodiment.

  Thereafter, the electrodes 43a and 42 brought into contact with each other are connected to each other as follows.

  That is, the second semiconductor circuit layer 2 and the first semiconductor circuit layer 1b in the states of FIG. 28D and FIG. 30B are heated from room temperature to a predetermined temperature. The temperature is set to a temperature at which the surface (exposed surface) of the adhesive film 44a in a pressure-deformed state is slightly softened or the surface is slightly fluidized. The temperature varies depending on the type of adhesive used for the adhesive film 44a, but is arbitrarily set within a range of, for example, 100 to 400 ° C. in consideration of the temperature at which the conductive plug 15 and the electrode 43a are “press-contacted”. Is done. At this time, depending on the heating temperature to be set, the electrode 43a may be partially melted and the surface may be curved.

  Subsequently, by applying a pressing force, the second semiconductor circuit layer 2 is brought closer to the first semiconductor circuit layer 1b from below, or the first semiconductor circuit layer 1b is viewed from above with respect to the second semiconductor circuit layer 2. As shown in FIGS. 29 (e) and 31 (d), the gap between the circuit layers 1b and 2 is narrowed. In other words, the interlayer gap between the circuit layers 1b and 2 is set to G2 smaller than G1 (G2 <G1). At this time, a compressive force acts between the electrode 43a of the second semiconductor circuit layer 2 and the conductive plug 15 of the first semiconductor circuit layer 1b. As a result, only the electrode 43a having a mechanical strength lower than that of the conductive plug 15 is selectively crushed so that the conductive plug 15 and the electrode 43 are joined to each other by “pressure contact” and the adhesive element 44aa. Are further expanded and connected and integrated with each other. At this time, the four electrodes 43a corresponding to one conductive plug 15 are crushed and integrated, and as a result, the conductive plug 15 and the electrode 43a have a one-to-one correspondence. In this way, the entire gap between the circuit layers 2 and 1b is filled with the adhesive film 44a except for the electrode 43a and the conductive plug 15 that are in pressure contact with each other, and the extra adhesive film 44b1 or 44b2 is filled with the adhesive film 44a. It does not protrude from the gap. The state at this time is as shown in FIGS. 29 (e) and 31 (d).

  In this heating and pressure welding process, when the interlayer gap is reduced from G1 to G2, the air (atmosphere) existing in the gap between the circuit layers 1a and 2 is removed from the back surface of the first semiconductor circuit layer 1b and the adhesive film 44a. (All of which are softened or fluidized by heating) and the minute space remaining between the adjacent adhesive elements 44aa and reliably discharged to the outside. Can do. Further, since the surface of the adhesive film 44a is softened or fluidized, when the interlayer gap becomes G2, the back surface of the first semiconductor circuit layer 1b and the adhesive film 44a are easily bonded, and as a result, the circuit layer 1b. And 2 can be securely bonded to each other.

  When the electrode 43a is partially melted during heating, the conductive plug 15 and the electrode 43a are joined by “re-solidification” of the molten electrode 43a, or “pressure welding” and “re-solidification” are performed. It is done in a mixed form. This is the same as in the first embodiment.

  The value of the interlayer gap G2 is appropriately determined within a range of 1 μm to 9 μm, for example, but is typically 3 μm. However, the heights Hc and Hb of the electrodes 42 and 43a can be further reduced to 1 μm or less. In this case, the value of the distance G2 is appropriately determined in the range of 0.05 μm to 1 μm, for example.

  As described above, the second semiconductor circuit layer 2 is fixed (that is, mechanically connected) to the back surface side of the first semiconductor circuit layer 1b using the conductive plug 15 and the electrode 43a, and both the circuit layers 1b. And the electrical connection between the two. At the same time, both circuit layers 1b and 2 are mutually connected by an adhesive film 44a filled in the entire gap between the circuit layers 1b and 2 except for the conductive plug 15 and the electrode 43a connected to each other. Glued to.

  When the mechanical and electrical connection between the conductive plug 15 and the electrode 43a and the bonding of the adhesive film 44a are completed as described above, the circuit layers 1b and 2 bonded to each other are naturally cooled to room temperature. Therefore, the integrated adhesive film 44a is finally cured by heating, ultraviolet irradiation, chemical addition, or the like. Since treatment is easy, it is preferable to cure by heating. The heating temperature is appropriately set within a range of 120 to 500 ° C., for example, depending on the properties of the adhesive used as the adhesive film 44a. Thus, the mechanical connection and electrical connection between the two semiconductor circuit layers 1b and 2 are completed.

  Since the subsequent steps are the same as those in the first embodiment, the description thereof is omitted.

  As described above, in the method of manufacturing an integrated circuit device according to the fifth embodiment of the present invention, the conductive plug 15 (the electrode 42 is not used) is used to join the first semiconductor circuit layer 1b and the second semiconductor circuit layer 2. And the electrode 43a are the same as the method for manufacturing the integrated circuit device according to the first embodiment described above, and it is clear that the same effect as that obtained in the first embodiment can be obtained. It is. Further, in the fifth embodiment, since the process of forming the electrode 42 is unnecessary, there is an advantage that the process is a little simpler than in the first embodiment.

(Sixth embodiment)
FIG. 33 is a partial enlarged cross-sectional view showing a method for manufacturing an integrated circuit device having a three-dimensional laminated structure according to the sixth embodiment of the present invention. The sixth embodiment corresponds to Modification 1 of the first embodiment described above.

  In the first embodiment, as shown in FIG. 9A, the height of the island-shaped adhesive element 44aa (the thickness of the adhesive film 44a) Ha is set larger than the height Hb of the electrode 43a. (Ha> Hb) and larger than the sum of the height Hc of the electrode 42 and the height Hb of the electrode 43a (Ha> Hb + Hc). For this reason, in the connection process of the first semiconductor circuit layer 1a and the second semiconductor circuit layer 2, the adhesive film 44a is first brought into contact with the first semiconductor circuit layer 1a and deformed, and then the electrodes 42 and 43a are mutually connected. To touch. However, the present invention is not limited to such a relationship.

  In the method of manufacturing an integrated circuit device according to the sixth embodiment described here, as shown in FIG. 33A, the height of the island-shaped adhesive element 44aa (the thickness of the adhesive film 44a) Ha is the electrode. The point set larger than the height Hb of 43a (Ha> Hb) is the same as in the first embodiment, but is set smaller than the sum of the height Hc of the electrode 42 and the height Hb of the electrode 43a. (Ha <Hb + Hc) is different. For this reason, in the connecting step of the first semiconductor circuit layer 1a and the second semiconductor circuit layer 2, as shown in FIG. 33 (b), the electrodes 42 and 43a are first brought into contact with each other, and then the electrode 43a by pressurization is applied. With the deformation, the adhesive film 44a comes into contact with the first semiconductor circuit layer 1a and is deformed. The other points are the same as in the first embodiment.

  Therefore, it is obvious that the same effect as that of the first embodiment can be obtained in the method of manufacturing an integrated circuit device according to the sixth embodiment.

(Seventh embodiment)
FIG. 34 is a partial enlarged cross-sectional view showing a method for manufacturing an integrated circuit device having a three-dimensional laminated structure according to the seventh embodiment of the present invention. The seventh embodiment corresponds to Modification 2 of the first embodiment described above.

  In the method of manufacturing an integrated circuit device according to the seventh embodiment described here, as shown in FIG. 34A, the height of the island-like adhesive element 44aa (the thickness of the adhesive film 44a) Ha is the electrode. It differs from the said 1st Embodiment by the point set smaller than the height Hb of 43a (Ha <Hb). For this reason, in the connecting step of the first semiconductor circuit layer 1a and the second semiconductor circuit layer 2, as shown in FIG. 34 (b), the electrodes 42 and 43a are first brought into contact with each other, and thereafter, the electrode 43a by pressure is applied. With the deformation, the adhesive film 44a comes into contact with the first semiconductor circuit layer 1a and is deformed. Further, the deformation amount of the electrode 43a is larger than that in the sixth embodiment. The other points are the same as in the first embodiment.

  In the seventh embodiment, it is necessary to increase the amount of deformation of the electrode 43a in order to fill the gap between the first semiconductor circuit layer 1a and the second semiconductor circuit layer 2 with the adhesive film 44a. Therefore, it is preferable to configure the electrode 42 so as to be plastically deformed together with the electrode 43a.

  It is clear that the same effect as that of the first embodiment can be obtained in the method of manufacturing an integrated circuit device according to the seventh embodiment.

(Eighth embodiment)
FIG. 35 is a partial enlarged cross-sectional view showing a method of manufacturing an integrated circuit device having a three-dimensional laminated structure according to the eighth embodiment of the present invention. The eighth embodiment corresponds to Modification 3 of the first embodiment described above.

  In the method of manufacturing an integrated circuit device according to the eighth embodiment described here, as shown in FIG. 35A, the height of the island-shaped adhesive element 44aa (the thickness of the adhesive film 44a) Ha is the electrode. The point set to be larger than the height Hb of 43a (Ha> Hb) is the same as in the first embodiment, but is set substantially equal to the sum of the height Hc of the electrode 42 and the height Hb of the electrode 43a. (Ha≈Hb + Hc) is different. For this reason, in the connection process of the first semiconductor circuit layer 1a and the second semiconductor circuit layer 2, the adhesive film 44a contacts the back surface of the first semiconductor circuit layer 1a almost simultaneously with the electrodes 42 and 43a contacting each other. To do. The other points are the same as in the first embodiment.

  Therefore, it is obvious that the same effect as that of the first embodiment can be obtained in the method of manufacturing an integrated circuit device according to the eighth embodiment.

(Ninth embodiment)
FIG. 36 is a partial enlarged cross-sectional view showing a method of manufacturing an integrated circuit device having a three-dimensional stacked structure according to the ninth embodiment of the present invention. The ninth embodiment corresponds to Modification 1 of the second embodiment described above.

  In the second embodiment, as shown in FIG. 14A, the height (the thickness of the adhesive film 44b2) Ha of the island-shaped adhesive element 44bb2 is set larger than the height Hb of the electrode 43a. (Ha> Hb), the height (the thickness of the adhesive film 44b1) Hd of the island-shaped adhesive element 44bb1 is set to be larger than the height Hc of the electrode 42 (Hc <Hd). For this reason, in the connection process of the first semiconductor circuit layer 1a and the second semiconductor circuit layer 2, the adhesive films 44b1 and 44b2 are first brought into contact with each other and deformed, and then the electrodes 42 and 43a are brought into contact with each other. . However, the present invention is not limited to such a relationship.

  In the method of manufacturing an integrated circuit device according to the ninth embodiment described here, as shown in FIG. 36A, the height of the island-shaped adhesive element 44bb2 (the thickness of the adhesive film 44b2) Ha is the electrode. The point set to be larger than the height Hb of 43a (Ha> Hb) is the same as that of the second embodiment, but the height of the island-shaped adhesive element 44bb1 (the thickness of the adhesive film 44b1). Hd is set smaller than the height Hc of the electrode 42 (Hc> Hd), and the height of the adhesive element 44bb2 (the thickness of the adhesive film 44b2) Ha and the height of the adhesive element 44bb1 ( The difference is that the sum of the thickness Hd of the adhesive film 44b1) is set to be larger than the sum of the height Hc of the electrode 42 and the height Hb of the electrode 43a (Ha + Hd> Hb + Hc). For this reason, in the connection process of the first semiconductor circuit layer 1a and the second semiconductor circuit layer 2, the adhesive films 44b1 and 44b2 are first in contact with each other, and then the electrodes 42 and 43a are in contact with each other. The other points are the same as in the second embodiment.

  Therefore, it is apparent that the same effect as that of the second embodiment can be obtained in the method of manufacturing an integrated circuit device according to the ninth embodiment.

(10th Embodiment)
FIG. 37 is a partial enlarged cross-sectional view showing a method for manufacturing an integrated circuit device having a three-dimensional stacked structure according to the tenth embodiment of the present invention. The tenth embodiment corresponds to the second modification of the second embodiment described above.

  In the method of manufacturing an integrated circuit device according to the ninth embodiment described here, as shown in FIG. 37A, the height of the island-shaped adhesive element 44bb2 (the thickness of the adhesive film 44b2) Ha is the electrode. The point set to be larger than the height Hb of 43a (Ha> Hb) is the same as that of the second embodiment, but the height of the island-shaped adhesive element 44bb1 (the thickness of the adhesive film 44b1). Hd is set smaller than the height Hc of the electrode 42 (Hc> Hd), and the sum of the height Ha of the adhesive element 44bb2 and the height Hd of the adhesive element 44bb1 is the height of the electrode 42. The difference is that it is set smaller than the sum of Hc and the height Hb of the electrode 43a (Ha + Hd <Hb + Hc). For this reason, in the connection process of the first semiconductor circuit layer 1a and the second semiconductor circuit layer 2, the electrodes 42 and 43a first contact each other, and then the adhesive films 44b1 and 44b2 contact each other. The other points are the same as in the second embodiment.

  Therefore, it is apparent that the same effect as that of the second embodiment can be obtained in the method of manufacturing an integrated circuit device according to the tenth embodiment.

  In the tenth embodiment, it is necessary to increase the amount of deformation of the electrode 43a in order to fill the gap between the first semiconductor circuit layer 1a and the second semiconductor circuit layer 2 with the adhesive films 44b1 and 44b2. . Therefore, it is preferable to configure the electrode 42 so as to be plastically deformed together with the electrode 43a.

(Eleventh embodiment)
FIG. 38 is a partial enlarged cross-sectional view showing a method of manufacturing an integrated circuit device having a three-dimensional stacked structure according to the eleventh embodiment of the present invention. The eleventh embodiment corresponds to the third modification of the second embodiment described above.

  In the method of manufacturing an integrated circuit device according to the eleventh embodiment described here, as shown in FIG. 38A, the height of the island-shaped adhesive element 44bb2 (the thickness of the adhesive film 44b2) Ha is the electrode. 43a is set smaller than the height Hb (Ha <Hb), and the island-shaped adhesive element 44bb1 height (the thickness of the adhesive film 44b1) Hd is set smaller than the height Hc of the electrode 42. (Hc> Hd) is different from the second embodiment. For this reason, in the connection process of the first semiconductor circuit layer 1a and the second semiconductor circuit layer 2, the electrodes 42 and 43a first contact each other, and then the adhesive films 44b1 and 44b2 contact each other. The other points are the same as in the second embodiment.

  Therefore, it is obvious that the same effects as those of the second embodiment can be obtained in the method of manufacturing an integrated circuit device according to the eleventh embodiment.

(Twelfth embodiment)
FIG. 39 is a partial enlarged cross-sectional view showing a method of manufacturing an integrated circuit device having a three-dimensional stacked structure according to the twelfth embodiment of the present invention. The twelfth embodiment corresponds to Modification 4 of the second embodiment described above.

  In the method of manufacturing an integrated circuit device according to the twelfth embodiment described here, as shown in FIG. 39A, the height of the island-like adhesive element 44bb1 (the thickness of the adhesive film 44b1) Hd is The point set larger than the height Hc of 42 (Hc <Hd) is the same as in the second embodiment, but the height of the island-shaped adhesive element 44bb2 (the thickness of the adhesive film 44b2). Ha is set smaller than the height Hb of the electrode 43a (Ha <Hb), and the sum of the height Ha of the adhesive element 44bb2 and the height Hd of the adhesive element 44bb1 is equal to the height Hc of the electrode 42. The difference is that it is set larger than the sum of the heights Hb of the electrodes 43a (Ha + Hd> Hb + Hc). For this reason, in the connection process of the first semiconductor circuit layer 1a and the second semiconductor circuit layer 2, the adhesive films 44b1 and 44b2 are first in contact with each other, and then the electrodes 42 and 43a are in contact with each other. The other points are the same as in the second embodiment.

  Therefore, it is obvious that the same effects as those of the second embodiment can be obtained in the method of manufacturing an integrated circuit device according to the twelfth embodiment.

(13th Embodiment)
FIG. 40 is a partial enlarged cross-sectional view showing a method of manufacturing an integrated circuit device having a three-dimensional stacked structure according to the thirteenth embodiment of the present invention. The thirteenth embodiment corresponds to Modification 5 of the second embodiment described above.

  In the method of manufacturing an integrated circuit device according to the thirteenth embodiment described here, as shown in FIG. 40A, the height of the island-like adhesive element 44bb1 (the thickness of the adhesive film 44b1) Hd is The point set larger than the height Hc of 42 (Hc <Hd) is the same as in the second embodiment, but the height of the island-shaped adhesive element 44bb2 (the thickness of the adhesive film 44b2). Ha is set smaller than the height Hb of the electrode 43a (Ha <Hb), and the sum of the height Ha of the adhesive element 44bb2 and the height Hd of the adhesive element 44bb1 is the height of the electrode 42. The difference is that it is set smaller than the sum of Hc and the height Hb of the electrode 43a (Ha + Hd <Hb + Hc). For this reason, in the connection process of the first semiconductor circuit layer 1a and the second semiconductor circuit layer 2, the electrodes 42 and 43a first contact each other, and then the adhesive films 44b1 and 44b2 contact each other. The other points are the same as in the second embodiment.

  Therefore, it is apparent that the same effect as that of the second embodiment can be obtained in the method of manufacturing an integrated circuit device according to the thirteenth embodiment.

  In the thirteenth embodiment, it is necessary to increase the deformation amount of the electrode 43a so that the adhesive films 44b1 and 44b2 are filled in the gap between the first semiconductor circuit layer 1a and the second semiconductor circuit layer 2. . Therefore, it is preferable to configure the electrode 42 so as to be plastically deformed together with the electrode 43a.

(14th Embodiment)
FIG. 41 is a partial enlarged cross-sectional view showing a method of manufacturing an integrated circuit device having a three-dimensional stacked structure according to the fourteenth embodiment of the present invention. The fourteenth embodiment corresponds to Modification 6 of the second embodiment described above.

  In the method of manufacturing an integrated circuit device according to the fourteenth embodiment described here, as shown in FIG. 41A, the height of the island-shaped adhesive element 44bb1 (the thickness of the adhesive film 44b1) Hd is The point set larger than the height Hc of 42 (Hc <Hd) is the same as in the second embodiment, but the height of the island-shaped adhesive element 44bb2 (the thickness of the adhesive film 44b2). Ha is set smaller than the height Hb of the electrode 43a (Ha <Hb), and the sum of the height Ha of the adhesive element 44bb2 and the height Hd of the adhesive element 44bb1 is the height of the electrode 42. The difference is that it is set to be substantially equal to the sum of Hc and the height Hb of the electrode 43a (Ha + Hd≈Hb + Hc). For this reason, in the connecting step of the first semiconductor circuit layer 1a and the second semiconductor circuit layer 2, the adhesive films 44b1 and 44b2 are in contact with each other almost simultaneously with the electrodes 42 and 43a being in contact with each other. The other points are the same as in the second embodiment.

  Therefore, it is apparent that the same effects as those of the second embodiment can be obtained also in the integrated circuit device manufacturing method according to the fourteenth embodiment.

(Fifteenth embodiment)
FIG. 42 is a partial enlarged cross-sectional view showing the method of manufacturing the integrated circuit device having a three-dimensional stacked structure according to the fifteenth embodiment of the present invention. The fifteenth embodiment corresponds to the first modification of the third embodiment described above.

  In the third embodiment, as shown in FIG. 19A, the height of the island-shaped adhesive element 44bb2 (the thickness of the adhesive film 44b2) Ha is set to be larger than the height Hb of the electrode 43a. (Ha> Hb), the thickness Hd of the continuous adhesive film 44c is set smaller than the height Hc of the electrode 42 (Hc> Hd), and the height Ha of the adhesive element 44bb2 and the adhesive film The sum of the thickness Hd of 44c is set larger than the sum of the height Hb of the electrode 43a and the height HC of the electrode (Ha + Hd> Hb + Hc). For this reason, in the connection process of the first semiconductor circuit layer 1a and the second semiconductor circuit layer 2, the adhesive films 44c and 44b2 are first brought into contact with each other and deformed, and then the electrodes 42 and 43a are brought into contact with each other. . However, the present invention is not limited to such a relationship.

  In the method of manufacturing the integrated circuit device according to the fifteenth embodiment described here, as shown in FIG. 42A, the height of the adhesive element 44bb2 (the thickness of the adhesive film 44b2) Ha is the height of the electrode 43a. Is set to be larger than the height Hb (Ha> Hb), and the thickness Hd of the continuous adhesive film 44c is set to be smaller than the height Hc of the electrode 42 (Hc> Hd). Although the same as the embodiment, the sum of the height Ha of the adhesive element 44bb2 and the thickness Hd of the adhesive film 44c is set to be smaller than the sum of the height Hb of the electrode 43a and the height Hc of the electrode 42. (Ha + Hd <Hb + Hc). For this reason, in the connection process of the first semiconductor circuit layer 1a and the second semiconductor circuit layer 2, the electrodes 42 and 43a first contact each other, and then the adhesive films 44b1 and 44b2 contact each other. The other points are the same as in the third embodiment.

  Therefore, it is apparent that the same effects as those of the third embodiment can be obtained also in the integrated circuit device manufacturing method according to the fifteenth embodiment.

  The fifteenth embodiment corresponds to the first modification of the fourth embodiment described above.

  In the fifteenth embodiment, it is necessary to increase the amount of deformation of the electrode 43a in order to fill the gap between the first semiconductor circuit layer 1a and the second semiconductor circuit layer 2 with the adhesive films 44c and 44b2. . Therefore, it is preferable to configure the electrode 42 so as to be plastically deformed together with the electrode 43a.

(Sixteenth embodiment)
FIG. 43 is a partial enlarged cross-sectional view showing a method of manufacturing an integrated circuit device having a three-dimensional laminated structure according to the sixteenth embodiment of the present invention. The sixteenth embodiment corresponds to the second modification of the third embodiment described above.

  In the method of manufacturing an integrated circuit device according to the sixteenth embodiment described here, as shown in FIG. 43A, the height of the adhesive element 44bb2 (the thickness of the adhesive film 44b2) Ha is the height of the electrode 43a. The point set to be larger than the height Hb (Ha> Hb) is the same as in the third embodiment, but the thickness Hd of the continuous adhesive film 44c is larger than the height Hc of the electrode 42. The set point (Hc <Hd) is different. For this reason, in the connection process of the first semiconductor circuit layer 1a and the second semiconductor circuit layer 2, the adhesive films 44b1 and 44b2 are first in contact with each other, and then the electrodes 42 and 43a are in contact with each other. The other points are the same as in the third embodiment.

  Therefore, it is apparent that the same effects as those of the third embodiment can be obtained also in the integrated circuit device manufacturing method according to the sixteenth embodiment.

  The sixteenth embodiment corresponds to the second modification of the fourth embodiment described above.

(17th Embodiment)
FIG. 44 is a partial enlarged cross-sectional view showing a method of manufacturing an integrated circuit device having a three-dimensional laminated structure according to the seventeenth embodiment of the present invention. The seventeenth embodiment corresponds to the third modification of the third embodiment described above.

  In the integrated circuit device manufacturing method according to the seventeenth embodiment described here, the thickness Hd of the continuous adhesive film 44c is set smaller than the height Hc of the electrode 42, as shown in FIG. (Hc> Hd) is the same as in the third embodiment, but the height of the adhesive element 44bb2 (the thickness of the adhesive film 44b2) Ha is smaller than the height Hb of the electrode 43a. The set point (Ha <Hb) is different. For this reason, in the connection process of the first semiconductor circuit layer 1a and the second semiconductor circuit layer 2, the electrodes 42 and 43a first contact each other, and then the adhesive films 44b1 and 44b2 contact each other. The other points are the same as in the third embodiment.

  Therefore, it is apparent that the same effect as that of the third embodiment can be obtained in the method of manufacturing an integrated circuit device according to the seventeenth embodiment.

  The seventeenth embodiment also corresponds to the third modification of the fourth embodiment described above.

  In the seventeenth embodiment, it is necessary to increase the deformation amount of the electrode 43a so that the adhesive films 44c and 44b2 are filled in the gap between the first semiconductor circuit layer 1a and the second semiconductor circuit layer 2. . Therefore, it is preferable to configure the electrode 42 so as to be plastically deformed together with the electrode 43a.

(Eighteenth embodiment)
FIG. 45 is a partial enlarged cross-sectional view showing a method of manufacturing an integrated circuit device having a three-dimensional laminated structure according to the eighteenth embodiment of the present invention. The eighteenth embodiment corresponds to Modification 4 of the third embodiment described above.

  In the integrated circuit device manufacturing method according to the eighteenth embodiment described here, the thickness Hd of the continuous adhesive film 44c is set smaller than the height Hc of the electrode 42, as shown in FIG. (Hc> Hd) is the same as in the third embodiment, but the height of the adhesive element 44bb2 (the thickness of the adhesive film 44b2) Ha is larger than the height Hb of the electrode 43a. Is set (Ha> Hb), and the sum of the height Ha of the adhesive film 44b2 and the thickness Hd of the adhesive film 44c is substantially equal to the sum of the height Hb of the electrode 43a and the height Hc of the electrode 43a. The difference is that they are set the same. For this reason, in the connecting step of the first semiconductor circuit layer 1a and the second semiconductor circuit layer 2, the adhesive films 44b1 and 44b2 are in contact with each other almost simultaneously with the electrodes 42 and 43a being in contact with each other. The other points are the same as in the third embodiment.

  Therefore, it is apparent that the same effect as that of the third embodiment can be obtained in the method of manufacturing an integrated circuit device according to the eighteenth embodiment.

  The eighteenth embodiment also corresponds to the fourth modification of the fourth embodiment described above.

(Nineteenth embodiment)
FIG. 46 is a partially enlarged cross-sectional view showing the method of manufacturing the integrated circuit device having a three-dimensional stacked structure according to the nineteenth embodiment of the present invention. The nineteenth embodiment corresponds to Modification 1 of the fifth embodiment described above.

  In the fifth embodiment, as shown in FIG. 30A, the height of the island-shaped adhesive element 44a (the thickness of the adhesive film 44a) Ha is set larger than the height Hb of the electrode 43a. (Ha> Hb), and the thickness Ha of the adhesive film 44a is set to be larger than the sum of the protruding height He of the conductive bump 15 and the height Hb of the electrode 43a (Ha> Hb + He). For this reason, in the connecting step of the first semiconductor circuit layer 1a and the second semiconductor circuit layer 2, the adhesive film 44a is first deformed by contacting the back surface of the first semiconductor circuit layer 1b, and then the conductive bump 15 And the electrode 43a are in contact with each other. However, the present invention is not limited to such a relationship.

  In the method of manufacturing an integrated circuit device according to the nineteenth embodiment described here, as shown in FIG. 46A, the height of the island-like adhesive element 44a (the thickness of the adhesive film 44a) Ha is the electrode. The point set to be larger than the height Hb of 43a (Ha> Hb) is the same as that of the fifth embodiment, but from the sum of the protruding height He of the conductive bump 15 and the height Hb of the electrode 43a. Is different (Ha <Hb + He). For this reason, in the connection process of the first semiconductor circuit layer 1a and the second semiconductor circuit layer 2, first, the conductive bump 15 and the electrode 43a are in contact with each other, and then the adhesive film 44a is the back surface of the first semiconductor circuit layer 1b. To touch. The other points are the same as in the fifth embodiment.

  Therefore, it is apparent that the same effect as that of the fifth embodiment can be obtained also in the manufacturing method of the integrated circuit device according to the nineteenth embodiment.

  In the nineteenth embodiment, it is necessary to increase the deformation amount of the electrode 43a in order to fill the gap between the first semiconductor circuit layer 1a and the second semiconductor circuit layer 2 with the adhesive film 44a. It has its limits. Therefore, the difference (Ha−Hb−He) between the thickness Ha of the adhesive film 44a and the sum of the protruding height He of the conductive bump 15 and the height Hb of the electrode 43a should not be so large. preferable.

(20th embodiment)
FIG. 47 is a partially enlarged cross-sectional view showing the method of manufacturing the integrated circuit device having a three-dimensional stacked structure according to the twentieth embodiment of the present invention. The twentieth embodiment corresponds to the second modification of the fifth embodiment described above.

  In the method of manufacturing an integrated circuit device according to the twentieth embodiment described here, as shown in FIG. 47A, the height of the island-shaped adhesive element 44a (the thickness of the adhesive film 44a) Ha is the electrode. The point which is set smaller than the height Hb of 43a (Ha <Hb) is different from the fifth embodiment. For this reason, in the connection process of the first semiconductor circuit layer 1a and the second semiconductor circuit layer 2, first, the conductive bump 15 and the electrode 43a are in contact with each other, and then the adhesive film 44a is the back surface of the first semiconductor circuit layer 1b. To touch. The other points are the same as in the fifth embodiment.

  Therefore, it is apparent that the same effect as that of the fifth embodiment can be obtained in the method of manufacturing an integrated circuit device according to the twentieth embodiment.

  In the twentieth embodiment, it is necessary to increase the deformation amount of the electrode 43a in order to fill the gap between the first semiconductor circuit layer 1a and the second semiconductor circuit layer 2 with the adhesive film 44a. It has its limits. Therefore, the difference (Ha−Hb−He) between the thickness Ha of the adhesive film 44a and the sum of the protruding height He of the conductive bump 15 and the height Hb of the electrode 43a should not be so large. preferable.

(21st Embodiment)
FIG. 48 is a partial enlarged cross-sectional view showing the method of manufacturing the integrated circuit device having a three-dimensional stacked structure according to the twenty-first embodiment of the present invention. The twentieth embodiment corresponds to the third modification of the fifth embodiment described above.

  In the method of manufacturing an integrated circuit device according to the twenty-first embodiment described here, as shown in FIG. 48A, the height of the island-like adhesive element 44a (the thickness of the adhesive film 44a) Ha is the electrode. The point set to be larger than the height Hb of 43a (Ha> Hb) is the same as in the fifth embodiment, but the sum of the protruding height He of the conductive bump 15 and the height Hb of the electrode 43a is The points that are set substantially the same (Ha≈Hb + He) are different. For this reason, in the connection process of the first semiconductor circuit layer 1a and the second semiconductor circuit layer 2, the adhesive film 44a is formed on the first semiconductor circuit layer 1b almost simultaneously with the contact between the conductive bump 15 and the electrode 43a. Touch the back of the. The other points are the same as in the fifth embodiment.

  Therefore, it is obvious that the same effect as that of the fifth embodiment can be obtained in the method of manufacturing an integrated circuit device according to the twenty-first embodiment.

  In the twenty-first embodiment, it is necessary to increase the deformation amount of the electrode 43a in order to fill the gap between the first semiconductor circuit layer 1a and the second semiconductor circuit layer 2 with the adhesive film 44a.

(Twenty-second embodiment)
FIG. 49 is a view similar to FIG. 32B, showing an electrode layout and an adhesive film pattern used in the method of manufacturing an integrated circuit device having a three-dimensional stacked structure according to the twenty-second embodiment of the present invention. It is.

  49. Four electrodes 43a (provided on the surface of the second semiconductor circuit layer 2) respectively disposed at the four vertices of the rectangle shown in FIG. 49 form a set, and are shown in FIG. 32 (a). Similarly to the above, one electrode 42 or the protruding portion of the conductive bump 15 (provided on the back surface of the first semiconductor circuit layer 1a or 1b) is connected on a one-to-one basis.

  In FIG. 32 (b), the adhesive film 44a is divided into a number of regularly arranged island-like adhesive elements 44aa, and surrounds each set of electrodes 43a. On the other hand, the adhesive film 44d shown in FIG. 49 is continuously formed in the X direction and the Y direction. That is, the adhesive film 44d has a lattice pattern, and includes a plurality of strips extending in the X direction and a plurality of strips extending in the Y direction orthogonal to them. The adhesive film 44d corresponds to the above-described adhesive films 44c, 44c1, and 44c2.

  In the manufacturing method of the twenty-second embodiment, since the lattice-like adhesive film 44d shown in FIG. 49 is used, there is no gas escape route in a plane (that is, in a plane including the adhesive film 44d). However, the gas existing in the gaps (around each set of electrodes 43a) between the first semiconductor circuit layer 1a and the second semiconductor circuit layer 2 passes through the gaps 45 (FIG. 6 (k)) formed between them. See) can be discharged to the outside.

(23rd Embodiment)
FIG. 50 is a view similar to FIG. 32B, showing an electrode layout and an adhesive film pattern used in the method of manufacturing an integrated circuit device having a three-dimensional stacked structure according to the twenty-third embodiment of the present invention. It is.

  The layout of the electrode 43a shown in FIG. 50 is the same as that of the electrode 43a in FIG. The adhesive film 44e shown in FIG. 50 is formed continuously only in the X direction. The adhesive film 44e has a striped pattern and is composed of a plurality of strips extending in the X direction. Between adjacent strips, there are gaps 51 that serve as degassing passages.

  In the manufacturing method of the twenty-third embodiment, since the lattice-like adhesive film 44e shown in FIG. 50 is used, the gaps between the first semiconductor circuit layer 1a and the second semiconductor circuit layer 2 (each set of the electrodes 43a). The gas existing in the vicinity of the gas is discharged to the outside through the gap 45 (see FIG. 6 (k)) formed between them and the gap 51 of the adhesive film 44e. For this reason, there exists an advantage which is easy to discharge | emit gas compared with 22nd Embodiment.

(24th Embodiment)
FIG. 51 is a view similar to FIG. 32B, showing an electrode layout and an adhesive film pattern used in the method of manufacturing an integrated circuit device having a three-dimensional stacked structure according to the twenty-fourth embodiment of the present invention. It is.

  The layout of the electrode 43a shown in FIG. 51 is the same as that of the electrode 43a in FIG. The adhesive film 44f shown in FIG. 51 is the same as the adhesive film 44d shown in FIG. 49 except that a plurality of slits 52 are formed in a belt-like portion extending in the Y direction.

  In the manufacturing method of the twenty-fourth embodiment, since the lattice-like adhesive film 44f shown in FIG. 51 is used, the gap between the first semiconductor circuit layer 1a and the second semiconductor circuit layer 2 (each set of the electrodes 43a). The gas existing in the vicinity of the gas is discharged to the outside through the gap 45 formed between them, the gap 51 of the adhesive film 44f, and the slit 52. For this reason, there exists an advantage which is easy to discharge | emit gas compared with 22nd Embodiment.

(25th Embodiment)
FIG. 52 is a view similar to FIG. 32B, showing an electrode layout and an adhesive film pattern used in the method of manufacturing an integrated circuit device having a three-dimensional stacked structure according to the twenty-fifth embodiment of the present invention. It is.

  The layout of the electrode 43a shown in FIG. 52 is the same as that of the electrode 43a in FIG. The adhesive film 44g shown in FIG. 52 is similar to the adhesive film shown in FIG. 49 except that a plurality of slits 52 and 53 are formed in the belt-like portion extending in the Y direction and the belt-like portion extending in the X direction. It is the same as the agent film 44d.

  In the manufacturing method of the twenty-fifth embodiment, since the lattice-like adhesive film 44g shown in FIG. 52 is used, the gaps between the first semiconductor circuit layer 1a and the second semiconductor circuit layer 2 (each set of the electrodes 43a). The gas existing in the periphery) is discharged to the outside through the gap 45 formed therebetween, the gap 51 of the adhesive film 44f, and the slits 52 and 53. For this reason, there exists an advantage which gas is easy to be discharged | emitted compared with 22nd Embodiment and 23rd Embodiment.

(Modification)
The first to 25th embodiments described above show examples embodying the present invention. Therefore, the present invention is not limited to these embodiments, and various modifications can be made without departing from the spirit of the present invention. It goes without saying that is possible. For example, in the first to 25th embodiments described above, the microbump electrodes of the adjacent semiconductor circuit layers (or the conductive plug and the microbump electrode) are joined together by “heating pressure welding”. It is not limited. Depending on the material of the micro-bump electrode and the conductive plug, pressure welding at room temperature, that is, “room temperature pressure welding” is possible. Needless to say, “room temperature pressure welding” may be used in such cases. Alternatively, the microbump electrodes (or the conductive plug and the microbump electrode) may be bonded to each other with an appropriate bonding metal (for example, a solder alloy) interposed therebetween.

  In the first to 25th embodiments described above, the case where the first semiconductor circuit layer is mainly fixed to the support substrate has been described, but the present invention is not limited to this. For example, when the present invention is applied to the second semiconductor circuit layer, the second semiconductor circuit layer is fixed to the first semiconductor circuit layer adjacent thereto.

  Furthermore, in the first to 25th embodiments described above, the case where each of the semiconductor circuit layers is formed by a single semiconductor wafer is described, but the present invention is not limited to these. For example, each of the semiconductor circuit layers may be formed by a plurality of semiconductor chips. Further, at least one semiconductor circuit layer may be formed by a single semiconductor wafer, and each of the remaining semiconductor circuit layers may be formed by a plurality of semiconductor chips. When a certain semiconductor circuit layer is formed of a plurality of semiconductor chips, all of the semiconductor chips do not have to incorporate an electronic circuit. That is, some semiconductor chips may be “dummy chips” that do not contain electronic circuits (or that contain electronic circuits but are not used). When a semiconductor circuit layer is formed of a single semiconductor wafer, the semiconductor wafer includes a “dummy region” that does not contain an electronic circuit (or that contains an electronic circuit but is not used). You may go out.

DESCRIPTION OF SYMBOLS 1 1st semiconductor circuit layer 1a, 1b Thinned first semiconductor circuit layer 2 Second semiconductor circuit layer 2a Thinned second semiconductor circuit layer 11 Semiconductor substrate 12 Silicon oxide (SiO ₂ ) film 12a Silicon nitride (Si ₃ N ₄ ) Film 12b Gate insulating film 13 Trench 14 Silicon oxide (SiO ₂ ) film 15 Conductive plug 15a End of conductive plug 16 Source / drain region 17 Photoresist film 18 Gate electrode 19 Interlayer insulating film 20 Metal wiring film 21 Conductive Conductive material 30 Multi-layer wiring structure 31 Insulating material 32, 33, 34 Wiring layer 35, 36 Conductor 37 Micro bump electrode 38 Conductor 39 Adhesive 40 Support substrate 41 Silicon oxide (SiO ₂ ) film 42, 43a Micro bump electrode 44a, 44b1, 44b2, 44c, 44c1, 44c2 Adhesive film 44b1b2, 44b2c, 44c1c2 Integrated adhesive film 44d, 44e, 44f, 44g Adhesive film 45 Degassing passage 51 formed between the first semiconductor circuit layer and the second semiconductor circuit layer 51 Degassing gap 52 53 Degassing slit

Claims (4)

An integrated circuit device having a three-dimensional stacked structure in which a plurality of semiconductor circuit layers are stacked on a support substrate,
One semiconductor circuit layer constituting the three-dimensional stacked structure has a plurality of embedded wirings, one end of which is exposed from the back surface of the semiconductor circuit layer,
The other semiconductor circuit layer constituting the three-dimensional laminated structure has a plurality of bump electrodes arranged on the surface thereof,
By connecting the bump electrode corresponding to the exposed end of the conductive material forming the embedded wiring either directly or via another conductive member, the back surface of the semiconductor circuit layer and the other semiconductor The surface of the circuit layer is electrically and mechanically interconnected,
Between the back surface of the semiconductor circuit layer and the surface of the other semiconductor circuit layer, an exposed end of the interconnected conductive material and a gap existing around the bump electrode are made of an electrically insulating adhesive. In addition to being filled, the back surface of the semiconductor circuit layer and the surface of the other semiconductor circuit layer are mutually bonded with the adhesive,
Wherein for the each of the exposed end of the conductive material, have a plurality of the bump electrodes corresponding with low mechanical strength than the electrically conductive material, wherein in a state in which crushed a plurality of the bump electrodes An integrated circuit device, wherein the integrated circuit device is bonded directly to each exposed end of the conductive material or via another conductive member. 2. The integrated circuit device according to claim 1, wherein the plurality of crushed bump electrodes are directly bonded to the exposed end of the conductive material forming the embedded wiring. Crushed plurality of the bump electrode was found other via the conductive member, the integrated circuit device according to claim 1 which is bonded to the exposed end of the conductive material forming the embedded wiring. The exposed end of the conductive material forming the embedded wiring is formed to protrude from the back surface of the semiconductor circuit layer;
The integrated circuit device according to claim 1, wherein the plurality of crushed bump electrodes are directly bonded to the exposed end.

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