KR20110079319A - Semiconductor device package and method for manufacturing the same - Google Patents

Semiconductor device package and method for manufacturing the same Download PDF

Info

Publication number
KR20110079319A
KR20110079319A KR1020090136337A KR20090136337A KR20110079319A KR 20110079319 A KR20110079319 A KR 20110079319A KR 1020090136337 A KR1020090136337 A KR 1020090136337A KR 20090136337 A KR20090136337 A KR 20090136337A KR 20110079319 A KR20110079319 A KR 20110079319A
Authority
KR
South Korea
Prior art keywords
pad
contact
layer
metal layer
forming
Prior art date
Application number
KR1020090136337A
Other languages
Korean (ko)
Inventor
고호순
Original Assignee
주식회사 동부하이텍
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 동부하이텍 filed Critical 주식회사 동부하이텍
Priority to KR1020090136337A priority Critical patent/KR20110079319A/en
Publication of KR20110079319A publication Critical patent/KR20110079319A/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H01L2021/60007—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation involving a soldering or an alloying process

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Geometry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE: A semiconductor device package and a manufacturing method thereof are provided to stably keep a connection to an outer electrode and a pad without a restriction of a design rule according to increase of thickness of a wiring or an additional process. CONSTITUTION: A substrate(100) includes a plurality of metal layers(M1,M2,M3) and a protective layer(100). Interlayer insulating layers(V1,V2,V3) are formed between the metal layers. The substrate forms a device area(250), a pad area(350) and a wiring area(450). Devices(200) are formed in the device area. A CSP pad is formed in the pad area. The wiring area connects the device area to the pad area. The devices are connected to the metal layers via a via. Pad contac layers(352,354,356) are formed between the CSP layers.

Description

Semiconductor device package and its manufacturing method {SEMICONDUCTOR DEVICE PACKAGE AND METHOD FOR MANUFACTURING THE SAME}

Embodiments relate to a semiconductor device package and a method of manufacturing the same.

Chip scale packages (hereinafter referred to as CSPs) are widely used in general electric devices and optoelectronic devices due to low packaging costs and compact package dimensions. In particular, the packaging process is very effective in that the packaging process is performed as part of the manufacturing process of the image sensor chip such as CMOS and CCD, it is a very high packaging method for the image sensor.

Some of the CSP methods use a technique of forming a pad connected to the chip on the outside of the chip, and connecting the side of the pad and the electrode of the package. As such, when the side of the pad is used, the contact resistance should be reduced by implementing the thickness of the entire metal to a certain level, for example, 1 μm or more, for stable connection.

However, in the case of a thin designed product having a small number of metal layers, it is necessary to use a wiring thickness more than necessary to increase the total metal thickness, so that the chip size increases and constraints occur in design rules and processes. There is this.

The embodiment provides a semiconductor device package and a method of manufacturing the same, which can stably maintain a connection between a pad and an external electrode, without restricting a design rule or an additional process according to an increase in wiring thickness.

A semiconductor device package according to an embodiment may include a pad metal layer in side contact with an external wiring; An interlayer insulating layer in contact with the pad metal layer; The pad contact layer is formed to contact the metal layer in the interlayer insulating layer and is in side contact with the external wiring.

A method of manufacturing a semiconductor device package according to an embodiment includes forming a pad metal layer on a substrate; Forming a pad contact layer in the substrate in contact with the pad metal layer; Exposing side surfaces of the pad metal layer and the pad contact layer; Forming an external line on side surfaces of the exposed pad metal layer and the pad contact layer.

According to the embodiment, it is possible to provide a semiconductor device package and a method of manufacturing the same, which can stably maintain a connection between a pad and an external electrode, without restricting design rules or additional processes due to an increase in wiring thickness.

Hereinafter, a semiconductor device package and a method of manufacturing the same according to an embodiment will be described in detail with reference to the accompanying drawings. In the description of an embodiment, each layer (film), region, pattern, or structure is formed “on” or “under” a substrate, each layer (film), region, pad, or pattern. In the case where it is described as "to", "on" and "under" include both "directly" or "indirectly" formed. Also, the criteria for top, bottom, or bottom of each layer will be described with reference to the drawings. In the drawings, the thickness or size of each layer is exaggerated, omitted, or schematically illustrated for convenience and clarity of description. In addition, the size of each component does not necessarily reflect the actual size.

1 is an enlarged view illustrating main parts of a semiconductor device package.

In the semiconductor device package, after forming the device 200 and the CSP pad 300 on the substrate 100, the glass substrate 10 is attached, and the lead 400 is formed on each package. It can be formed by cutting per package according to).

The substrate 100 may be formed using a silicon wafer or the like, and a multilayer substrate may be applied.

The glass substrate 10 may be fixed on the cavity wall 120 formed in the substrate 100.

In the substrate 100, a device 200 such as an image sensor and the CSP pad 300 may be formed. The device 200 and the CSP pad 300 may be electrically connected to each other through wirings formed on the substrate 100.

Lead 400 is formed along the side of the substrate 100 of each package. The lead 400 is connected to the side surface of the CSP pad 300 formed on the substrate 100, and the solder 400 may be formed with solder bumps or solder balls 318 for connection with an external circuit.

Accordingly, the device 200 is electrically connected to the CSP pad 300, and the CSP pad 300 is connected to the solder bumps or the solder balls 420 of the package through the lead 400. Therefore, the device 200 on the substrate 100 may be connected to an external circuit through the CSP pad 300 and the lead 400.

2 to 4 are process flowcharts of the semiconductor device package according to the first embodiment, and show an enlarged view of a connection area between the CSP pad 300 and the lead 400.

As shown in FIG. 2, the substrate 100 includes a plurality of metal layers M1, M2, and M3 and a passivation layer 110, and an interlayer between the metal layers M1, M2, and M3. Insulation layers V1, V2, and V3 are formed.

The substrate 100 includes a device region 250 in which the device 200 is formed, a pad region 350 in which the CSP pad 300 is formed, and a wiring region interconnecting the device region 250 and the pad region 350. 450 may be formed.

A device 200, such as an image sensor chip, may be formed in the device region 250, and the device 200 may be connected to the metal layers M1, M2, and M3 through vias.

CSP pad layers 310, 320, and 330 are formed in the pad region 350, and pad contact layers 352, 354, and 356 are formed between the CSP pad layers 310, 320, and 330. The pad contact layers 352, 354, and 356 form box-type vias close to those of the CSP pad layers 310, 320, and 330, and then form Al, W, Cu, etc. in the box-type vias to perform a plug process. It can form by doing.

 In the wiring area 450, wirings connecting the internal wirings of the device 200 and the CSP pad layers 310, 320, and 330 are formed. The metal layers M1, M2, and M3 of the device region 250 connected to the wiring region 450 may be internal wirings or bonding pads.

Thereafter, as shown in FIG. 3, sawing is performed to expose the side surface of the pad region 350. Accordingly, the CSP pad layers 310, 320, 330 and the pad contact layers 352, 354, and 356 are exposed.

Next, as shown in FIG. 4, the lead 400 is formed on the outer surface of the substrate 100, and the solder ball 318 for connecting to an external circuit is formed on the lead 400. The lead 400 may be formed by depositing a metal and then patterning the metal.

The pad region of the semiconductor device package formed according to this process is shown in FIG. 5.

As shown in FIG. 5, the sidewalls of the CSP pad layers 310, 320, and 330 formed in the pad region 350 are not only in contact with the leads 400, but also formed between the CSP pad layers 310, 320, and 330. Sidewalls of the pad contact layers 352, 354, and 356 are also in contact with the leads 400.

That is, not only the metal layers M1, M2, and M3 for implementing the CSP pad 300, but also the pad contact layers 352, 354, and 356 formed on the IMD or the ILD may be used as the CSP pads. Accordingly, the yield and reliability of the package may be improved by increasing the contact surface of the CSP pad in contact with the lead 400.

6 illustrates an enlarged pad region of a semiconductor device package according to another embodiment, and illustrates a case where the pad region of the semiconductor device package is implemented in the substrate 100 having the single metal layer M1.

When the single metal layer M1 has a single metal layer M1, the CSP pad 300 is formed on the metal layer M1, and a pad contact layer 352 connected to the CSP pad 300 is formed on the interlayer insulating layer. Thus, since the CSP pad 300 and the pad contact layer 352 are in contact with the lead 400 together, the stability of the connection may be improved. In addition, since both the CSP pad 300 and the pad contact layer 352 are in contact with the lead 400, the minimum thickness of the CSP pad required in the package may be easily satisfied.

FIG. 7 is a top perspective view schematically illustrating a connection area between a chip and a CSP pad of the semiconductor device package according to the first embodiment.

A bonding pad 202 and a sealing 600 are formed inside the device 200, and the CSP pad 300 is formed outside the device 200.

The bonding pads 202 and the CSP pads 300 are interconnected through the wiring 450 passing through the sealing 600 region. Here, the sealing 600 and the wiring 450 are electrically separated, and the sealing 600 is formed using silicon, poly-silicon, via, metal, or the like. can do.

The CSP pad 300 is connected to the wiring 450 connected to the bonding pad 202 and to the lead 400 of the package. The CSP pad 300 may include a pad contact layer 352 in the form of a wide box to expand the contact area with the lid 400. The pad contact layer 352 having a wide box shape is formed by forming a box-shaped via close to the size of the CSP pad 300 and performing a plug process of forming Al, W, Cu, etc. in the via. can do. Accordingly, the side surfaces of the CSP pad 300 layer and the pad contact layer 352 are in contact with the lead 400 together, thereby improving the contact resistance and the stability of the package process.

FIG. 8 is a top perspective view schematically illustrating a connection area between a chip and a CSP pad of the semiconductor device package according to the second embodiment.

A bonding pad 202 and a sealing 600 are formed inside the device 200, and the CSP pad 300 is formed outside the device 200.

The bonding pads 202 and the CSP pads 300 are interconnected through the wiring 450 passing through the sealing 600 region. Here, the sealing 600 and the wiring 450 are electrically separated, and the sealing 600 is formed using silicon, poly-silicon, via, metal, or the like. can do.

The CSP pad 300 is connected to the wiring 450 connected to the bonding pad 202 and to the lead 400 of the package. The CSP pad 300 may include a pad contact layer 352 in the form of a line array to extend the contact area with the leads 400. The pad contact layer 352 of the line array type may be formed by forming a line array type via in the region of the CSP pad 300 and performing a plug process of forming Al, W, Cu, etc. in the via. As such, in the case of forming vias or contacts in the form of a line array, planarization problems that may occur during the plug process may be solved. In addition, side surfaces of the CSP pad layer 300 and the pad contact layer 352 may contact the lead 400 together, thereby improving contact resistance and stability of the package process.

In the above description, the case of applying the present embodiment in the CSP process is illustrated, but the present invention can be applied to both the package method for connecting the side of the chip pad and the wiring.

Features, structures, effects, and the like described in the above embodiments are included in at least one embodiment of the present invention, and are not necessarily limited to only one embodiment. Furthermore, the features, structures, effects, and the like illustrated in the embodiments may be combined or modified with respect to other embodiments by those skilled in the art to which the embodiments belong. Therefore, it should be understood that the present invention is not limited to these combinations and modifications.

In addition, the above description has been made with reference to the embodiment, which is merely an example, and is not intended to limit the present invention. Those skilled in the art to which the present invention pertains will be illustrated as above without departing from the essential characteristics of the present embodiment. It will be appreciated that various modifications and applications are possible. For example, each component specifically shown in the embodiment can be modified. And differences relating to such modifications and applications will have to be construed as being included in the scope of the invention defined in the appended claims.

1 is an enlarged view illustrating main parts of a semiconductor device package;

2 to 4 are process progress diagrams of the semiconductor device package according to the first embodiment.

5 is an enlarged view illustrating main parts of a semiconductor device package according to a first embodiment;

6 is an enlarged view illustrating main parts of a semiconductor device package according to a second embodiment;

FIG. 7 is a top perspective view schematically illustrating a connection area between a chip and a CSP pad of the semiconductor device package according to the first embodiment; FIG.

FIG. 8 is a top perspective view schematically illustrating a connection area between a chip and a CSP pad of the semiconductor device package according to the second embodiment; FIG.

Claims (9)

A pad metal layer in side contact with the external wiring; An interlayer insulating layer in contact with the pad metal layer; And a pad contact layer formed to contact the metal layer in the interlayer insulating layer and in side contact with the external wiring. The method of claim 1, The pad contact layer, And a via or contact in contact with the pad metal layer and the external wiring. The method of claim 1, The pad contact layer, And a box-shaped via or contact formed to a size similar to that of the pad metal layer. The method of claim 1, The pad contact layer, And a via or contact in the form of a line array formed in an area of the pad metal layer. Forming a pad metal layer on the substrate; Forming a pad contact layer in the substrate in contact with the pad metal layer; Exposing side surfaces of the pad metal layer and the pad contact layer; Forming an external wiring on side surfaces of the exposed pad metal layer and the pad contact layer. The method of claim 5, Forming a pad contact layer in the substrate in contact with the pad metal layer; Forming vias or contacts in the substrate in contact with the pad metal layer. The method of claim 5, Forming a pad contact layer in the substrate in contact with the pad metal layer; Forming a box-shaped via hole having a size similar to that of the pad metal layer; A method of manufacturing a semiconductor device package comprising forming a plug in the box-shaped via hole. The method of claim 5, Forming a pad contact layer in the substrate in contact with the pad metal layer; Forming via holes in the form of line arrays formed in regions of the pad metal layer; And forming a plug in the via array in the line array form. 9. The method according to claim 7 or 8, The plug is a method of manufacturing a semiconductor device package containing one or more of Al, W, Cu.
KR1020090136337A 2009-12-31 2009-12-31 Semiconductor device package and method for manufacturing the same KR20110079319A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020090136337A KR20110079319A (en) 2009-12-31 2009-12-31 Semiconductor device package and method for manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020090136337A KR20110079319A (en) 2009-12-31 2009-12-31 Semiconductor device package and method for manufacturing the same

Publications (1)

Publication Number Publication Date
KR20110079319A true KR20110079319A (en) 2011-07-07

Family

ID=44918702

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020090136337A KR20110079319A (en) 2009-12-31 2009-12-31 Semiconductor device package and method for manufacturing the same

Country Status (1)

Country Link
KR (1) KR20110079319A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101409664B1 (en) * 2011-07-19 2014-06-18 옵티즈 인코포레이티드 Low stress cavity package for back side illuminated image sensor, and method of making same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101409664B1 (en) * 2011-07-19 2014-06-18 옵티즈 인코포레이티드 Low stress cavity package for back side illuminated image sensor, and method of making same

Similar Documents

Publication Publication Date Title
US11961867B2 (en) Electronic device package and fabricating method thereof
US10177104B2 (en) Package on package structure and method for forming the same
KR102379165B1 (en) Integrated circuit device having through silicon via structure and method of manufacturing the same
US20190157333A1 (en) Hybrid bonded structure
US9378982B2 (en) Die package with openings surrounding end-portions of through package vias (TPVs) and package on package (PoP) using the die package
KR101918608B1 (en) Semiconductor package
US8564101B2 (en) Semiconductor apparatus having a through-hole interconnection
TWI499021B (en) Semiconductor device and method for manufacturing the same
TWI521616B (en) Package assembly having a semiconductor substrate
US7176555B1 (en) Flip chip package with reduced thermal stress
US20220013502A1 (en) Semiconductor packages
TW201717343A (en) Package-on-package assembly and method for manufacturing the same
TW201822330A (en) Chip package structure
KR20130053338A (en) Integrated circuit device having through silicon via structure
TWI556379B (en) Semiconductor package and manufacturing method thereof
KR20090002644A (en) Semiconductor device having through electrode and method of fabricating the same
TW201322418A (en) Package assembly including a semiconductor substrate with stress relief structure
JP2008182235A (en) Chip having side pad, method of manufacturing the same and package using the same
KR20130082315A (en) Integrated circuit device
TWI721564B (en) Semiconductor structure and method of fabricating the same
US10319611B2 (en) Semiconductor device package with warpage prevention
US20230138813A1 (en) Semiconductor package
CN109216209B (en) Integrated circuit package and method of forming the same
TW201411752A (en) Stress reduction apparatus
TW201911434A (en) Semicondcutor device and semicondcutor package

Legal Events

Date Code Title Description
WITN Withdrawal due to no request for examination