JP5383593B2 - Semiconductor inspection apparatus and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor inspection apparatus that inputs and outputs an electrical signal for inspecting a semiconductor device that is an inspection object, and a manufacturing method thereof.

  Conventionally, in the inspection process of a semiconductor device, the tip of a contact (probe) of the semiconductor inspection device is directly pressed against the electrode pad of the semiconductor device, and the external semiconductor inspection system and the semiconductor device are temporarily electrically connected. Probing inspection to determine the quality of continuity between circuits, burn-in inspection that accelerates and sorts out defects by applying thermal or electrical stress to the circuit at high temperature, and final inspection at high frequency Inspection of electrical characteristics such as inspection was performed.

  In recent years, in semiconductor devices, the number of electrode pads formed in a semiconductor device has increased (multiple pins) and the pitch of electrode pads has been reduced due to higher integration of semiconductor elements and an increase in the number of processing signals. Yes. As a result, it is becoming necessary to increase the number of pins and the pitch of a contact (probe) of a semiconductor inspection apparatus used for inspection of electrical characteristics of a semiconductor device.

  For a semiconductor device having a relatively large pitch of electrode pads and a peripheral arrangement, for example, a hard pin such as tungsten or nickel is used as a contact (probe) of the semiconductor inspection device. In addition, recent semiconductor devices in which electrode pads are narrowed by area array arrangement cannot be handled by the above-mentioned hard pins as contacts (probes) of semiconductor inspection devices, so contact using MEMS technology A child (probe) is being considered.

JP 2000-171383 A JP 2002-5992 A

  However, a semiconductor inspection apparatus that can accurately contact a semiconductor device with electrode pads having a large number of pins and a narrow pitch and that is unlikely to damage the semiconductor device with a low needle pressure has not been realized.

  The present invention has been made in view of the above points, and an object of the present invention is to provide a semiconductor inspection apparatus that can accurately contact an electrode pad of a semiconductor device and hardly damage the semiconductor device.

The semiconductor inspection apparatus is a semiconductor inspection apparatus that inputs and outputs an electrical signal for inspecting a semiconductor device that is an inspection object, and includes a first substrate and the first substrate via an elastically deformable joint. A second substrate bonded, and the first substrate is sealed with an elastically deformable resin at one end of a through hole formed so as to penetrate the first substrate, and on the second substrate side. An opening recess, a wiring formed on the inner surface of the recess, a wiring pattern electrically connected to the wiring, and a conductive ball housed in the recess and in contact with and in conduction with the wiring And the second substrate is formed on one surface at a position corresponding to the concave portion of the first substrate, and one end of the first substrate is in contact with the conductive ball and is conductive. If, on the other side, via a through electrode penetrating the second substrate, the first collision A second protruding portion of the conductive which is electrically connected to the part, in that it comprises a requirement.

  According to the disclosed technology, it is possible to provide a semiconductor inspection apparatus that can contact the electrode pads of the semiconductor device with high accuracy and hardly damage the semiconductor device.

1 is a cross-sectional view illustrating a semiconductor inspection apparatus according to a first embodiment. It is a figure explaining the method to test | inspect a semiconductor device using the semiconductor inspection apparatus which concerns on 1st Embodiment. It is a figure explaining the case where a semiconductor device inclines. FIG. 6 is a diagram (part 1) illustrating a manufacturing process of the semiconductor inspection apparatus according to the first embodiment; FIG. 6 is a diagram (part 2) illustrating a manufacturing process of the semiconductor inspection apparatus according to the first embodiment; FIG. 6 is a diagram (No. 3) for exemplifying the manufacturing process for the semiconductor inspection apparatus according to the first embodiment; FIG. 7 is a diagram (No. 4) for exemplifying the manufacturing process for the semiconductor inspection apparatus according to the first embodiment; FIG. 10 is a diagram (No. 5) for exemplifying the manufacturing process for the semiconductor inspection apparatus according to the first embodiment; FIG. 8 is a diagram (No. 6) for exemplifying the manufacturing process for the semiconductor inspection apparatus according to the first embodiment; FIG. 10 is a diagram (No. 7) for exemplifying the manufacturing process for the semiconductor inspection apparatus according to the first embodiment; It is FIG. (The 8) which illustrates the manufacturing process of the semiconductor inspection apparatus which concerns on 1st Embodiment. It is FIG. (The 9) which illustrates the manufacturing process of the semiconductor inspection apparatus which concerns on 1st Embodiment. It is FIG. (The 10) which illustrates the manufacturing process of the semiconductor inspection apparatus which concerns on 1st Embodiment. It is FIG. (The 11) which illustrates the manufacturing process of the semiconductor inspection apparatus which concerns on 1st Embodiment. It is FIG. (The 12) which illustrates the manufacturing process of the semiconductor inspection apparatus which concerns on 1st Embodiment. It is sectional drawing which illustrates the semiconductor inspection apparatus which concerns on the modification of 1st Embodiment. It is sectional drawing which illustrates the semiconductor inspection apparatus which concerns on 2nd Embodiment.

  Hereinafter, embodiments for carrying out the invention will be described with reference to the drawings. In addition, in each drawing, the same code | symbol is attached | subjected to the same component and the overlapping description may be abbreviate | omitted.

<First Embodiment>
[Structure of Semiconductor Inspection Apparatus According to First Embodiment]
First, the structure of the semiconductor inspection apparatus according to the first embodiment will be described. FIG. 1 is a cross-sectional view illustrating a semiconductor inspection apparatus according to the first embodiment. In FIG. 1, the X direction is a direction parallel to a surface 21a of a substrate body 21 to be described later, the Y direction is a direction perpendicular to the X direction (depth direction on the paper), and the Z direction is a direction perpendicular to the X direction and the Y direction (substrate body). 21 in the thickness direction) (the same applies to the subsequent drawings).

  Referring to FIG. 1, the semiconductor inspection apparatus 10 according to the first embodiment includes a first substrate 20, a second substrate 30, and a bonding portion 40, and the first substrate 20 and the second substrate 30. Is fixed through a joint 40.

  The first substrate 20 includes a substrate body 21, a via hole 21 x, an insulating layer 22, a via wiring 23, a wiring pattern 24, a ball support portion 25, and a conductive ball 26. The second substrate 30 includes a substrate body 31, a via hole 31 x, an insulating layer 32, a through electrode 33, a wiring pattern 34, a protruding bump 35, and a post 36. Hereinafter, the first substrate 20, the second substrate 30, and the bonding portion 40 constituting the semiconductor inspection apparatus 10 will be described in detail.

In the first substrate 20, the substrate body 21 is a portion that becomes a base on which the wiring pattern 24 and the like are formed. As a material of the substrate body 21, silicon, glass, ceramic, insulating resin (epoxy resin or the like), or the like can be used. However, since many semiconductor devices which are inspection objects of the semiconductor inspection apparatus 10 have a silicon substrate, from the viewpoint of matching the thermal expansion coefficient, the material of the substrate body 21 has a thermal expansion coefficient of silicon or silicon. It is preferred to use near borosilicate glass. Borosilicate glass is glass containing boric acid (B ₂ O ₃ ) and silicic acid (SiO ₂ ) as main components, and has a thermal expansion coefficient of about 3 ppm / ° C.

  The thickness of the substrate body 21 can be set to, for example, about 600 to 800 μm. The reason why the coefficient of thermal expansion of the substrate body 21 is matched with the coefficient of thermal expansion of the semiconductor device that is the inspection object of the semiconductor inspection apparatus 10 is that the semiconductor inspection apparatus 10 and the semiconductor inspection apparatus 10 This is to make it difficult for positional deviation from the semiconductor device that is the inspection object. Hereinafter, a case where the substrate body 21 is silicon will be described as an example.

  The via hole 21x is a through hole penetrating from the surface 21a of the substrate body 21 to the surface 21b. The arrangement pitch of the via holes 21x can be selected as appropriate, and can be, for example, about 400 to 1500 μm. The via hole 21x is, for example, a circle in a plan view (same as viewed from the Z direction), and a diameter of the via hole 21x can be, for example, about 300 to 1000 μm.

The insulating layer 22 is formed on the surface of the substrate body 21 including the surfaces 21a and 21b of the substrate body 21 and the inner surface of the via hole 21x. The insulating layer 22 is a film for insulating the substrate body 21 from the via wiring 23 and the wiring pattern 24. As a material of the insulating layer 22, for example, silicon dioxide (SiO ₂ ), silicon nitride (SiN), polyimide, or the like can be used. The thickness of the insulating layer 22 can be set to about 1 to 2 μm, for example.

  The via wiring 23 is formed on the inner surface of the via hole 21x via the insulating layer 22. As a material for the via wiring 23, for example, copper (Cu) or the like can be used. The via wiring 23 may be composed of a plurality of layers, and the surface thereof may be subjected to gold (Au) plating or the like. The thickness of the via wiring 23 can be about 10 μm, for example.

  The wiring pattern 24 is formed on the surface 21 a of the substrate body 21 via the insulating layer 22. The wiring pattern 24 is electrically connected to the via wiring 23. The wiring pattern 24 functions as an electrode pad that is electrically connected to a test board described later. As a material of the wiring pattern 24, for example, copper (Cu) or the like can be used. The wiring pattern 24 may be composed of a plurality of layers, and the surface thereof may be subjected to gold (Au) plating or the like. The thickness of the wiring pattern 24 can be about 10 μm, for example.

  On the wiring pattern 24, an insulating layer and a wiring pattern may be stacked as many as necessary as necessary. Further, an overcoat layer having a predetermined opening may be formed on the wiring pattern 24. In this case, the portion exposed from the opening of the overcoat layer of the wiring pattern 24 functions as an electrode pad that is electrically connected to a test substrate described later.

  The ball support portion 25 is provided so as to seal one side of the via hole 21x (the substrate body surface 21a side). The via hole 21x and the ball support portion 25 form a recess, and the depth of the recess can be, for example, about 500 to 700 μm.

  The thickness of the ball support portion 25 can be set to about 100 μm, for example. As a material of the ball support portion 25, an elastically deformable resin such as a silicon resin or a rubber-based resin can be used. Examples of rubber resins include resins such as polyurethane rubber, styrene butadiene rubber, butadiene rubber, isoprene rubber, chloroprene rubber, isobutylene / isoprene rubber, acrylonitrile butadiene rubber, chlorinated butyl rubber, acrylic rubber, and epichlorohydrin rubber.

  The ball support portion 25 has a function of supporting the conductive ball 26 when the conductive ball 26 is pushed by the second substrate 30 from the surface 21b side of the substrate body 21 to the surface 21a side. At this time, since the ball support portion 25 absorbs the force received from the second substrate 30 by elastic deformation, it is possible to prevent the conductive balls 26 and the posts 36 from being damaged.

  A plurality of conductive balls 26 are movably accommodated in a recess formed by the via hole 21x and the ball support portion 25. The conductive ball 26 is not fully accommodated so as to fill the concave portion, and is accommodated in a state where there is play around the conductive ball 26. Accordingly, when the conductive balls 26 are pushed from the surface 21b side to the surface 21a side of the substrate body 21 by the second substrate 30, each conductive ball 26 moves and a large force is applied to each conductive ball 26. I can prevent that. Each conductive ball 26 is in contact with another conductive ball 26 even if it is movable, and any of the conductive balls 26 is in contact with the via wiring 23 and is electrically connected to the via wiring 23.

  Thus, the conductive ball 26 is damaged by providing the ball support portion 25 that can be elastically deformed and by providing play around the conductive ball 26 so that each conductive ball 26 can be moved. Can withstand repeated use. However, since the force applied to the conductive ball 26 can be reduced only by providing play around the conductive ball 26 and accommodating each conductive ball 26 in a movable state, depending on the specifications, the material of the ball support portion 25 may be reduced. As an alternative, an elastically deformable resin such as a silicon resin or a rubber-based resin may not be used, and an epoxy resin, a metal layer, or the like may be used. In this case as well, it can withstand repeated use to some extent.

  As the conductive ball 26, a conductive ball such as a gold (Au) ball, a copper (Cu) ball, a nickel (Ni) ball, a resin core ball (Ni, Cu, solder, etc.), or a solder ball is used. it can. It is preferable that the surface of the conductive ball 26 be subjected to gold (Au) plating with little resistance change. The diameter of the conductive ball 26 is smaller than the diameter of the via hole 21x and the depth of the concave portion formed by the via hole 21x and the ball support portion 25, and can be, for example, about 10 to 200 μm. The number of conductive balls 26 accommodated in one recess formed by the via hole 21x and the ball support portion 25 varies depending on the diameter, but can be, for example, about several to several thousand.

  In the second substrate 30, the substrate body 31 is a portion that becomes a base on which the wiring pattern 34 and the like are formed. As the material of the substrate body 31, as with the substrate body 21, silicon, glass, ceramic, insulating resin (epoxy resin, etc.) can be used. However, for the same reason as the substrate body 21, it is preferable to use silicon or borosilicate glass having a thermal expansion coefficient close to that of silicon as the material of the substrate body 31.

  The thickness of the substrate body 31 can be, for example, about 200 to 300 μm. The reason for matching the thermal expansion coefficient of the substrate body 31 with the thermal expansion coefficient of the semiconductor device that is the inspection object of the semiconductor inspection apparatus 10 is the same as that of the substrate body 21. Hereinafter, a case where the substrate body 31 is silicon will be described as an example.

  The via hole 31x is a through-hole penetrating from the surface 31a of the substrate body 31 to the surface 31b. The via hole 31x is provided at a position corresponding to the via hole 21x in plan view. That is, the arrangement pitch of the via holes 31x is the same as the arrangement pitch of the via holes 21x. The via hole 21x is, for example, circular in plan view, and the diameter thereof can be, for example, about 50 to 200 μm.

The insulating layer 32 is formed on the surface of the substrate body 31 including the surfaces 31a and 31b of the substrate body 31 and the inner surface of the via hole 31x. The insulating layer 32 is a film for insulating the substrate body 31 from the through electrode 33, the wiring pattern 34, and the post 36. As a material of the insulating layer 32, for example, silicon dioxide (SiO ₂ ), silicon nitride (SiN), polyimide, or the like can be used. The thickness of the insulating layer 32 can be about 1 to 2 μm, for example.

  The through electrode 33 is formed so as to fill the via hole 31x. One surface of the through electrode 33 is substantially flush with the upper surface of the insulating layer 32 formed on the surface 31 a of the substrate body 31, and the other surface of the through electrode 33 is an insulating layer formed on the surface 31 b of the substrate body 31. It is substantially flush with the upper surface of 32. The diameter of the through electrode 33 is substantially the same as the diameter of the via hole 31x (for example, about 50 to 200 μm). As a material of the through electrode 33, for example, copper (Cu) or the like can be used.

  The wiring pattern 34 is formed on the surface 31 b of the substrate body 31 via the insulating layer 32. The wiring pattern 34 is electrically connected to the through electrode 33. The wiring pattern 34 is provided for converting the pitch of the through electrodes 33 and the pitch of the bumps 35. The thickness of the wiring pattern 34 can be set to about 10 μm, for example. As a material of the wiring pattern 34, for example, copper (Cu) or the like can be used. The wiring pattern 34 may be composed of a plurality of layers, and the surface thereof may be subjected to gold (Au) plating or the like.

  The bumps 35 are formed on the wiring pattern 34. The protruding bumps 35 are, for example, cylindrical, and have a function as a contact (probe) that contacts an electrode pad of a semiconductor device that is an inspection object of the semiconductor inspection device 10. Therefore, the bumps 35 are provided at positions corresponding to the electrode pads of the semiconductor device that is the inspection object. For example, if the electrode pads of the semiconductor device that is the inspection object are provided in a peripheral shape, the bumps 35 are also provided in the peripheral shape, and the electrode pads of the semiconductor device that is the inspection object are provided in an area array shape. In this case, the bumps 35 are also provided in an area array. The bumps 35 may be conical, truncated cone, hemispherical, prismatic, pyramidal, etc., for example.

  The pitch of the bumps 35 corresponds to the pitch of the electrode pads of the semiconductor device, and can be about 10 to 100 μm, for example. Note that the bumps 35 are pitch-converted by the wiring pattern 34, and therefore have a narrower pitch than the through electrodes 33. Since the bumps 35 are portions that repeatedly come into contact with the electrode pads of the semiconductor device, it is preferable to use a material that is hard and difficult to deform and wear. For example, nickel (Ni), copper (Cu), gold (Au) Rhodium (Rh) or the like can be used.

  The protrusion amount (height) of the protrusion bump 35 from the upper surface of the wiring pattern 34 can be set to about 20 to 50 μm, for example. An overcoat layer that exposes the bumps 35 may be formed on the wiring pattern 34. The protruding bump 35 is a typical example of the conductive second protruding portion according to the present invention.

  The post 36 is formed on a portion including one surface of the through electrode 33 (the surface on the surface 31 a side of the substrate body 31). The post 36 has, for example, a cylindrical shape, and its center substantially coincides with the center of the through electrode 33. The diameter of the post 36 is preferably equal to or greater than the diameter of the through electrode 33 (for example, about 50 to 200 μm), and can be, for example, about 200 to 900 μm. The protrusion amount (height) from the upper surface of the insulating layer 32 of the post 36 can be set to, for example, about 150 to 200 μm. Note that the post 36 may have a conical shape, a truncated cone shape, a hemispherical shape, a prismatic shape, a pyramid shape, or the like.

  One end of the post 36 (the side not in contact with the through electrode 33) enters the recess formed by the via hole 21 x and the ball support portion 25, and is in contact with any of the conductive balls 26 accommodated in the recess. . The post 36 has a function of confining the conductive ball 26 in the via hole 21x. Further, the post 36 electrically connects the protruding bump 35 to the conductive ball 26 accommodated in the recess formed by the via hole 21 x and the ball support portion 25 of the first substrate 20 via the wiring pattern 34 and the through electrode 33. It has a function to connect to. As a material of the post 36, for example, nickel (Ni), copper (Cu), gold (Au) or the like can be used. The post 36 is a typical example of the conductive first protrusion according to the present invention.

  The joint 40 joins the insulating layer 22 formed on the surface 21 b of the substrate body 21 of the first substrate 20 and the insulating layer 32 formed on the surface 31 a of the substrate body 31 of the second substrate 30. The thickness of the joining part 40 can be about 100 μm, for example. As a material of the joint portion 40, an elastically deformable resin such as a silicon resin or a rubber-based resin can be used. Examples of rubber resins include resins such as polyurethane rubber, styrene butadiene rubber, butadiene rubber, isoprene rubber, chloroprene rubber, isobutylene / isoprene rubber, acrylonitrile butadiene rubber, chlorinated butyl rubber, acrylic rubber, and epichlorohydrin rubber.

  Since the joint portion 40 is elastically deformable, the second substrate 30 is not completely fixed to the first substrate 20, and all the electrode pads of the semiconductor device in which all the bumps 35 are inspection objects. Slightly move to contact. For example, if the semiconductor device that is the inspection object is inclined with respect to the first substrate 20, the elastically deformable joint 40 is elastically deformed, and the second substrate 30 is substantially parallel to the semiconductor device that is the inspection object. It is automatically adjusted to become. Note that the fine movement range can be, for example, about several μm to several tens of μm in each of the XYZ directions.

  Note that the second substrate 30 and the bonding portion 40 can be separated from the first substrate 20. Therefore, for example, when the replacement of the second substrate 30 becomes necessary due to the life of the bumps 35 functioning as contacts (probes), the first substrate 20 is reused, and only the second substrate 30 is regarded as a new one. Can be exchanged.

  Next, a method for inspecting a semiconductor device using the semiconductor inspection apparatus 10 will be described. FIG. 2 is a diagram illustrating a state in which the semiconductor inspection apparatus according to the first embodiment is brought into contact with a semiconductor device that is an inspection object. In FIG. 2, reference numeral 100 denotes a test substrate, and reference numeral 200 denotes a semiconductor device that is an inspection object.

  The test substrate 100 includes a substrate body 110 provided with a wiring pattern 120, a via wiring 130, an overcoat layer 140, a connection terminal 150, and the like, and the wiring pattern 24 of the semiconductor inspection apparatus 10 is connected via the connection terminal 150. And are electrically connected. The test substrate 100 is electrically connected to a semiconductor inspection system (not shown), and an electrical signal for inspection is input / output to / from the semiconductor inspection apparatus 10 via the test substrate 100. In the example of FIG. 2, the connection terminal 150 for connecting the first substrate 20 and the test substrate 100 is provided on the substrate body 110 side, but the connection terminal 150 is on the first substrate 20 side (on the wiring pattern 24). May be provided.

  The semiconductor device 200 is a semiconductor substrate 210 provided with electrode pads 220 and the like. The semiconductor substrate 210 is obtained by forming a semiconductor integrated circuit (not shown) on a substrate made of, for example, silicon (Si). The electrode pad 220 is formed in a peripheral shape or an area array shape on one side of the semiconductor substrate 210, and is electrically connected to a semiconductor integrated circuit (not shown).

  When inspecting the semiconductor device 200, the semiconductor device 200 is placed on a mounting table (not shown) that can be aligned with the semiconductor inspection device 10, and each bump bump 35 of the semiconductor inspection device 10 and each electrode of the semiconductor device 200. The pad 220 is aligned. The semiconductor inspection apparatus 10 is configured to be movable in the Z direction. When the semiconductor inspection apparatus 10 is moved in the Z direction (the direction of the semiconductor device 200), the semiconductor inspection apparatus has a function as a contact (probe). Each protruding bump 35 of the device 10 is pressed against each electrode pad 220 of the semiconductor device 200 with a predetermined force, and the upper surface (surface opposite to the wiring pattern 34) of each protruding bump 35 is the upper surface ( A surface opposite to the semiconductor substrate 210).

  The semiconductor inspection apparatus 10 can bring the bumps 35 into contact with the electrode pads 220 due to the flexibility of the elastically deformable joint 40. In addition, a needle pressure is generated between each bump 35 and each electrode pad 220. However, due to the flexibility of the elastically deformable joint 40, the needle pressure is extremely low, so that the semiconductor device 200 is hardly damaged. It has a structure.

  The electrode pads 220 of the semiconductor device 200 come into contact with the bumps 35, the wiring patterns 34, the through-electrodes 33, the posts 36, the conductive balls 26 that come into contact with the posts 36, due to the contact between the bumps 35 and the electrode pads 220. It is electrically connected to the test substrate 100 through the via wiring 23 and the wiring pattern 24 that are electrically connected to the conductive ball 26 on the side surface. As a result, the semiconductor inspection system (not shown) performs probing inspection for determining whether or not each circuit of the semiconductor device 200 is good, and accelerates and sorts out defects by applying thermal or electrical stress to the circuit at high temperatures. Electrical characteristics such as burn-in inspection and final inspection in which high-frequency inspection is finally performed can be performed.

  Note that, as described above, the second substrate 30 of the semiconductor inspection apparatus 10 is not completely fixed to the first substrate 20, and all the bumps 35 are all objects of the semiconductor device 200 to be inspected. It is finely moved so as to come into contact with the electrode pad 220. For example, as shown in FIG. 3, if the semiconductor device 200 that is the inspection object is inclined with respect to the first substrate 20, the elastically deformable joint 40 is elastically deformed, and the second substrate 30 is It is automatically adjusted so as to be approximately parallel to 200.

  As described above, the semiconductor inspection apparatus 10 is arranged between the test substrate 100 and the semiconductor device 200 that is the inspection object, and temporarily connects the test substrate 100 and the semiconductor device 200 to each other. Input and output electrical signals for testing. At this time, the upper surfaces of the bumps 35 of the semiconductor inspection apparatus 10 can be in contact with the upper surfaces of the electrode pads 220 of the semiconductor device 200 with high accuracy. Further, the semiconductor device 200 can be prevented from being damaged by the action of the elastically deformable ball support portion 25 and the elastically deformable joint portion 40 of the semiconductor inspection apparatus 10.

[Method of Manufacturing Semiconductor Inspection Device According to First Embodiment]
Next, a method for manufacturing the semiconductor inspection apparatus according to the first embodiment will be described. 4 to 6 are diagrams illustrating the manufacturing process of the semiconductor inspection apparatus according to the first embodiment. 4A to 4E illustrate a part of the manufacturing process of the first substrate 20, FIGS. 5A to 5D illustrate the manufacturing process of the second substrate 30, and FIGS. 6A to 6C illustrate the first substrate. It is a figure which illustrates the process of joining the remainder of 20 manufacturing processes, the 1st board | substrate 20, and the 2nd board | substrate 30 via the junction part 40. FIG.

  First, in the step shown in FIG. 4A, the substrate body 21 is prepared, and a resist layer 80 having an opening 80x corresponding to the through hole 21x is formed on the surface 21a of the substrate body 21. The substrate body 21 is obtained by dividing a silicon wafer of 6 inches (about 150 mm), 8 inches (about 200 mm), 12 inches (about 300 mm), etc. into a predetermined size. The thickness of the silicon wafer is, for example, 0.625 mm (in the case of 6 inches), 0.725 mm (in the case of 8 inches), 0.775 mm (in the case of 12 inches) or the like. can do. In the present embodiment, the step of separating the substrate main body 21 first is exemplified. However, each step described later may be performed first in the state of a silicon wafer and finally separated.

  In order to form the resist layer 80, a liquid or paste resist made of a photosensitive resin composition containing, for example, an acrylic resin, an epoxy resin, an imide resin, or the like is applied to the surface 21a of the substrate body 21. Alternatively, a film resist made of a photosensitive resin composition containing, for example, an acrylic resin, an epoxy resin, an imide resin, or the like is laminated on the surface 21a of the substrate body 21. Then, the opening 80x is formed by exposing and developing the coated or laminated resist. Thereby, the resist layer 80 having the opening 80x is formed. Note that a film-like resist in which the opening 80x is formed in advance may be laminated on the surface 21a of the substrate body 21.

Next, in the process shown in FIG. 4B, the substrate body 21 is etched using the resist layer 80 shown in FIG. 4A as a mask to form via holes 21x that are through holes penetrating from the surface 21a of the substrate body 21 to the surface 21b. The via hole 21x can be formed by an anisotropic etching method such as reactive ion etching (DRIE) using SF ₆ (sulfur hexafluoride), for example. The arrangement pitch of the via holes 21x corresponds to the arrangement pitch of the openings 80x, and can be, for example, about 400 to 1500 μm. The via hole 21x is, for example, circular in plan view, and the diameter thereof can be, for example, about 300 to 1000 μm.

4C, after the resist layer 80 shown in FIG. 4B is removed, the insulating layer 22 is formed on the surface of the substrate body 21 including the surfaces 21a and 21b of the substrate body 21 and the inner surface of the via hole 21x. . As the insulating layer 22, a thermal oxide film (SiO ₂ ) can be used. The insulating layer 22 can be formed by thermal oxidation by a wet thermal oxidation method in which the temperature in the vicinity of the surface of the substrate body 21 is set to 1000 ° C. or higher, for example. The thickness of the insulating layer 22 can be set to about 1 to 2 μm, for example. As the insulating layer 22, a film such as silicon dioxide (SiO ₂ ) or silicon nitride (SiN) may be formed by a CVD method or the like.

  Next, in a step shown in FIG. 4D, a via wiring 23 is formed on the insulating layer 22 on the inner surface of the via hole 21x. As a material for the via wiring 23, for example, copper (Cu) or the like can be used. The via wiring 23 can be formed by, for example, sputtering, electroless plating, electrolytic plating, or the like. The via wiring 23 may be composed of a plurality of layers, and the surface thereof may be subjected to gold (Au) plating or the like.

  4E, a wiring pattern 24 that is electrically connected to the via wiring 23 is formed on the insulating layer 22 formed on the surface 21a of the substrate body 21. The wiring pattern 24 can be formed by, for example, a semi-additive method, a subtractive method, a lift-off method, or the like. The thickness of the wiring pattern 24 can be about 10 μm, for example. As a material of the wiring pattern 24, for example, copper (Cu) or the like can be used. The wiring pattern 24 may be composed of a plurality of layers, and the surface thereof may be subjected to gold (Au) plating or the like.

  Next, in the process shown in FIG. 5A, the substrate body 31 having the via hole 31x is manufactured by the same processes as in FIGS. 4A to 4C, and the substrate body 31 including the surfaces 31a and 31b of the substrate body 31 and the inner surface of the via hole 31x. After the insulating layer 32 is formed on the surface, the through electrode 33 is filled in the via hole 31x. The diameter of the through electrode 33 is substantially the same as the diameter of the via hole 31x (for example, about 50 to 200 μm). As a material of the through electrode 33, for example, copper (Cu) or the like can be used.

  The through electrode 33 can be formed by, for example, an electroless plating method or an electrolytic plating method. The through electrode 33 may be formed, for example, by filling the via hole 31x with a copper (Cu) paste or the like. The material of the through electrode 33 is not limited to copper (Cu), and a conductive material such as gold (Au) or nickel (Ni) can be appropriately selected. If necessary, planarization may be performed by CMP (Chemical Mechanical Polishing) or the like. Due to the planarization, one surface of the through electrode 33 is substantially flush with the upper surface of the insulating layer 32 formed on the surface 31 a of the substrate body 31, and the other surface of the through electrode 33 is formed on the surface 31 b of the substrate body 31. Further, the upper surface of the insulating layer 32 can be substantially flush with the upper surface.

  5B, a wiring pattern 34 that is electrically connected to the through electrode 33 is formed on the insulating layer 32 formed on the surface 31b of the substrate body 31. The wiring pattern 34 can be formed by, for example, a semi-additive method, a subtractive method, a lift-off method, or the like. The thickness of the wiring pattern 34 can be set to about 10 μm, for example. As a material of the wiring pattern 34, for example, copper (Cu) or the like can be used. The wiring pattern 34 may be composed of a plurality of layers, and the surface thereof may be subjected to gold (Au) plating or the like.

  Next, in the step shown in FIG. 5C, a bump bump 35 that is electrically connected to the wiring pattern 34 is formed on the wiring pattern 34. The bumps 35 can be formed by, for example, an electroless plating method or an electrolytic plating method. The protruding bumps 35 are, for example, cylindrical and are provided at positions corresponding to the electrode pads of the semiconductor device that is the inspection object. For example, if the electrode pads of the semiconductor device that is the inspection object are provided in a peripheral shape, the bumps 35 are also provided in the peripheral shape, and the electrode pads of the semiconductor device that is the inspection object are provided in an area array shape. In this case, the bumps 35 are also provided in an area array. The bumps 35 may be conical, truncated cone, hemispherical, prismatic, pyramidal, etc., for example.

  The pitch of the bumps 35 corresponds to the pitch of the electrode pads of the semiconductor device, and can be about 10 to 100 μm, for example. Since the bumps 35 are portions that repeatedly come into contact with the electrode pads of the semiconductor device, it is preferable to use a material that is hard and difficult to deform and wear. For example, nickel (Ni), copper (Cu), gold (Au) Rhodium (Rh) or the like can be used. The protrusion amount (height) of the protrusion bump 35 from the upper surface of the wiring pattern 34 can be set to about 20 to 50 μm, for example.

  Next, in the step shown in FIG. 5D, the post 36 is formed on a portion including one surface of the through electrode 33 (the surface on the surface 31a side of the substrate body 31). The post 36 can be formed by, for example, an electroless plating method or an electrolytic plating method. The post 36 has, for example, a cylindrical shape, and is formed so that the center thereof substantially coincides with the center of the through electrode 33. The diameter of the post 36 is preferably equal to or greater than the diameter of the through electrode 33 (for example, about 50 to 200 μm), and can be, for example, about 200 to 900 μm.

  The protrusion amount (height) from the upper surface of the insulating layer 32 of the post 36 can be set to, for example, about 150 to 200 μm. Note that the post 36 may have a conical shape, a truncated cone shape, a hemispherical shape, a prismatic shape, a pyramid shape, or the like. As a material of the post 36, for example, nickel (Ni), copper (Cu), gold (Au) or the like can be used.

  Note that an overcoat layer having an opening exposing the post 36 may be formed on the surface 31a of the substrate body 31 after the step shown in FIG. 5D. Further, an overcoat layer having an opening for exposing the bumps 35 may be formed on the surface 31 b of the substrate body 31.

  Next, in the step shown in FIG. 6A, one side of the via hole 21 x (the substrate body surface 21 a side) is sealed by the ball support portion 25. The thickness of the ball support portion 25 can be set to about 100 μm, for example. As a material of the ball support portion 25, an elastically deformable resin such as a silicon resin or a rubber-based resin can be used. Examples of the rubber-based resin are as described above.

  Next, in the step shown in FIG. 6B, the structure shown in FIG. 6A is turned upside down, and a plurality of conductive balls 26 are movably accommodated in the recesses formed by the via holes 21x and the ball support portions 25. As the conductive ball 26, a conductive ball such as a gold (Au) ball, a copper (Cu) ball, a nickel (Ni) ball, a resin core ball (Ni, Cu, solder, etc.), or a solder ball is used. it can. It is preferable that the surface of the conductive ball 26 be subjected to gold (Au) plating with little resistance change.

  The diameter of the conductive ball 26 is smaller than the diameter of the via hole 21x and the depth of the concave portion formed by the via hole 21x and the ball support portion 25, and can be, for example, about 10 to 200 μm. The number of conductive balls 26 accommodated in one recess formed by the via hole 21x and the ball support portion 25 varies depending on the diameter, but can be, for example, about several to several thousand.

  Next, in the step illustrated in FIG. 6C, the first substrate 20 and the second substrate 30 are bonded via the bonding portion 40. Specifically, the insulating layer 22 formed on the surface 21 b of the substrate main body 21 of the first substrate 20 and the insulating layer 32 formed on the surface 31 a of the substrate main body 31 of the second substrate 30 are connected via the joint 40. And join. The thickness of the joining part 40 can be about 100 μm, for example. As a material of the joint portion 40, an elastically deformable resin such as a silicon resin or a rubber-based resin can be used. Therefore, the second substrate 30 is not completely fixed to the first substrate 20 and can be moved finely. In addition, although the junction part 40 may be continuously formed in the vicinity of the outer edge part of the second substrate 30, if it is formed so as to be scattered at a predetermined interval in a plurality of locations in the vicinity of the outer edge part of the second substrate 30. It is enough.

  As described above, according to the semiconductor inspection apparatus according to the first embodiment, the first substrate serving as the support substrate and the second substrate on which the bumps that function as the contacts (probes) are formed are made of silicon or the like. The first substrate and the second substrate are manufactured using a material capable of narrowing the pitch, and are bonded using an elastically deformable resin. As a result, bumps that function as contacts (probes) can be formed in an area array with a narrow pitch, and not only in a semiconductor device in which electrode pads are provided in a peripheral shape, but also in an area array. It can also be applied to existing semiconductor devices.

  Further, the second substrate finely moves with respect to the first substrate by the function of the resin that can be elastically deformed. For example, if the semiconductor device as the inspection object is inclined with respect to the first substrate, the joint is elastically deformed. The second substrate is automatically adjusted so as to be substantially parallel to the semiconductor device. As a result, the bumps that function as contacts (probes) can contact the electrode pads of the semiconductor device with high accuracy. Further, since play is provided around the elastically deformable resin and the conductive balls, the force applied at each important point can be reduced, and the semiconductor device can be prevented from being damaged.

  Further, since the first substrate and the second substrate are electrically connected via a conductive ball that is movable in a recess having via wiring formed on the inner surface, the second substrate is connected to the first substrate. Even when tilted, the conductive ball moves and the conductive ball and the via wiring always come into contact with each other, so that stable conduction can be ensured.

<Modification of First Embodiment>
In the first embodiment, the pitch is changed by the wiring pattern 34 in the second substrate 30 so that the through electrodes 33 and the posts 36 are wider than the bumps 35. In the modification of the first embodiment, an example in which the wiring pattern 34 is not provided on the second substrate 30 and pitch conversion is not performed is shown. In the modification of the first embodiment, the description of the same components as those in the first embodiment may be omitted.

  FIG. 7 is a cross-sectional view illustrating a semiconductor inspection apparatus according to a modification of the first embodiment. Referring to FIG. 7, in the semiconductor inspection apparatus 10A according to the modification of the first embodiment, no component corresponding to the wiring pattern 34 of the semiconductor inspection apparatus 10 is provided, and no pitch conversion is performed. . That is, in the semiconductor inspection apparatus 10 </ b> A, the bumps 35 are directly formed on the exposed portion on the surface 31 b side of the through electrode 33.

  In other words, in the semiconductor inspection apparatus 10 (see FIG. 1), the pitch is changed by the wiring pattern 34 in the second substrate 30, and the through electrode 33 and the post 36 have a wider pitch than the bumps 35. Therefore, in the first substrate 20, the pitch of the via holes 21 x corresponds to the pitch of the through electrodes 33 and the posts 36 and is wider than the bumps 35. In the semiconductor inspection apparatus 10 </ b> A (see FIG. 7), pitch conversion is not performed on the second substrate 30, so the bumps 35, the through electrodes 33 and the posts 36 of the second substrate 30, and the via holes 21 x of the first substrate 20. Are all the same pitch.

  As described above, it is not always necessary to change the pitch in the second substrate 30 so that the through electrodes 33 and the posts 36 have a wider pitch than the bumps 35. Unless there is a special reason such as difficulty in manufacturing, the process of forming a wiring pattern for pitch conversion can be eliminated, which can contribute to a reduction in manufacturing cost.

  As described above, the semiconductor inspection apparatus according to the modification of the first embodiment has the same effects as the semiconductor inspection apparatus according to the first embodiment, but also has the following effects. That is, since the process of forming a wiring pattern for performing pitch conversion on the second substrate can be eliminated, the manufacturing cost can be reduced.

<Second Embodiment>
In the first embodiment, one side of the via hole 21x is sealed by the ball support portion 25 to form a recess, and the conductive ball 26 is accommodated. In the second embodiment, an example in which a concave portion is formed directly in the substrate body and the ball support portion 25 and the conductive ball 26 are accommodated in the concave portion is shown. In the second embodiment, the description of the same components as in the first embodiment may be omitted.

  FIG. 8 is a cross-sectional view illustrating a semiconductor inspection apparatus according to the second embodiment. Referring to FIG. 8, the semiconductor inspection apparatus 10B according to the second embodiment is different from the semiconductor inspection apparatus 10 (see FIG. 1) in that the first substrate 20 is replaced with the first substrate 50. Yes.

  The first substrate 50 includes a substrate body 51, a recess 51x, a via hole 51y, an insulating layer 52, a via wiring 53, a wiring pattern 54, a ball support portion 55, a conductive ball 56, and a through electrode 57. And a wiring pattern 58. The substrate body 51 is a portion that becomes a base on which the wiring pattern 54 and the like are formed. Since the material, thickness, function, and the like of the substrate body 51 can be the same as those of the substrate body 21, description thereof is omitted. Hereinafter, a case where the substrate body 51 is silicon will be described as an example.

  The recess 51x is provided so as to open to the surface 51b side of the substrate body 51. The arrangement pitch of the recesses 51x can be selected as appropriate, and can be, for example, about 400 to 1500 μm. The recess 51x is, for example, circular in plan view, and the diameter can be, for example, about 300 to 1000 μm.

  The via hole 51y is a through hole penetrating from the surface 51a of the substrate body 51 to the surface 51b. The arrangement pitch of the via holes 51y can be selected as appropriate, and can be, for example, about 600 to 1500 μm. The via hole 51y is, for example, circular in plan view, and the diameter thereof can be, for example, about 300 to 1000 μm.

The recess 51x and the via hole 51y are formed by reactive ion etching (DRIE: Deep Reactive Ion Etching) using, for example, SF ₆ (sulfur hexafluoride), as in the process shown in FIGS. 4A and 4B of the first embodiment. It can form by anisotropic etching methods, such as.

  The insulating layer 52 is formed on the surface of the substrate body 51 including the surfaces 51a and 51b of the substrate body 51, the inner and inner bottom surfaces of the recess 51x, and the inner surface of the via hole 21x. The insulating layer 52 is a film for insulating the substrate body 51 from the via wiring 53 and the through electrode 57 and the wiring patterns 54 and 58. Since the material, thickness, function, and the like of the insulating layer 52 can be the same as those of the insulating layer 22, the description thereof is omitted.

  The via wiring 53 is formed on the inner surface of the recess 51x with an insulating layer 52 interposed. Since the material, thickness, function, and the like of the via wiring 53 can be the same as those of the via wiring 23, description thereof is omitted. The wiring pattern 54 is formed on the surface 51 a of the substrate body 51 via the insulating layer 52. Since the material, thickness, function, and the like of the wiring pattern 54 can be the same as those of the wiring pattern 24, description thereof is omitted.

  The ball support portion 55 is provided on the inner bottom surface of the recess 51x. Since the material, thickness, function, and the like of the ball support portion 55 can be the same as those of the ball support portion 25, description thereof is omitted. However, since the force applied to the conductive ball 56 can be reduced by providing play around the conductive ball 56 and accommodating each conductive ball 56 in a movable state, the ball support portion 55 is not provided depending on the specifications. Even when the conductive ball 56 is in direct contact with the inner bottom surface of the recess 51x, it can withstand repeated use to some extent.

  The conductive ball 56 is accommodated in the recess 51x. Since the material, thickness, function, and the like of the conductive ball 56 can be the same as those of the conductive ball 26, description thereof is omitted.

  The through electrode 57 is formed so as to fill the via hole 51y. The through electrode 57 electrically connects the wiring patterns 54 and 58. One surface of the through electrode 57 is substantially flush with the upper surface of the insulating layer 52 formed on the surface 51 a of the substrate body 51, and the other surface of the through electrode 57 is an insulating layer formed on the surface 51 b of the substrate body 51. 52 is substantially flush with the upper surface of 52. The diameter of the through electrode 57 is substantially the same as the diameter of the via hole 51y (for example, about 300 to 1000 μm). As a material of the through electrode 57, for example, copper (Cu) or the like can be used.

  The wiring pattern 58 is formed on the surface 51 b of the substrate body 51 via the insulating layer 52. The wiring pattern 58 electrically connects the via wiring 53 and the through electrode 57. Since the material and thickness of the wiring pattern 58 can be the same as those of the wiring pattern 54, description thereof is omitted. An overcoat layer having a predetermined opening may be formed on the wiring pattern 58.

  As described above, in the semiconductor inspection apparatus, the ball support portion and the conductive ball may be accommodated in a recess formed directly on the substrate body.

  As described above, the semiconductor inspection apparatus according to the second embodiment has the same effects as the semiconductor inspection apparatus according to the first embodiment.

  The preferred embodiment and its modification have been described in detail above, but the present invention is not limited to the above-described embodiment and its modification, and the above-described implementation is performed without departing from the scope described in the claims. Various modifications and substitutions can be added to the embodiment and its modifications.

  For example, in the second embodiment, the same modification as the modification of the first embodiment may be added.

10, 10A, 10B Semiconductor inspection apparatus 20, 50 First substrate 21, 31, 110 Substrate body 21a, 21b, 31a, 31b, 51a, 51b Surface 21x, 31x, 51y Via hole 22, 32, 52 Insulating layer 23, 53, 130 Via wiring 24, 34, 54, 58, 120 Wiring pattern 25, 55 Ball support part 26, 56 Conductive ball 30 Second substrate 33, 57 Through electrode 35 Projection bump 36 Post 40 Joint part 51 x Recess 80 Resist layer 80 x Opening Part 100 Test substrate 140 Solder 200 Semiconductor device 210 Semiconductor substrate 220 Electrode pad

Claims (9)

A semiconductor inspection apparatus that inputs and outputs electrical signals for inspecting a semiconductor device that is an inspection object,
A first substrate, and a second substrate joined to the first substrate via an elastically deformable joint,
The first substrate is
One end of a through-hole formed through the first substrate is sealed with an elastically deformable resin, and a recess opening to the second substrate side;
Wiring formed on the inner surface of the recess;
A wiring pattern electrically connected to the wiring;
A conductive ball housed in the recess and in electrical contact with the wiring,
The second substrate is
A conductive first protrusion formed on one surface at a position corresponding to the concave portion of the first substrate and having one end in contact with the conductive ball and conducting;
A semiconductor inspection , comprising: a conductive second protrusion that is electrically connected to the first protrusion via a through electrode penetrating the second substrate on the other surface. apparatus. A semiconductor inspection apparatus that inputs and outputs electrical signals for inspecting a semiconductor device that is an inspection object,
A first substrate, and a second substrate joined to the first substrate via an elastically deformable joint,
The first substrate is
Open to the second substrate side without penetrating the first substrate, and the recess that are elastically deformable resin is disposed on the inner bottom surface,
Wiring formed on the inner surface of the recess, a wiring pattern electrically connected to the wiring,
A conductive ball housed in the recess and in contact with the wiring to conduct,
The second substrate is
A conductive first protrusion formed on one surface at a position corresponding to the concave portion of the first substrate and having one end in contact with the conductive ball and conducting;
A semiconductor inspection , comprising: a conductive second protrusion that is electrically connected to the first protrusion via a through electrode penetrating the second substrate on the other surface. apparatus. A plurality of the conductive balls are accommodated in a movable state, and each conductive ball is in contact with another conductive ball, and any of the conductive balls is in contact with the wiring formed on the inner surface of the recess. the semiconductor inspection apparatus according to claim 1 or 2, characterized in that conducting and. 4. The end portion on the concave portion side of the first protrusion portion enters the concave portion, and is in contact with the conductive ball accommodated in the concave portion to be conductive. Semiconductor inspection equipment.   5. The semiconductor device according to claim 1, wherein when the second protrusion comes into contact with the electrode pad of the semiconductor device, the joint is elastically deformed to automatically adjust the parallelism between the second substrate and the semiconductor device. The semiconductor inspection apparatus as described.   The semiconductor inspection apparatus according to claim 1, wherein the first substrate and the second substrate have a substrate body made of silicon.   The semiconductor inspection apparatus according to claim 1, wherein the bonding portion is a silicon resin. A method for manufacturing a semiconductor inspection apparatus that inputs and outputs electrical signals for inspecting a semiconductor device that is an inspection object,
A first step of manufacturing a first substrate, a second step of manufacturing a second substrate, and a third step of bonding the first substrate and the second substrate through an elastically deformable joint. Have
The first step includes
Forming a through hole penetrating the substrate body of the first substrate;
Sealing one end of the through hole with an elastically deformable resin and forming a recess in the substrate body of the first substrate;
Forming a wiring on the inner surface of the recess,
The second step includes
Forming a through electrode penetrating the substrate body of the second substrate;
Forming a conductive first protrusion electrically connected to the through electrode at a position corresponding to the concave portion of the first substrate on one surface of the substrate body of the second substrate;
Forming a conductive second protrusion electrically connected to the first protrusion via the through electrode on the other surface of the substrate body of the second substrate ,
The third step includes
Containing a conductive ball so as to be conductive in contact with the wiring in the recess;
Bonding the first substrate and the second substrate through the bonding portion so that one end of the first protruding portion is in contact with the conductive ball and is conductive. Manufacturing method of inspection device. A method for manufacturing a semiconductor inspection apparatus that inputs and outputs electrical signals for inspecting a semiconductor device that is an inspection object,
A first step of manufacturing a first substrate, a second step of manufacturing a second substrate, and a third step of bonding the first substrate and the second substrate through an elastically deformable joint. Have
The first step includes
Forming a recess in the substrate body of the first substrate;
Placing an elastically deformable resin on the inner bottom surface of the recess;
Forming a wiring on the inner surface of the recess,
The second step includes
Forming a through electrode penetrating the substrate body of the second substrate;
Forming a conductive first protrusion electrically connected to the through electrode at a position corresponding to the concave portion of the first substrate on one surface of the substrate body of the second substrate;
Forming a conductive second protrusion electrically connected to the first protrusion via the through electrode on the other surface of the substrate body of the second substrate ,
The third step includes
Containing a conductive ball so as to be conductive in contact with the wiring in the recess;
Bonding the first substrate and the second substrate through the bonding portion so that one end of the first protruding portion is in contact with the conductive ball and is conductive. Manufacturing method of inspection device.

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