JP5381767B2 - Semiconductor integrated circuit and method for testing semiconductor integrated circuit - Google Patents

Description

  The present invention relates to a semiconductor integrated circuit and a semiconductor integrated circuit testing method, and more particularly to a semiconductor integrated circuit capable of detecting an electromigration phenomenon and a semiconductor integrated circuit testing method.

  With the recent increase in speed of LSI, the electromigration (hereinafter also referred to as EM) phenomenon of wiring inside the LSI has become a problem. The electromigration phenomenon in the wiring inside the LSI is a phenomenon in which the electron current flowing through the wiring gradually “pushes” the metal atoms constituting the wiring and causes a defect of metal atoms called voids inside the wiring. The average life of the wiring due to the electromigration phenomenon is expressed by Black's empirical formula, which greatly depends on the type of metal atom (wiring material), current density, and temperature. Al (aluminum) was the majority of wiring materials in LSIs at first, but degradation due to electromigration became a major problem as process technology evolved from 150 nm to 90 nm generation. By replacing the wiring material from Al to Cu (copper), the problem of wiring deterioration due to electromigration has been greatly improved.

  In addition, along with the miniaturization of wiring due to the evolution of process technology, the ON current of MOS transistors continues to increase, and the current density in the wiring is significantly increased. In other words, due to the synergistic effect of increasing the ON current of the MOS transistor and reducing the cross-sectional area of the wiring (reducing the area by about half for each generation), the current density per unit area of the wiring has increased several times for each generation, This exacerbates the electromigration problem. A drastic solution is the review of wiring materials such as replacement of Al with Cu, but at present, no material with better performance and cost than Cu has been discovered, and at least a few generations of LSI design in the future Need to do. Due to the above situation, the electromigration resistance (margin) of the wiring is relatively decreased as compared with the previous generation process, and the possibility of the occurrence of electromigration problems in the field cannot be denied.

  Various inspection methods have been proposed for the deterioration phenomenon due to electromigration as described above, focusing on the inspection before shipping LSI products. The semiconductor integrated circuit described in Patent Document 1 employs a configuration in which a direct current is applied from the outside to the wiring in the LSI to be measured, and the electromigration life of the wiring is measured from the change in resistance value. Yes.

  In addition, in the semiconductor integrated circuit described in Patent Document 2, a pilot wiring for inspection is provided in the LSI so as to share the main function part of the LSI and the IO terminal, and a burn-in test is performed by selecting the pilot wiring at the time of inspection. By doing so, defective LSIs are eliminated. In addition, in the semiconductor integrated circuit described in Patent Document 3, heating is promoted by applying direct current and alternating current to the internal wiring itself to be tested, instead of installing a heat source necessary for the acceleration test outside. The system is configured so that an accelerated test can be performed only by the test object.

  Patent Document 4 discloses a technique for highly accurately evaluating the electromigration resistance of a metal wiring having the same specifications that a semiconductor integrated circuit has. Further, Patent Document 5 discloses a semiconductor integrated circuit that can evaluate deterioration of characteristics of a semiconductor integrated circuit while being actually installed and operated in a system, thereby preventing an operation stop of the entire system. Techniques related to this are disclosed. Patent Document 6 discloses a technique related to a semiconductor integrated circuit capable of detecting an electromigration deterioration phenomenon in an LSI after shipment.

Japanese Patent Laid-Open No. 4-191684 JP-A-1-238134 JP 2005-536871 A Japanese Patent Laid-Open No. 11-67861 JP-A-11-27128 JP 2009-176832 A

  However, the techniques disclosed in Patent Documents 1 to 4 require an external test device such as a tester in order to detect the electromigration phenomenon. For this reason, these techniques can be applied only to the pre-shipment test of the semiconductor integrated circuit, and the deterioration phenomenon of the wiring due to electromigration in each semiconductor integrated circuit after the shipment cannot be detected.

The technique disclosed in Patent Document 5 is configured for the purpose of detecting the deterioration of the wiring. However, only the wiring portion to be measured is provided, and the resistance measuring device is provided outside the LSI for detecting the deterioration. Need to be connected. For this reason, there has been a problem that deterioration cannot be detected with a single LSI. In addition, there is a problem that a measure against the variation in wiring is not provided, and pessimism due to the variation cannot be excluded.
Moreover, since the technique disclosed in Patent Document 6 is configured to detect the disconnection of the wiring, it has not been possible to detect signs for performing preventive maintenance.

  Accordingly, an object of the present invention is to provide a semiconductor integrated circuit and a semiconductor integrated circuit testing method capable of detecting an electromigration deterioration phenomenon under actual operating conditions and detecting a failure sign.

  A semiconductor integrated circuit according to the present invention generates a count value based on a clock signal, resets the count value when a predetermined count value is reached, and delays the clock signal according to the count value of the counter circuit. A delay element that generates the delayed clock signal, a first flip-flop that is driven based on the clock signal and that inputs data that toggles every clock cycle of the clock signal, and an output signal from the first flip-flop , A second flip-flop that is driven based on the delayed clock signal and receives an output signal from the wiring, is driven based on the clock signal, and outputs an output signal from the first flip-flop. Input third flip-flop and outputs from the second and third flip-flops The Type each item, having, an exclusive OR circuit for outputting an exclusive OR of the output signal.

  The method for testing a semiconductor integrated circuit according to the present invention drives a first flip-flop based on a clock signal, inputs data that toggles every clock cycle of the clock signal, and outputs from the first flip-flop. A signal is input to the wiring, a count value is generated based on the clock signal, a delayed clock signal is generated by delaying the clock signal according to the count value, and a second flip-flop is generated based on the delayed clock signal. Driving, inputting an output signal from the wiring, driving a third flip-flop based on the clock signal, inputting an output signal from the first flip-flop, and inputting the second and third The exclusive OR of the output signals from the flip-flop is output.

  According to the present invention, it is possible to provide a semiconductor integrated circuit and a semiconductor integrated circuit testing method capable of detecting a degradation phenomenon of electromigration under actual operating conditions and detecting a sign of failure.

1 is a block diagram showing a semiconductor integrated circuit according to a first exemplary embodiment; 3 is a timing chart showing an operation of the semiconductor integrated circuit according to the first exemplary embodiment; It is a figure for demonstrating the principle of operation of the semiconductor integrated circuit concerning this invention. FIG. 3 is a block diagram showing a semiconductor integrated circuit according to a second embodiment; FIG. 6 is a block diagram showing a semiconductor integrated circuit according to a third embodiment;

Embodiment 1
Embodiments of the present invention will be described below with reference to the drawings.
FIG. 1 is a block diagram showing a semiconductor integrated circuit according to a first embodiment of the present invention (hereinafter, the semiconductor integrated circuit may be referred to as an EM degradation sensor). A semiconductor integrated circuit 10 shown in FIG. 1 is a semiconductor integrated circuit capable of detecting deterioration in the wiring 4. The wiring 4 is a wiring that is a detection target of deterioration caused by electromigration, and is driven by the buffer 8. For the purpose of detecting electromigration degradation, the wiring 4 is designed with the thinnest width and the thinnest film thickness permitted by the design rule of the process generation, for example.

  A data signal 51 is applied to the wiring 4 via the first flip-flop 1, and the transmission result is held by the second flip-flop 2. The first flip-flop 1 is driven based on a clock signal 52 input to the semiconductor integrated circuit 10. The second flip-flop 2 is driven based on a delayed clock signal 56 obtained by delaying the clock signal 52 input to the semiconductor integrated circuit 10 by the delay element 5. That is, by setting a predetermined delay value in the delay element 5, the second flip-flop 2 can be driven at a timing delayed by a predetermined time with respect to the timing of driving the first flip-flop 1.

  Here, the set delay value is not a constant value but can be increased or decreased by the count value given by the counter circuit 6. A clock signal 52 is input to the counter circuit 6, and a digital signal that increases or decreases in synchronization with the clock signal 52 is output to the delay control circuit 11. The delay control circuit 11 controls the delay element 5 so as to give the clock signal 52 a delay value corresponding to the digital signal (count value) of the counter circuit 6. For example, the digital signal generated by the counter circuit 6 is reset to 0 when counting up to a certain value and restarts counting up again.

  The third flip-flop 3 inputs the output of the first flip-flop 1 through the buffer 9. That is, the same logical result as that received by the second flip-flop 2 is input. Here, the second flip-flop 2 receives the delayed clock signal 56 via the delay element 5, whereas the third flip-flop 3 receives the clock signal 52 having the same phase as that of the first flip-flop 1. . The outputs of the second flip-flop 2 and the third flip-flop 3 are input to the exclusive OR circuit 7. The exclusive OR circuit 7 outputs “0” when the outputs of the second flip-flop 2 and the third flip-flop 3 match, and outputs “1” when they do not match. That is, if the second flip-flop 2 receives the data correctly, the output of the exclusive OR circuit 7 is always “0”.

  In this way, by combining the first flip-flop 1, the second flip-flop 2, the delay element 5, and the counter circuit 6, the timing of the second flip-flop 2 that captures the transmission signal via the wiring 4 is The clock signal 52 can be shifted every clock cycle. Further, by appropriately setting the initial delay value set by the delay element 5 and the delay fluctuation width of the delay given by the delay element 5 for each clock cycle, the signal is correctly transmitted at the initial stage of the count value given by the counter circuit 6. Capturing is performed, the count value is gradually incremented, and a setting that makes capture impossible at a certain count value is possible. In this case, “0” is initially output as an output signal of the exclusive OR circuit 7, and “1” is output from a certain count value. When these are arranged in time series, “0” is arranged at the initial count value, but “1” continues after being inverted from a certain count value.

  The output signal of the exclusive OR circuit 7 obtained in this way is stored in the detection result memory 13. The detection result memory 13 is composed of, for example, a shift register, and sequentially stores the output signal of the exclusive OR circuit 7 that is input. The length of the shift register is configured to be equal to or greater than the count value of the counter circuit 6, and can hold the output data of the exclusive OR circuit 7 for the cycle until the counter value is reset from 0.

  The detection result stored in the detection result memory 13 is compared with the detection result in the initial stage of manufacture stored in the initial value storage memory 12 in the comparison circuit 14. Since a certain error may occur in the circuit delay depending on the environmental conditions, a predetermined value (bias value) among the differences obtained by the comparison circuit 14 using the bias circuit 15 to cancel the error. ) The following differences are considered the same. The bias condition is input from the outside as a bias control signal 54. That is, the determination result is calculated as follows.

Abnormal: | Initial detection result-Current detection result |> Bias value Normal: | Initial detection result-Current detection result | ≤ Bias value

  The determination result obtained in this way is held in the result holding circuit 16. The result holding circuit 16 outputs a determination result 55. If it is determined that there is an abnormality, the subsequent comparison result in the comparison circuit 14, that is, the comparison result while the counter circuit 6 is counting up, is not a correct result, and thus the count-up is completed. In order to hold the data at the time of resetting, the count result of the counter circuit 6 is input, and the count holding timing is detected by the result holding circuit 16.

  The initial value storage memory 12 is controlled by the storage control circuit 17 and stores detection results at the initial stage of manufacture. The storage control circuit 17 inputs the initialization signal 53 and the count value of the counter circuit 6. The storage control circuit 17 controls the initial value storage memory 12 and copies the contents of the detection result memory 13 at the initial manufacturing stage to the initial value storage memory 12. At this time, since it is necessary that the detection result memory 13 has the detection results at the initial stage of manufacture, the storage control circuit 17 inputs the count value of the counter circuit 6 and acquires the timing. In addition, since the initial value storage memory 12 needs to retain the initial value during the operation period of the apparatus, the initial value storage memory 12 can be configured by, for example, a nonvolatile RAM so that data can be retained even when power is not supplied.

  In the deterioration phenomenon due to the electromigration of the wiring, the wiring does not break at a stretch, but at the initial stage of the deterioration, the deterioration becomes obvious in the form of an increase in the resistance value of the wiring. That is, in terms of a circuit, it is possible to measure in the form of an increase in the delay value. In the semiconductor integrated circuit (EM deterioration sensor) 10 according to the present embodiment, the delay information of the wiring 4 at the initial stage is stored, and the resistance information at the initial stage of deterioration is compared with the delay information of the wiring 4 at the present time. It becomes possible to detect an increase in value. Here, since the variation range of the resistance value of the wiring 4 varies depending on the process generation and environmental conditions, the variation variation range for each cycle controlled by the delay element 5 according to the conditions and the total count output by the counter circuit 6. The number is set for each product at the time of design. At this time, the delay variation width per cycle × the total count number of the counter circuit 6 = the total delay time in which the delay elements can be varied.

  Next, the operation of the semiconductor integrated circuit 10 according to the present embodiment will be described with reference to FIG. FIG. 2 is a timing chart for explaining the operation of the semiconductor integrated circuit 10 according to the present embodiment. In this embodiment, in order to simplify the explanation, the output of the counter circuit 6 is a 3-bit digital signal. Further, the counter value of the counter circuit 6 starts from “000” at the beginning and sequentially counts up. Then, it is reset when it reaches “111”, and is sequentially counted up again from “000”. As shown in FIG. 2, the output of the counter circuit 6 is output in synchronization with the clock signal 52.

  The delayed clock signal 56 output from the delay element 5 is delayed from the clock signal 52 by the width (delay value) indicated by the arrow in FIG. The delay value of the delayed clock signal 56 with respect to the clock signal 52 increases as the count value is counted up.

  As shown in FIG. 2, the output of the first flip-flop 1 is output in synchronization with the clock signal 52. The output of the second flip-flop 2 is output in synchronization with the delayed clock signal 56. The output of the third flip-flop 3 is output in synchronization with the clock signal 52.

  As shown in FIG. 2, at the timing T1, the clock signal 52 and the delayed clock signal 56 rise simultaneously. Then, the data signal “1” (high level) is output from the first flip-flop 1 at the timing of T1. Then, the clock signal 52 rises at the timing T2, and the third flip-flop 3 receives the data signal “1” from the first flip-flop 1 and outputs the data signal “1”. Further, the delayed clock signal 56 rises at a timing T2 ′ delayed by a predetermined time from the timing T2. At the timing T2 ′, the second flip-flop 2 receives the data signal “1” from the first flip-flop 1 and outputs the data signal “1”.

  At this time, since the data signal “1” output from the second flip-flop 2 and the data signal “1” output from the third flip-flop 3 match, the output of the exclusive OR circuit 7 is “0” (low level). Since the output of the exclusive OR circuit 7 is “0”, the detection result memory 13 outputs “xxxxxxxx0”.

  Similarly, the data signal “0” is output from the first flip-flop 1 at the timing of T2. Then, the clock signal 52 rises at the timing T3, and the third flip-flop 3 receives the data signal “0” from the first flip-flop 1 and outputs the data signal “0”. Further, the delayed clock signal 56 rises at a timing T3 ′ delayed by a predetermined time from the timing T3. At the timing T3 ′, the second flip-flop 2 receives the data signal “0” from the first flip-flop 1 and outputs the data signal “0”.

At this time, since the data signal “0” output from the second flip-flop 2 and the data signal “0” output from the third flip-flop 3 match, the output of the exclusive OR circuit 7 is It becomes “0”. Since the output of the exclusive OR circuit 7 is “0”, the detection result memory 13 outputs “xxxxxxxx00”.
Thereafter, as long as the second flip-flop 2 correctly receives the data signal, the output of the exclusive OR circuit 7 becomes “0”.

  The data signal “0” is output from the first flip-flop 1 at the timing of T6. At time T7, the clock signal 52 rises, and the third flip-flop 3 receives the data signal “0” from the first flip-flop 1 and outputs the data signal “0”. On the other hand, the delayed clock signal 56 rises at a timing T7 ′ delayed by a predetermined time from the timing T7. However, in this case, since the second flip-flop 2 cannot correctly receive the data signal “0” from the first flip-flop 1 at the timing of T7 ′, the data output from the second flip-flop 2 The signal is “1”.

  At this time, since the data signal “1” output from the second flip-flop 2 and the data signal “0” output from the third flip-flop 3 do not match, the output of the exclusive OR circuit 7 is “1”. "Become. Since the output of the exclusive OR circuit 7 is “1”, the detection result memory 13 outputs “xx000001”.

  Similarly, the data signal “1” is output from the first flip-flop 1 at the timing of T7. At time T8, the clock signal 52 rises, and the third flip-flop 3 receives the data signal “1” from the first flip-flop 1 and outputs the data signal “1”. On the other hand, the delayed clock signal 56 rises at a timing T8 ′ delayed by a predetermined time from the timing T8. However, in this case as well, the second flip-flop 2 cannot correctly receive the data signal “1” from the first flip-flop 1 at the timing T8 ′. The signal is “0”.

  At this time, since the data signal “0” output from the second flip-flop 2 and the data signal “1” output from the third flip-flop 3 do not match, the output of the exclusive OR circuit 7 is “1”. "Become. Since the output of the exclusive OR circuit 7 is “1”, the detection result memory 13 outputs “x0000011”.

  Thus, since the delay value of the delay element 5 is small at the initial stage, the second flip-flop 2 can correctly receive the data signal from the first flip-flop 1. Therefore, the output of the exclusive OR circuit 7 is “0”. However, at the timing T7 ′, the second flip-flop 2 fails to receive the data signal, and as a result, the output of the exclusive OR circuit 7 becomes “1”. The data signal output from the second flip-flop 2 is shifted by one cycle compared to the data signal output from the third flip-flop 3. Therefore, thereafter, the output of the exclusive OR circuit 7 is fixed to “1”. As a result, the detection result memory 13 gradually holds the bit pattern in which “0” and “1” are arranged in the initial stage, and the bit pattern of this result is held in the eighth cycle. At the same time, comparison with the output of the initial value storage memory 12 is executed by the comparison circuit 14 and the bias circuit 15, and the contents of the result holding circuit 16 are rewritten at the timing of the counter output “111”.

  FIG. 3 is a diagram for explaining the operation principle of the semiconductor integrated circuit (EM deterioration sensor) 10 according to the present embodiment. The delay clock 56 output from the delay element 5 shown in FIG. 3 shows a state in which the delay value that the delay element 5 gives to the clock signal 52 increases as the count value of the counter circuit 6 increases. That is, T1 ′ of the delay clock 56 shown in FIG. 3 corresponds to T1 ′ of the delay clock 56 of FIG. 2, and T8 ′ of the delay clock 56 shown in FIG. 3 corresponds to T8 ′ of the delay clock 56 of FIG. Yes.

  As shown in FIG. 3, when the resistance value of the wiring 4 is low (initial resistance value), the delay is smaller than that after the resistance value of the wiring 4 is increased. Therefore, when the resistance value of the wiring 4 is low, the second flip-flop 2 can normally receive the data signal from the first flip-flop 1 until the timing T4 ′. However, after the timing of T5 ′, the data signal from the first flip-flop 1 cannot be normally received because the delay of the wiring 4 is small. At this time, the output of the detection result memory 13 is “00001111”.

  On the other hand, after the resistance value of the wiring 4 is increased, the second flip-flop 2 can normally receive the data signal from the first flip-flop 1 until the timing T6 ′. However, after the timing T7 ′, the data signal from the first flip-flop 1 cannot be normally received. At this time, the output of the detection result memory 13 is “00000011”.

  In this way, the delay of the wiring 4 increases as the resistance value of the wiring 4 increases, and the deterioration state of the wiring 4 can be detected by detecting this increase in delay using the delay amount of the delay clock signal 56. it can. In other words, the output (“000011111”) of the detection result memory 13 in the initial state (low resistance value) of the wiring 4 is stored in the initial value storage memory, and after this value and the resistance value of the wiring 4 increase. By comparing the output (“00000011”) of the detection result memory 13 with the comparison circuit 14, the deterioration state of the wiring 4 can be detected.

  With the semiconductor integrated circuit according to the present embodiment described above, it is possible to provide a semiconductor integrated circuit capable of detecting a deterioration phenomenon of electromigration under actual operating conditions and detecting signs of failure. It becomes. In other words, by incorporating a method of comparing the resistance of the wiring 4 at the initial stage of manufacture of the semiconductor integrated circuit and the resistance of the current wiring 4 at the time of operation, it is possible to detect a change in resistance value that is an indication of wiring deterioration due to electromigration Can do.

  The techniques disclosed in Patent Documents 1 to 4 require a test device such as a tester outside in order to detect the electromigration phenomenon. For this reason, these techniques can be applied only to the pre-shipment test of the semiconductor integrated circuit, and the electromigration deterioration phenomenon in each semiconductor integrated circuit after the shipment cannot be detected. In addition, since the techniques disclosed in Patent Documents 5 and 6 are configured to perform only disconnection detection, it is not possible to detect signs for performing preventive maintenance. However, the semiconductor integrated circuit according to the present embodiment incorporates a method of comparing the resistance of the wiring 4 at the initial stage of manufacture of the semiconductor integrated circuit and the resistance of the current wiring 4 during operation. Therefore, it is possible to detect an electromigration deterioration phenomenon in each semiconductor integrated circuit after shipment, and it is possible to detect a change in resistance value that is an indication of wiring deterioration.

The semiconductor integrated circuit testing method according to the present embodiment includes the following steps.
A step of driving the first flip-flop 1 based on the clock signal 52 and inputting data to be toggled every clock cycle of the clock signal 52. A step of inputting an output signal from the first flip-flop 1 to the wiring 4. A step of generating a count value based on the clock signal 52 and generating a delayed clock signal 56 obtained by delaying the clock signal according to the count value. A step of driving the second flip-flop 2 based on the delayed clock signal 56 and inputting an output signal from the wiring 4. A step of driving the third flip-flop 3 based on the clock signal 52 and inputting an output signal from the first flip-flop 1. A step of outputting an exclusive OR of output signals from the second and third flip-flops 2 and 3;

  Note that the semiconductor integrated circuit testing method according to the present embodiment may include the following steps. Holding the output of the exclusive OR. A step of comparing the output of the exclusive OR and the output of the exclusive OR in the initial stage of manufacturing the wiring 4 to determine the deterioration of the wiring 4.

  In the semiconductor integrated circuit testing method according to the present embodiment, the same effects as those of the semiconductor integrated circuit can be obtained.

Embodiment 2
The second embodiment of the present invention will be described below. FIG. 4 is a block diagram for explaining the semiconductor integrated circuit 20 according to the present embodiment. The semiconductor integrated circuit 20 according to the present embodiment includes a plurality of EM deterioration sensors 10_1 to 10_n (n is a positive integer). The data signal 51, the clock signal 52, and the initialization signal 53 are supplied to the EM deterioration sensors 10_1 to 10_n. Here, the data signal 51, the clock signal 52, and the initialization signal 53 supplied to the EM deterioration sensors 10_1 to 10_n are the same signal.

  On the other hand, the bias control signal 54 is given a different value for each of the EM deterioration sensors 10_1 to 10_n. The detection results of the EM deterioration sensors 10_1 to 10_n are output to the totaling circuit 21. The aggregation circuit 21 counts the determination results output from the EM deterioration sensors 10_1 to 10_n, and outputs an error signal based on the determination results. For example, the counting circuit 21 outputs the error signal 57 when the determination result that is abnormal is larger than the determination result that is normal. The EM deterioration sensors 10_1 to 10_n used in the semiconductor integrated circuit 20 according to the present embodiment have the same configuration as that of the semiconductor integrated circuit (EM deterioration sensor) 10 according to the first embodiment, and thus detailed description thereof is omitted. To do.

  The semiconductor integrated circuit 20 according to the present embodiment includes a plurality of EM deterioration sensors 10_1 to 10_n having the same configuration, and the determination results are totaled by the totaling circuit 21, and a final error can be determined by majority vote. . By adopting such a configuration, even if some EM deterioration sensors malfunction, it is possible to eliminate the influence.

  In recent semiconductor processes, variations in wiring width and film thickness tend to increase. Therefore, when only one set of the EM deterioration sensor 10 according to the first embodiment is provided, if the wiring width of the wiring 4 to be detected and the film thickness of the wiring 4 vary, all the other wirings have a sufficient lifetime. Even if this is maintained, the failure is detected earlier than the expected life. In contrast, the semiconductor integrated circuit 20 according to the present embodiment includes a plurality of EM deterioration sensors 10_1 to 10_n, and generates a final error signal 57 by majority from the determination results of the EM deterioration sensors 10_1 to 10_n. doing. For this reason, even if there is a variation in the wiring width or the film thickness of the wiring 4 to be detected, the detection result of the EM deterioration sensor having a variation in the wiring can be eliminated, so that the wiring can be more accurately performed. Degradation can be detected.

Embodiment 3
The third embodiment of the present invention will be described below. FIG. 5 is a block diagram for explaining the semiconductor integrated circuit 30 according to the present embodiment. The semiconductor integrated circuit 30 according to the present embodiment includes some of the components included in the semiconductor integrated circuit 10 according to the first embodiment shown in FIG.

  That is, the semiconductor integrated circuit 30 according to the present embodiment shown in FIG. 5 generates a count value based on the clock signal 52 and resets the count value when the count value reaches a predetermined count value. A delay element 5 that generates a delayed clock signal 56 obtained by delaying the clock signal 52 according to the count value, and a first flip-flop that is driven based on the clock signal 52 and inputs data that toggles every clock cycle of the clock signal 52. 1 is provided. Further, based on the wiring 4 that inputs the output signal from the first flip-flop 1, the second flip-flop 2 that inputs the output signal from the wiring 4, and the clock signal 52. The third flip-flop 3 that inputs the output signal from the first flip-flop 1 and the output signals from the second and third flip-flops 2 and 3 are input, and the exclusive OR of the output signals is input. And an exclusive OR circuit 7 for outputting. Note that the operation of the semiconductor integrated circuit 30 according to the present embodiment is basically the same as the operation of the semiconductor integrated circuit 10 according to the first embodiment, and therefore redundant description is omitted.

  Also in the semiconductor integrated circuit 30 according to the present embodiment, it is possible to provide a semiconductor integrated circuit capable of detecting a deterioration phenomenon of electromigration under actual operating conditions and detecting signs of failure. .

  Although the present invention has been described with reference to the above embodiment, the present invention is not limited to the configuration of the above embodiment, and can be made by those skilled in the art within the scope of the invention of the claims of the claims of the present application. It goes without saying that various modifications, corrections, and combinations are included.

DESCRIPTION OF SYMBOLS 1 1st flip-flop 2 2nd flip-flop 3 3rd flip-flop 4 Wiring (deterioration detection object)
5 Delay element 6 Counter circuit 7 Exclusive OR circuit 8, 9 Buffer 10 Semiconductor integrated circuit (EM degradation sensor)
11 Delay control circuit 12 Initial value storage memory 13 Detection result memory 14 Comparison circuit 15 Bias circuit 16 Result holding circuit 17 Storage control circuit 20 Semiconductor integrated circuit 21 Aggregation circuit 30 Semiconductor integrated circuit (EM deterioration sensor)
51 Data signal 52 Clock signal 53 Initialization signal 54 Bias control signal 55 Determination result 56 Delayed clock signal 57 Error signal

Claims (10)

A counter circuit that generates a count value based on the clock signal and resets the count value when a predetermined count value is reached;
A delay element that generates a delayed clock signal obtained by delaying the clock signal in accordance with a count value of the counter circuit;
A first flip-flop that is driven based on the clock signal and inputs data that toggles every clock cycle of the clock signal;
Wiring for inputting an output signal from the first flip-flop;
A second flip-flop driven based on the delayed clock signal and receiving an output signal from the wiring;
A third flip-flop driven based on the clock signal and receiving an output signal from the first flip-flop;
An exclusive OR circuit that inputs an output signal from each of the second and third flip-flops and outputs an exclusive OR of the output signals;
A semiconductor integrated circuit. A detection result memory for holding the output of the exclusive OR circuit;
An initial value storage memory for holding an output of the exclusive OR circuit at the initial stage of manufacturing the wiring;
A comparison circuit for comparing the output of the detection result memory and the output of the initial value storage memory;
The semiconductor integrated circuit according to claim 1, further comprising: a result holding circuit that holds a determination result relating to deterioration of the wiring obtained based on an output signal of the comparison circuit. A storage control circuit that inputs an initialization signal and a count value of the counter circuit, and outputs a signal instructing to copy the value of the detection result memory to the initial value storage memory, to the initial value storage memory;
The semiconductor integrated circuit according to claim 2, further comprising: a bias circuit that inputs a bias control signal and an output signal of the comparison circuit, and corrects a value of the output signal of the comparison circuit according to a bias value.   When the difference between the output of the detection result memory obtained by the comparison circuit and the output of the initial value storage memory is equal to or less than a predetermined value, the bias circuit outputs the detection result memory and the initial value storage memory. The semiconductor integrated circuit according to claim 3, wherein the outputs are regarded as the same.   The result holding circuit holds a determination result that is normal when a difference between an output of the detection result memory and an output of the initial value storage memory is a predetermined value or less, and outputs the detection result memory and the output 5. The semiconductor integrated circuit according to claim 2, wherein a determination result indicating an abnormality is held when a difference from an output of the initial value storage memory is larger than a predetermined value. 6. A plurality of semiconductor integrated circuits according to any one of claims 2 to 5;
A semiconductor integrated circuit comprising: a totaling circuit that inputs a determination result regarding deterioration of the wiring from the plurality of semiconductor integrated circuits and outputs an error signal based on the determination result.   The summing circuit outputs an error signal when the number of semiconductor integrated circuits determined to be abnormal exceeds the number of semiconductor integrated circuits determined to be normal among the determination results regarding the deterioration of the wiring. Semiconductor integrated circuit.   The semiconductor integrated circuit according to claim 1, wherein the wiring is the thinnest wiring in a design rule of a process used for manufacturing the semiconductor integrated circuit. The first flip-flop is driven based on the clock signal, and data that toggles every clock cycle of the clock signal is input.
The output signal from the first flip-flop is input to the wiring,
Generate a count value based on the clock signal, generate a delayed clock signal obtained by delaying the clock signal according to the count value,
Based on the delayed clock signal, the second flip-flop is driven to input an output signal from the wiring,
Driving a third flip-flop based on the clock signal, and inputting an output signal from the first flip-flop,
A test method for a semiconductor integrated circuit, which outputs an exclusive OR of output signals from the second and third flip-flops. Holding the output of the exclusive OR,
The test method for a semiconductor integrated circuit according to claim 9, wherein the deterioration of the wiring is determined by comparing the output of the exclusive OR and the output of the exclusive OR in the initial stage of manufacturing the wiring.

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