JP5381637B2 - Liquid crystal display device, electronic apparatus, and driving method - Google Patents

Description

  The present invention relates to a liquid crystal display device, an electronic apparatus, and a driving method.

  An active matrix liquid crystal display device is configured by disposing a common electrode on a counter substrate opposite to pixel electrodes arranged in a matrix on a substrate, and filling the liquid crystal between these substrates. The

Japanese Patent Laid-Open No. 7-028091 JP-A-8-015723

  By the way, the liquid crystal display device has viewing angle dependency. That is, the appearance of the display screen changes depending on the viewing angle of the display screen. Therefore, it is desired to improve the viewing angle dependency of the display state.

  An object of the present invention is to reduce the viewing angle dependency in a liquid crystal display device.

In order to solve the above problems, according to the present invention,
Liquid crystal display device
A first scan line and a second scan line arranged adjacently along a first direction;
A signal line provided along a second direction orthogonal to the first direction;
A first pixel electrode and a second pixel electrode connected to the first scanning line and the signal line and disposed along the first direction, wherein the first pixel electrode and the second pixel electrode; A first display pixel having areas different from each other by the second pixel electrode;
A third pixel disposed adjacent to the first display pixel in the second direction, connected to the second scanning line and the signal line, and disposed along the first direction; A third pixel electrode having the same area as the second pixel electrode, and the fourth pixel electrode having the same area as the first pixel electrode. The third pixel electrode is disposed adjacent to the first pixel electrode along the second direction, and the fourth pixel electrode is disposed on the second pixel electrode. A second display pixel disposed adjacently along the direction;
An auxiliary electrode line provided in a plane overlapping with one of the first pixel electrode and the fourth pixel electrode, or the second pixel electrode and the third pixel electrode;
I have a,
The auxiliary electrode line is (1) provided in a position overlapping with the first pixel electrode and the fourth pixel electrode in a plane, and is planar with the second pixel electrode and the third pixel electrode. (2) The first pixel electrode and the fourth pixel are provided at a position that overlaps the second pixel electrode and the third pixel electrode in a plane. It is determined that the electrode is provided at a position that does not overlap the electrode in a planar manner .

Preferably,
When the auxiliary electrode line is provided at a position overlapping the first pixel electrode and the fourth pixel electrode in a plane, the auxiliary electrode line overlaps the second pixel electrode and the third pixel electrode in a plane. Provided at a position where the second pixel electrode and the third pixel electrode are planarly overlapped with each other, the first pixel electrode and the fourth pixel electrode are planarly overlapped with each other. It was decided that it was provided at a position that would not be.
Preferably,
A second effective voltage applied to the second pixel electrode is made different from a first effective voltage applied to the first pixel electrode, and a third effective voltage applied to the third pixel electrode is changed. A voltage application circuit for applying a voltage signal to the auxiliary electrode line that makes the fourth effective voltage applied to the fourth pixel electrode different from the effective voltage is provided.
Preferably,
A scanning driver for sequentially selecting the first scanning line and the second scanning line for each selection period;
The voltage signal has a waveform signal having the selection period as a half cycle.
Preferably,
A common electrode facing the first pixel electrode, the second pixel electrode, the third pixel electrode, and the fourth pixel electrode through a liquid crystal layer;
A data driver that outputs, to the plurality of signal lines, gradation signals whose polarity is inverted in synchronization with the selection period with reference to the potential of the common electrode;
Have
The second pixel electrode has a larger area than the first pixel electrode;
The auxiliary electrode line is provided at a position overlapping the second pixel electrode and the third pixel electrode in a plane,
The voltage signal has a waveform signal in phase with the gradation signal.
Preferably,
A common electrode facing the first pixel electrode, the second pixel electrode, the third pixel electrode, and the fourth pixel electrode through a liquid crystal layer;
A data driver that outputs to the plurality of signal lines gradation signals whose polarity is inverted in synchronization with the selection period with reference to the voltage of the common electrode;
Have
The second pixel electrode has a smaller area than the first pixel electrode;
The auxiliary electrode line is provided at a position overlapping the second pixel electrode and the third pixel electrode in a plane,
The voltage signal has a waveform signal having a phase opposite to that of the gradation signal.
Preferably,
A third display pixel disposed adjacent to the first display pixel along the first direction; and a third display pixel disposed adjacent to the third display pixel in the second direction. A fourth display pixel disposed adjacent to the second display pixel along the first direction,
The third display pixel includes a fifth pixel electrode and a sixth pixel electrode arranged along the first direction, and the fifth pixel electrode is connected to the second pixel electrode. The sixth pixel electrode has the same area as the first pixel electrode;
The fourth display pixel includes a seventh pixel electrode and an eighth pixel electrode arranged along the first direction, and the seventh pixel electrode is connected to the first pixel electrode. The eighth pixel electrode has the same area as the second pixel electrode;
The seventh pixel electrode is disposed adjacent to the fifth pixel electrode along the second direction, and the eighth pixel electrode is disposed in the second direction with respect to the sixth pixel electrode. Arranged adjacent to each other,
The second pixel electrode and the fifth pixel electrode are disposed adjacent to each other along the first direction,
The fourth pixel electrode and the seventh pixel electrode are disposed adjacent to each other along the first direction.
Preferably,
The auxiliary electrode line is provided at a position overlapping in plan with respect to one of the fifth pixel electrode and the eighth pixel electrode, or the sixth pixel electrode and the seventh pixel electrode. It was decided that
Preferably,
A fifth display pixel disposed adjacent to the second display pixel along the second direction; and a fifth display pixel disposed adjacent to the fifth display pixel along the second direction. A sixth display pixel provided,
The fifth display pixel includes a ninth pixel electrode and a tenth pixel electrode arranged along the first direction, and the ninth pixel electrode is connected to the second pixel electrode. The tenth pixel electrode has the same area as the first pixel electrode;
The sixth display pixel includes an eleventh pixel electrode and a twelfth pixel electrode arranged along the first direction, and the eleventh pixel electrode is connected to the first pixel electrode. The twelfth pixel electrode has the same area as the second pixel electrode;
The eleventh pixel electrode is disposed adjacent to the ninth pixel electrode along the second direction, and the twelfth pixel electrode is disposed in the second direction with respect to the tenth pixel electrode. Arranged adjacent to each other,
The ninth pixel electrode is disposed adjacent to the third pixel electrode along the second direction, and the tenth pixel electrode is disposed in the second direction with respect to the fourth pixel electrode. Are arranged adjacent to each other.
Preferably,
The auxiliary electrode line is provided at a position overlapping in plan with one of the ninth pixel electrode and the twelfth pixel electrode, or the tenth pixel electrode and the eleventh pixel electrode. It was decided that

  In order to solve the above problems, according to the present invention, an electronic device includes the liquid crystal display device.

In order to solve the above problems, according to the present invention,
A driving method for driving the liquid crystal display panel,
A first scanning line and a second scanning line arranged adjacently along a first direction; a signal line provided along a second direction perpendicular to the first direction; and the signal A first pixel electrode and a second pixel electrode connected to the first scanning line and disposed along the first direction, wherein the second pixel electrode is the first pixel electrode. A first display pixel having an area larger than that of the pixel electrode, and disposed adjacent to the first display pixel in the second direction, connected to the signal line and the second scanning line, A third pixel electrode and a fourth pixel electrode disposed along the first direction, the third pixel electrode having the same area as the second pixel electrode; The fourth pixel electrode has the same area as the first pixel electrode, and the third pixel electrode extends along the second direction with respect to the first pixel electrode. A second display pixel disposed adjacent to the second pixel electrode along the second direction with respect to the second pixel electrode; and the first pixel. The second pixel is provided at a position that does not overlap the second pixel electrode and the third pixel electrode when it is provided at a position that overlaps the electrode and the fourth pixel electrode. An auxiliary electrode line provided at a position that does not overlap the first pixel electrode and the fourth pixel electrode when provided in a position that overlaps the electrode and the third pixel electrode in a plane; A driving method for driving a liquid crystal display panel having a first electrode, a second pixel electrode, a third pixel electrode, and a common electrode facing the fourth pixel electrode through a liquid crystal layer Because
A scanning line driving step of sequentially selecting the first scanning line and the second scanning line for each selection period;
A common electrode driving step of setting the common electrode to a constant potential;
A signal line driving step for outputting to the signal line a gradation signal whose polarity is inverted in synchronization with the selection period with reference to the potential of the common electrode;
An auxiliary electrode line that has a waveform signal with the selection period as a half cycle and applies a voltage signal that makes the effective voltage of the second pixel electrode different from the effective voltage of the first pixel electrode. A driving step;
It was decided to include.

Preferably,
The auxiliary electrode line driving step includes a first voltage signal setting step of setting the voltage signal to a waveform signal in phase with the gradation signal.
Preferably,
The auxiliary electrode line driving step includes a second voltage signal setting step of setting the voltage signal to a waveform signal having a phase opposite to that of the gradation signal.

  According to the present invention, it is possible to reduce the viewing angle dependency of the liquid crystal display device and to suppress the occurrence of so-called gradation inversion.

It is a perspective view of the electronic device in 1st embodiment to which this invention is applied. It is a disassembled perspective view of a display system. It is a block diagram which shows the structure of a liquid crystal display device. It is a figure which shows the equivalent circuit of one display pixel provided in a liquid crystal display panel. It is a top view of one display pixel provided in a liquid crystal display panel. It is arrow sectional drawing of the surface along the VI-VI line of FIG. It is arrow sectional drawing of the surface along the VII-VII line of FIG. It is arrow sectional drawing of the surface along the VIII-VIII line of FIG. It is arrow sectional drawing of the surface along the IX-IX line of FIG. It is a timing chart figure which shows the signal waveform of each signal. It is a block diagram which shows the structure of a scanning driver. It is a circuit diagram which shows an example of a circuit structure of a holding circuit. It is a block diagram which shows the structure of a data driver. It is a circuit diagram which shows an example of the circuit structure of a gradation reference voltage generation circuit and a DA converter. It is a timing chart of the voltage regarding a small subpixel. It is a timing chart of the voltage regarding a large subpixel. It is the graph which showed the viewing angle dependence of the liquid crystal in the conventional liquid crystal display panel. It is the graph which showed the viewing angle dependence of the liquid crystal in the liquid crystal display panel of this embodiment. It is a figure which shows an example of the light transmittance characteristic of the liquid crystal which overlaps with a small subpixel electrode, and the light transmittance characteristic of the liquid crystal which overlaps with a large subpixel electrode. It is a figure which shows an example of the light transmittance characteristic of the liquid crystal which overlaps with a small subpixel electrode, and the light transmittance characteristic of the liquid crystal which overlaps with a large subpixel electrode. It is a top view which shows the 1st example of the arrangement | sequence of a display pixel. It is a top view which shows the 2nd example of the arrangement | sequence of a display pixel. It is a top view which shows the 3rd example of the arrangement | sequence of a display pixel. It is a top view which shows the 4th example of the arrangement | sequence of a display pixel. It is a top view of one display pixel in a second embodiment. In the same embodiment, it is a timing chart which shows the signal waveform of each signal. It is a figure which shows an example of the light transmittance characteristic of the liquid crystal which overlaps with a small subpixel electrode, and the light transmittance characteristic of the liquid crystal which overlaps with a large subpixel electrode. It is a figure which shows an example of the light transmittance characteristic of the liquid crystal which overlaps with a small subpixel electrode, and the light transmittance characteristic of the liquid crystal which overlaps with a large subpixel electrode. In the same embodiment, it is a figure which shows an example of the light transmittance characteristic of the liquid crystal which overlaps with a small subpixel electrode, and the light transmittance characteristic of the liquid crystal which overlaps with a large subpixel electrode. In the same embodiment, it is a figure which shows an example of the light transmittance characteristic of the liquid crystal which overlaps with a small subpixel electrode, and the light transmittance characteristic of the liquid crystal which overlaps with a large subpixel electrode. In the embodiment, it is a top view which shows an example of the arrangement | sequence of a display pixel.

  EMBODIMENT OF THE INVENTION Below, the form for implementing this invention is demonstrated using drawing. However, although various technically preferable limitations for implementing the present invention are given to the embodiments described below, the scope of the invention is not limited to the following embodiments and illustrated examples.

<First embodiment>
First, a first embodiment of the present invention will be described.
FIG. 1 is a perspective view of the electronic device 100. As shown in FIG. 1, a display system 110 is mounted on the electronic device 100.

  FIG. 2 is an exploded perspective view of the display system 110. The display system 110 includes the liquid crystal display device 1, a backlight 130, and the like.

  The liquid crystal display device 1 includes a liquid crystal display panel 10, an IC chip 81, and the like. The liquid crystal display panel 10 is of an active matrix driving method. The liquid crystal display panel 10 includes a transistor array substrate 10a and a counter substrate 10b. The counter substrate 10b faces the transistor array substrate 10a. A seal material is provided in a frame shape along the edge portion of the counter substrate 10b, and the seal material is sandwiched between the counter substrate 10b and the transistor array substrate 10a, and the transistor array substrate 10a and the counter substrate 10b are separated by the seal material. It is glued. A liquid crystal 10g (shown in FIGS. 6 to 9 and the like) is sealed between the transistor array substrate 10a and the counter substrate 10b and inside the sealing material. A polarizing plate 10e is adhered on the counter substrate 10b.

  The size of the transistor array substrate 10a is larger than the size of the counter substrate 10b, and a part of the transistor array substrate 10a protrudes from the edge of the counter substrate 10b. A portion where the transistor array substrate 10a and the counter substrate 10b overlap is a display area. In the display area, a plurality of scanning lines 16 (shown in FIG. 3 and the like) are provided, and a plurality of signal lines 15 (shown in FIG. 3 and the like) are provided. In the display area, a switch element 212, a switch element 222 (shown in FIG. 4 and the like), a small subpixel electrode 211, and a large subpixel electrode 221 (shown in FIG. 4 and the like) are formed. The switch element 212, the switch element 222, the small subpixel electrode 211, and the large subpixel electrode 221 are provided for each display pixel. A transparent common electrode 14 (shown in FIG. 4 and the like) is formed on the surface of the counter substrate 10b that faces the transistor array substrate 10a.

An IC chip 81 is surface-mounted on the non-display area 10c that protrudes from the edge of the counter substrate 10b in the transistor array substrate 10a. The common electrode 14, the scanning line 16, and the signal line 15 are connected to the IC chip 81 through a lead wiring. The IC chip 81 includes a drive device 90 (shown in FIG. 3).
Further, a flexible circuit sheet (so-called FPC: Flexible Printed Circuit) 10d is joined to the non-display area 10c. A flexible circuit sheet 10 d is connected to a main circuit board built in the electronic device 100. The video signal (image signal) output by the main circuit board is transferred to the driving device 90 of the IC chip 81 by the flexible circuit sheet 10d. The driving device 90 drives the liquid crystal display panel 10 based on the video signal, and an image is displayed on the liquid crystal display panel 10.

  The backlight 130 faces the surface opposite to the display surface of the liquid crystal display panel 10, that is, faces the transistor array substrate 10a. The backlight 130 emits light toward the liquid crystal display panel 10. The backlight 130 is, for example, a configuration in which point light emitting elements such as LEDs are arranged in a matrix, a combination of point light emitting elements such as LEDs arranged in a row and a light guide plate, a linear light emitting element such as a cold cathode tube, and the like. A combination of light guide plates or a surface light emitting element such as an electroluminescence element is used. A flexible circuit sheet 131 is connected to the backlight 130. The flexible circuit sheet 131 is connected to a main circuit board built in the electronic device 100. When power is supplied from the main circuit board to the backlight 130 by the flexible circuit sheet 131, the backlight 130 emits light.

FIG. 3 is a block diagram showing a configuration of the liquid crystal display device 1. The liquid crystal display device 1 includes a liquid crystal display panel 10 and a driving device 90.
The liquid crystal display panel 10 is provided with a plurality of scanning lines 16 extending in the horizontal direction (horizontal direction) in parallel to each other. The plurality of signal lines 15 are provided so as to be orthogonal to the plurality of scanning lines 16 and to be parallel to each other and extend in the vertical direction (vertical direction). Display pixels 200 are provided in the vicinity of intersections between the signal lines 15 and the scanning lines 16. These display pixels 200 are arranged in a matrix.

  FIG. 4 is an equivalent circuit diagram of one display pixel 200 provided in the liquid crystal display panel 10.

  A display pixel 200 provided at each intersection of the signal line 15 and the scanning line 16 includes a small sub-pixel 210 and a large sub-pixel 220.

The small sub-pixel 210 is provided with a first liquid crystal capacitor 17a, a first auxiliary capacitor (first auxiliary capacitor) 18a, and a switch element 212. The switch element 212 is a thin film transistor. A gate electrode 213 of the switch element 212 is connected to the scanning line 16. A source electrode 218 of the switch element 212 is connected to the signal line 15. A first liquid crystal capacitor 17 a and a first auxiliary capacitor 18 a are connected in parallel between the drain electrode 217 of the switch element 212 and the output terminal of the common voltage generation circuit 60.
The switch element 212 opens and closes the connection between the first auxiliary capacitor 18 a and the first liquid crystal capacitor 17 a and the signal line 15.

The large sub-pixel 220 is provided with a second liquid crystal capacitor 17b, a second auxiliary capacitor (second auxiliary capacitor) 18b, a third auxiliary capacitor (third auxiliary capacitor) 18c, and a switch element 222. The switch element 222 is a thin film transistor. A gate electrode 223 of the switch element 222 is connected to the scanning line 16. A source electrode 228 of the switch element 222 is connected to the signal line 15. Between the drain electrode 227 of the switch element 222 and the output terminal of the common voltage generating circuit 60, the second liquid crystal capacitor 17b and the second auxiliary capacitor 18b are connected in parallel. The drain electrode 227 of the switch element 222 is connected to the output terminal of the waveform signal generation circuit 70 as a voltage application circuit via the third auxiliary capacitor 18c.
The switch element 222 opens and closes the connection between the second auxiliary capacitor 18b, the third auxiliary capacitor 18c, the second liquid crystal capacitor 17b, and the signal line 15.
The electrodes 217 and 227 may be source electrodes, and the electrodes 218 and 228 may be drain electrodes.

  In the present embodiment, the switch element 212 is a first switch element, and the switch element 222 is a second switch element.

The common voltage generation circuit 60 applies the common voltage Vcom to the first liquid crystal capacitor 17a, the first auxiliary capacitor 18a, the second liquid crystal capacitor 17b, and the second auxiliary capacitor 18b.
The waveform signal generation circuit 70 outputs a waveform signal Vd having a pulse waveform to the third auxiliary capacitor 18c.

FIG. 5 is a plan view of the display pixel 200 when the transistor array substrate 10a is viewed from the counter substrate 10b side.
The first auxiliary capacitor 18a shown in FIG. 4 includes the auxiliary capacitance line 191 and the small subpixel electrode 211 shown in FIG. In the present embodiment, the small subpixel electrode 211 is the first pixel electrode.
The second auxiliary capacitor 18b shown in FIG. 4 includes an auxiliary capacitance line 191 and a large subpixel electrode 221.
The third auxiliary capacitor 18c shown in FIG. 4 includes an auxiliary electrode line 192 and a large subpixel electrode 221. In the present embodiment, the large subpixel electrode 221 is the second pixel electrode.
The first liquid crystal capacitor 17a shown in FIG. 4 includes the small subpixel electrode 211 shown in FIG. 5 and the common electrode 14 formed on the counter substrate 10b shown in FIG. A liquid crystal 10 g is sandwiched between the common electrode 14 and the small subpixel electrode 211.
The second liquid crystal capacitor 17b shown in FIG. 4 includes the large sub-pixel electrode 221 shown in FIG. 5 and the common electrode 14 formed on the counter substrate 10b shown in FIG. A liquid crystal 10 g is sandwiched between the common electrode 14 and the large subpixel electrode 211.

A planar structure of the display pixel 200 will be described with reference to FIG.
The auxiliary capacitance line 191 and the auxiliary electrode line 192 are provided in parallel to the scanning line 16. The auxiliary capacitance line 191 is disposed between the scanning line 16 and the auxiliary electrode line 192.

The switch element 212 and the switch element 222 are provided in the vicinity of each intersection of the signal line 15 and the scanning line 16. The switch element 212 is disposed on one side of the signal line 15, and the switch element 222 is disposed on the other side of the signal line 15. The switch element 212 and the switch element 222 are arranged at positions that are line-symmetric with respect to the signal line 15.
The switch element 212 is disposed on one side of the scanning line 16, and the switch element 222 is disposed on the same side as the switch element 212 with respect to the scanning line 16.

The small subpixel electrode 211 is disposed on one side of the signal line 15, and the large subpixel electrode 221 is disposed on the other side of the signal line 15. The small subpixel electrode 211 and the large subpixel electrode 221 are arranged at positions that are line-symmetric with respect to the signal line 15.
The small subpixel electrode 211 is disposed on the same side as the switch element 212 with respect to the signal line 15. The large subpixel electrode 221 is disposed on the same side as the switch element 222 with respect to the signal line 15.
The length of the large subpixel electrode 221 in the direction along the signal line 15 is longer than the length of the small subpixel electrode 211 in the same direction. The area of the large subpixel electrode 221 is larger than the area of the small subpixel electrode 211. The area of the small subpixel electrode 211 is, for example, about one third of the area of the large subpixel electrode 221.

The auxiliary capacitance line 191 overlaps the small subpixel electrode 211 and the large subpixel electrode 221. Thus, as described above, the auxiliary capacitance line 191 forms the first auxiliary capacitor 18 a between the small subpixel electrode 211 and the second auxiliary capacitor 18 b between the large subpixel electrode 221. On the other hand, the auxiliary electrode line 192 overlaps the large subpixel electrode 221 but does not overlap the small subpixel electrode 211. As a result, the auxiliary electrode line 192 forms a third auxiliary capacitor 18 c with the large subpixel electrode 221.
Note that the small sub-pixel 210 and the large sub-pixel 220 constituting one display pixel 200 may be provided so as to be connected to the same signal line 15 and the same scanning line 16, and are limited to the arrangement shown in FIG. is not.

  The planar structure of the switch elements 212 and 222 will be specifically described with reference to FIG. The gate electrodes 213 and 223 are provided integrally with the scanning line 16. The gate electrodes 213 and 223 extend from the scanning line 16 in the direction along the signal line 15, and the gate electrodes 213 and 223 extend in the same direction. The source electrodes 218 and 228 are provided integrally with the signal line 15. The source electrodes 218 and 228 extend from the signal line 15 in the direction along the scanning line 16, and the source electrode 218 and the source electrode 228 extend in opposite directions. The source electrodes 218 and 228 are provided so that the tips thereof overlap the gate electrodes 213 and 223, respectively. The tip portions of the source electrodes 218 and 228 are disposed so as to overlap the gate electrodes 213 and 223. The drain electrodes 217 and 227 are each provided in parallel with the scanning line 16. One end of the drain electrode 217 is provided so as to overlap the gate electrode 213, and the other end of the drain electrode 217 is provided so as to overlap the small sub-pixel electrode 211. One end of the drain electrode 227 is provided so as to overlap the gate electrode 223, and the other end of the drain electrode 227 is provided so as to overlap the large subpixel electrode 221.

  The cross-sectional structures of the liquid crystal display panel 10 and the display pixel 200 will be described with reference to FIGS. 6 to 9 are cross-sectional views of the liquid crystal display panel 10. Specifically, FIG. 6 is a cross-sectional view taken along the line VI-VI shown in FIG. FIG. 7 is a cross-sectional view taken along the line VII-VII shown in FIG. FIG. 8 is a cross-sectional view taken along the line VIII-VIII shown in FIG. FIG. 9 is a cross-sectional view taken along the line IX-IX shown in FIG.

  As shown in FIGS. 6 to 9, a transparent common electrode 14 is formed on one surface of the transparent counter substrate 10b. The counter substrate 10b and the transistor array substrate 10a face each other, and a liquid crystal 10g is sealed between them. An alignment film is formed on the upper surface of the common electrode 14 of the counter substrate 10b and the surface of the transistor array substrate 10a facing the counter substrate 10b.

  In the transistor array substrate 10a, a gate insulating film 231 is formed on the transparent substrate 10f, and an insulating overcoat film 232 is formed on the gate insulating film 231. The gate insulating film 231 and the overcoat film 232 are made of silicon nitride or silicon oxide.

  Between the transparent substrate 10f and the gate insulating film 231, gate electrodes 213 and 223 of the switch elements 212 and 222 are formed. Further, the auxiliary capacitance line 191, the auxiliary electrode line 192, and the scanning line 16 are also formed between the transparent substrate 10f and the gate insulating film 231. The gate electrodes 213 and 223, the auxiliary capacitance line 191, the auxiliary electrode line 192, and the scanning line 16 are covered with the gate insulating film 231. In the manufacturing process of the transistor array substrate 10a, the gate electrode 213, 223, the auxiliary capacitance line 191, the auxiliary electrode are formed by processing the conductive film formed on the transparent substrate 10f by photolithography / etching. The line 192 and the scanning line 16 are collectively formed.

  A signal line 15 is formed between the gate insulating film 231 and the overcoat film 232. Further, the drain electrodes 217 and 227, the source electrodes 218 and 228, the contact layers 216a, 216b, 226a, and 226b, the channel protective films 215 and 225, and the semiconductor thin films 214 and 224 of the switch elements 212 and 222 are overcoated with the gate insulating film 231. It is formed between the films 232. The signal line 15, drain electrodes 217 and 227, source electrodes 218 and 228, contact layers 216 a, 216 b, 226 a, 226 b, channel protective films 215, 225, and semiconductor thin films 214, 224 are covered with an overcoat layer 232. Yes. In the manufacturing process of the transistor array substrate 10a, the conductive film formed on the gate insulating film 231 is processed by photolithography / etching to form the signal line 15, the drain electrodes 217, 227, and the source electrode. 218 and 228 are collectively formed.

  As shown in FIG. 6, a semiconductor thin film 214 made of intrinsic amorphous silicon or polycrystalline silicon is provided on the gate insulating film 231 at a position corresponding to the gate electrode 213. The semiconductor thin film 214 is opposed to the gate electrode 213 with the gate insulating film 231 interposed therebetween. An insulating channel protective film 215 is provided on the central portion of the semiconductor thin film 214. On the semiconductor thin film 214 and on both sides of the channel protective film 215, contact layers 216a and 216b made of n-type or P-type amorphous silicon are respectively provided. A drain electrode 217 is provided on one contact layer 216a. A source electrode 218 is provided on the other contact layer 216b.

  The switch element 212 is configured by the gate electrode 213, the gate insulating film 231, the semiconductor thin film 214, the channel protective film 215, the contact layers 216 a and 216 b, the drain electrode 217, and the source electrode 218. The layer structure of the switch element 222 is configured similarly to the layer structure of the switch element 212. That is, the switch element 222 includes a gate electrode 223, a gate insulating film 231, a semiconductor thin film 224, a channel protective film 225, contact layers 226 a and 226 b, a drain electrode 227, and a source electrode 228.

  In the overcoat film 232, a contact hole 219 is provided in a portion corresponding to a predetermined portion of the drain electrode 217. Similarly, a contact hole 229 is provided in a portion corresponding to the drain electrode 227. A small subpixel electrode 211 and a large subpixel electrode 221 made of a transparent conductive material (for example, ITO: Indium-Tin-Oxide) are provided on the overcoat film 232. The small subpixel electrode 211 is connected to the drain electrode 217 of the first switch element 212 through the contact hole 219, and the large subpixel electrode 221 is connected to the drain electrode 227 of the switch element 222 through the contact hole 229. The small subpixel electrode 211 and the large subpixel electrode 221 are opposed to the common electrode 14.

As shown in FIG. 7, the small subpixel electrode 211 and the auxiliary capacitance line 191 are partially opposed to each other with the gate insulating film 231 and the overcoat film 232 interposed therebetween. Thereby, the first auxiliary capacitor 18a is formed.
The small subpixel electrode 211 faces the common electrode 14, and the liquid crystal 10g is sandwiched between them. Thereby, the first liquid crystal capacitor 17a is formed.

As shown in FIG. 8, the large subpixel electrode 221 and the auxiliary capacitance line 191 are partially opposed to each other with the gate insulating film 231 and the overcoat film 232 interposed therebetween. Thereby, the second auxiliary capacitor 18b is formed.
Further, the large sub-pixel electrode 221 and the auxiliary electrode line 192 partially face each other with the gate insulating film 231 and the overcoat film 232 interposed therebetween. Thereby, the third auxiliary capacitor 18c is formed.
Further, the large subpixel electrode 221 faces the common electrode 14, and the liquid crystal 10g is sandwiched therebetween. Thereby, the second liquid crystal capacitor 17b is formed.

  7 and 9, the auxiliary capacitance line 191 and the auxiliary electrode line 192 are formed between the transparent substrate 10f and the gate insulating film 231, but the auxiliary capacitance line 191 and the auxiliary electrode line 192 are formed. It may be formed between the gate insulating film 231 and the overcoat film 232. In this case, in plan view, the auxiliary capacitance line 191 and the auxiliary electrode line 192 are not provided in parallel to the scanning line 16 as shown in FIG. It has been. Two auxiliary capacitance lines 191 are arranged on both sides of the signal line 15, one auxiliary capacitance line 191 overlaps the small subpixel electrode 211, and the other auxiliary capacitance line 191 overlaps the large subpixel electrode 221. Yes. An auxiliary electrode line 192 is disposed on one side of the signal line 15, and the auxiliary electrode line 192 overlaps the large subpixel electrode 221.

  Hereinafter, the configuration of the driving device 90 will be specifically described, and the driving method of the liquid crystal display panel 10 by the driving device 90 will be specifically described.

  As shown in FIG. 3, the driving device 90 includes a data driver 30, a scan driver 40, a common voltage generation circuit 60, a waveform signal generation circuit 70, and a control circuit 80.

The data driver 30, the scan driver 40, the common voltage generation circuit 60, the waveform signal generation circuit 70, and the control circuit 80 are built in the IC chip 81 shown in FIG. The image memory 50 is provided on a main circuit board built in the electronic device 100 shown in FIG.
The image memory 50 temporarily stores a video signal input from the outside of the liquid crystal display device 1. The image memory 50 outputs the stored video signal to the control circuit 80.
The control circuit 80 generates a gradation signal Data, a horizontal synchronization signal H, and a vertical synchronization signal V based on the video signal input from the image memory 50. The control circuit 80 generates a clock signal CLK, a polarity inversion signal Pol, and other control signals. The control circuit 80 outputs horizontal control signals such as a gradation signal Data, a horizontal synchronization signal H, a vertical synchronization signal V, a clock signal CLK, and a polarity inversion signal Pol to the data driver 30. The control circuit 80 outputs vertical control signals such as a horizontal synchronizing signal H and a vertical synchronizing signal V to the scanning driver 40. The control circuit 80 outputs the polarity inversion signal Pol to the waveform signal generation circuit 70.

Here, each signal generated by the control circuit 80 will be described with reference to FIG.
The gradation signal Data is a signal of n (n is a natural number of 1 or more) bits. The gradation signal Data indicates the gradation for each display pixel 200.
The clock signal CLK is a signal having a predetermined cycle, and is a signal for synchronizing the operation timing of the data driver 30 and the control circuit 80. For example, the clock signal CLK is a timing signal at a timing corresponding to each display pixel 200 with respect to the gradation signal Data.
The horizontal synchronization signal H is a signal for synchronizing in the horizontal direction (the direction along the scanning line 16). The horizontal synchronization signal H is a signal output at a timing for each horizontal synchronization period (1H, one selection period), and drawing for one row is performed within one horizontal synchronization period. The first gate clock signal GCK1 and the second gate clock signal GCK2 are signals whose rising and falling edges are synchronized with the horizontal synchronizing signal H, and a 1/2 cycle is one horizontal synchronizing period, and the first gate clock signal GCK1 And the second gate clock signal GCK2 have opposite phases.
The vertical synchronization signal V is a signal for synchronizing in the vertical direction. The vertical synchronization signal V is a signal output at a timing for each frame period, and one screen is drawn in one frame period.
The polarity inversion signal Pol is a signal whose polarity is inverted every horizontal synchronization period. Further, the phase of the polarity inversion signal Pol is delayed by 180 ° or advanced every frame period. That is, if the polarity inversion signal Pol is high in the first horizontal synchronization period of one frame period, the polarity inversion signal Pol becomes low in the first one horizontal synchronization period of the next one frame period. If the polarity inversion signal Pol is low in one horizontal synchronization period, the polarity inversion signal Pol becomes high in the first one horizontal synchronization period of the next one frame period. The polarity inversion signal Pol is used for line inversion driving and frame inversion driving. The line inversion driving is a method of driving the liquid crystal display panel 10 by inverting the polarity of the voltage of the signal line 15 with respect to the voltage of the common electrode 14 every horizontal synchronization period. The frame inversion drive is a method of driving the liquid crystal display panel 10 so that the polarity of the voltage of the subpixel electrodes 211 and 221 with respect to the common voltage Vcom of the common electrode 14 is inverted every frame period.

  As shown in FIGS. 3 and 10, the common voltage generation circuit 60 generates a common voltage Vcom. The common voltage generation circuit 60 applies a common voltage Vcom to the common electrode 14 and the auxiliary capacitance line 191. The common voltage Vcom is a constant voltage. Since the voltage value of the common electrode 14 is constant at the common voltage Vcom, so-called common DC drive is performed. The common DC drive is a method of driving the liquid crystal display panel 10 with the voltage of the common electrode 14 being a constant voltage.

The scan driver 40 will be described with reference to FIGS. 11 and 12.
FIG. 11 is a diagram showing an outline of the configuration of the scan driver 40. The scanning driver 40 outputs a signal to each scanning line 16 based on the vertical synchronizing signal V and the horizontal synchronizing signal H output from the control circuit 80.

  The scanning driver 40 includes N-stage holding circuits 41 arranged in series (N represents the number of scanning lines 16). The holding circuits 41 in the first to Nth stages output signals to the scanning lines 16 in the first to Nth lines, respectively. The holding circuit 41 includes an input terminal IN, an output terminal OUT, a reset terminal RST, a clock signal input terminal CK, a high potential power input terminal Th, and a low potential power input terminal Tl. The vertical synchronizing signal V corresponding to the scanning line 16 in the first row is supplied to the input terminal IN of the holding circuit 41 in the first stage. The output signal of the holding circuit 41 immediately preceding the holding circuit 41 is supplied to the input terminal IN of the holding circuit 41 in the second and subsequent stages. Further, the output signal of the holding circuit 41 after one stage of the holding circuit is supplied to the reset terminal RST of the holding circuit 41. Note that the reset signal END may be separately supplied to the reset terminal RST of the holding circuit (not shown) in the final stage (Nth stage), or the output signal of the first stage holding circuit 41 is supplied. It is good also as a structure to be made.

  Further, the first gate clock signal GCK1 is supplied to the clock signal input terminal CK of the odd-numbered holding circuit 41. The second gate clock signal GCK2 is supplied to the clock signal input terminal CK of the even-stage holding circuit 41. A predetermined high voltage Vgh is supplied to the high potential power input terminal Th of each holding circuit 41, and a predetermined low voltage Vgl lower than the high voltage Vgh is supplied to the low potential power input terminal Tl of each holding circuit 41. Supplied.

  FIG. 12 is a diagram showing an example of the circuit configuration of the holding circuit 41. The holding circuit 41 includes six MOS field effect transistors (MOS transistors) 411 to 416 and a capacitor 417.

  The scan driver 40 sequentially selects the plurality of scan lines 16 and repeats such selection. Specifically, when the pulse of the vertical synchronization signal V is input, the scanning driver 40 sequentially selects the plurality of scanning lines 16 from the first row in synchronization with the first and second gate clock signals GCK1 and GCK2. . The scanning driver 40 receives the vertical synchronization signal V after the sequential selection of the scanning lines 16 has been completed, and sets the plurality of scanning lines 16 to the first row in synchronization with the first and second gate clock signals GCK1 and GCK2. Select again sequentially.

  In FIG. 10, G (1), G (2),..., G (N) are scanned by the scanning driver 40 in the first scanning line 16, the second scanning line 16,. A signal (scanning signal) output to the scanning line 16 in the row (N represents the number of scanning lines 16). The scan driver 40 applies a high level high voltage Vgh to the selected scan line 16 only for one horizontal synchronization period. Thereby, for the display pixel 200 connected to the selected scanning line 16, the switch element 212 closes between the signal line 15 and the small sub-pixel electrode 211, and the switch element 222 connects the signal line 15 and the large sub-pixel. The space between the electrodes 221 is closed. On the other hand, for the display pixel 200 connected to the unselected scanning line 16, the switch element 212 opens between the signal line 15 and the small subpixel electrode 211, and the switch element 222 includes the signal line 15 and the large subpixel. The space between the electrodes 221 is opened. In FIG. 10, the period in which G (1), G (2),..., G (N) is at the high level Vgh is a period slightly shorter than one horizontal synchronization period. This is based on an operation margin in actual circuit operation, but the present invention is not limited to this, and G (1), G (2),..., G (N) are high levels Vgh. This period may coincide with one horizontal synchronization period. The same applies to FIG. 26 described later.

The data driver 30 will be described with reference to FIGS.
FIG. 13 is a diagram showing the configuration of the data driver 30. The data driver 30 includes a shift register circuit 31, a data register circuit 32, a data latch circuit 33, and a DA converter 24. The DA converter 34 includes a DAC circuit 341 and a buffer amplifier 342. The data register circuit 32, the data latch circuit 33, the DAC circuit 341, and the buffer amplifier 342 are provided for each signal line 15, and M (M represents the number of signal lines 15) is provided.

The shift register circuit 31 starts the address of the data register circuit 32 in synchronization with the rising edge of the horizontal synchronization signal H. In other words, when the pulse of the horizontal synchronization signal H rises, the shift register circuit 31 sequentially outputs the selection signal to the data register circuit 32 in synchronization with the clock signal CLK, whereby the data register circuit 32 is output during one horizontal synchronization period. Are selected sequentially.
The selected data register circuit 32 sequentially stores the gradation signal Data corresponding to the display pixels 200 for one row.
The data latch circuit 33 fetches and holds the gradation signal Data for one row stored in the data register circuit 32 in accordance with the control signal CTL in the horizontal control signal, and the held gradation signal Data is a DAC circuit. 341.
The gradation reference voltage generation circuit 35 generates ²ⁿ (n is the number of bits of the gradation signal Data) gradation reference voltages and outputs the generated ²ⁿ gradation reference voltages to the DAC circuit 341. . In FIG. 13, n = 8.
The DAC circuit 341 selects a gradation reference voltage corresponding to the input gradation signal Data from the ²ⁿ gradation reference voltages generated by the gradation reference voltage generation circuit 35, and selects the selected gradation reference voltage. The gradation reference voltage is output to the signal line 15 as the gradation signal S (i) (i = 1 to M).

FIG. 14 is a diagram illustrating an example of the circuit configuration of the gradation reference voltage generation circuit 35 and the DA converter 24.
The gradation reference voltage generation circuit 35 includes open / close switches SA1, SA2, SB1, and SB2, ladder resistors 351 and 352, and changeover switches SY (1) to SY (2 ⁿ ). The ladder resistor 351 includes resistors RA (1) to RA (2 ⁿ +1) connected in series, and the ladder resistor 352 includes resistors RB (1) to RB (2 ⁿ +1) connected in series. The potential of the first high potential voltage source VH1 is higher than the potential of the first low potential voltage source VL1, and the first high potential voltage source VH1 and the first low potential voltage source VL1 are equal to or higher than the common voltage Vcom. Have The potential of the second high potential voltage source VH2 is higher than the potential of the second low potential voltage source VL2, and the second high potential voltage source VH2 and the second low potential voltage source VL2 are equal to or more than the common voltage Vcom. Has a low potential. The open / close switch SA1 opens and closes between one end of the ladder resistor 351 and the first low potential voltage source VL1. The open / close switch SA2 opens and closes the connection between the other end of the ladder resistor 351 and the first high potential voltage source VH1. The open / close switch SB1 opens and closes the connection between one end of the ladder resistor 352 and the second high potential voltage source VH2. The open / close switch SB2 opens and closes the connection between the other end of the ladder resistor 352 and the second low potential voltage source VL2.
Here, the opening / closing switches SA1, SA2, SB1, and SB2 are switched according to the level of the polarity inversion signal Pol. That is, when the polarity inversion signal Pol is at a high level, the opening / closing switches SA1 and SA2 are closed and the opening / closing switches SB1 and SB2 are opened. When the polarity inversion signal Pol is at a low level, the opening / closing switches SA1 and SA2 are opened. The open / close switches SB1 and SB2 are closed. Accordingly, when the polarity inversion signal Pol is at a high level, the ladder resistor 351 is selected. Therefore, the first high-potential voltage source VH1 potential difference of the first low-potential voltage source VL1 is divided by the resistors ^{RA (1) ~RA (2 n} +1), the resistance RA (1) ~ resistor RA ⁽² n +1) Are generated as ²ⁿ gradation reference voltages. On the other hand, when the polarity inversion signal Pol is at a low level, the ladder resistor 352 is selected. Therefore, the second high-potential voltage source VH2 potential difference of the second low-potential voltage source VL2 is divided by the resistors ^{RB (1) ~RB (2 n} +1), resistor RB (1) ~ resistor RB ⁽² n +1) Are generated as ²ⁿ gradation reference voltages.

The voltage application lines V (1) to V (2 ⁿ ) are the outputs of the gradation reference voltage generation circuit 35. Connected to the resistor ^{RA (1) ~RA (2 n} +1) the connection parts each changeover switch SY (1) between ~SY ^{(2 n)} via a voltage applying line ^{V (1) ~V (2 n} ) Has been. The resistance ^{RB (1) ~RB (2 n} +1) the connection parts each changeover switch SY (1) between ~SY ^{(2 n)} via a voltage applying line ^{V (1) ~V (2 n} ) It is connected to the. The changeover switch SY (1) selectively connects a connection portion between the resistors RA (1) and RA (2) and a connection portion between the resistors RB (1) and RB (2) to the voltage application line V ( Conduct to 1). The same applies to the changeover switch SY (2) to the changeover switch SY ( ²ⁿ ).
The changeover switches SY (1) to SY (2 ⁿ ) are changed according to the level of the polarity inversion signal Pol. That is, when the polarity inversion signal Pol is at a high level, each connection portion between the resistors RA (1) to RA (2 ⁿ ) is connected to the voltage application line by the respective changeover switches SY (1) to SY (2 ⁿ ). Each of V (1) to V (2 ⁿ ) conducts. On the other hand, when the polarity inversion signal Pol is at the low level, each connection portion between the resistors RB (1) to RB (2 ⁿ ) is connected to the voltage application line by the respective changeover switches SY (1) to SY (2 ⁿ ). Each of V (1) to V (2 ⁿ ) conducts.
Therefore, when the polarity inversion signal Pol is at a high level, the gradation reference voltages output to the voltage application lines V (1) to V (2 ⁿ ) by the ladder resistor 351 are in descending order from the first stage. The gradation reference voltage output to the voltage application lines V (1) to V (2 ⁿ ) by the ladder resistor 351 is equal to or higher than the common voltage Vcom generated by the common voltage generation circuit 60. On the other hand, when the polarity inversion signal Pol is at a low level, the gradation reference voltages output to the voltage application lines V (1) to V (2 ⁿ ) by the ladder resistor 352 are in ascending order from the first stage. The gradation reference voltage output to the voltage application lines V (1) to V (2 ⁿ ) by the ladder resistor 352 is equal to or lower than the common voltage Vcom generated by the common voltage generation circuit 60. In addition, although it was set as the structure which has the two ladder resistors 351 and 352 in the above, you may have only one ladder resistor.

Each DAC circuit 341 includes a decoder 343 and open / close switches SW (1) to SW (2 ⁿ ). Closing the switch ^{SW (1) ~SW (2 n} ) opens and closes the connection between one of the voltage applying line ^{V (1) ~V (2 n} ) and the voltage output line SL. The decoder 343 receives the gradation signal Data output from the data latch circuit 33, and selects one corresponding to the gradation signal Data from the open / close switches SW (1) to SW (2 ⁿ ). Of the on / off switches SW (1) to SW (2 ⁿ ), the one selected by the decoder 343 is closed, and the other switches are opened. The voltage application line and the voltage output line SL corresponding to the open / close switch in the closed state are brought into conduction, and the gradation reference voltage applied to the voltage application line is applied to the voltage output line SL. The gradation reference voltage applied to the voltage output line SL is output to the signal line 15 via the buffer amplifier 342.

In FIG. 10, the gradation signal S (i) represents a voltage applied to a certain signal line 15 by the data driver 30. That is, the gradation signal S (i) is an analog version of the gradation signal Data for a certain signal line 15. When the polarity inversion signal Pol is at a high level, ²ⁿ gradation reference voltages generated by the ladder resistor 351 are equal to or higher than the common voltage Vcom, and when the polarity inversion signal Pol is at a low level, The ²ⁿ gradation reference voltages generated by the ladder resistor 352 are equal to or lower than the common voltage Vcom. Therefore, the polarity of the gradation signal S (i) based on the common voltage Vcom of the common electrode 14 is inverted every horizontal synchronization period. Therefore, line inversion driving is performed.

  Also, frame inversion driving is performed. That is, in any display pixel 200, the polarity of the voltage of the subpixel electrodes 211 and 221 with the common voltage Vcom of the common electrode 14 as a reference is inverted every frame period. This is because the phase of the polarity inversion signal Pol is delayed by 180 ° or advanced every frame period.

  As shown in FIG. 3, the waveform signal generation circuit 70 generates a waveform signal Vd and applies it to the X auxiliary electrode line 192. As shown in FIG. 10, the waveform signal Vd is a waveform signal synchronized with the polarity inversion signal Pol, and has the same phase as the polarity inversion signal Pol. That is, when the polarity inversion signal Pol is at the high level Vsh, the voltage of the waveform signal Vd is at the high level Vdh. On the other hand, when the polarity inversion signal Pol is at the low level Vsl, the voltage of the waveform signal Vd is at the low level Vdl. The high level Vdh is higher than the common voltage Vcom, and the low level Vdl is lower than the common voltage Vcom. The values of the high level Vdh and the low level Vdl are set to values at which the average is equal to the common voltage Vcom, for example. In this case, the waveform signal Vd is a rectangular AC signal that oscillates in synchronization with the polarity inversion signal Pol with the common voltage Vcom as the center voltage. The period of the waveform signal Vd is twice as long as one horizontal synchronization period. In addition, the waveform signal Vd has the same phase as the gradation signal S (i) output to the signal line 15.

In the liquid crystal display device 1 configured as described above, the scanning driver 40 selects the plurality of scanning lines 16 in synchronization with the horizontal synchronization signal H in order from the first row. On the other hand, the data driver 30 outputs the gradation signal S (i) AD-converted by each DAC circuit 341 to each signal line 15. That is, the data driver 30 amplifies the gradation reference voltage corresponding to the gradation signal Data latched in each data latch circuit 33 and applies it to each signal line 15.
For each display pixel 200 corresponding to the selected scanning line 16, the switch elements 212 and 222 are opened. Therefore, the analog gradation signal S (i) output to the signal line 15 is written to the small subpixel 210 and the large subpixel 220. Thereafter, when the selection of the scanning line 16 is released, the switch elements 212 and 222 are closed, and the analog gradation signal S (i) is selected next to the small sub-pixel 210 and the large sub-pixel until the scanning line 16 is selected. It is held in the pixel 220. A horizontal synchronization period in which the scanning line 16 is selected is also referred to as a selection period, and a period in which the selection of the scanning line 16 is subsequently released is referred to as a non-selection period.

  Here, the voltages applied to the small subpixel electrode 211 and the large subpixel electrode 221 will be described with reference to FIGS. 15 and 16.

FIG. 15 is a voltage timing chart regarding the small sub-pixel 210.
As shown in FIG. 15, in the selection period (horizontal synchronization period), since the switch element 212 is open, the voltage Vsig corresponding to the gradation signal S (i) is applied to the small subpixel electrode 211. In the subsequent non-selection period, when the switch element 212 is closed, the voltage of the small subpixel electrode 211 falls by ΔV from the voltage Vsig, and the difference between the voltage of the small subpixel electrode 211 and the common voltage Vcom of the common electrode 14 becomes Vlc. Become. Such behavior is the same regardless of whether the polarity of the gradation signal S (i) with respect to the common voltage Vcom of the common electrode 14 is positive or negative.
ΔV indicates a pull-in voltage generated by a parasitic capacitance between the gate electrode 213 and the small subpixel electrode 211 of the scanning line 16 when the switch element 212 is closed. The common voltage Vcom is preferably set in consideration of ΔV. That is, the common voltage Vcom is the amplitude center voltage of the gradation signal S (i) (the voltage at the connection between the resistors RA (1) and RA (2) in FIG. 14 and the resistors RB (1) and RB (2). It is preferable to set the voltage shifted (decreased) by ΔV from the average value of the voltage at the connection portion between (1).

FIG. 16 is a voltage timing chart regarding the large sub-pixel 220.
First, a case where the polarity of the gradation signal S (i) with the common voltage Vcom of the common electrode 14 as a reference in the selection period is positive will be described. As shown in FIG. 16, since the switch element 222 is open in the selection period, the voltage Vsig corresponding to the gradation signal S (i) is applied to the large subpixel electrode 221. In the selection period, since the waveform signal Vd is at the high level Vdh, the voltage at the high level Vdh is applied to the auxiliary electrode line 192. In the subsequent non-selection period, since the switch element 222 is closed, the large subpixel electrode 221 is in a floating state. Since the waveform signal Vd is output to the auxiliary electrode line 192 even in the non-selection period, the voltage of the large subpixel electrode 221 vibrates according to the waveform signal Vd. Therefore, in the period T2 in which the waveform signal Vd is at the low level Vdl in the non-selection period, the voltage of the large subpixel electrode 221 is shifted from the voltage Vsig, and the amount of shift is in addition to ΔV and the voltage Vdl of the auxiliary electrode line 192. Affected by. This is because the voltage of the auxiliary electrode line 192 in the period T2 in which the waveform signal Vd is at the low level Vdl in the non-selection period is lower than the voltage of the auxiliary electrode line 192 in the selection period.
On the other hand, in the period T1 during which the waveform signal Vd is at the high level Vdh in the non-selection period, the voltage of the large subpixel electrode 221 is shifted from the voltage Vsig, and the shift amount is only ΔV. This is because the voltage of the auxiliary electrode line 192 in the period T1 during which the waveform signal Vd is at the high level Vdh in the non-selection period is equal to the voltage of the auxiliary electrode line 192 in the selection period.
Further, the difference Vlc1 between the voltage of the large subpixel electrode 221 and the voltage of the common electrode 14 in the period T2 in which the waveform signal Vd is at the low level Vdl in the non-selection period is the waveform signal Vd in the non-selection period is the high level Vdh. It is lower than the difference Vlc between the voltage of the large subpixel electrode 221 and the voltage of the common electrode 14 during the period T1. This is because the voltage of the auxiliary electrode line 192 in the period T2 in which the waveform signal Vd is at the low level Vdl in the non-selection period, and the voltage of the auxiliary electrode line 192 in the period T1 in which the waveform signal Vd is at the high level Vdh in the non-selection period. In addition to being lower than the voltage, the amount of charge accumulated in the capacitors (second liquid crystal capacitor 17b, second auxiliary capacitor 18b, and third auxiliary capacitor 18c) formed by the large subpixel electrode 221 in both periods T2 and T1 is This is because it does not change.
Therefore, the absolute value of the effective voltage of the large sub-pixel electrode 221 in the non-selection period with reference to the voltage of the common electrode 14 is the square root mean square of the voltage difference Vlc1 and the voltage difference Vlc.
Further, the difference Vlc1 between the voltage of the large subpixel electrode 221 and the voltage of the common electrode 14 in the period T2 in which the waveform signal Vd is at the low level Vdl in the non-selection period is the same as the voltage of the small subpixel electrode 211 in the non-selection period. It is lower than the voltage difference Vlc of the electrode 14. In addition, the difference Vlc between the voltage of the large subpixel electrode 221 and the voltage of the common electrode 14 in the period T1 in which the waveform signal Vd is at the high level Vdh in the non-selection period is the same as the voltage of the small subpixel electrode 211 in the non-selection period. It is approximately equal to the voltage difference Vlc of the electrode 14. Therefore, the absolute value of the effective voltage of the large subpixel electrode 221 in the non-selection period with reference to the voltage of the common electrode 14 is the effective value of the effective voltage of the small subpixel electrode 211 in the nonselection period with reference to the voltage of the common electrode 14. It becomes smaller than the absolute value by | Vlc−Vlc1 | / 2.

  Even when the polarity of the gradation signal S (i) with respect to the common voltage Vcom of the common electrode 14 is negative in the selection period, the waveform signal Vd is at the high level Vdh during the selection period, and thus the same behavior is exhibited. . That is, in the period T2 in which the waveform signal Vd is at the high level Vdh in the non-selection period, the voltage of the large subpixel electrode 221 is shifted from the voltage Vsig, and the shift amount is in addition to ΔV, the voltage Vdh of the auxiliary electrode line 192. Affected by. On the other hand, in the period T1 in which the waveform signal Vd is at the low level Vdl in the non-selection period, the voltage of the large subpixel electrode 221 is shifted from the voltage Vsig, and the shift amount is only ΔV. Therefore, the absolute value of the effective voltage of the large subpixel electrode 221 in the non-selection period with reference to the voltage of the common electrode 14 is the effective value of the effective voltage of the small subpixel electrode 211 in the nonselection period with reference to the voltage of the common electrode 14. It becomes smaller than the absolute value by | Vlc−Vlc1 | / 2.

  As described above, even when the voltage of the large subpixel electrode 221 and the voltage of the small subpixel electrode 211 are equal during the selection period, the voltage of the large subpixel electrode 221 and the voltage of the small subpixel electrode 211 are displayed during the non-selection period. Is different. Therefore, during the non-selection period, the light transmittance of the liquid crystal overlapping the large subpixel electrode 221 is different from the light transmittance of the liquid crystal overlapping the small subpixel electrode 211. Therefore, the light transmittance of the display pixel 200 can be considered as a combination of the light transmittance of the liquid crystal overlapping the large subpixel electrode 221 and the light transmittance of the liquid crystal overlapping the small subpixel electrode 211.

  FIG. 17 is a graph showing the relationship between the viewing angle and the light transmittance for each voltage (that is, for each gradation) applied to the liquid crystal in a conventional liquid crystal display panel. In the graph of FIG. 17, the horizontal axis represents the viewing angle (deg), and the vertical axis represents the light transmittance (%). The transmittance on the vertical axis is a relative value when the maximum value of the transmittance is 100%. As shown in FIG. 17, the viewing angle is zero (deg) when viewed from the vertical direction, the angle perpendicular to the vertical direction is positive on the surface perpendicular to the panel, and the opposite angle is negative. A value in a viewing angle range of -80 to +80 degrees was shown. Each curve in FIG. 17 indicates that the gradation signal Data is 0 gradation, 8 gradation, 16 gradation, 24 gradation, 32nd floor when the gradation signal Data is a 6-bit signal with 0 to 63 gradations. The light transmittance is shown for the tone, 40 gradation, 48 gradation, 56 gradation, and 63 gradation. As is apparent from the graph of FIG. 17, the light transmittance of the liquid crystal depends on the viewing angle. In particular, since the curves intersect in a region where the viewing angle is −20 degrees or less and the viewing angle is 45 degrees or more, it can be seen that gradation inversion occurs here. Here, the gradation inversion means that the gradation appears to be inverted at a certain position when the viewing angle with respect to the liquid crystal display is changed.

  FIG. 18 shows a case where the light transmittance of the liquid crystal overlapping the large subpixel electrode 221 and the light transmittance of the liquid crystal overlapping the small subpixel electrode 211 are combined in the liquid crystal display panel 10 of the present embodiment. It is a graph which shows the relationship between the transmittance | permeability and a viewing angle. In the graph of FIG. 18, the horizontal axis represents the viewing angle (deg), and the vertical axis represents the relative value (%) of the light transmittance, as in FIG. As in FIG. 17, each curve in FIG. 17 indicates that the gradation signal Data is 0 gradation, 8 gradation, 16 gradation, when the gradation signal Data is a 6-bit signal with 0 to 63 gradations. The light transmittance is shown for 24, 32, 40, 48, 56, and 63 gradations. Compared with the curves in FIG. 17, it can be seen that the curves in the region where the viewing angle is negative are gentle, and the intersections between the curves are greatly reduced. As described above, in the liquid crystal display device 1 of the present embodiment, the change in the display state due to the viewing angle can be made smaller than before, and the viewing angle dependency can be reduced.

  Also, it can be seen that the graph of FIG. 18 has fewer intersections of curves than the graph of FIG. Therefore, in the liquid crystal display device 1 of the present embodiment, the occurrence of gradation inversion can be suppressed compared to the conventional case, and the viewing angle range in which the gradation inversion does not occur can be made larger than the conventional one.

  19 and 20 are diagrams illustrating an example of the light transmittance characteristic of the liquid crystal overlapping the small subpixel electrode 211 and the light transmittance characteristic of the liquid crystal overlapping the large subpixel electrode 221. FIG. 19 and 20, the horizontal axis represents the absolute value of the voltage of the signal line 15 (based on the voltage of the common electrode 14) in the selection period. The vertical axis represents the transmittance of the liquid crystal during the non-selection period. The transmittance on the vertical axis is a relative value with respect to the maximum value of transmittance in each light transmittance characteristic. A curve VT1 represents the relationship between the voltage and the transmittance with respect to the liquid crystal overlapping the small subpixel electrode 211. A curve VT2 represents the relationship between the voltage and the transmittance for the liquid crystal overlapping the large subpixel electrode 221. As is clear from FIG. 19, the absolute value of the effective voltage of the large sub-pixel electrode 221 in the non-selection period based on the voltage of the common electrode 14 is the first sub-period in the non-selection period based on the voltage of the common electrode 14. Since it is smaller than the effective voltage of the pixel electrode 211, the curve VT2 is shifted to a higher voltage side than the curve VT1. That is, even one display pixel 200 has the characteristics of the curve VT1 and the characteristics of the curve VT2.

  FIG. 20 is a diagram in the case where the curve VT2 is shifted in a direction approaching the curve VT1. By reducing the amplitude width of the waveform signal Vd generated by the waveform signal generation circuit 70, the curve VT2 can be shifted closer to the curve VT1. That is, by adjusting or controlling the waveform signal generation circuit 70, the difference between the light transmittance of the liquid crystal overlapping the small subpixel electrode 211 and the light transmittance of the liquid crystal overlapping the large subpixel electrode 221 is increased. It can be made smaller. When the waveform signal Vd is set to a constant voltage or controlled, the curve VT1 and the curve VT2 overlap. 19 and 20, curves VT1 and VT2 when the liquid crystal 10g is a normally white type are shown. However, when the liquid crystal 10g is a normally black type, the curves VT1 and VT2 are on the right. It ’s going to rise.

In the liquid crystal display device 1 configured as described above, since the display pixel 200 is divided into the small sub-pixel 210 and the large sub-pixel 220, the display pixel 200 is applied to the divided small sub-pixel 210 and large sub-pixel 220. The voltage can be varied. Thereby, the light transmittance of the sub-pixels 210 and 220 divided in one display pixel 200 can be set to different values. The light transmittance can be adjusted for each of the subpixels 210 and 220 divided in this way, so that the transmittance suitable for one display pixel 200 can be obtained. As a result, the viewing angle dependency can be suppressed and gradation inversion can be eliminated. Therefore, high image quality can be achieved.
Further, since the waveform signal Vd is output to the auxiliary electrode line 192, occurrence of flicker can be suppressed.
In addition, since one display pixel 200 is divided into left and right sub-pixels 210 and 220, the display pixel 200 can be increased in the horizontal direction, and a viewing angle can be increased.
Further, since the waveform signal generation circuit 70 only needs to adjust the amplitude of the waveform voltage Vd, the circuit configuration can be simplified. Therefore, the viewing angle dependency can be adjusted with a simpler circuit configuration.
In addition, since the common electrode 14 is not divided for each of the sub-pixels 210 and 220 but formed on the entire surface, the manufacturing process of the liquid crystal display device 1 and the liquid crystal display panel 10 may be increased. Absent.
In addition, since the analog gradation signal S (i) is directly applied to the subpixel electrodes 211 and 221 via the switch elements 212 and 222, a voltage is applied to the pixel electrode only via the capacitor ( For example, the voltage can be more stably applied to the liquid crystal 10g as compared with the one described in Patent Document 1.

  In the above embodiment, the waveform signal generation circuit 70 outputs the waveform signal Vd to the auxiliary electrode line 192, so that the effective voltage of the auxiliary electrode line 192 in the selection period and the effective voltage of the auxiliary electrode line 192 in the non-selection period are changed. I was different. As long as the effective voltage of the auxiliary electrode line 192 in the selection period is different from the effective voltage of the auxiliary electrode line 192 in the non-selection period, the signal is not limited to the waveform signal Vd.

  In the above embodiment, the driving method of the liquid crystal display panel 10 is a combination of frame inversion driving, line inversion driving, and common DC driving, but other driving methods may be used. For example, dot inversion driving may be used instead of line inversion driving. In the case of the dot inversion driving method, for example, two gradation reference voltage generation circuits 35 shown in FIG. 13 are prepared. Then, one gradation reference voltage generation circuit 35 outputs a gradation reference voltage to the DAC circuit 341 connected to the odd-numbered signal line 15, and the other gradation reference voltage generation circuit 35 outputs the signal of the even-numbered column. The data is output to the DAC circuit 341 connected to the line 15. Then, the polarity inversion signal Pol is input to one gradation reference voltage generation circuit 35, but the polarity inversion signal Pol is inverted and input to the other gradation reference voltage generation circuit 35. In this way, the voltage applied from the data driver 30 to the odd-numbered signal lines 15 (based on the common voltage Vcom) and the voltage applied from the data driver 30 to the signal lines 15 in the multiple-numbered column (common voltage Vcom). Is the opposite phase.

Further, common AC drive may be used instead of common DC drive. That is, the common voltage Vcom applied to the common electrode 14 is not a constant voltage, and the polarity of the common voltage Vcom may be inverted every horizontal synchronization period or every frame period. That is, the common voltage generation circuit 60 outputs the common voltage Vcom whose polarity is inverted every horizontal synchronization period or every frame period to the common electrode 14 and the auxiliary capacitance line 191. In this case, RA (1) of the gray-scale reference voltage generating circuit 35 ~RA ⁽² n +1) and RB (1) ~RB the resistance value or by appropriately changing the ⁽² n +1), the voltage source VH and the low high potential It is desirable to appropriately change the potential of the potential voltage source VL.

  Alternatively, a combination of frame inversion driving and common DC driving or a combination of frame inversion driving and common AC driving may be used without performing line inversion driving. In this case, the polarity of the polarity inversion signal Pol input to the gradation reference voltage generation circuit 35 is not inverted every horizontal synchronization period but inverted every frame period. In this way, the polarity of the voltage (referenced to the common voltage Vcom) applied from the data driver 30 to the signal line 15 is inverted every frame period.

  Next, the arrangement of the display pixels 200 will be specifically described.

[1] First Example FIG. 21 is a plan view showing a first example of the arrangement of the display pixels 200.
In the liquid crystal display panel 10, a plurality of signal lines 15 extend vertically (in the vertical direction). These signal lines 15 are arranged on the left and right at equal intervals.

  A plurality of scanning lines 16 extend left and right (horizontal direction). These scanning lines 16 are arranged one above the other. Each scanning line 16 has two adjacent scanning lines 16 arranged close to each other, and is spaced from each other by the two scanning lines 16. It is arranged. Two scanning lines 16 adjacent to each other with this interval are taken into consideration as a set. One of two scanning lines 16 that are adjacent to each other with a space therebetween corresponds to the first scanning line of the present invention, and the other corresponds to the second scanning line of the present invention.

The plurality of auxiliary capacitance lines 191 extend to the left and right and are parallel to the scanning line 16. The number of auxiliary capacitance lines 191 and the number of scanning lines 16 are the same number (= N). These auxiliary capacitance lines 191 are arranged vertically. Two auxiliary capacitance lines 191 are arranged between a pair of adjacent scanning lines 16 with a space therebetween.
The plurality of auxiliary electrode lines 192 extend left and right and are parallel to the scanning line 16. The number of auxiliary electrode lines 192 is half the number of scanning lines 16 (= N / 2). These auxiliary electrode lines 192 are arranged vertically. One auxiliary capacitance line 191 is arranged between a pair of adjacent scanning lines 16 with a space therebetween, and two auxiliary capacitance lines 191 located between the pair of scanning lines 16. It is arranged between.

Display pixels 200 </ b> A and display pixels 200 </ b> B are alternately arranged along each signal line 15. Here, the display pixel 200B is obtained by rotating the display pixel 200A by 180 ° around an axis perpendicular to the display surface. That is, for the display pixel 200A, the small sub-pixel 210A is disposed on the left side of the signal line 15, the large sub-pixel 220A is disposed on the right side of the signal line 15, and for the display pixel 200B, the small sub-pixel 210B is disposed on the right side of the signal line 15. In addition, the large sub-pixel 220 </ b> B is disposed on the left side of the signal line 15. Note that the display pixel 200A and the display pixel 200B are provided in the same manner as the display pixel 200 described with reference to FIGS.
The display pixels 200A and the display pixels 200B are arranged between a pair of adjacent scanning lines 16 with a space therebetween.
These display pixels 200 </ b> A are arranged along one of a pair of adjacent scanning lines 16 with a space therebetween, and are connected to the one scanning line 16. These display pixels 200 </ b> B are arranged along the other of a pair of adjacent scanning lines 16 with a space therebetween, and are connected to the other scanning line 16. Therefore, for the display pixel 200A, the switch element 212A and the switch element 222A are arranged downward from the scanning line 16 connected thereto, and for the display pixel 200B, the switch element 212B and the switch element 222B are connected thereto. The scanning line 16 is arranged upward.
Between a pair of adjacent scanning lines 16 spaced apart, the large sub-pixel electrode 221A of the display pixel 200A and the large sub-pixel electrode 221B of the display pixel 200B are one in the direction along the arrangement direction of the signal lines 15. It is arranged at the position where the part overlaps.
One of the two auxiliary capacitance lines 191 arranged between a pair of adjacent scanning lines 16 with an interval between them is a small sub-pixel electrode 211A and a large sub-pixel electrode 221A of all the display pixels 200A for one row. It overlaps with. The other of the two auxiliary capacitance lines 191 arranged between a pair of adjacent scanning lines 16 with an interval between them is the small sub-pixel electrode 211B and the large sub-pixel electrode 221B of all the display pixels 200B for one row. It overlaps with.
The auxiliary electrode line 192 overlaps the large sub-pixel electrodes 221A and 221B of all the display pixels 200A and 200B for two rows. Specifically, the auxiliary electrode line 192 overlaps the overlapping portion of the large subpixel electrodes 221A and 221B. Further, the auxiliary electrode line 192 does not overlap the small sub-pixel electrodes 211A and 211B of the display pixels 200A and 200B.
A pair of pixel groups 241 is configured by two display pixels 200A and 200B that are arranged between a pair of adjacent scanning lines 16 with a space therebetween and connected to the same signal line 15. Such pixel groups 241 are arranged in a matrix on the liquid crystal display panel 10.

[2] Second Example FIG. 22 is a plan view showing a second example of the arrangement of the display pixels 200.
The arrangement and arrangement of the signal lines 15, the scanning lines 16, the auxiliary capacitance lines 191, and the auxiliary electrode lines 192 are the same as those in the first example.

  The display pixels 200 </ b> A and the display pixels 200 </ b> B are alternately arranged along the odd-numbered signal lines 15. The display pixels 200 </ b> C and the display pixels 200 </ b> D are alternately arranged along the signal lines 15 in the even columns. Here, the display pixel 200B is obtained by rotating the display pixel 200A by 180 ° around an axis perpendicular to the display surface. The display pixel 200C is obtained by horizontally inverting the display pixel 200A. The display pixel 200D is obtained by vertically inverting the display pixel 200A. The display pixel 200A, the display pixel 200B, the display pixel 200C, and the display pixel 200D are provided in the same manner as the display pixel 200 described with reference to FIGS.

The display pixel 200A, the display pixel 200B, the display pixel 200C, and the display pixel 200D are arranged between a pair of adjacent scanning lines 16 with a space therebetween.
The display pixels 200 </ b> A and the display pixels 200 </ b> C are alternately arranged along one of a pair of adjacent scanning lines 16 with a space therebetween, and are connected to the one scanning line 16.
The display pixels 200 </ b> B and 200 </ b> D are alternately arranged along the other of the pair of adjacent scanning lines 16 with a space therebetween, and are connected to the other scanning line 16.
Between a pair of scanning lines 16 that are adjacent to each other at an interval, the large subpixel electrode 221A of the display pixel 200A, the large subpixel electrode 221B of the display pixel 200B, the large subpixel electrode 221C of the display pixel 200C, and the display The large subpixel electrode 221 </ b> D of the pixel 200 </ b> D is arranged at a position that partially overlaps in the direction along the arrangement direction of the signal lines 15.
One of the two auxiliary capacitance lines 191 arranged between a pair of adjacent scanning lines 16 with an interval between them is a small sub-pixel electrode 211A, 211C and a large sub-pixel electrode 211A, 211C of all the display pixels 200A, 200C for one row. It overlaps with the subpixel electrodes 221A and 221C. The other of the two auxiliary capacitance lines 191 arranged between a pair of adjacent scanning lines 16 with an interval between them is the small sub-pixel electrodes 211B and 211D and the large sub-pixel electrodes 211B and 211D of all the display pixels 200B and 200D for one row. It overlaps with the subpixel electrodes 221B and 221D.
The auxiliary electrode line 192 overlaps the large sub-pixel electrodes 221A, 221B, 221C, and 221D of all the display pixels 200A, 200B, 200C, and 200D for two rows. Specifically, the auxiliary electrode line 192 overlaps the overlapping portion of the large subpixel electrodes 221A, 221B, 221C, 221D. Further, the auxiliary electrode line 192 does not overlap the small sub-pixel electrodes 211A, 211B, 211C, and 211D of the display pixels 200A, 200B, 200C, and 200D.

  In the second example, a set of four display pixels 200 </ b> A, 200 </ b> B, 200 </ b> C, and 200 </ b> D that are arranged between a pair of adjacent scanning lines 16 with an interval and connected to two adjacent signal lines 15. Pixel group 242 is configured. Such pixel groups 242 are arranged in a matrix on the liquid crystal display panel 10.

[3] Third Example FIG. 23 is an enlarged plan view showing a third example of the arrangement of the display pixels 200.
The arrangement and arrangement of the signal lines 15, the scanning lines 16, the auxiliary capacitance lines 191, and the auxiliary electrode lines 192 are the same as those in the first example.

  The display pixels 200A, the display pixels 200B, the display pixels 200E, and the display pixels 200F are repeatedly arranged in this order along the odd-numbered signal lines 15. The display pixels 200C, the display pixels 200D, the display pixels 200G, and the display pixels 200H are repeatedly arranged in this order along the even-numbered signal lines 15. Here, the display pixel 200B is obtained by rotating the display pixel 200A by 180 ° around an axis perpendicular to the display surface. The display pixel 200C is obtained by horizontally inverting the display pixel 200A. The display pixel 200D is obtained by vertically inverting the display pixel 200A. The display pixel 200E and the display pixel 200G are in the same direction as the display pixel 200A. The display pixel 200F and the display pixel 200H are in the same direction as the display pixel 200B. The display pixels 200A to 200H are provided in the same manner as the display pixel 200 described with reference to FIGS.

The display pixels 200 </ b> A to 200 </ b> D are arranged between a pair of adjacent scanning lines 16 with a space therebetween. Display pixels 200E to 200H are arranged between a pair of scanning lines adjacent to the pair of scanning lines 16 in which the display pixels 200A, the display pixels 200B, the display pixels 200C, and the display pixels 200D are arranged.
In the set of scanning lines 16 in which the display pixels 200 </ b> A, 200 </ b> B, 200 </ b> C, and 200 </ b> D are arranged, the display pixels 200 </ b> A and the display pixels 200 </ b> C are alternately arranged along one scanning line 16. At the same time, the display pixel 200B and the display pixel 200D are alternately arranged along the other scanning line 16 and connected to the other scanning line 16.
In the set of scanning lines 16 in which the display pixels 200E, 200F, 200G, and 200H are arranged, the display pixels 200E and the display pixels 200G are alternately arranged along one scanning line 16. The display pixel 200F and the display pixel 200H are alternately arranged along the other scanning line 16, and are connected to the other scanning line 16.
Between the set of scanning lines 16 in which the display pixels 200A to 200D are arranged, the large subpixel electrode 221A of the display pixel 200A, the large subpixel electrode 221B of the display pixel 200B, and the large subpixel electrode 221C of the display pixel 200C. And the large sub-pixel electrode 221D of the display pixel 200D are arranged at positions that partially overlap in the direction along the arrangement direction of the signal lines 15.
Between the set of scanning lines 16 in which the display pixels 200E to 200H are arranged, the large subpixel electrode 221E of the display pixel 200E, the large subpixel electrode 221F of the display pixel 200F, and the large subpixel electrode 221G of the display pixel 200G. And the large sub-pixel electrode 221H of the display pixel 200H are arranged at positions that partially overlap in the direction along the arrangement direction of the signal lines 15.

One of the two auxiliary capacitance lines 191 arranged between the pair of scanning lines 16 in which the display pixels 200A to 200D are arranged is one of the small sub-pixel electrodes 211A and the sub-sub-pixel electrodes 211A of all the display pixels 200A and 200C for one row. 211C and the large subpixel electrodes 221A and 221C are overlapped. Of the two auxiliary capacitance lines 191 arranged between the set of scanning lines 16 in which the display pixels 200A to 200D are arranged, the other is the small sub-pixel electrode 211B of all the display pixels 200B and 200D for one row. 211D and large subpixel electrodes 221B and 221D overlap.
The auxiliary electrode lines 192 arranged between the set of scanning lines 16 in which the display pixels 200A to 200D are arranged are large sub-pixel electrodes 221A and 221B of all the display pixels 200A, 200B, 200C, and 200D for two rows. , 221C, 221D. Specifically, the auxiliary electrode line 192 overlaps the overlapping portion of the large subpixel electrodes 221A, 221B, 221C, 221D.

One of the two auxiliary capacitance lines 191 arranged between the set of scanning lines 16 in which the display pixels 200E to 200H are arranged is one of the small sub-pixel electrodes 211E and 200E of the display pixels 200E and 200G for one row. 211G and the large subpixel electrodes 221E and 221G overlap. Of the two auxiliary capacitance lines 191 disposed between the set of scanning lines 16 in which the display pixels 200E to 200H are arranged, the other is the small sub-pixel electrode 211F of all the display pixels 200F and 200H for one row. 211H and large subpixel electrodes 221F and 221H.
The auxiliary electrode lines 192 arranged between the pair of scanning lines 16 in which the display pixels 200E to 200H are arranged are large sub-pixel electrodes 221E and 221F of all the display pixels 200E, 200F, 200G, and 200H for two rows. , 221G, 221H. Specifically, the auxiliary electrode line 192 overlaps the overlapping portion of the large subpixel electrodes 221E, 221F, 221G, and 221G.

  In the third example, a set of pixel groups 243 is constituted by eight display pixels 200A to 200H arranged close to each other as shown in FIG. 23. Such a pixel group 243 is formed on the liquid crystal display panel 10. They are arranged in a matrix.

[4] Fourth Example FIG. 24 is an enlarged plan view showing a fourth example of the arrangement of the display pixels 200.
The arrangement of the signal line 15, the scanning line 16, the auxiliary capacitance line 191 and the auxiliary electrode line 192 is the same as that in the first example.

  The display pixels 200 </ b> A and the display pixels 200 </ b> B are alternately arranged along the predetermined signal line 15. Display pixels 200 </ b> C and display pixels 200 </ b> D are alternately arranged along the adjacent signal line 15. Further, the display pixels 200E and the display pixels 200F are alternately arranged along the adjacent signal lines 15. Further, the display pixels 200G and the display pixels 200H are alternately arranged along the adjacent signal lines 15. The display pixel 200A and the display pixel 200B, the display pixel 200C and the display pixel 200D, the display pixel 200E and the display pixel 200F, and the display pixel 200G and the display pixel 200H are repeated in this order. Are arranged.

  Here, the display pixel 200B is obtained by rotating the display pixel 200A by 180 ° around an axis perpendicular to the display surface. The display pixel 200C and the display pixel 200E are obtained by horizontally inverting the display pixel 200A. The display pixel 200D is obtained by vertically inverting the display pixel 200A. The display pixel 200E is in the same direction as the display pixel 200C. The display pixel 200F is in the same direction as the display pixel 200D. The display pixel 200H is in the same direction as the display pixel 200B. The display pixels 200A to 200H are provided in the same manner as the display pixel 200 described with reference to FIGS.

The display pixels 200 </ b> A to 200 </ b> H are arranged between a pair of adjacent scanning lines 16 with a space therebetween.
The display pixel 200A, the display pixel 200C, the display pixel 200E, and the display pixel 200G are repeatedly arranged in this order along one of a pair of adjacent scanning lines 16 with a space therebetween, and one of the scans Connected to line 16.
The display pixel 200B, the display pixel 200D, the display pixel 200F, and the display pixel 200H are repeatedly arranged in this order along the other of the pair of adjacent scanning lines 16 with an interval therebetween, and the other scanning. Connected to line 16.
Between a pair of scanning lines 16 that are adjacent to each other at intervals, the large subpixel electrodes 221A to 221H of the display pixels 200A to 200H are arranged at positions that partially overlap in the direction along the arrangement direction of the signal lines 15. Has been.
One of the two auxiliary capacitance lines 191 arranged between a pair of adjacent scanning lines 16 with an interval between them is a small sub-pixel electrode 211A of all the display pixels 200A, 200C, 200E, and 200G for one row. , 211C, 211E, 211G and large subpixel electrodes 221A, 221C, 221E, 221G. The other of the two auxiliary capacitance lines 191 arranged between a pair of adjacent scanning lines 16 with an interval between them is the small sub-pixel electrode 211B of all the display pixels 200B, 200D, 200F, and 200G for one row. , 211D, 211F, 211G and large subpixel electrodes 221B, 221D, 221F, 221G.
The auxiliary electrode line 192 overlaps the large sub-pixel electrodes 221A to 221H of all the display pixels 200A to 200H for two rows. Specifically, the auxiliary electrode line 192 overlaps the overlapping portion of the large subpixel electrodes 221A to 221H.

  In the fourth example, a set of pixel groups 243 is constituted by eight display pixels 200A to 200H arranged close to each other as shown in FIG. 23. Such a pixel group 243 is formed on the liquid crystal display panel 10. They are arranged in a matrix.

  As described above, in any of the first to fourth examples, since horizontal sub-columns include the small sub-pixel electrodes 211 and the large sub-pixel electrodes 221, horizontal stripes are generated on the display screen. Can be suppressed. On the other hand, since the small subpixel electrode 211 and the large subpixel electrode 221 are also mixed in the vertical column, it is possible to suppress the occurrence of vertical stripes on the display screen.

<Second Embodiment>
Next, a second embodiment of the present invention will be described with reference to FIGS. The portions corresponding to the liquid crystal display device 1 of the first embodiment are denoted by the same reference numerals. Except as described below, the first embodiment and the second embodiment are similarly provided.

FIG. 25 is a plan view of the display pixel 200 in the second embodiment. The auxiliary electrode line 192 is bent. The auxiliary electrode line 192 is provided so as to overlap the small subpixel electrode 211 in the display pixel 200. On the other hand, the auxiliary electrode line 192 is provided so as to be avoided from the large subpixel electrode 221. That is, the large subpixel electrode 221 is formed so that the end thereof is notched, the auxiliary electrode line 192 is bent at the notched portion, and the auxiliary electrode line 192 and the large subpixel electrode 221 do not overlap. Therefore, the auxiliary electrode line 192 forms a third auxiliary capacitor 18c with the small subpixel electrode 211, and does not form a capacitor with the large subpixel electrode 221.
Here, in this embodiment, the large sub-pixel electrode 221 is the first pixel electrode, the small sub-pixel electrode 211 is the second pixel electrode, the switch element 222 is the first switch element, and the switch The element 212 is a second switch element.

  FIG. 26 is a diagram illustrating signals input / output in each unit constituting the liquid crystal display device 1 according to the second embodiment. The waveform signal Vd becomes the low voltage Vdl when the polarity inversion signal Pol is at the high level Vsh. On the other hand, when the polarity inversion signal Pol is at the low level Vsl, the high voltage Vdh is obtained. That is, the waveform signal Vd is a rectangular AC signal having an opposite phase synchronized with the polarity inversion signal Pol. The waveform signal Vd has an opposite phase to the gradation signal S (i) output to the signal line 15.

The voltage applied to the small subpixel electrode 211 and the large subpixel electrode 221 in the liquid crystal display device 1 according to the second embodiment will be described with reference to FIGS. 27 and 28. FIG.
FIG. 27 is a voltage timing chart regarding the large sub-pixel 220. As shown in FIG. 27, since the switch element 222 is open in the selection period, the voltage Vsig corresponding to the gradation signal S (i) is applied to the large subpixel electrode 221. In the subsequent non-selection period, when the switch element 222 is closed, the voltage of the large subpixel electrode 221 drops by ΔV from the voltage Vsig, and the difference between the voltage of the large subpixel electrode 221 and the common voltage Vcom of the common electrode 14 becomes Vlc. Become.

FIG. 28 is a voltage timing chart regarding the small sub-pixel 210. As shown in FIG. 28, since the switch element 212 is open in the selection period, the voltage Vsig corresponding to the gradation signal S (i) is applied to the small subpixel electrode 211. In the subsequent non-selection period, since the switch element 212 is closed, the small sub-pixel electrode 211 is in a floating state. Even during the non-selection period, since the waveform signal Vd is output to the auxiliary electrode line 192, the voltage of the small subpixel electrode 211 vibrates. Therefore, the absolute value of the effective voltage of the small sub-pixel electrode 211 in the non-selection period with the voltage of the common electrode 14 as a reference is the square root mean square of the voltage difference Vlc2 and the voltage difference Vlc.
Therefore, the absolute value of the effective voltage of the small subpixel electrode 211 in the non-selection period with respect to the voltage of the common electrode 14 is the effective voltage of the large subpixel electrode 221 in the non-selection period with reference to the voltage of the common electrode 14. It is larger than the absolute value by | Vlc2−Vlc | / 2.

  29 and 30 are diagrams illustrating an example of the light transmittance characteristic of the liquid crystal overlapping the small subpixel electrode 211 and the light transmittance characteristic of the liquid crystal overlapping the large subpixel electrode 221. FIG. 29 and 30, the horizontal axis indicates the absolute value of the voltage of the signal line 15 (based on the voltage of the common electrode 14) in the selection period. The vertical axis represents the transmittance of the liquid crystal during the non-selection period. The transmittance on the vertical axis is a relative value with respect to the maximum value of transmittance in each light transmittance characteristic. A curve VT1 represents the relationship between the voltage and the transmittance with respect to the liquid crystal overlapping the small subpixel electrode 211. A curve VT2 represents the relationship between the voltage and the transmittance for the liquid crystal overlapping the large subpixel electrode 221. As is clear from FIG. 29, the absolute value of the effective voltage of the small sub-pixel electrode 211 in the non-selection period based on the voltage of the common electrode 14 is the large sub-pixel in the non-selection period based on the voltage of the common electrode 14. Since the voltage is higher than the effective voltage of the electrode 221, the curve VT1 is shifted to a lower voltage side than the curve VT2. That is, even one display pixel 200 has the characteristics of the curve VT1 and the characteristics of the curve VT2.

  FIG. 30 is a diagram in the case where the curve VT1 is shifted in a direction approaching the curve VT2. By reducing the amplitude width of the waveform signal Vd generated by the waveform signal generation circuit 70, the curve VT1 can be shifted closer to the curve VT2.

FIG. 31 is a plan view showing the arrangement of the display pixels 200 in the second embodiment.
A plurality of signal lines 15 extend vertically (in the vertical direction). These signal lines 15 are arranged on the left and right at equal intervals.

  A plurality of scanning lines 16 extend left and right (horizontal direction). These scanning lines 16 are arranged one above the other. Each scanning line 16 has two adjacent scanning lines 16 arranged close to each other, and is spaced from each other by the two scanning lines 16. It is arranged. Two scanning lines 16 adjacent to each other with this interval are taken into consideration as a set.

The plurality of auxiliary capacitance lines 191 extend to the left and right and are parallel to the scanning line 16. The number of auxiliary capacitance lines 191 and the number of scanning lines 16 are the same number (= N). These auxiliary capacitance lines 191 are arranged vertically. Two auxiliary capacitance lines 191 are arranged between a pair of adjacent scanning lines 16 with a space therebetween.
The number of auxiliary electrode lines 192 is half the number of scanning lines 16 (= N / 2). These auxiliary electrode lines 192 are provided in a twisted manner and are laid in the left-right direction so as to meander up and down. One auxiliary capacitance line 192 is disposed between a pair of adjacent scanning lines 16 with a space therebetween, and two auxiliary capacitance lines 191 between the pair of scanning lines 16 are provided. It is arranged between.

Display pixels 200 </ b> A and display pixels 200 </ b> B are alternately arranged along each signal line 15. Here, the display pixel 200B is obtained by rotating the display pixel 200A by 180 ° around an axis perpendicular to the display surface. The display pixel 200A and the display pixel 200B are provided in the same manner as the display pixel 200 described with reference to FIG.
The display pixels 200A and the display pixels 200B are arranged between a pair of adjacent scanning lines 16 with a space therebetween.
These display pixels 200 </ b> A are arranged along one of a pair of adjacent scanning lines 16 with a space therebetween, and are connected to the one scanning line 16. These display pixels 200 </ b> B are arranged along the other of a pair of adjacent scanning lines 16 with a space therebetween, and are connected to the other scanning line 16.
One of the two auxiliary capacitance lines 191 arranged between a pair of adjacent scanning lines 16 with an interval between them is a small sub-pixel electrode 211A and a large sub-pixel electrode 221A of all the display pixels 200A for one row. It overlaps with. The other of the two auxiliary capacitance lines 191 arranged between a pair of adjacent scanning lines 16 with an interval between them is the small sub-pixel electrode 211B and the large sub-pixel electrode 221B of all the display pixels 200B for one row. It overlaps with.
The auxiliary electrode line 192 overlaps the small sub-pixel electrodes 211A and 211B of all the display pixels 200A and 200B for two rows. On the other hand, the auxiliary electrode line 192 meanders so as to avoid the large subpixel electrodes 221A and 211B of the display pixels 200A and 200B, and does not overlap the large subpixel electrodes 221A and 211B.
A pair of pixel groups 241 is configured by two display pixels 200A and 200B that are arranged between a pair of adjacent scanning lines 16 with a space therebetween and connected to the same signal line 15. Such pixel groups 241 are arranged in a matrix on the liquid crystal display panel 10.

  As described above, also in the second embodiment, the viewing angle dependency can be suppressed and gradation inversion can be eliminated as in the first embodiment. Therefore, high image quality can be achieved.

DESCRIPTION OF SYMBOLS 1 Liquid crystal display device 10 Liquid crystal display panel 14 Common electrode 15 Signal line 16 Scan line 18c Third auxiliary capacitor 30 Data driver 40 Scan driver 70 Waveform signal generation circuit (voltage application circuit)
90 Drive device 100 Electronic device 191 Auxiliary capacitance line 192 Auxiliary electrode line (auxiliary electrode)
211 Large pixel electrode (first pixel electrode, second pixel electrode)
212 switch elements (first switch element, second switch element)
222 switch element (second switch element, first switch element)
221 Small pixel electrode (second pixel electrode, first pixel electrode)

Claims (13)

A first scan line and a second scan line arranged adjacently along a first direction;
A signal line provided along a second direction orthogonal to the first direction;
A first pixel electrode and a second pixel electrode connected to the first scanning line and the signal line and disposed along the first direction, wherein the first pixel electrode and the second pixel electrode; A first display pixel having areas different from each other by the second pixel electrode;
A third pixel disposed adjacent to the first display pixel in the second direction, connected to the second scanning line and the signal line, and disposed along the first direction; A third pixel electrode having the same area as the second pixel electrode, and the fourth pixel electrode having the same area as the first pixel electrode. The third pixel electrode is disposed adjacent to the first pixel electrode along the second direction, and the fourth pixel electrode is disposed on the second pixel electrode. A second display pixel disposed adjacently along the direction;
An auxiliary electrode line provided in a plane overlapping with one of the first pixel electrode and the fourth pixel electrode, or the second pixel electrode and the third pixel electrode;
I have a,
The auxiliary electrode line is (1) provided in a position overlapping with the first pixel electrode and the fourth pixel electrode in a plane, and is planar with the second pixel electrode and the third pixel electrode. (2) The first pixel electrode and the fourth pixel are provided at a position that overlaps the second pixel electrode and the third pixel electrode in a plane. A liquid crystal display device, wherein the liquid crystal display device is provided at a position that does not overlap the electrode in a planar manner . A second effective voltage applied to the second pixel electrode is made different from a first effective voltage applied to the first pixel electrode, and a third effective voltage applied to the third pixel electrode is changed. 2. The liquid crystal according to claim 1 , further comprising: a voltage application circuit that applies a voltage signal to the auxiliary electrode line that makes the fourth effective voltage applied to the fourth pixel electrode different from the effective voltage. Display device. A scanning driver for sequentially selecting the first scanning line and the second scanning line for each selection period;
The liquid crystal display device according to claim 2 , wherein the voltage signal includes a waveform signal having the selection period as a half cycle. A common electrode facing the first pixel electrode, the second pixel electrode, the third pixel electrode, and the fourth pixel electrode through a liquid crystal layer;
A data driver that outputs, to the plurality of signal lines, gradation signals whose polarity is inverted in synchronization with the selection period with reference to the potential of the common electrode;
Have
The second pixel electrode has a larger area than the first pixel electrode;
The auxiliary electrode line is provided at a position overlapping the second pixel electrode and the third pixel electrode in a plane,
The liquid crystal display device according to claim 3 , wherein the voltage signal has a waveform signal in phase with the gradation signal. A common electrode facing the first pixel electrode, the second pixel electrode, the third pixel electrode, and the fourth pixel electrode through a liquid crystal layer;
A data driver that outputs to the plurality of signal lines gradation signals whose polarity is inverted in synchronization with the selection period with reference to the voltage of the common electrode;
Have
The second pixel electrode has a smaller area than the first pixel electrode;
The auxiliary electrode line is provided at a position overlapping the second pixel electrode and the third pixel electrode in a plane,
The liquid crystal display device according to claim 3 , wherein the voltage signal has a waveform signal having an opposite phase to the gradation signal. A third display pixel disposed adjacent to the first display pixel along the first direction; and a third display pixel disposed adjacent to the third display pixel in the second direction. A fourth display pixel disposed adjacent to the second display pixel along the first direction,
The third display pixel includes a fifth pixel electrode and a sixth pixel electrode arranged along the first direction, and the fifth pixel electrode is connected to the second pixel electrode. The sixth pixel electrode has the same area as the first pixel electrode;
The fourth display pixel includes a seventh pixel electrode and an eighth pixel electrode arranged along the first direction, and the seventh pixel electrode is connected to the first pixel electrode. The eighth pixel electrode has the same area as the second pixel electrode;
The seventh pixel electrode is disposed adjacent to the fifth pixel electrode along the second direction, and the eighth pixel electrode is disposed in the second direction with respect to the sixth pixel electrode. Arranged adjacent to each other,
The second pixel electrode and the fifth pixel electrode are disposed adjacent to each other along the first direction,
The fourth pixel electrode and the seventh pixel electrode of the liquid crystal display device according to any one of claims 1 to 3, characterized in that it is arranged adjacent along the first direction. The auxiliary electrode line is provided at a position overlapping in plan with respect to one of the fifth pixel electrode and the eighth pixel electrode, or the sixth pixel electrode and the seventh pixel electrode. The liquid crystal display device according to claim 6 . A fifth display pixel disposed adjacent to the second display pixel along the second direction; and a fifth display pixel disposed adjacent to the fifth display pixel along the second direction. A sixth display pixel provided,
The fifth display pixel includes a ninth pixel electrode and a tenth pixel electrode arranged along the first direction, and the ninth pixel electrode is connected to the second pixel electrode. The tenth pixel electrode has the same area as the first pixel electrode;
The sixth display pixel includes an eleventh pixel electrode and a twelfth pixel electrode arranged along the first direction, and the eleventh pixel electrode is connected to the first pixel electrode. The twelfth pixel electrode has the same area as the second pixel electrode;
The eleventh pixel electrode is disposed adjacent to the ninth pixel electrode along the second direction, and the twelfth pixel electrode is disposed in the second direction with respect to the tenth pixel electrode. Arranged adjacent to each other,
The ninth pixel electrode is disposed adjacent to the third pixel electrode along the second direction, and the tenth pixel electrode is disposed in the second direction with respect to the fourth pixel electrode. the liquid crystal display device according to any one of claims 1 to 3, characterized in that it is disposed adjacent along. The auxiliary electrode line is provided at a position overlapping in plan with one of the ninth pixel electrode and the twelfth pixel electrode, or the tenth pixel electrode and the eleventh pixel electrode. The liquid crystal display device according to claim 8 . An electronic apparatus comprising the liquid crystal display device according to any one of claims 1 to 9 . A first scanning line and a second scanning line arranged adjacently along a first direction; a signal line provided along a second direction perpendicular to the first direction; and the signal A first pixel electrode and a second pixel electrode connected to the first scanning line and disposed along the first direction, wherein the second pixel electrode is the first pixel electrode. A first display pixel having an area larger than that of the pixel electrode, and disposed adjacent to the first display pixel in the second direction, connected to the signal line and the second scanning line, A third pixel electrode and a fourth pixel electrode disposed along the first direction, the third pixel electrode having the same area as the second pixel electrode; The fourth pixel electrode has the same area as the first pixel electrode, and the third pixel electrode extends along the second direction with respect to the first pixel electrode. A second display pixel disposed adjacent to the second pixel electrode along the second direction with respect to the second pixel electrode; and the first pixel. The second pixel is provided at a position that does not overlap the second pixel electrode and the third pixel electrode when it is provided at a position that overlaps the electrode and the fourth pixel electrode. An auxiliary electrode line provided at a position that does not overlap the first pixel electrode and the fourth pixel electrode when provided in a position that overlaps the electrode and the third pixel electrode in a plane; A driving method for driving a liquid crystal display panel having a first electrode, a second pixel electrode, a third pixel electrode, and a common electrode facing the fourth pixel electrode through a liquid crystal layer Because
A scanning line driving step of sequentially selecting the first scanning line and the second scanning line for each selection period;
A common electrode driving step of setting the common electrode to a constant potential;
A signal line driving step for outputting to the signal line a gradation signal whose polarity is inverted in synchronization with the selection period with reference to the potential of the common electrode;
An auxiliary electrode line that has a waveform signal with the selection period as a half cycle and applies a voltage signal that makes the effective voltage of the second pixel electrode different from the effective voltage of the first pixel electrode. A driving step;
A driving method comprising: 12. The driving method according to claim 11, wherein the auxiliary electrode line driving step includes a first voltage signal setting step of setting the voltage signal to a waveform signal in phase with the gradation signal. 12. The driving method according to claim 11, wherein the auxiliary electrode line driving step includes a second voltage signal setting step of setting the voltage signal to a waveform signal having a phase opposite to that of the gradation signal.

Images