JP5381223B2 - Multilayer printed wiring board manufacturing method and multilayer printed wiring board - Google Patents

Description

  The present invention relates to a printed circuit board on which electronic equipment components are mounted, a method for manufacturing a multilayer printed wiring board used as an interposer substrate for mounting a semiconductor in a semiconductor package, and a multilayer printed wiring board using the same.

  In recent years, with the advancement of electronic technology, in order to achieve high-speed computing functions in electronic devices such as computers and network-related devices, a dramatic increase in I / O due to multicore MPUs, multiprocessors, etc. Due to advances in parallel processing, the number of signal transmission bus lines has increased dramatically, the density of signal lines per unit area has increased, and a higher density of printed wiring boards has been demanded. . For this reason, there is a multilayered number of layers that can meet such a demand, and a multilayer printed wiring board is becoming more necessary.

  The wiring rules of multilayer printed wiring boards tend to become finer year by year, and in particular, in applications called interposer substrates for semiconductor packages or semiconductor package substrates, it has become prominent, and wiring widths of 25 μm or less A gap has been required. The demand for a printed wiring board for a semiconductor package is entering a region where it is difficult to achieve it by the semi-additive method, which is a typical method for forming fine wiring.

  From the viewpoint of wiring formation, it is possible to form fine wiring when the wiring layer is thinner than the semi-additive method by using a method called the full additive method, but the conventional full additive method can be used. However, since the resist for patterning is finally used as an insulating layer, there is a big problem that the reliability of the insulating layer is low, and the present state is hardly used as a construction method.

  As a method for solving these problems, as shown in Patent Document 1, a damascene method, which is a method used for manufacturing a semiconductor and developed for forming the internal wiring, is used for a printed wiring board. Although there is a construction method, there is a major drawback in that when the pattern becomes fine, the difficulty of producing a press die for the insulating layer increases, and the cost increases dramatically.

Japanese Patent No. 4129971

  The present invention has been made in view of the disadvantages of the prior art, and achieves a higher wiring width and a gap between the wirings than the conventional method, and a multilayer printed wiring board using a highly reliable insulating material. It is an object to provide a manufacturing method.

The present invention solves such problems, and the invention according to claim 1 for solving the above problems is a method for producing a multilayer printed wiring board,
(1) Press work is performed on the upper and lower surfaces of the insulating layer 1 by using an upper pattern forming die and a lower pattern forming die having different wiring pattern shapes,
(2) forming grooves of each wiring pattern shape on the upper and lower surfaces of the insulating layer 1;
(3) Remove the lower lower pattern forming mold,
(4) Form a wiring pattern 1 by filling a conductive material at least inside the groove of the wiring pattern shape on the lower side of the insulating layer 1;
(5) Form the plane 1 by processing the lower surface of the wiring pattern 1 and the lower surface of the insulating layer to be in the same plane,
(6) An insulating layer 2 is formed under the plane 1, and then an adhesive layer is further formed on the lower surface thereof,
(7) Remove the upper pattern forming mold,
(8) Form a wiring pattern 2 by filling a conductive material inside the groove of the wiring pattern shape on the upper side of the insulating layer 1 exposed at least;
(9) Form the plane 2 by processing the upper surface of the wiring pattern 2 and the upper surface of the insulating layer 1 to be in the same plane,
(10) From the lower surface side , a hole is formed through the adhesive layer and the insulating layer 2 so that the wiring pattern 1 is exposed, and / or the adhesive layer, the insulating layer 2 and the insulating layer 1 are formed. A hole is formed so that the wiring pattern 2 is exposed through,
(11) A hole is formed so that the wiring pattern 1 is exposed through the insulating layer 1 from the upper surface side,
( 12 ) Filling the hole with a conductive material to form a via hole for electrical connection;
A multilayer printed wiring board formed by laminating a plurality of layers using the unit layer formed by performing each step of (1) to ( 12 ) so as to ensure conduction of the via hole during lamination. Production method.
It is.

  According to a second aspect of the present invention, the convex portions of the upper pattern forming mold for the upper surface of the insulating layer 1 and the lower pattern forming mold for the lower surface are arranged at positions where the upper surface and the lower surface do not overlap each other. The method for producing a multilayer printed wiring board according to claim 1.

  The invention according to claim 3 is the method for producing a multilayer printed wiring board according to claim 1 or 2, wherein the material of the insulating layer is made of at least an organic polymer material.

  Invention of Claim 4 is a multilayer printed wiring board manufactured with the manufacturing method of the multilayer printed wiring board described in any one of Claims 1-3.

  According to the present invention, the insulating layer is pressed to form a groove, and the inside of the groove is filled with a conductive material, so that a higher wiring width and a gap between the wirings can be obtained than in the conventional semi-additive method. Since an insulating material that can be realized and has high reliability can be used, a method for manufacturing a multilayer printed wiring board with high density and high reliability can be provided. Moreover, the printed wiring board using the manufacturing method can be provided.

It is a figure explaining the manufacturing method of the multilayer printed wiring board of this invention. It is a figure explaining the manufacturing method of the multilayer printed wiring board of this invention demonstrated in an Example.

  Although an example of the manufacturing method of the multilayer printed wiring board of this invention is demonstrated using FIG. 1, this invention is not necessarily limited to this.

  A material for the insulating layer 101 is prepared (FIG. 1A). As a material for the insulating layer 101, a thermosetting resin or a photopolymerization resin that is an organic polymer material can be used. The material of the insulating layer 101 is preferably a B stage or a C stage.

Press processing is performed using the lower surface pattern forming die 102 and the upper surface pattern forming die 103 in which wiring patterns are formed from above and below the insulating layer 101 (FIG. 1B). A vacuum laminator, a vacuum press machine, etc. can be used for pressing. Further, the lower surface pattern forming mold 102 and the upper surface pattern forming mold 103 can be made of metal by etching or cutting, or ceramic or resin can be used. In view of the burden on the mold during pressing, it is desirable that the metal is used. The gap between the pattern forming dies at the time of pressing is preferably about 1 to 50 μm.

  Next, the lower surface pattern forming mold 102 is removed (FIG. 1C).

  Next, a conductive material layer is formed on the entire surface of the insulating layer 101 from which the lower surface pattern forming mold 102 is removed. A metal can be used as the material of the conductive material layer, but the present invention is not limited to this.

The case where a metal is used as the conductive material layer will be described next.
First, a metal seed layer for electrolytic plating is formed by performing electroless plating or vapor deposition. The thickness of the metal seed layer is preferably about 0.1 to 1.0 μm. Examples of the method for forming the metal seed layer include electroless plating methods and vapor deposition methods. In view of cost, electroless plating is preferable.

  The metal seed layer can be selected from metals such as Ni, Cr, Au, Cu, Ag, Al, Sn, Zn, and Pb. From the viewpoint of conductivity, workability, cost, etc., Cu is preferable.

In order to improve the adhesion between the metal seed layer formed on the insulating layer 101 and the insulating layer 101, the surface of the insulating layer 101 preferably has a surface roughness Rz of 0.1 μm or more. The insulating layer 101 having such a surface roughness can be obtained by surface ashing using a surface roughening method using a chemical solution or a dry process. Here, as the chemical solution used for the surface roughening method, permanganate and dichromate can be used. As the dry process, Ar plasma ashing, O ₂ plasma ashing, and N ₂ plasma ashing can be used. Next, a conductive material layer 104 is formed on the metal seed layer by electrolytic plating (FIG. 4). The material of the conductive material layer 104 can be selected from metals such as Ni, Cr, Au, Cu, Ag, Al, Sn, Zn, and Pb. From the viewpoint of conductivity, workability, cost, etc., Cu is preferable.

  Next, the conductive material layer 104 is removed until the insulating layer 101 appears on the same plane (FIG. 1E). The method for removing the conductive material layer can be selected from wet etching, dry etching, and mechanical polishing. Thereby, a part of the conductive material layer 104 becomes the wiring portion 105. In this way, a first plane in which the insulating layer 101 and the wiring portion 105 are mixed on the same plane is formed.

  Next, an insulating layer 106 is formed on the first plane (FIG. 1 (f)). As a material of the insulating layer 106, an organic polymer material such as a thermosetting resin or a photopolymerization resin can be used. In consideration of shrinkage due to heat, the same material as the insulating layer 101 is preferable. In addition, as a method for forming the insulating layer 106, a press method, a laminating method, and a die coating can be given. Thereafter, an adhesive layer is formed on the surface of the insulating layer 106.

  Next, the upper surface pattern forming mold 103 remaining on the insulating layer 101 is removed (FIG. 1G). A wiring portion 107 is formed on the surface of the insulating layer 101 from which the upper surface pattern forming mold 103 has been removed by the same method as described above (FIG. 1H). In this way, in FIG. 1H, the upper plane composed of the wiring portion 107 and the insulating layer 101 is defined as the second plane.

  A predetermined via hole pattern is aligned with the insulating layer 106, a hole 108 is formed by a laser, and a desmear process is performed (FIG. 1 (i)). The hole 108 is filled with a conductive material to form a buried via hole (FIG. 1 (j)). Examples of the method for filling the conductive material include plating, filling a conductive paste with a dispenser, and embedding a conductive metal post.

  Similarly, a via hole is formed in the insulating layer 101.

  The first unit layer 110 of the multilayer printed wiring board is formed by performing the above steps (FIG. 1 (j)).

  A second unit layer 111 manufactured by the same manufacturing method using a pattern forming mold different from the first unit layer 110 is aligned and stacked on the first unit layer 110 (FIG. 1 (k)).

  The steps described in the method for manufacturing a multilayer printed wiring board are repeated until the desired number of layers are stacked. When laminating, a laminating method or a pressing method can be selected. An insulating layer is formed on the outermost layer with a solder resist. Thus, the manufacturing method of a multilayer printed wiring board can be shown.

  Hereinafter, the present invention will be described with reference to FIG. 2, but the present invention is not limited thereto.

Insulating resin with a thickness of 35 μm (ABF-GX code13, Ajinomoto Fine Techno Co., Ltd. product name) Double-side pressing was performed at cm ² for 60 seconds, and then the insulating layer 201 was formed by curing at 180 ° C. for 30 minutes (FIG. 2B) The gap between the pattern forming dies at the time of pressing was 10 μm. This corresponds to the width of the gap between the wirings in the wiring layer, and the size of the groove corresponding to the wiring width is also 10 μm, so that L / S (Line / Space) = 10/10 ( The pattern forming molds 202 and 203 were manufactured by etching stainless steel and performing nickel plating on the surface.

  The lower surface pattern forming mold 202 is peeled off from the insulating layer 201 (FIG. 2C), and the insulating layer 201 is immersed in a 60 ° C. solution of potassium permanganate 6 g / L and sodium hydroxide 40 g / L for 5 minutes. The surface was roughened.

  Next, as a pretreatment for electroless copper plating, the insulating layer 201 is immersed in a pre-dip liquid PD-301 (trade name, manufactured by Hitachi Chemical Co., Ltd.) having a concentration of 250 g / L, and then a sensitizer HS-202B. (Product name, manufactured by Hitachi Chemical Co., Ltd.) is dipped, then immersion treatment ADP-601 (product name, manufactured by Hitachi Chemical Co., Ltd.) is dipped, and then CUST-201 (Hitachi Chemical Co., Ltd.). Electroless copper plating was performed for 20 minutes using a trade name, manufactured by Co., Ltd. to form a metal seed layer having a thickness of 0.8 μm.

  Next, electrolytic copper plating was performed on the entire surface of the metal seed layer under the following conditions to form an electrolytic copper plating film 204 having a thickness of 30 μm (FIG. 2D).

(Electrolytic plating aqueous solution)
Sulfuric acid 180g / L
Copper sulfate 80g / L
Additive (Kaparaside GL, manufactured by Atotech Japan) 1mL / L
[Electrolytic plating conditions]
Current density 1A / dm ²
Time 60 minutes Temperature Room temperature Thereafter, the electrolytic copper plating film was polished by heavy buffing until the wiring portion 205 and the insulating layer 201 were on the same plane (FIG. 2 (e)).

On the insulating resin layer 201, a 0.1 μm thick adhesive layer is vacuum-laminated at 110 ° C. and 0.7 MPa on an insulating resin (ABF-GX code13, Ajinomoto Fine Techno Co., Ltd.) having a thickness of 35 μm. ℃, 6kgf / ^cm 2, 60 sec 180 ° C. after fluttering with both sides pressed, the formation of the insulating layer 206 by cured at 30 min (FIG. 2 (f)). Further, an adhesive layer was formed on the insulating layer 206 by pressing.

  The upper surface pattern forming mold 203 is peeled off from the insulating resin layer (FIG. 2G). A wiring layer 207 made of copper was formed on the peeled surface of the lower surface pattern forming mold 202 by the same method as described above (FIG. 2H).

  A predetermined via pattern alignment was aligned on both surfaces of the insulating layers 201 and 206, and a via hole 208 of φ90 μm was formed with a carbon dioxide laser. Furthermore, it was immersed in a 60 ° C. solution of potassium permanganate 60 g / L and sodium hydroxide 40 g / L for 5 minutes to perform desmearing and roughening treatment (FIG. 2 (i)).

  A via paste was filled in the via to form a via hole 209 (FIG. 2 (j)), and a first unit layer was created. The second unit layer 210 produced by the same method as described above was aligned and then laminated and laminated by lamination (FIG. 2 (k)).

  Through the above steps, a multilayer printed wiring board having L / S = 10/10 (μm), which is a specification difficult to realize by the conventional method, was prepared. Since the wiring rule of the wiring plate is one layer up and down, the pattern forming mold can be easily manufactured. Further, as a result of the reliability test, no disconnection or short circuit of the copper wiring was found.

DESCRIPTION OF SYMBOLS 101 Insulating layer 102 Lower surface pattern formation type 103 Upper surface pattern formation type 104 Conductive material layer 105 Wiring part 106 Insulating layer 107 Wiring part 108 Hole 109 Via hole 110 1st unit layer (multilayer printed wiring board 1st layer)
111 Second unit layer (multilayer printed wiring board second layer
201 Insulating layer 202 Lower surface pattern forming die 203 Upper surface pattern forming die 204 Conductive material layer 205 Wiring portion 206 Insulating layer 207 Wiring portion 208 Hole 209 Via hole 210 First unit layer (multilayer printed wiring board first layer)
211 Second unit layer (multilayer printed wiring board second layer)

Claims (4)

In a manufacturing method of a multilayer printed wiring board, wherein a multilayer printed wiring board is manufactured by laminating unit layers composed of at least an insulating layer and a wiring portion,
(1) Pressing the upper and lower surfaces of the insulating layer 1 by using an upper surface pattern forming die and a lower surface pattern forming die having different wiring pattern shapes,
(2) forming grooves of each wiring pattern shape on the upper and lower surfaces of the insulating layer 1;
(3) Remove the lower lower surface pattern forming mold,
(4) Form a wiring pattern 1 by filling a conductive material at least inside the groove of the wiring pattern shape on the lower side of the insulating layer 1;
(5) Form the plane 1 by processing the lower surface of the wiring pattern 1 and the lower surface of the insulating layer to be in the same plane,
(6) An insulating layer 2 is formed under the plane 1, and then an adhesive layer is further formed on the lower surface thereof,
(7) Remove the upper surface pattern forming mold,
(8) Form a wiring pattern 2 by filling a conductive material inside the groove of the wiring pattern shape on the upper side of the insulating layer 1 exposed at least;
(9) Form the plane 2 by processing the upper surface of the wiring pattern 2 and the upper surface of the insulating layer 1 to be in the same plane,
(10) From the lower surface side , a hole is formed through the adhesive layer and the insulating layer 2 so that the wiring pattern 1 is exposed, and / or the adhesive layer, the insulating layer 2 and the insulating layer 1 are formed. A hole is formed so that the wiring pattern 2 is exposed through,
(11) A hole is formed so that the wiring pattern 1 is exposed through the insulating layer 1 from the upper surface side,
( 12 ) Filling the hole with a conductive material to form a via hole for electrical connection;
A multilayer printed wiring board formed by laminating a plurality of layers using the unit layer formed by performing each step of (1) to ( 12 ) so as to ensure conduction of the via hole during lamination. Production method.   2. The convex portions of the upper pattern forming mold for the upper surface of the insulating layer 1 and the lower pattern forming mold for the lower surface are arranged at positions where the upper surface and the lower surface do not overlap each other. The manufacturing method of the multilayer printed wiring board as described in 2 ..   3. The method of manufacturing a multilayer printed wiring board according to claim 1, wherein the material of the insulating layer is made of at least an organic polymer material.   The multilayer printed wiring board manufactured with the manufacturing method of the multilayer printed wiring board described in any one of Claims 1-3.

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