JP5371164B2 - Bidirectional two-terminal thyristor - Google Patents

Bidirectional two-terminal thyristor Download PDF

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JP5371164B2
JP5371164B2 JP2001240165A JP2001240165A JP5371164B2 JP 5371164 B2 JP5371164 B2 JP 5371164B2 JP 2001240165 A JP2001240165 A JP 2001240165A JP 2001240165 A JP2001240165 A JP 2001240165A JP 5371164 B2 JP5371164 B2 JP 5371164B2
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昌明 冨田
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Shindengen Electric Manufacturing Co Ltd
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Abstract

PROBLEM TO BE SOLVED: To provide a surge protection element in which the surge withstand strength is improved. SOLUTION: A first n-type conductive region 2 and a second n-type conductive region 3 are formed on a p-type semiconductor substrate 1. First p-type conductive regions 4, 5, and 6 having hole-like conductive regions 12, 13, and 14, respectively, are formed in the first n-type conductive region 2 in point symmetry, and second p-type conductive regions 7, 8, and 9 having hole-like conductive regions 15, 16, and 17, respectively, are formed in the second n-type conductive region 3 in point symmetry. The first p-type conductive regions 4, 5, and 6 and the second p-type conductive regions 7, 8, and 9 overlap each other with their end parts in plan view. With this structure, the variation in base width of unit thyristors becomes less, so that the unit thyristor regions are easy to fire simultaneously for easy splitting the surge current, resulting in improved surge withstand strength.

Description

発明の属する分野Field of Invention

本発明は、サイリスタ、特に異常電圧または異常電流から電子回路系を保護するサージ防護素子等に用いる双方向型二端子サイリスタに関するものである。  The present invention relates to a thyristor, and more particularly to a bidirectional two-terminal thyristor used for a surge protection element for protecting an electronic circuit system from an abnormal voltage or current.

双方向型二端子サイリスタは、電話回線などの通信回線に発生した異常電圧や異常電流から電子回路を保護するサージ防護素子として、通信業界等で幅広く用いられている。  Bidirectional two-terminal thyristors are widely used in the communication industry and the like as surge protection elements that protect electronic circuits from abnormal voltages and currents generated in communication lines such as telephone lines.

図2は、従来技術に係る双方向型二端子サイリスタを示す断面図である。図2において、1は半導体基板、2は第1N型導電領域、3は第2N型導電領域、4は第1P型導電領域、7は第2P型導電領域、10は第1電極、11は第2電極、51はPNPN構造である。また、図4は、従来技術に係る双方向型二端子サイリスタの等価回路図である。  FIG. 2 is a cross-sectional view showing a bidirectional two-terminal thyristor according to the prior art. In FIG. 2, 1 is a semiconductor substrate, 2 is a first N-type conductive region, 3 is a second N-type conductive region, 4 is a first P-type conductive region, 7 is a second P-type conductive region, 10 is a first electrode, and 11 is a first electrode. Two electrodes 51 have a PNPN structure. FIG. 4 is an equivalent circuit diagram of a bidirectional two-terminal thyristor according to the prior art.

半導体基板1は、P型の導電型を有するものである。第1N型導電領域2と第2N型導電領域3は、半導体基板1内部に不純物拡散によって形成されたN型の導電型を有するものである。第1P型導電領域4と第2P型導電領域7は、半導体基板1内部に不純物拡散によって形成されたP型の導電型を有するものである。第1電極10と第2電極11は、半導体基板1の両主面に形成された電極である。ここで、電極10は、第1N型導電領域2と第1P型導電領域4の双方と電気的に接続される。また、第2電極11は、第2N型導電領域3と第2P型導電領域7の双方と電気的に接続されるが、電極10及び電極11からみた電気的特性が同一になるように、全体の構造を点対称とするのが一般的である。なお、図2に示した双方向型二端子サイリスタの等価回路図は、図4に示すものとなる。  The semiconductor substrate 1 has a P-type conductivity type. The first N-type conductive region 2 and the second N-type conductive region 3 have an N-type conductivity type formed by impurity diffusion inside the semiconductor substrate 1. The first P-type conductive region 4 and the second P-type conductive region 7 have a P-type conductivity type formed by impurity diffusion inside the semiconductor substrate 1. The first electrode 10 and the second electrode 11 are electrodes formed on both main surfaces of the semiconductor substrate 1. Here, the electrode 10 is electrically connected to both the first N-type conductive region 2 and the first P-type conductive region 4. In addition, the second electrode 11 is electrically connected to both the second N-type conductive region 3 and the second P-type conductive region 7, but the entire electrical characteristics viewed from the electrodes 10 and 11 are the same. In general, the structure is point-symmetric. An equivalent circuit diagram of the bidirectional two-terminal thyristor shown in FIG. 2 is as shown in FIG.

前記した双方向型二端子サイリスタにおいて、第1N型導電領域2が設けられた上面側を第2N型導電領域3が設けられた下面側に対して正の電位とする電圧の印加方向を順方向、上面側を下面側に対して負の電位とする電圧の印加方向を逆方向とする。図3は、従来技術に係る双方向型二端子サイリスタの順方向の電気的特性を示すグラフである。図3に示すように、順方向においては、第1P型導電領域4をエミッタ、第1N型導電領域2をベース、半導体基板1をコレクタとするPNPトランジスタと、第2N型導電領域3をエミッタ、半導体基板1をベース、第1N型導電領域2をコレクタとするNPNトランジスタの間で電子と正孔の交換が行なわれて、オフ状態からオン状態へ移行する点弧動作が行なわれる。  In the bidirectional two-terminal thyristor, the voltage application direction in which the upper surface side where the first N-type conductive region 2 is provided is positive with respect to the lower surface side where the second N-type conductive region 3 is provided is forward. The voltage application direction in which the upper surface side is a negative potential with respect to the lower surface side is the reverse direction. FIG. 3 is a graph showing electrical characteristics in the forward direction of a bidirectional two-terminal thyristor according to the prior art. As shown in FIG. 3, in the forward direction, a PNP transistor having the first P-type conductive region 4 as an emitter, the first N-type conductive region 2 as a base, and the semiconductor substrate 1 as a collector, and a second N-type conductive region 3 as an emitter, Electrons and holes are exchanged between NPN transistors having the semiconductor substrate 1 as a base and the first N-type conductive region 2 as a collector, and an ignition operation for shifting from an off state to an on state is performed.

すなわち、最初オフ状態にあった図2のPNPN構造51において、当該二端子電極領域に印加される電圧が、ブレークオ−バー電圧Vbに達すると雪崩降伏あるいはパンチスルーにより、逆バイアス状態にあるN型の導電領域2とP型半導体基板の境界及び当該境界近傍において、電子と正孔の交換が活発に行なわれるようになる。そして、前記のPNPトランジスタのベースと前記のNPNトランジスタのコレクタが共通の第1N型導電領域2であるため、当該PNPN構造からなるサイリスタが点弧してオン状態へ遷移する。なお、構造が上下で対称であることから逆方向においても全く同様な動作が行なわれる。  That is, in the PNPN structure 51 of FIG. 2 that was initially in the OFF state, when the voltage applied to the two-terminal electrode region reaches the breakover voltage Vb, the N-type is in a reverse bias state due to avalanche breakdown or punch-through. Electrons and holes are actively exchanged at the boundary between the conductive region 2 and the P-type semiconductor substrate and in the vicinity of the boundary. Since the base of the PNP transistor and the collector of the NPN transistor are the common first N-type conductive region 2, the thyristor having the PNPN structure is ignited and transitions to the on state. Since the structure is symmetrical vertically, the same operation is performed in the reverse direction.

なお、PNPN構造からなるサイリスタが点弧動作してオフ状態からオン状態へ移行することは周知の事実であるので、ここでは内部動作のより詳細な説明については省略する。  Since it is a well-known fact that the thyristor having the PNPN structure is ignited and shifts from the off state to the on state, a detailed description of the internal operation is omitted here.

以上のような点弧動作を行うサイリスタは、前記したように、ブレークオーバー電圧Vbでサージ電圧を抑圧するが、雷誘導サージのようにかなり速い電気的サージに対してもその応答が他のサージ防護素子、例えば避雷管や金属酸化物バリスタなどと比較して非常に速いために、高い信頼性を要求される通信ネットワーク系の電子機器のように雷誘導サージを拾いやすいところでは殆ど利用されている状況にある。  As described above, the thyristor that performs the ignition operation as described above suppresses the surge voltage by the breakover voltage Vb, but the response to other electrical surges such as a lightning induced surge is much faster than other surges. Because it is very fast compared to protective elements such as lightning arresters and metal oxide varistors, it is mostly used in places where lightning-induced surges are easily picked up, such as electronic devices in communication networks that require high reliability. Is in a situation.

また、半導体基板で出来ているため、サージ電流によって消耗するところがなく長期間に亘って信頼性を維持することが可能であるという保守上の大きな利点を有している。  In addition, since it is made of a semiconductor substrate, it has a great maintenance advantage that it can maintain reliability over a long period without being consumed by a surge current.

ところが、このような利点を有する双方向型二端子サイリスタにおいても、どのような電気的サージに対してもサージ電圧を抑圧出来るわけではなく、雷誘導サージのような非常に時間変化の大きいサージに対してはおのずと限界があり、そのサージに十分速く応答出来ず、素子内で電流の集中が生じて局所的に高温となり、素子が溶解して破壊する場合がある。  However, even in a bidirectional type two-terminal thyristor having such advantages, it is not possible to suppress the surge voltage for any electrical surge. However, there is a limit in nature, and it is impossible to respond to the surge fast enough, current concentration occurs in the element, and the temperature locally rises, and the element may melt and break down.

そこで、時間変化の大きいサージに対する対策の1つとして、本件の発明者らによるサイリスタがある。図5は、本件の発明者らによる双方向型二端子サイリスタの概略を示す断面図である。図5において、1は半導体基板、2は第1N型導電領域、3は第2N型導電領域、4,5,6は第1P型導電領域、7,8,9は第2P型導電領域、10は第1電極、11は第2電極、18,19,20,21は絶縁体、52はPNPN構造である。また、図6は、図5に示した双方向型二端子サイリスタにおける単位サイリスタ構造の等価回路図である。  Therefore, as one of countermeasures against a surge with a large time change, there is a thyristor by the inventors of the present invention. FIG. 5 is a cross-sectional view showing an outline of a bidirectional two-terminal thyristor by the present inventors. In FIG. 5, 1 is a semiconductor substrate, 2 is a first N-type conductive region, 3 is a second N-type conductive region, 4, 5 and 6 are first P-type conductive regions, and 7, 8 and 9 are second P-type conductive regions. Is a first electrode, 11 is a second electrode, 18, 19, 20, and 21 are insulators, and 52 is a PNPN structure. FIG. 6 is an equivalent circuit diagram of a unit thyristor structure in the bidirectional two-terminal thyristor shown in FIG.

図5に示されるように、上面側と下面側のP型導電領域は、それぞれ分割して形成されており、さらに平面的に見て上面側と下面側のエミッタを重ねている。この構成によって、図6の回路モデルで示される単位サイリスタを並列に形成し、各単位サイリスタにサージ電流の分流を図り、内部温度の上昇を抑制したものである。実験によると、4個の単位サイリスタで、サージ耐量が図2に示したような従来構造のサイリスタよりも30%以上向上することなどが確認されている。  As shown in FIG. 5, the P-type conductive regions on the upper surface side and the lower surface side are formed separately, and the upper surface side and lower surface side emitters are overlapped when viewed in plan. With this configuration, unit thyristors shown in the circuit model of FIG. 6 are formed in parallel, and a surge current is shunted to each unit thyristor to suppress an increase in internal temperature. According to experiments, it has been confirmed that with four unit thyristors, the surge resistance is improved by 30% or more compared to the thyristor having the conventional structure as shown in FIG.

しかしながら、前記の構造では、図2に示される従来構造のものより各単位サイリスタが点弧しやすい構造になっているとはいえ、各単位サイリスタの特性に製造上のばらつきが生じて、サージ電流が1つの単位サイリスタに集中して当該単位サイリスタが点弧するような場合、点弧後も電流が当該サイリスタに集中するため、残りの単位サイリスタには電流が分流されず、サージ耐量が必ずしも期待したほど十分には大きくならないことがあるという問題が残る。  However, in the above structure, although each unit thyristor is more easily ignited than that of the conventional structure shown in FIG. Is concentrated on one unit thyristor and the unit thyristor is ignited, the current is concentrated on the thyristor even after the ignition, so the current is not shunted to the remaining unit thyristors, and surge resistance is not necessarily expected. The problem remains that it may not be large enough.

発明が解決しようとする課題Problems to be solved by the invention

本発明は、図5に示される従来構造をさらに改良して、当該構造で複数形成されている単位サイリスタの全てを出来るだけ同時に点弧させて一部の単位サイリスタに電流が集中することを防止してサージ耐量を大きくすることを目的としている。  The present invention further improves the conventional structure shown in FIG. 5 and ignites all unit thyristors formed in the structure as simultaneously as possible to prevent current from concentrating on some unit thyristors. The purpose is to increase the surge resistance.

課題を解決するための手段Means for solving the problem

【課題を解決するための手段】
上記課題を解決するための手段として、本発明は、P型の半導体基板に、前記半導体基板の一方の面に露出させて形成してなる型の第1の導電領域と、前記一方の面に露出させて形成するとともに前記第1の導電領域内に配列してなるN個(N≧2)の前記第1の導電領域とは反対型の型の第2の導電領域と、前記一方の面に露出させて形成するとともにN個の前記第2の導電領域を各々貫通するように形成されるN個の前記第2の導電領域とは反対型の型の第1の孔状導電領域と、前記半導体基板の前記一方の面に背向する他方の面に露出させて形成してなる型の第3の導電領域と、前記他方の面に露出させて形成するとともに前記第3の導電領域内に配列してなるN個の前記第1の導電領域とは反対型の型の第4の導電領域と、前記他方の面に露出させて形成するとともにN個の前記第4の導電領域を各々貫通するように形成されるN個の前記第4の導電領域とは反対型の型の第2の孔状導電領域を有し、前記第2の導電領域及び前記第4の導電領域は、平面的に見て等間隔で交互に配列されるとともに同一形状で同一面積に形成されており、1番目の前記第2の導電領域は、平面的に見てその2番目の前記第2の導電領域に近い側の端部及びその近傍部分が1番目の前記第4の導電領域と重なり合うように配置され、N番目の前記第4の導電領域は、平面的に見てそのN−1番目の前記第4の導電領域に近い側の端部及びその近傍部分がN番目の前記第2の導電領域と重なり合うように配置され、1番目以外の前記第2の導電領域は、平面的に見てそれらの両端部及びそれらの近傍部分がN個の前記第4の導電領域と重なり合うように配置され、N番目以外の前記第4の導電領域は、平面的に見てそれらの両端部及びそれらの近傍部分がN個の前記第2の導電領域と重なり合うように配置されてなることを特徴とするとするものとした。
[Means for Solving the Problems]
As means for solving the above-mentioned problems, the present invention provides an N- type first conductive region formed on a P-type semiconductor substrate so as to be exposed on one surface of the semiconductor substrate, and the one surface. N type (N ≧ 2) P- type second conductive regions opposite to the first conductive regions formed by being exposed to the first conductive region and arranged in the first conductive region, N- type first hole-conducting conductors that are opposite to the N second conductive regions that are formed so as to be exposed on the surfaces of the N- type and penetrate through the N second conductive regions, respectively. An N- type third conductive region formed exposed on the other surface opposite to the one surface of the semiconductor substrate, the third conductive region exposed on the other surface, and the third A P- type fourth conductive region opposite to the N first conductive regions arranged in the conductive region; The N- type second electrode is formed so as to be exposed on the other surface and is opposite to the N fourth conductive regions formed so as to penetrate each of the N fourth conductive regions. The second conductive region and the fourth conductive region have a hole-shaped conductive region, and are alternately arranged at equal intervals in a plan view, and are formed in the same shape and the same area. The second conductive region is arranged so that the end portion on the side close to the second conductive region in the plan view and the vicinity thereof overlap the first fourth conductive region in plan view. The Nth fourth conductive region has an end portion on the side close to the (N-1) th fourth conductive region and a portion near the Nth fourth conductive region in plan view and the Nth second conductive region. The second conductive regions other than the first, which are arranged so as to overlap with each other, have both ends thereof in plan view. And the vicinity thereof are arranged so as to overlap the N fourth conductive regions, and the fourth conductive regions other than the Nth are arranged in such a manner that both ends thereof and the vicinity thereof are N The second conductive regions are arranged so as to overlap each other.

前記した構成においては、ブレークオーバー電圧を変更しないで、ベース接地電流増幅率αが低下することを補償するためには、第1の導電領域と半導体基板、および第3の導電領域と半導体基板との接合面に変更を加えず、第2の導電領域及び第4の導電領域からなるエミッタを深くしなければならない。そのために、エミッタの拡散時間が長くなるが、拡散深さが深くなればなるほど拡散しにくいため、エミッタの深さのばらつきが小さくなって、ベース幅のばらつきが小さくなるようにした。さらに、エミッタを深くしても一定程度の保持電流値(IH)が確保されるように、第2の導電領域及び第4の導電領域内にそれぞれ第1の孔状導電領域及び第2の孔状導電領域を形成した。従って、各単位サイリスタの特性のばらつきが小さくなり、すべての単位サイリスタが同時に点弧動作し易くなる。そのため、サージ電流を全ての単位サイリスタに分流させやくサージ耐量を向上させることが出来る。  In the configuration described above, in order to compensate for the decrease in the base ground current amplification factor α without changing the breakover voltage, the first conductive region and the semiconductor substrate, and the third conductive region and the semiconductor substrate The emitter of the second conductive region and the fourth conductive region must be deepened without changing the bonding surface. For this reason, the diffusion time of the emitter becomes longer, but the diffusion becomes harder as the diffusion depth becomes deeper. Therefore, the variation in the depth of the emitter is reduced and the variation in the base width is reduced. Furthermore, the first hole-shaped conductive region and the second hole are provided in the second conductive region and the fourth conductive region, respectively, so that a certain holding current value (IH) is secured even when the emitter is deepened. A conductive region was formed. Therefore, the variation in the characteristics of each unit thyristor is reduced, and all the unit thyristors are easily fired simultaneously. Therefore, the surge current can be easily shunted to all the unit thyristors and the surge resistance can be improved.

また、前記の構成において、前記第2の導電領域の孔と前記第4の導電領域の孔は、N個の前記第2の導電領域とN個の前記第4の導電領域が平面的に見てて重なりあうような領域に設けることも出来る。その場合、前記第1の孔状導電領域と第2の孔状導電領域を、平面的に見て重なりあわないように配置することも出来る。  Further, in the above structure, the holes of the second conductive region and the holes of the fourth conductive region are formed so that the N second conductive regions and the N fourth conductive regions are viewed in a plan view. It can also be provided in areas that overlap. In that case, the first hole-shaped conductive region and the second hole-shaped conductive region can be arranged so as not to overlap each other when seen in a plan view.

以下に、本発明の第1の実施の形態に係る双方向型二端子サイリスタを図面に基づいて詳細に説明する。図1は、本発明の第1の実施の形態に係る双方向型二端子サイリスタを示す断面図である。図1において、1は半導体基板、2は第1N型導電領域、3は第2N型導電領域、4,5,6は第1P型導電領域、7,8,9は第2P型導電領域、10は第1電極、11は第2電極、12,13,14,15,16,17は孔状導電領域、18,19,20,21は絶縁体、53はPNPN構造である。  Hereinafter, a bidirectional two-terminal thyristor according to a first embodiment of the present invention will be described in detail with reference to the drawings. FIG. 1 is a sectional view showing a bidirectional two-terminal thyristor according to a first embodiment of the present invention. In FIG. 1, 1 is a semiconductor substrate, 2 is a first N-type conductive region, 3 is a second N-type conductive region, 4, 5 and 6 are first P-type conductive regions, 7, 8 and 9 are second P-type conductive regions, 10 Is a first electrode, 11 is a second electrode, 12, 13, 14, 15, 16, and 17 are hole-shaped conductive regions, 18, 19, 20, and 21 are insulators, and 53 is a PNPN structure.

図1に示されるように、本発明の第1の実施の形態に係る双方向型二端子サイリスタは、双方向で電気的特性が対称となるように形成している。すなわち、P型の半導体基板1に第1N型導電領域2、第2N型導電領域3を形成する。また、第1N型導電領域2内に3つの第1P型導電領域4,5,6、第2N型導電領域3内に3つの第2P型導電領域7,8,9を相対向するP型導電領域と点対称になるように且つ等間隔に形成する。また、第1P型導電領域4を、平面的に見て第1P型導電領域5に近い側の端部及びその近傍部分が第2P型導電領域7に重なり合うように配置する。さらに、第2P型導電領域9を、平面的に見て第2P型導電領域8に近い側の端部及びその近傍部分が第1P型導電領域6に重なり合うように配置する。くわえて、第1P型導電領域5,6と第2P型導電領域7,8とを、平面的に見てそれらの両端部及びそれらの近傍部分が相対向するP型導電領域とそれぞれ重なり合うように配置する。また、第1P型導電領域4,5,6に孔状導電領域12、13、14を、同様に、第2P型導電領域7,8,9に孔状導電領域15、16、17を形成する。電極は上面側の第1の電極を前記第1P型導電領域及び前記第1N型導電領域に形成し、下面側の第2の電極を前記第2P型導電領域及び前記第2N型導電領域に接するように形成して構成する。  As shown in FIG. 1, the bidirectional two-terminal thyristor according to the first embodiment of the present invention is formed so that the electrical characteristics are symmetrical in both directions. That is, the first N-type conductive region 2 and the second N-type conductive region 3 are formed on the P-type semiconductor substrate 1. Further, three first P-type conductive regions 4, 5, 6 in the first N-type conductive region 2, and three second P-type conductive regions 7, 8, 9 in the second N-type conductive region 3 are opposed to each other. It is formed so as to be point-symmetric with the region and at equal intervals. Further, the first P-type conductive region 4 is arranged so that the end portion on the side close to the first P-type conductive region 5 and the vicinity thereof are overlapped with the second P-type conductive region 7 in plan view. Further, the second P-type conductive region 9 is arranged so that the end portion on the side close to the second P-type conductive region 8 and the vicinity thereof overlap the first P-type conductive region 6 when viewed in plan. In addition, the first P-type conductive regions 5 and 6 and the second P-type conductive regions 7 and 8 are viewed in plan view so that their both ends and their neighboring portions overlap with the opposing P-type conductive regions, respectively. Deploy. Further, the hole-shaped conductive areas 12, 13, and 14 are formed in the first P-type conductive areas 4, 5, and 6, and the hole-shaped conductive areas 15, 16, and 17 are formed in the second P-type conductive areas 7, 8, and 9 in the same manner. . The first electrode on the upper surface side is formed in the first P-type conductive region and the first N-type conductive region, and the second electrode on the lower surface side is in contact with the second P-type conductive region and the second N-type conductive region. It is formed and configured as follows.

なお、第1P型導電領域4,5,6、及び第2P型導電領域7,8,9は、上述した単位サイリスタの特性を均一にするために、全て同一形状で同一面積に形成することが好ましい。同様に、第1P型導電領域4,5,6の孔状導電領域12,13,14と第2P型導電領域7,8,9の孔状導電領域15,16,17は、全て同一形状で同一面積に形成することが好ましい。また、第1P型導電領域4,5,6と第2P型導電領域7,8,9との重ね幅は、例えば2.6mmチップの場合、マスク幅250μmに対して、25μm重なるようにすればよく、サージ耐量が30%以上向上することなどが確認されている。重なりが大きくなるとオン電流が流れる領域が狭くなるため、マスク幅の50%未満とする必要がある。したがって、これらの重ね幅はあまり大きく出来ないが、サージの種類に応じて適当な重ね幅に変更することが可能である。第1P型導電領域4,5,6の孔状導電領域12,13,14と第2P型導電領域7,8,9の孔状導電領域15,16,17は、第1P型導電領域4,5,6を形成するための写真マスクのパターンと第2P型導電領域7,8,9を形成するための写真マスクのパターンに孔状導電領域を描画して容易に形成出来るが、他の方法によって形成しても問題はない。  The first P-type conductive regions 4, 5, 6 and the second P-type conductive regions 7, 8, 9 are all formed in the same shape and the same area in order to make the characteristics of the unit thyristor uniform. preferable. Similarly, the hole-shaped conductive areas 12, 13, and 14 of the first P-type conductive areas 4, 5, and 6 and the hole-shaped conductive areas 15, 16, and 17 of the second P-type conductive areas 7, 8, and 9 have the same shape. It is preferable to form in the same area. The overlapping width of the first P-type conductive regions 4, 5, 6 and the second P-type conductive regions 7, 8, 9 may be 25 μm overlapping with the mask width of 250 μm in the case of a 2.6 mm chip, for example. It has been confirmed that the surge resistance is improved by 30% or more. When the overlap becomes large, the region where the on-current flows is narrowed, so it is necessary to make it less than 50% of the mask width. Therefore, these overlap widths cannot be made very large, but can be changed to an appropriate overlap width depending on the type of surge. The hole-shaped conductive areas 12, 13, and 14 of the first P-type conductive areas 4, 5, and 6 and the hole-shaped conductive areas 15, 16, and 17 of the second P-type conductive areas 7, 8, and 9 5 and 6 can be easily formed by drawing a hole-shaped conductive region on the pattern of the photographic mask for forming 5 and 6 and the pattern of the photographic mask for forming the second P-type conductive regions 7, 8, 9. There is no problem even if formed by.

図1に示される構造においては、サージ防護素子で重要となる保持電流が変わらないようにするために、単位となるサイリスタ構造のベース幅を図5に示した構造とは大きく異ならせる必要がある。すなわち、図1に示される構造においては、ベース深さを変えるとブレークオーバー電圧が変わるため、エミッタを深く拡散させてベース幅を小さくし、保持電流が変わらないようにする。不純物拡散は、深くなればなるほど、拡散が生じにくくなってばらつきが小さくなるため、図1に示される構造では、各単位サイリスタのベース幅のばらつきが小さくなって特性のばらつきを低減出来る。また、孔状導電領域を形成しているので、エミッタを深くしても一定程度の保持電流値(IH)が確保出来る。  In the structure shown in FIG. 1, it is necessary to make the base width of the thyristor structure as a unit greatly different from the structure shown in FIG. 5 in order to prevent the holding current that is important in the surge protection element from changing. . That is, in the structure shown in FIG. 1, since the breakover voltage changes when the base depth is changed, the emitter is diffused deeply to reduce the base width so that the holding current does not change. As the impurity diffusion becomes deeper, the diffusion is less likely to occur and the variation becomes smaller. Therefore, in the structure shown in FIG. 1, the variation in the base width of each unit thyristor is reduced and the variation in characteristics can be reduced. In addition, since the hole-shaped conductive region is formed, a certain holding current value (IH) can be secured even if the emitter is deepened.

従って、本発明の第1の実施の形態における構造では、各単位サイリスタの特性が揃いやすくなって、各単位サイリスタが同時に点弧し易くなって一部の単位サイリスタに電流が集中しにくくなる。これは、電流の分流を理想状態に近づけられることを意味し、素子破壊に繋がる発熱を抑制出来、サージ耐量を向上させることが出来るようになる。  Therefore, in the structure according to the first embodiment of the present invention, the characteristics of each unit thyristor are easily aligned, and each unit thyristor is easily fired at the same time, making it difficult for current to concentrate on some unit thyristors. This means that the current shunt can be brought close to the ideal state, heat generation leading to element destruction can be suppressed, and surge resistance can be improved.

図1に示した構造の等価回路モデルは、図7に示すものとなる。図7は、図1に示した双方向型二端子サイリスタの等価回路図である。本発明の第1の実施の形態に係る双方向型二端子サイリスタにおいては、PNPトランジスタのベース接地電流増幅率α±1 、α±1 、α±1 、が完全には一致せず、多少のばらつきが生じるが、ベース幅のばらつきが低減されているため、前記ベース接地電流増幅率α±1 、α±1 、α±1 のばらつきが従来構造と比較して小さく、一部の単位サイリスタに電流が集中しにくくなるため、サージ耐量を向上させることが出来る。An equivalent circuit model having the structure shown in FIG. 1 is shown in FIG. FIG. 7 is an equivalent circuit diagram of the bidirectional two-terminal thyristor shown in FIG. In the bidirectional two-terminal thyristor according to the first embodiment of the present invention, the base ground current amplification factors α ± 1 1 , α ± 1 2 , and α ± 1 3 of the PNP transistor do not completely match. However, since variations in the base width are reduced, variations in the base ground current amplification factors α ± 1 1 , α ± 1 2 , and α ± 1 3 are small compared to the conventional structure. Since it becomes difficult for current to concentrate on some unit thyristors, surge resistance can be improved.

また、図1に示した構造では、製造上のばらつきがあっても、第1P型導電領域4,5,6と第2P型導電領域7,8,9が平面的に見て必ず重なるように余裕をもってマスクパターンを設計することで、製造上のばらつきから、一部のサイリスタ領域において、第1P型導電領域4,5,6と第2P型導電領域7,8,9が平面的に見て必ず重なるようにしている。熱拡散によって第1P型導電領域4,5,6と第2P型導電領域7,8,9を形成する場合、深さ方向と垂直な横方向にも不純物拡散が生じるため、孔状導電領域の大きさには限界がある。  In the structure shown in FIG. 1, the first P-type conductive regions 4, 5, 6 and the second P-type conductive regions 7, 8, 9 are always overlapped in plan view even if there are manufacturing variations. By designing the mask pattern with a margin, the first P-type conductive regions 4, 5, 6 and the second P-type conductive regions 7, 8, 9 are viewed in plan in some thyristor regions due to manufacturing variations. Make sure they overlap. When the first P-type conductive regions 4, 5, 6 and the second P-type conductive regions 7, 8, 9 are formed by thermal diffusion, impurity diffusion also occurs in the lateral direction perpendicular to the depth direction. There is a limit to the size.

さらに、本発明の第2の実施の形態に係る双方向型二端子サイリスタを図面に基づいて詳細に説明する。図8は、本発明の第2の実施の形態に係る双方向型二端子サイリスタを示す断面図である。図8において、1は半導体基板、2は第1N型導電領域、3は第2N型導電領域、4,5,6は第1P型導電領域、7,8,9は第2P型導電領域、10は第1電極、11は第2電極、18,19,20,21は絶縁体、22,23,24、25,26,27,28,29,30,31は孔状導電領域、54はPNPN構造である。  Further, a bidirectional two-terminal thyristor according to a second embodiment of the present invention will be described in detail based on the drawings. FIG. 8 is a sectional view showing a bidirectional two-terminal thyristor according to the second embodiment of the present invention. In FIG. 8, 1 is a semiconductor substrate, 2 is a first N-type conductive region, 3 is a second N-type conductive region, 4, 5 and 6 are first P-type conductive regions, 7, 8, and 9 are second P-type conductive regions, 10 Is a first electrode, 11 is a second electrode, 18, 19, 20, and 21 are insulators, 22, 23, 24, 25, 26, 27, 28, 29, 30, and 31 are porous conductive regions, and 54 is a PNPN Structure.

本発明の第2の実施の形態に係る双方向型二端子サイリスタにおいては、前記した第1の実施の形態に係る双方向型二端子サイリスタの構成に加えて、孔状導電領域を第1P型導電領域4,5,6と第2P型導電領域7,8,9とを平面的に見て重なりあうところに設け、更に、孔状導電領域22,23,24,25,26と孔状導電領域27,28,29,30,31とが平面的に見て重なりあわないように配置する。  In the bidirectional two-terminal thyristor according to the second embodiment of the present invention, in addition to the configuration of the bidirectional two-terminal thyristor according to the first embodiment, the hole-shaped conductive region is a first P-type. The conductive regions 4, 5, 6 and the second P-type conductive regions 7, 8, 9 are provided so as to overlap in plan view, and the hole-shaped conductive regions 22, 23, 24, 25, 26 and the hole-shaped conductive regions are provided. The regions 27, 28, 29, 30, and 31 are arranged so as not to overlap each other when seen in a plan view.

前記の双方向型二端子サイリスタでは、第1N型導電領域2と第2N型導電領域3を流れるサージ電流が単位サイリスタのベース電位を下げる経路を通ることとなり、単位サイリスタが点弧しやすくなるため、サージ耐量を大きくすることが出来る。また、この双方向型二端子サイリスタで示したように、孔状導電領域の個数をエミッタであるP型導電領域よりも多くすることも可能である。  In the bidirectional two-terminal thyristor, the surge current flowing through the first N-type conductive region 2 and the second N-type conductive region 3 passes through a path for lowering the base potential of the unit thyristor, and the unit thyristor is likely to be ignited. , Surge resistance can be increased. Further, as shown in the bidirectional two-terminal thyristor, the number of hole-shaped conductive regions can be made larger than that of the P-type conductive region that is an emitter.

さらに、本発明の第3の実施の形態に係る双方向型二端子サイリスタを図面に基づいて詳細に説明する。図9は、本発明の第3の実施の形態に係る双方向型二端子サイリスタを示す断面図である。図9において、1は半導体基板、2は第1N型導電領域、3は第2N型導電領域、4,5,6は第1P型導電領域、7,8,9は第2P型導電領域、10は第1電極、11は第2電極、18,19,20,21は絶縁体、22,23,24、25,26,27,28,29,30,31は孔状導電領域、32,33,34は第1抵抗体、35,36,37は第2抵抗体、55はPNPN構造である。  Further, a bidirectional two-terminal thyristor according to a third embodiment of the present invention will be described in detail based on the drawings. FIG. 9 is a sectional view showing a bidirectional two-terminal thyristor according to a third embodiment of the present invention. In FIG. 9, 1 is a semiconductor substrate, 2 is a first N-type conductive region, 3 is a second N-type conductive region, 4, 5 and 6 are first P-type conductive regions, 7, 8 and 9 are second P-type conductive regions, 10 Is a first electrode, 11 is a second electrode, 18, 19, 20, and 21 are insulators, 22, 23, 24, 25, 26, 27, 28, 29, 30, and 31 are hole conductive regions, and 32 and 33 , 34 are first resistors, 35, 36, 37 are second resistors, and 55 is a PNPN structure.

本発明の第3の実施の形態に係る双方向型二端子サイリスタにおいては、前記した第1の実施の形態に係る双方向型二端子サイリスタの構成に加えて、半導体基板1と第1電極10との間、及び半導体基板1と第2電極11との間の接触抵抗である第1抵抗体32,33,34及び第2抵抗体35,36,37を形成する。  In the bidirectional two-terminal thyristor according to the third embodiment of the present invention, in addition to the configuration of the bidirectional two-terminal thyristor according to the first embodiment, the semiconductor substrate 1 and the first electrode 10 are provided. And the first resistors 32, 33, and 34 and the second resistors 35, 36, and 37, which are contact resistances between the semiconductor substrate 1 and the second electrode 11, are formed.

前記の双方向型二端子サイリスタでは、半導体基板1と第1電極10との間、及び半導体基板1と第2電極11との間に追加された第1抵抗体32,33,34及び第2抵抗体35,36,37は、各々エミッタに直列に挿入されている。従って、本発明の第1の実施の形態における構造では、一部の単位サイリスタに電流が集中しても当該単位サイリスタのベース電位が上昇して他の単位サイリスタが点弧し易くなって一部の単位サイリスタに電流が集中しにくくなる。これは、電流の分流を理想状態に近づけられることを意味し、素子破壊に繋がる発熱を抑制出来、サージ耐量を向上させることが出来るようになる。  In the bidirectional two-terminal thyristor, the first resistors 32, 33, 34 and the second added between the semiconductor substrate 1 and the first electrode 10 and between the semiconductor substrate 1 and the second electrode 11 are used. Resistors 35, 36, and 37 are each inserted in series with the emitter. Therefore, in the structure according to the first embodiment of the present invention, even when current is concentrated on some unit thyristors, the base potential of the unit thyristor rises and other unit thyristors are easily ignited. It is difficult for current to concentrate on the unit thyristor. This means that the current shunt can be brought close to the ideal state, heat generation leading to element destruction can be suppressed, and surge resistance can be improved.

くわえて、本発明の第4の実施の形態に係る双方向型二端子サイリスタを図面に基づいて詳細に説明する。図10は、本発明の第4の実施の形態に係る双方向型二端子サイリスタを示す断面図である。図10において、1は半導体基板、2は第1N型導電領域、3は第2N型導電領域、4,5,6は第1P型導電領域、7,8,9は第2P型導電領域、10は第1電極、11は第2電極、18,19,20,21は絶縁体、22,23,24、25,26,27,28,29,30,31は孔状導電領域、32,33,34は第1抵抗体、35,36,37は第2抵抗体、38,39,40は第3N型導電領域、41,42,43は第4N型導電領域、56はPNPN構造である。  In addition, a bidirectional two-terminal thyristor according to a fourth embodiment of the present invention will be described in detail with reference to the drawings. FIG. 10 is a sectional view showing a bidirectional two-terminal thyristor according to the fourth embodiment of the present invention. In FIG. 10, 1 is a semiconductor substrate, 2 is a first N-type conductive region, 3 is a second N-type conductive region, 4, 5 and 6 are first P-type conductive regions, and 7, 8 and 9 are second P-type conductive regions. Is a first electrode, 11 is a second electrode, 18, 19, 20, and 21 are insulators, 22, 23, 24, 25, 26, 27, 28, 29, 30, and 31 are hole conductive regions, and 32 and 33 , 34 are first resistors, 35, 36, 37 are second resistors, 38, 39, 40 are third N-type conductive regions, 41, 42, 43 are fourth N-type conductive regions, and 56 is a PNPN structure.

前記の双方向型二端子サイリスタでは、半導体基板1と第1電極10との間、及び半導体基板1と第2電極11との間の接触抵抗がそれぞれ第3N型導電領域38,39,40及び第4N型導電領域41,42,43が存在することによって低減する。したがって、点弧動作に必要な電流が流れやすくなるとともに、一部の単位サイリスタに電流が集中することを防止しながら点弧後のオン電圧を小さく出来る。ひいては、電気的損失すなわち破壊に繋がる熱の発生を低減出来、サージ耐量をより向上させることが出来る。  In the bidirectional two-terminal thyristor, the contact resistances between the semiconductor substrate 1 and the first electrode 10 and between the semiconductor substrate 1 and the second electrode 11 are the third N-type conductive regions 38, 39, and 40, respectively. The presence of the fourth N-type conductive regions 41, 42, 43 is reduced. Therefore, the current required for the ignition operation can easily flow, and the on-voltage after ignition can be reduced while preventing the current from concentrating on some unit thyristors. As a result, electrical loss, that is, generation of heat leading to destruction can be reduced, and surge resistance can be further improved.

発明の効果Effect of the invention

このように本発明によれば、第2の導電領域及び第4の導電領域からなるエミッタを深く形成し、第2の導電領域及び第4の導電領域内にそれぞれ第1の孔状導電領域及び第2の孔状導電領域を形成することにより、複数形成されている各単位サイリスタの特性のばらつきを小さくして、一部の単位サイリスタへの電流集中を防止し易いようにしたので、各単位サイリスタの並列動作の安定化を図り易い。また、サージが入力したときに、発熱を抑制しやすく、従来技術に係るサイリスタよりもサージ耐量を向上させることが出来る。また、製造上のばらつきが構造に反映されにくい構造になっているため、従来技術に係るサイリスタよりも同時点弧が容易になる。Thus, according to the present invention, the emitter composed of the second conductive region and the fourth conductive region is formed deeply, and the first hole-shaped conductive region and the fourth conductive region are respectively formed in the second conductive region and the fourth conductive region. By forming the second hole-shaped conductive region, the variation in the characteristics of the plurality of unit thyristors is reduced, and it is easy to prevent current concentration in some unit thyristors. It is easy to stabilize the parallel operation of thyristors. Moreover, when a surge is input, it is easy to suppress heat generation, and the surge resistance can be improved as compared with the thyristor according to the prior art. In addition, since the manufacturing variation is less likely to be reflected in the structure, simultaneous firing is easier than in the thyristor according to the related art.

本発明の第1の実施の形態に係る双方向型二端子サイリスタを示す断面図である。  1 is a cross-sectional view showing a bidirectional two-terminal thyristor according to a first embodiment of the present invention. 従来技術に係る双方向型二端子サイリスタを示す断面図である。  It is sectional drawing which shows the bidirectional | two-way type two-terminal thyristor based on a prior art. 従来技術に係る双方向型二端子サイリスタの順方向の電気的特性を示すグラフである。  It is a graph which shows the electrical property of the forward direction of the bidirectional | two-way type | mold two terminal thyristor which concerns on a prior art. 従来技術に係る双方向型二端子サイリスタの等価回路図である。  It is an equivalent circuit diagram of a bidirectional two-terminal thyristor according to the prior art. 本件の発明者らによる双方向型二端子サイリスタの概略を示す断面図である。  It is sectional drawing which shows the outline of the bidirectional | two-way type two-terminal thyristor by the inventors of this case. 図5に示した双方向型二端子サイリスタにおける単位サイリスタ構造の等価回路図である。  FIG. 6 is an equivalent circuit diagram of a unit thyristor structure in the bidirectional two-terminal thyristor shown in FIG. 5. 図1に示した双方向型二端子サイリスタの等価回路図である。  FIG. 2 is an equivalent circuit diagram of the bidirectional two-terminal thyristor shown in FIG. 1. 本発明の第2の実施の形態に係る双方向型二端子サイリスタを示す断面図である。  It is sectional drawing which shows the bidirectional | two-way type two-terminal thyristor which concerns on the 2nd Embodiment of this invention. 本発明の第3の実施の形態に係る双方向型二端子サイリスタを示す断面図である。  It is sectional drawing which shows the bidirectional | two-way type two terminal thyristor which concerns on the 3rd Embodiment of this invention. 本発明の第4の実施の形態に係る双方向型二端子サイリスタを示す断面図である。  It is sectional drawing which shows the bidirectional | two-way type 2 terminal thyristor which concerns on the 4th Embodiment of this invention.

符号の簡単な説明Brief description of symbols

1 半導体基板
2 第1N型導電領域
3 第2N型導電領域
4 第1P型導電領域
5 第1P型導電領域
6 第1P型導電領域
7 第2P型導電領域
8 第2P型導電領域
9 第2P型導電領域
10 第1電極
11 第2電極
12 孔状導電領域
13 孔状導電領域
14 孔状導電領域
15 孔状導電領域
16 孔状導電領域
17 孔状導電領域
18 絶縁体
19 絶縁体
20 絶縁体
21 絶縁体
22 孔状導電領域
23 孔状導電領域
24 孔状導電領域
25 孔状導電領域
26 孔状導電領域
27 孔状導電領域
28 孔状導電領域
29 孔状導電領域
30 孔状導電領域
31 孔状導電領域
32 第1抵抗体
33 第1抵抗体
34 第1抵抗体
35 第2抵抗体
36 第2抵抗体
37 第2抵抗体
38 第3N型導電領域
39 第3N型導電領域
40 第3N型導電領域
41 第4N型導電領域
42 第4N型導電領域
43 第4N型導電領域
51 PNPN構造
52 PNPN構造
53 PNPN構造
54 PNPN構造
55 PNPN構造
56 PNPN構造
DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 1st N-type conductive area 3 2nd N-type conductive area 4 1st P-type conductive area 5 1st P-type conductive area 6 1st P-type conductive area 7 2nd P-type conductive area 8 2nd P-type conductive area 9 2nd P-type conductive Region 10 First electrode 11 Second electrode 12 Hole conductive region 13 Hole conductive region 14 Hole conductive region 15 Hole conductive region 16 Hole conductive region 17 Hole conductive region 18 Insulator 19 Insulator 20 Insulator 21 Insulation Body 22 Hole-shaped conductive area 23 Hole-shaped conductive area 24 Hole-shaped conductive area 25 Hole-shaped conductive area 26 Hole-shaped conductive area 27 Hole-shaped conductive area 28 Hole-shaped conductive area 29 Hole-shaped conductive area 30 Hole-shaped conductive area 31 Hole-shaped conductive area Region 32 First resistor 33 First resistor 34 First resistor 35 Second resistor 36 Second resistor 37 Second resistor 38 Third N-type conductive region 39 Third N-type conductive region 40 Third N-type conductor Electrical region 41 4th N-type conductive region 42 4th N-type conductive region 43 4th N-type conductive region 51 PNPN structure 52 PNPN structure 53 PNPN structure 54 PNPN structure 55 PNPN structure 56 PNPN structure

Claims (3)

P型の半導体基板に、
前記半導体基板の一方の面に露出させて形成してなる型の第1の導電領域と、
前記一方の面に露出させて形成するとともに前記第1の導電領域内に配列してなるN個(N≧2)の前記第1の導電領域とは反対型の型の第2の導電領域と、
前記一方の面に露出させて形成するとともにN個の前記第2の導電領域を各々貫通するように形成されるN個の前記第2の導電領域とは反対型の型の第1の孔状導電領域と、
前記半導体基板の前記一方の面に背向する他方の面に露出させて形成してな型の第3の導電領域と、
前記他方の面に露出させて形成するとともに前記第3の導電領域内に配列してなるN個の前記第1の導電領域とは反対型の型の第4の導電領域と、
前記他方の面に露出させて形成するとともにN個の前記第4の導電領域を各々貫通するように形成されるN個の前記第4の導電領域とは反対型の型の第2の孔状導電領域を有し、
前記第2の導電領域及び前記第4の導電領域は、平面的に見て等間隔で交互に配列されるとともに同一形状で同一面積に形成されており、
1番目の前記第2の導電領域は、平面的に見てその2番目の前記第2の導電領域に近い側の端部及びその近傍部分が1番目の前記第4の導電領域と該第4の導電領域における所定の重ね幅で重なり合うように配置され、
N番目の前記第4の導電領域は、平面的に見てそのN−1番目の前記第4の導電領域に近い側の端部及びその近傍部分がN番目の前記第2の導電領域と該第2の導電領域における所定の重ね幅で重なり合うように配置され、
1番目以外の前記第2の導電領域は、平面的に見てそれらの両端部及びそれらの近傍部分がN個の前記第4の導電領域と該第4の導電領域における所定の重ね幅で重なり合うように配置され、
N番目以外の前記第4の導電領域は、平面的に見てそれらの両端部及びそれらの近傍部分がN個の前記第2の導電領域と該第2の導電領域における所定の重ね幅で重なり合うように配置されてなることを特徴とする双方向型二端子サイリスタ。
On a P-type semiconductor substrate,
An N- type first conductive region formed by being exposed on one surface of the semiconductor substrate ;
N type (N ≧ 2) P- type second conductive regions opposite to N- type first conductive regions formed by being exposed on the one surface and arranged in the first conductive region When,
An N- type first hole which is formed to be exposed on the one surface and which is formed so as to penetrate each of the N second conductive regions, and which is opposite to the N second conductive regions. A conductive region;
An N- type third conductive region formed to be exposed on the other surface facing away from the one surface of the semiconductor substrate ;
A P- type fourth conductive region of the opposite type to the N first conductive regions formed to be exposed on the other surface and arranged in the third conductive region;
An N- type second hole which is formed to be exposed on the other surface and which is formed so as to penetrate each of the N fourth conductive regions. A conductive region,
The second conductive region and the fourth conductive region are alternately arranged at equal intervals in a plan view and are formed in the same shape and the same area.
The first second conductive region has the end portion on the side close to the second second conductive region in a plan view and the vicinity thereof in the fourth conductive region and the fourth conductive region. Arranged to overlap with a predetermined overlap width in the conductive region of
The Nth fourth conductive region has an end portion on the side close to the (N−1) th fourth conductive region and a portion near the Nth fourth conductive region in plan view and the second conductive region. Arranged to overlap with a predetermined overlap width in the second conductive region,
The second conductive regions other than the first have their both end portions and their neighboring portions in plan view overlapping with the N number of the fourth conductive regions and a predetermined overlap width in the fourth conductive regions. Arranged as
In the fourth conductive regions other than the Nth, both end portions and their neighboring portions in a plan view overlap with N second conductive regions with a predetermined overlap width in the second conductive regions. A bidirectional two-terminal thyristor characterized by being arranged as described above.
前記第1の孔状導電領域及び前記第2の孔状導電領域は、N個の前記第2の導電領域とN個の前記第4の導電領域との平面的に見て重なりあう領域内に設けられていることを特徴とする請求項1に記載の双方向型二端子サイリスタ。
The first hole-shaped conductive region and the second hole-shaped conductive region are in a region where the N number of the second conductive regions and the N number of the fourth conductive regions overlap each other in plan view. The bidirectional two-terminal thyristor according to claim 1, wherein the bidirectional two-terminal thyristor is provided.
前記第1の孔状導電領域及び前記第2の孔状導電領域は、平面的に見て重なりあわないように配置されていることを特徴とする請求項2に記載の双方向型二端子サイリスタ。   3. The bidirectional two-terminal thyristor according to claim 2, wherein the first hole-shaped conductive region and the second hole-shaped conductive region are arranged so as not to overlap each other in plan view. .
JP2001240165A 2001-08-08 2001-08-08 Bidirectional two-terminal thyristor Expired - Fee Related JP5371164B2 (en)

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