JP5364781B2 - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce variation in current to be supplied to a plurality of organic EL elements. <P>SOLUTION: An element drive TFT 20 for controlling the amount of current to be supplied from a power supply line VL is provided between an organic EL element 50 and a power supply line VL. A channel length direction of the TFT 20 is arranged in a direction parallel to a lengthwise direction of a pixel, an extending direction of a data line DL for supplying a data signal to a switching TFT 10 for controlling the TFT 20, or a scanning direction of laser annealing for polycrystallization of an active layer 16 of the TFT 20. Furthermore, a compensating TFT 30 having reverse characteristics of the TFT 20 may be provided between the power supply line VL and the TFT 20. <P>COPYRIGHT: (C)2012,JPO&amp;INPIT

Description

  The present invention relates to an electroluminescence display device, and more particularly to a circuit configuration transistor of a pixel portion thereof.

  An EL display device using an electroluminescence (hereinafter referred to as EL) element, which is a self-luminous element, as a light-emitting element for each pixel is advantageous in that it is self-luminous and thin and consumes less power. Attention has been focused on as a display device that replaces a display device such as a device (LCD) or CRT, and research has been underway.

  In particular, an active matrix EL display device in which a switching element such as a thin film transistor (TFT) for individually controlling an EL element is provided in each pixel and the EL element is controlled for each pixel is expected as a high-definition display device. ing.

  FIG. 1 shows a circuit configuration per pixel in an active matrix EL display device of m rows and n columns. In the EL display device, a plurality of gate lines GL extend in the row direction on the substrate, and a plurality of data lines DL and power supply lines VL extend in the column direction. Each pixel includes an organic EL element 50, a switching TFT (first TFT) 10, an EL element driving TFT (second TFT) 20, and an auxiliary capacitor Cs.

  The first TFT 10 is connected to the gate line GL and the data line DL, and is turned on when the gate electrode receives a gate signal (selection signal). At this time, the data signal supplied to the data line DL is held in the auxiliary capacitor Cs connected between the first TFT 10 and the second TFT 20. A voltage corresponding to the data signal supplied via the first TFT 10 is supplied to the gate electrode of the second TFT 20, and the second TFT 20 supplies a current corresponding to the voltage value from the power supply line VL to the organic EL element 50. To do. By such an operation, the organic EL element emits light at a luminance corresponding to the data signal for each pixel, and a desired image is displayed.

  Here, the organic EL element is a current-driven element that emits light by supplying current to an organic light emitting layer provided between a cathode and an anode. On the other hand, the data signal output to the data line DL is a voltage signal having an amplitude corresponding to the display data. Therefore, conventionally, in an organic EL display device, each pixel is provided with a first TFT 10 and a second TFT 20 for the purpose of accurately emitting light from the organic EL element by such a data signal.

  In the above-described organic EL display device, the display quality and reliability are not yet sufficient, and it is necessary to eliminate the characteristic variations of the first and second TFTs 10 and 20. In particular, variation in the characteristics of the second TFT that controls the amount of current supplied from the power supply line VL to the organic EL element 50 directly causes variation in light emission luminance, and therefore, it is required to reduce the variation.

  Further, it is preferable that the first and second TFTs 10 and 20 are constituted by polycrystalline silicon TFTs having a high operating speed and capable of being driven at a low voltage. In order to obtain polycrystalline silicon, amorphous silicon is polycrystallized by laser annealing. However, the grain size of polycrystalline silicon is unsatisfactory due to variations in energy within the irradiation surface of the irradiation laser. It becomes uniform. If this grain size variation, particularly in the vicinity of the TFT channel, occurs, there is a problem that the on-current characteristics of the TFT vary.

  The present invention has been made in view of the above-described problems, and an active matrix organic EL panel capable of causing each light emitting pixel to emit light with uniform brightness by alleviating variation in characteristics of TFTs that control organic EL elements. The purpose is to provide.

  Another object of the present invention is to improve the reliability and characteristics of an apparatus provided with an organic EL element or the like as a driven element.

  In order to achieve the above object, the present invention provides an electroluminescence element comprising a light emitting layer between a first electrode and a second electrode, and a switching thin film transistor that operates by receiving a gate signal at the gate and takes in a data signal. And an element driving thin film transistor that is provided between the driving power supply and the electroluminescence element, and controls power supplied from the driving power supply to the electroluminescence element in accordance with a data signal supplied from the switching thin film transistor; Furthermore, a compensation thin film transistor having a reverse conductivity characteristic to that of the element driving thin film transistor is provided between the driving power supply and the element driving thin film transistor.

  With such a thin film transistor for compensating reverse conductivity, it is possible to absorb variations in characteristic shifts with the element driving thin film transistor, so that variations in individual transistors as a whole can be alleviated. Variations in emission luminance can be prevented.

  Another aspect of the present invention is that the compensation thin film transistor is diode-connected between the drive power supply and the element drive thin film transistor.

  This makes it possible to compensate for variations in the characteristics of the element driving thin film transistor without having to supply a special control signal to the compensating thin film transistor.

  Another aspect of the present invention is that in the above display device, the element driving thin film transistor includes a plurality of thin film transistors connected in parallel to each other.

  According to still another aspect of the present invention, the element driving thin film transistor includes a plurality of thin film transistors connected in parallel between the driving power source and the electroluminescent element, and the compensation thin film transistor includes the parallel connection. Each of the thin film transistors is provided between the thin film transistor and the driving power source.

  By providing a plurality of element driving thin film transistors in parallel in this manner, even if characteristic variations occur in individual transistors, the influence on the overall characteristics of the transistors connected in parallel can be reduced. For this reason, current can be supplied to the EL element with little variation. Furthermore, if a plurality of compensation thin film transistors are provided, the influence of variations in the characteristics of individual transistors on the characteristics of the entire pixel transistor can be reduced, and light emission with uniform luminance of the EL element is facilitated.

  In another aspect of the present invention, in the semiconductor device, each pixel arranged in a matrix includes the switching thin film transistor, the element driving thin film transistor, the compensation thin film transistor, and the driven element as a display element. Can be used for an active matrix display device.

  In another aspect of the present invention, in the semiconductor device, the channel length directions of the element driving thin film transistor and the compensation thin film transistor are arranged along a direction in which a data line for supplying the data signal to the switching thin film transistor extends. Has been.

  Another aspect of the present invention is an active matrix in which each of a plurality of pixels arranged in a matrix includes at least a driven element and an element driving thin film transistor that supplies power from a driving power source to the driven element. Each pixel region of the plurality of pixels has one of the rows in the row and column directions of the matrix longer than the other, and the thin film transistor for driving an element has a channel length direction in the pixel region. It is arranged along the longer side.

  In the display device according to another aspect of the present invention, the pixel region has a longer side in the column direction than the row direction of the matrix, and the channel length direction of the element driving thin film transistor is arranged along the column direction. Has been.

  In a semiconductor device according to another aspect of the present invention, at least one element driving thin film transistor that supplies a driving current from a power supply line to a corresponding driven element, and the element driving thin film transistor based on data supplied at the time of selection And a channel length direction of the element driving thin film transistor is arranged along an extending direction of a data line for supplying the data signal to the switching thin film transistor.

  By adopting the above arrangement, the channel length of the element driving thin film transistor that supplies power to the driven element can be increased, and the reliability of the transistor such as a withstand voltage can be improved. In addition, the characteristics of the element driving thin film transistors provided for the driven elements can be averaged, and even when the driven element is a light emitting element whose emission luminance differs depending on the supplied power, the variation in the emission luminance of each element Can be suppressed. Further, for example, it is easy to efficiently arrange a plurality of element driving thin film transistors each having a sufficient channel length for one driven element in a pixel by connecting them in parallel or in series. In the case where is a light emitting element or the like, the light emitting region can be increased.

  In the semiconductor device or the display device according to another aspect of the present invention, the element driving is performed so that a channel length direction of the element driving thin film transistor is along a scanning direction of a linear pulse laser for annealing the channel region of the transistor. Thin film transistors are formed.

  Thus, by aligning the scanning direction of laser annealing with the channel length direction of the element driving thin film transistor, the difference from the transistor characteristics of the element driving thin film transistor that supplies power to other driven elements can be reliably reduced. .

  In laser annealing, there is a variation in laser output energy. This variation includes a variation within one irradiation region of the pulse laser and a variation between shots. On the other hand, for example, an element driving thin film transistor employed in a semiconductor device such as an active matrix display device is often designed such that the channel length is very long relative to the channel width. Further, as described above, the channel length of the element driving thin film transistor is reduced by arranging the element driving thin film transistor along the longer side of the pixel region or by forming the element driving thin film transistor along the column direction or the data line extending direction. It becomes easy to make it sufficient length. Then, by setting the laser scanning direction to substantially match the channel length direction of the element driving thin film transistor, in other words, by setting the longitudinal direction of the laser irradiation region to cross the channel in the width direction, one element driving The entire channel region of the thin film transistor can be easily adjusted so that it is not annealed by a single shot. This can be easily realized, for example, by setting the channel length of the element driving thin film transistor to be longer than one movement pitch of the pulse laser. Therefore, when a plurality of driven elements are formed on the same substrate and a plurality of element driving thin film transistors for supplying power to the elements are formed, the active layer of the thin film transistor is laser annealed by a plurality of shots. Thus, each transistor is evenly subjected to energy variation between shots, and the characteristics of each thin film transistor can be reliably averaged. Accordingly, for example, in an organic EL display device using an organic EL element in which an organic compound is used in a light emitting layer as a driven element, variation in light emission luminance in the organic EL element provided in each pixel is extremely reduced. Can do.

  In another aspect of the present invention, in the semiconductor device, a channel length direction of the element driving thin film transistor does not coincide with a channel length direction of the switching thin film transistor.

  The switching thin film transistor is disposed in the vicinity of a selection line for selecting the transistor and a data line for supplying a data signal. In many cases, the extending direction of the selection line and the channel length direction of the switching thin film transistor are approximately They are arranged in parallel. In such a case, by disposing the channel length direction of the element driving thin film transistor in a direction different from that of the switching thin film transistor, it is easy to increase the channel length of the element driving thin film transistor.

  In a semiconductor device according to another aspect of the present invention, power supplied to the driven element is between a driven element that operates according to the supplied power and a power supply line for supplying power to the driven element. N (n is an integer of 2 or more) thin film transistors, and the driven elements corresponding to the plurality of n thin film transistors are electrically connected by n-1 or less contacts. It is connected.

  Providing a plurality of element driving thin film transistors that supply power to the driven elements is highly effective in terms of reliability of power supply to the driven elements and prevention of variations. On the other hand, for example, when the driven element is a light emitting element, the contact portion often becomes a non-light emitting region. Therefore, by setting the number of contacts between the n thin film transistors that supply power to the driven element and the driven element to n−1 or less, the actual operation region (light emission) of the driven element is improved while improving the reliability of the device. In the case of an element, it is possible to secure a maximum light emitting region).

  A semiconductor device according to another aspect of the present invention provides power supplied to the driven element between a driven element that operates according to supplied power and a power supply line for supplying power to the driven element. The driven element corresponding to the thin film transistor is electrically connected to each other by a wiring layer, the contact position between the wiring layer and the thin film transistor, the wiring layer, and the driven The contact position with the element is spaced apart.

  As described above, the contact position between the wiring layer and the thin film transistor and the contact position between the wiring layer and the driven element are spaced apart from each other, so that the contact layer that is often formed above the wiring layer is formed. It becomes easy to form the drive element on a flatter surface. The thin film transistor and the wiring layer are separated by an insulating layer, and these contacts are made in contact holes formed in the insulating layer. The wiring layer and the driven element are connected through a contact hole formed in an insulating layer that insulates the wiring layer and the driven element. Therefore, when the contact hole connecting the thin film transistor and the wiring layer and the contact hole connecting the wiring layer and the driven element overlap each other, two driven elements are formed in the uppermost layer (2 It is formed on a large concavo-convex surface formed by the contact hole of the step). When a light-emitting element, for example, an organic EL element in which an organic compound is used for a light-emitting layer is employed as a driven element, an electric field concentration occurs when the layer containing the organic compound has poor flatness of the formation surface. Dark spots that can not emit light from the place are likely to occur. Therefore, by separating the contact between the wiring layer and the driven element from the contact portion between the thin film transistor and the wiring layer, it is possible to improve the flatness in the region where the driven element is formed.

  In the semiconductor device according to another aspect of the present invention, the driven element is a light-emitting element including a light-emitting element layer between the first and second electrodes, and an insulating layer formed on the wiring layer. Has a contact hole, and in the contact hole, the wiring layer is connected to the first electrode of the light emitting element formed on the insulating layer so as to cover the contact hole, and the first electrode At least a contact hole region is covered with a planarization layer, and the light emitting element layer is formed on the first electrode and the planarization layer.

  By covering the contact hole region of the first electrode with the planarizing layer, that is, filling the recessed portion due to the presence of the contact hole with the planarizing layer, a surface with very high flatness can be formed between the first electrode and the planarizing layer. Can be configured. Therefore, it is possible to improve the reliability of the element by forming the light emitting element layer on the highly flat surface.

  A semiconductor device according to another aspect of the present invention operates according to supplied power, and includes a driven element including a light emitting element layer between first and second electrodes, and power for supplying the driven element to the driven element. A thin film transistor for controlling power supplied to the driven element is provided between the power supply line, and the driven element corresponding to the thin film transistor is defined as the thin film transistor formed in the lower layer and the driven element. In contact holes formed in the insulating layer separating the layers, they are electrically connected to each other directly or indirectly, and at least the contact hole region of the first electrode is covered with a planarizing layer, and the first electrode and the planarizing layer The light emitting element layer is formed on the upper layer.

  A light emitting element layer is formed above the first electrode. Since the depression caused by the presence of the contact hole in the first electrode is covered with a planarization layer, even if the depression is deep, One electrode and the planarization layer can form a surface with very high flatness, and the reliability of the device can be improved by forming a light emitting element layer on the surface with high flatness.

  Another aspect of the present invention is that the driven element described above is an organic electroluminescence element using an organic compound in a light emitting layer. In such an organic EL element, the selection range of the high luminance, the emission color, and the material is wide, but since the current is driven, the variation in the amount of supplied current affects the variation in the emission luminance. By adopting the configuration and arrangement, it is easy to keep the supply current amount uniform. Further, by employing the contact arrangement and structure as described above, the aperture ratio is large, and an element layer such as a light-emitting layer can be formed on a flat surface, so that a highly reliable element can be obtained.

  As described above, in the present invention, it is possible to alleviate variations in characteristics of transistors that supply power to driven elements such as organic EL elements, and to average variations in power supplied to driven elements, It is possible to prevent variations in light emission luminance in the driven element.

  Further, in the present invention, by connecting a driven element and a transistor that supplies power to the element with a minimum number of contacts, necessary transistors and elements can be efficiently arranged in a limited area. Accordingly, when an EL element, for example, is employed as the driven element, the light emission area ratio in one pixel unit can be improved.

  Furthermore, in the present invention, the flatness of the surface on which the driven element is formed can be improved, and the reliability of the driven element can be improved.

It is a figure which shows the circuit structure of 1 pixel of an active matrix type organic electroluminescence display. It is a figure which shows the circuit structural example per pixel of the active-matrix organic electroluminescent display apparatus of Embodiment 1 of this invention. It is a figure which shows the IV characteristic of TFT. It is a figure which shows the effect implement | achieved by this invention and the conventional circuit structure. It is a figure which shows another circuit structure per pixel of the active matrix type organic electroluminescence display of Embodiment 1 of this invention. It is a figure which shows another circuit structure per pixel of the active matrix type organic electroluminescence display of Embodiment 1 of this invention. It is a figure which shows another circuit structure per pixel of the active matrix type organic electroluminescence display of Embodiment 1 of this invention. FIG. 8 is a plan configuration diagram of an active matrix organic EL panel according to Embodiment 1 having the circuit configuration shown in FIG. 7. It is a figure which shows the cross-sectional structure along the AA of FIG. 8, BB, and CC line. FIG. 6 is a plan view and a cross-sectional view per pixel of an active matrix organic EL panel according to Embodiment 2. 12 is another example of a planar configuration per pixel of the active matrix organic EL panel according to the second embodiment. FIG. 5 is a plan view per pixel of an active matrix organic EL panel according to Embodiment 3. 10 is another example of a planar configuration per pixel of an active matrix organic EL panel according to Embodiment 3. 12 is another example of a planar configuration per pixel of the active matrix organic EL panel according to the second embodiment. It is a figure which shows the cross section and planar structure in the contact part of the active layer 16 of a 2nd TFT, and the anode 52 of the organic EL element 50. FIG. 6 is a diagram showing a cross-sectional and planar structure example in a contact portion between an active layer 16 of a second TFT and an anode 52 of an organic EL element 50 according to Embodiment 3. FIG. 6 is a diagram showing another cross-sectional structure example in a contact portion between an active layer 16 of a second TFT and an anode 52 of an organic EL element 50 according to Embodiment 3. FIG. 6 is a diagram showing another cross-sectional structure example in a contact portion between an active layer 16 of a second TFT and an anode 52 of an organic EL element 50 according to Embodiment 3. FIG. 6 is a diagram showing another cross-sectional structure example in a contact portion between an active layer 16 of a second TFT and an anode 52 of an organic EL element 50 according to Embodiment 3. FIG. 6 is a diagram showing another cross-sectional structure example in a contact portion between an active layer 16 of a second TFT and an anode 52 of an organic EL element 50 according to Embodiment 3. FIG.

  Hereinafter, preferred embodiments of the present invention (hereinafter referred to as embodiments) will be described with reference to the drawings.

[Embodiment 1]
FIG. 2 shows a circuit configuration per pixel in the active matrix EL display device of m rows and n columns according to the first embodiment of the present invention. As shown in the drawing, each pixel includes an organic EL element 50, a switching TFT (first TFT) 10, an element driving TFT (second TFT) 20, and an auxiliary capacitor Cs. Here, a gate line GL extending in the row direction; The area is surrounded by data lines DL extending in the column direction. In the present embodiment, a compensation TFT 30 having a conductivity characteristic opposite to that of the second TFT 20 is further inserted between the power supply line VL and the second TFT 20. The compensation TFT 30 is diode-connected with the gate and one of the source and drain connected, and the diode is connected between the power supply line VL and the second TFT 20 in the forward direction. Therefore, it is possible to operate without supplying a special control signal.

  The first TFT 10 receives the gate signal at its gate and turns on, whereby the auxiliary capacitor Cs connected between the first TFT 10 and the second TFT 20 holds the data signal supplied to the data line DL, and the auxiliary capacitor Cs. The one electrode potential is equal to the data signal. The second TFT 20 is provided between the power supply line VL and the organic EL element (anode of the element) 50, and a current corresponding to the voltage value of the data signal applied to the gate is supplied from the power supply line VL to the organic EL element 50. Operates to supply. In the example shown in FIG. 2, an nch-TFT capable of high-speed response is used for the first TFT 10, and a pch-TFT is used for the second TFT 20.

  The compensation TFT 30 is an nch-TFT having a polarity opposite to that of the second TFT 20, and when the I (current) -V (voltage) characteristic of the second TFT 20 fluctuates, the IV characteristic is just in the opposite direction. It fluctuates and compensates for the characteristic variation of the second TFT 20.

  FIG. 3 shows IV characteristics of an nch-TFT and a pch-TFT using polycrystalline silicon as an active layer. In the nch-TFT, when the voltage applied to the gate exceeds a predetermined sex voltage (+ Vth), the current value increases rapidly, and in one pch-TFT, the voltage applied to the gate is less than a predetermined negative voltage (−Vth). The current value increases rapidly. Here, for example, an nch-TFT and a pch-TFT formed on the same substrate have a pch-TFT when the threshold value + Vth of the nch-TFT increases, that is, changes so as to shift to the right in FIG. The threshold value −Vt is shifted to the right in FIG. 3 by the same amount. Conversely, when the threshold value + Vth of the nth-TFT shifts to the left, the threshold value −Vth of the pth-TFT also shifts to the left side. For example, if the -Vth of the pch-TFT used in the second TFT 20 of FIG. 2 is shifted to the right due to variations in manufacturing conditions, the amount of current supplied to the organic EL element 50 under the same conditions is conventional. It decreases immediately. However, in this embodiment, the amount of current flowing through the compensation TFT 30 formed of an nch-TFT provided between the second TFT 20 and the power supply line VL increases.

  In the present embodiment, as shown in FIG. 2, the second TFT 20 and the compensating TFT 30 having opposite polarities are provided between the power supply line VL and the organic EL element 50, so that the two TFTs are always It will be balanced so as to compensate for the amount of current flowing to each other. Of course, in the circuit configuration of the present embodiment, the maximum current value that can be supplied to the organic EL element 50 is reduced by the presence of the compensation TFT 30 in the circuit configuration of this embodiment as compared with the conventional circuit configuration as shown in FIG. However, since the identification sensitivity on the high luminance side is very low compared to the sensitivity at the intermediate luminance, the human eye hardly affects the display quality even if the maximum supply current value is slightly reduced. On the other hand, in each pixel, since the currents that the second TFT 20 and the compensation TFT 30 flow out to each other are adjusted, it is possible to reduce variations in the amount of current supplied to the organic EL element 50 between the pixels.

  Next, with reference to FIG. 4, the effect realized by the circuit configuration of the present embodiment will be described. 4 shows the case where the organic EL element emits light by the pixel circuit configuration of the present embodiment shown in FIG. 2, and the lower part of FIG. 4 shows the case where the organic EL element emits light by the conventional pixel circuit configuration shown in FIG. An example of the relationship between applied voltage (data signal) and light emission luminance is shown. In the setting of FIG. 4, when the applied voltage (data signal) is 8 V, the required maximum luminance for the organic EL element is set, and a case where gradation display is performed between 8 V and 10 V is taken as an example. Further, each of the three samples in the upper and lower stages of FIG. 4 intentionally varies the characteristics of the TFT in the pixel portion when the organic EL panel having the circuit configuration of FIGS. 2 and 1 is formed under different manufacturing conditions. It is the light emission luminance characteristic when it is allowed to go.

  As is clear from FIG. 4, in the conventional circuit configuration, the luminance characteristics greatly change in the set data signal voltage range 8V to 10V in three samples having different characteristics of the pixel portion TFT, whereas In the circuit configuration of the embodiment, the difference in the luminance characteristics in the halftone area of the three samples is very small, only the characteristics in the high luminance area that is not perceived are different. Therefore, by making each pixel have the circuit configuration as in the present embodiment, even if the characteristics of the TFT, particularly the EL element driving TFT 20 that has a great influence, vary, Variations can be compensated, and variations in emission luminance of the organic EL elements can be suppressed.

  FIG. 5 shows another example of the circuit configuration of the present embodiment. The difference from FIG. 2 described above is that the second TFT 22 is configured by using an nch-TFT, and a diode-connected pch-TFT is used for the compensation TFT 32. Even with such a configuration, the characteristic variation in the second TFT 22 can be compensated by the compensating TFT 32.

  FIG. 6 shows still another example of the circuit configuration of the present embodiment. The difference from the circuit configuration of FIG. 2 is that a plurality of second TFTs are provided in parallel between the compensation TFT 30 and the organic EL element 50. The polarities of the TFTs are pch for the second TFT 24 and nch for the compensation TFT 30 as in FIG. The gates of the two second TFTs 24 are both connected to the first TFT 10 and the first electrode side of the auxiliary capacitor Cs, each source is connected to the compensation TFT 30, and the drain is connected to the organic EL element 50. By providing the second TFTs 24 in parallel in this way, it is possible to further reduce variations in supply current to the organic EL element due to variations in characteristics of the second TFTs.

  Here, if the current value target of each of the two second TFTs 24 is i, the total target current value of the two second TFTs 24 is naturally 2i. For example, even if the current supply capability of one of the second TFTs 24 becomes i / 2 due to the variation, if the other second TFT 24 allows current to flow through i, (3/2) i is set to the organic EL element with respect to the target 2i. Can be supplied to. Further, even if the current supply capability of one of the worst TFTs becomes zero, in the example of FIG. 6, it is possible to supply the current i to the organic EL element by the other TFT. In the case where the second TFT 24 is configured by a single TFT, when the current supply capability becomes zero, the effect is remarkably large as compared with the pixel becoming defective.

  In addition, each TFT of the present embodiment polycrystallizes a-Si by laser annealing, but when a plurality of second TFTs 24 are provided in parallel, laser scanning is performed so that the active region of each second TFT 24 is not irradiated with laser simultaneously. It is easy to devise such as shifting the formation place with respect to the direction. With such an arrangement, the possibility that all the second TFTs 24 become defects can be remarkably reduced, and characteristic variations caused by laser annealing can be minimized. In addition, since the compensation TFT 30 is provided between the second TFT 24 and the power supply line VL as described above, even if the threshold value of the second TFT 24 is shifted due to variations in annealing conditions, the compensation TFT 30 Can be relaxed.

  FIG. 7 shows still another pixel circuit configuration of the present embodiment. 6 differs from the configuration of FIG. 6 described above in that not only the second TFT 24 but also a plurality of compensation TFTs are provided, and each compensation TFT 34 is provided between the power supply line VL and the second TFT 24. If a plurality of compensation TFTs 34 are also used as shown in FIG. 7, the variation in current supply capability generated in each compensation TFT 34 can be alleviated as a whole, and the variation in supply current capability to the organic EL element 50 can be more reliably ensured. It is possible to reduce it.

  FIG. 8 shows an example of a planar configuration of the organic EL display device having the circuit configuration as shown in FIG. 9A is a schematic cross section taken along the line AA in FIG. 8, FIG. 9B is a schematic cross section taken along the line BB in FIG. 8, and FIG. The schematic cross section along CC line | wire of FIG. In FIG. 9, layers (films) formed at the same time are basically denoted by the same reference numerals except those having different functions.

  As shown in FIG. 8, each pixel includes a first TFT 10, an auxiliary capacitor Cs, two pch second TFTs 24, and two nch compensation TFTs 34 provided in diode connection between the power supply line VL and the second TFT 24. And an organic EL element 50 connected to the drain of the second TFT 24. In the example of FIG. 8 (although not limited to this), one pixel is arranged in a region surrounded by the gate line GL extending in the row direction, the power supply line VL extending in the column direction, and the data line DL. In the example of FIG. 8, in order to realize a higher-definition color display device, a so-called delta arrangement in which the arrangement positions of the R, G, and B pixels are shifted for each row is adopted. The power supply line VL is not straight, but extends in the column direction so as to fill the gaps between the pixels whose positions are shifted for each row.

  In each pixel region, the first TFT 10 is formed in the vicinity of the intersection between the gate line GL and the data line DL. The active layer 6 is made of p-Si obtained by polycrystallizing a-Si by laser annealing, and the active layer 6 has a pattern straddling the gate electrode 2 protruding from the gate line GL twice. In FIG. 7, a single gate structure is shown, but a dual gate structure is used in terms of circuit. The active layer 6 is formed on a gate insulating film 4 formed so as to cover the gate electrode 2, a region immediately above the gate electrode 2 is a channel, and on both sides, a source region 6 S doped with impurities, a drain region 6D is formed. Since the first TFT 10 is desired to respond at high speed to a selection signal output to the gate line GL, the source / drain regions 6S and 6D are doped with impurities such as phosphorus (P) to form an nch-TFT. It is configured.

  The drain region 6D of the first TFT 10 is connected to a data line DL formed on the interlayer insulating film 14 formed so as to cover the entire first TFT 10 and a contact hole opened in the interlayer insulating film 14.

  An auxiliary capacitor Cs is connected to the source region 6S of the first TFT 10. The auxiliary capacitor Cs is formed in a region where the first electrode 7 and the second electrode 8 overlap with each other with the gate insulating film 4 interposed therebetween. The first electrode 7 extends in the row direction in the same manner as the gate line GL in FIG. 8, and is formed integrally with a capacitor line SL formed of the same material as the gate. The second electrode 8 is integrated with the active layer 6 of the first TFT 10, and the active layer 6 extends to the position where the first electrode 7 is formed. The second electrode 8 is connected to the gate electrode 25 of the second TFT 24 via the connector 42.

  The cross-sectional configurations of the two pch second TFTs 24 and the two nch compensation TFTs 34 are as shown in FIG. These second TFTs and compensation TFTs 24 and 34 use the semiconductor layer 16 patterned in an island shape for each TFT in the direction along the data line DL (power supply line VL) as each active layer. Accordingly, in this example, the channels of the second TFT 24 and the compensation TFT 34 are arranged such that the channel length direction is along the longitudinal direction of the data line DL, here, one pixel having an elongated shape. The semiconductor layer 16 is formed at the same time as the active layer 6 of the first TFT 10, and uses polycrystalline silicon formed by polycrystallizing a-Si by laser annealing.

  The compensation TFTs 34 located at both ends in FIG. 9B are connected to the same power supply line VL through contact holes whose drain regions are opened in the interlayer insulating film 14. A gate electrode 35 is disposed immediately below the channel region of the compensation TFT 34 with the gate insulating film 4 interposed therebetween. The gate electrode 35 is a layer formed of the same material and at the same time as the gate line GL, but is connected to the power supply line VL in the contact hole as shown in FIG. Accordingly, as shown in the circuit diagram of FIG. 7, the compensation TFT 34 constitutes a diode in which the gate and the drain are both connected to the power supply line VL. Further, the source region of the compensation TFT 34 is spaced apart from the source region of the second TFT 24 composed of the pch TFT, and is connected to each other by the contact wiring 43.

  Each gate electrode 25 of the second TFT 24 is a conductive layer formed of the same material as the gate line GL at the same time as the gate electrode 35 of the compensation TFT 34, and is connected to the second electrode 8 of the auxiliary capacitor Cs via the connector 42. Then, it extends along the power supply line VL from the region where the auxiliary capacitor Cs is formed, and further extends under the active layer 16 to constitute the gate electrodes 25 of the two second TFTs 24.

  The organic EL element 50 has a cross-sectional structure as shown in FIG. 9C, for example. After each TFT as described above is formed, planarization insulation formed on the entire surface of the substrate for the purpose of planarizing the upper surface. Formed on layer 18. The organic EL element 50 is configured by laminating an organic layer between an anode (transparent electrode) 52 and a cathode (metal electrode) 57 formed on the uppermost layer in common with each pixel. Here, the anode 52 is not directly connected to the source region of the second TFT 24 but is connected via the connector 40 constituting the wiring layer.

  Here, in this embodiment, as shown in FIG. 8, the two second TFTs 24 are commonly connected to one connector 40, and this connector 40 is connected to the first electrode 52 of the organic EL element 50 at one location. I'm in contact. That is, the organic EL element 50 is connected to the n second TFTs 24 by n−1 or less contacts. The contact region may be a non-light-emitting region. Thus, the light-emitting region can be made as large as possible by reducing the number of contacts between the organic EL element 50 and the connector 40 (second TFT 24) as much as possible. Other examples regarding the number of contacts will be described later as a third embodiment.

  In this embodiment, as shown in FIGS. 8 and 9C, the connection position between the connector 40 and the anode 52 is shifted from the connection position between the connector 40 and the second TFT 24. The light emitting element layer 51 containing an organic compound, which will be described later, is likely to cause electric field concentration when there is a locally thin place, and may start to deteriorate from the place where the electric field concentration occurs. Therefore, it is desirable that the surface on which the light emitting element layer 51 using an organic material is formed be as flat as possible. In the upper layer of the contact hole, a depression due to the contact hole is formed, and the deeper the contact hole, the larger the depression. Therefore, by arranging a contact hole connecting the connector 40 and the source region of the second TFT 24 outside the formation region of the anode 52, the upper surface of the anode 52 on which the organic layer is formed can be made as flat as possible. It is said. An example of flattening the upper surface of the anode 52 will be described later as a fourth embodiment.

In the light emitting element layer (organic layer) 51, for example, a first hole transport layer 53, a second hole transport layer 54, an organic light emitting layer 55, and an electron transport layer 56 are sequentially stacked from the anode side. As an example, the first hole transport layer 52 is MTDATA: 4,4 ′, 4 ″ -tris (3-methylphenylphenylamino) triphenylamine, and the second hole transport layer 54 is TPD: N, N′-diphenyl-N, N. '-di (3-methylphenyl) -1,1'-biphenyl-4,4'-diamine, the organic light-emitting layer 55 varies depending on the intended light emission colors of R, G, and B. For example, quinacridone BeBq ₂ : bis (10-hydroxybenzo [h] quinolinato) beryllium containing a derivative is included, and the electron transport layer 56 is composed of BeBq. In the example shown in FIG. 9C, the organic EL element 50 includes an anode 52 made of ITO (Indium Tin Oxide) or the like, organic layers (53, 54, 56) other than the organic light emitting layer 55, Al, and the like. The cathode 57 is formed in common for each pixel.

  Another example of the structure of the EL element is an element in which the left layers using the materials listed on the right are sequentially stacked.

a. Transparent electrode (anode)
b. Hole transport layer: NBP
c. Light emitting layer: Red (R): Host material (Alq ₃ ) doped with red dopant (DCJTB) Green (G): Host material (Alq ₃ ) doped with green dopant (Coumarin 6) blue ( B)... Host material (Alq ₃ ) doped with blue dopant (Perylene) d. Electron transport layer: Alq ₃
e. Electron injection layer: lithium fluoride (LiF)
f. Electrode (cathode): Aluminum (Al)
Here, the formal names of the materials described in the above abbreviations are as follows.
・ "NBP" ... N, N'-Di ((naphthalene-1-yl) -N, N'-diphenyl-benzidine)
- "Alq _3" ··· Tris (8-hydroxyquinolinato) aluminum
・ 「DCJTB」 ・ ・ ・ (2- (1,1-Dimethylethyl) -6- (2- (2,3,6,7-tetrahydro-1,1,7,7-tetramethyl-1H, 5H-benzo [ ij] quinolizin-9-yl) ethenyl) -4H-pyran-4-ylidene) propanedinitrile
・ "Coumarin 6" ... 3- (2-Benzothiazolyl) -7- (diethylamino) coumarin
・ "BAlq" ... (1,1'-Bisphenyl-4-Olato) bis (2-methyl-8-quinolinplate-N1,08) Aluminum
However, it is of course not limited to such a configuration.

  In the pixel having the above-described structure, when a selection signal is applied to the gate line GL, the first TFT 10 is turned on, and the potential of the data line DL and the source region connected to the second electrode 8 of the auxiliary capacitor Cs. The potentials are equal. A voltage corresponding to the data signal is supplied to the gate electrode 25 of the second TFT 24, and the second TFT 24 supplies a current supplied from the power supply line VL via the compensation TFT 34 according to the voltage value to the anode of the organic EL element 50. 52. By such an operation, a current corresponding to the data signal can be accurately supplied to the organic EL element 50 for each pixel, and a display without variations can be achieved.

  As shown in FIG. 8, since the compensation TFT 34 and the second TFT 24 are provided in this order between the power supply line VL and the organic EL element 50 in this order (two series in this case), characteristics due to variations in one of the systems. Even if a shift or a defect occurs, the presence of the other system having normal characteristics makes it possible to alleviate variations in the amount of supply current determined by the sum of a plurality of series.

  In the planar arrangement shown in FIG. 8, a polycrystalline silicon layer whose active layer is polycrystallized by a laser annealing process is used. This annealing process, for example, uses a long laser beam in the row direction of the figure. Scan in the column direction. Even in such a case, the channel direction of the first TFT 10 does not coincide with the channel direction of each active layer length of the second and compensation TFTs 24 and 34, and the formation position is separated between the first and second TFTs 10 and 24. ing. For this reason, it is possible to prevent the first and second TFTs 10 and 24, and further the second and compensation TFTs 24 and 34 from being troubled simultaneously by laser annealing.

  The first TFT 10, the second TFT 24, and the compensation TFT 34 are all described as having a bottom gate structure, but may have a top gate structure in which a gate electrode is formed above the active layer.

[Embodiment 2]
Next, another embodiment 2 of the present invention will be described. In the first embodiment, in order to prevent variation in light emission luminance between pixels due to variation in transistor characteristics, a thin film transistor for driving an element and a thin film transistor for compensating for reverse conductivity are provided. On the other hand, in the second embodiment, attention is paid to the arrangement of the element driving thin film transistors (second TFTs), and variations in the light emission luminance among the pixels are suppressed. FIG. 10 shows a configuration example per pixel according to the second embodiment. FIG. 10A is a schematic plan view, and FIG. 10B is a cross section taken along line BB in FIG. FIG. This configuration is shown by the same circuit configuration as FIG. Further, in the figure, the same reference numerals are given to the portions corresponding to the already described figures.

  In the second embodiment, one pixel includes an organic EL element 50, a first TFT (switching thin film transistor) 10, an auxiliary capacitor Cs, and a second TFT (element driving thin film transistor) 20. Unlike the first embodiment, a single second TFT 20 is formed between the power supply line VL and the organic EL element 50. As in the above-described FIG. They are arranged along the longitudinal direction of the elongated pixels. In the second embodiment, the second TFT 20 having a very long channel length is arranged as shown in FIG. 10A by arranging the second TFT 20 so that the channel length direction faces the longitudinal direction of the pixel region. In addition, when the second TFT 20 and the compensation TFT 30 need to be disposed between the power supply line VL and the organic EL element 50 as shown in FIG. It is possible to efficiently arrange necessary TFTs in one pixel region having a limited area while ensuring the maximum area.

  In the second embodiment, by disposing the second TFT 20 in the longitudinal direction of the pixel, as shown in FIGS. 10A and 10B, the channel length of the second TFT 20 can be made sufficiently long. By making the channel length of the second TFT 20 sufficiently long, the reliability by improving the TFT breakdown voltage is improved. In addition, the transistor characteristics of the second TFT 20 can be averaged, the variation in the current supply capability of the second TFT 20 for each pixel can be reduced, and the variation in light emission luminance of the organic EL element 50 caused by this variation in capability can be extremely reduced. It becomes.

  In the second embodiment, as in the first embodiment, the second TFT 20 uses a polycrystalline silicon layer obtained by polycrystallizing an amorphous silicon layer by laser annealing as the semiconductor layer (active layer) 16. In this case, the scanning direction of laser annealing is set to a direction that coincides with the channel length direction of the second TFT 20, in other words, the longitudinal edge of the irradiation region of the pulse laser is arranged so as to cross the channel 16c in the width direction, In addition, by increasing the channel length of the second TFT 20 as described above, it is possible to reduce the characteristic variation of the second TFT 20. This is easy to adjust so that the entire channel region of the second TFT 20 is not annealed by a single laser shot, and it is possible to prevent a large difference from occurring in the characteristics of the second TFT 20 of other pixels. This is because it is possible to obtain a higher averaging effect with respect to the characteristics of the 2 TFT 20.

  The second TFT 20 is required to supply a relatively large current from the drive power supply (power supply line VL) to the organic EL element 50. However, a p-Si-TFT using polycrystalline silicon for the active layer 16 is required. When used for the second TFT 20, the mobility of p-Si is a sufficient value compared to the required capacity, and the second TFT 20 can exhibit a sufficient current supply capacity even if its channel length is designed to be long. Further, since the second TFT 20 is directly connected to the power supply line VL, the required breakdown voltage is high, and the channel length CL is often required to be larger than the channel width. Therefore, from this point of view, it is preferable that the second TFT 20 has a sufficiently long channel length. For this purpose, the second TFT 20 is formed so that the channel length direction is along the longitudinal direction of the pixel region. It becomes possible to efficiently arrange the second TFT 20 having a long channel in the pixel region.

  In a display device configured with a plurality of pixels arranged in a matrix on a display surface, in many cases, higher resolution is required in the horizontal direction (row direction) than in the vertical direction (column direction). Each pixel has a strong tendency to be designed in a long shape in the column direction as shown in FIG. 8 and FIG. In such a case, if the second TFT 20 is arranged so that the channel length direction is in the column direction, the channel length direction is along the longitudinal direction of the pixel region, and the required channel length can be ensured as described above. It becomes easy.

  As shown in the second embodiment, in an active matrix display device in which each pixel is provided with a switch element for driving a display element, a data line DL for supplying a data signal to the first TFT 10 is arranged in the column direction. A selection line (gate line) GL is arranged in the row direction. Therefore, by arranging the second TFT 20 so that the channel length direction extends along the direction (column direction) in which the data line DL extends, the second TFT 20 can be efficiently arranged in the pixel region while ensuring a long channel length. It becomes easy. In the example of FIG. 10, a layout in which power is supplied to each pixel from the drive power supply Pvdd by the power supply line VL is adopted, and this power supply line VL also extends in the column direction like the data line DL. The channel length direction of the second TFT 20 also coincides with the extending direction of the power supply line VL.

  By the way, in the second embodiment, as described above, the channel length direction of the second TFT 20 is set to coincide with the scanning direction of laser annealing or to be parallel to the column direction (extending direction of the data line DL). However, the first TFT 10 is arranged so that the channel length direction thereof coincides with the row direction in which the gate line GL extends. Therefore, in the second embodiment, the first TFT 10 and the second TFT 20 are arranged in different channel length directions.

  Next, a cross-sectional structure of the display device according to the second embodiment will be described with reference to FIG. FIG. 10B shows a cross-sectional structure of the second TFT 20 and the organic EL element 50 connected to the TFT 20. The basic configuration of the first TFT 10 (not shown) is almost the same as that of the second TFT 20 in FIG. 10B except that the channel length, the double gate, and the conductivity type of the active layer 6 are different. ing.

  Both the first and second TFTs exemplified in the first embodiment have a bottom gate structure, but in the second embodiment, the first and second TFTs 10 and 20 have a top gate structure in which a gate electrode is formed above the active layer. Adopted. Of course, the structure is not limited to the top gate structure, and may be a bottom gate structure.

  As described above, the active layer 16 of the second TFT 20 and the active layer 6 of the first TFT 10 are both composed of polycrystalline silicon obtained by polycrystallizing the amorphous silicon layer formed on the substrate 1 by laser annealing. Yes. A gate insulating film 4 is formed on the active layer 6 and the active layer 16 made of polycrystalline silicon. The gate electrodes 2 and 25 of the first TFT 10 and the second TFT 20 are formed on the gate insulating film 4. The gate electrode 25 of the second TFT 20 is a second auxiliary capacitor Cs integrated with the active layer 6 of the first TFT 10. As shown in FIG. 10A, it is connected to the electrode 8 and extends in the column direction from the connection portion with the auxiliary capacitor Cs so as to be widely covered on the gate insulating film 4 above the active layer 16.

  The active layer 16 of the second TFT 20 has a channel region 16c that is covered by the gate electrode 25. A source region 16s and a drain region 16d are formed on both sides of the channel region 16c. In the second embodiment, the source region 16s of the active layer 16 is electrically connected to the power supply line VL through a contact hole formed through the gate insulating film 4 and the interlayer insulating film 14 in the vicinity of the auxiliary capacitor Cs. It is connected to the. The drain region 16d is connected to the connector (wiring layer) 40 through a contact hole formed through the gate insulating film 4 and the interlayer insulating film 14 in the vicinity of the gate line GL corresponding to the next row of the matrix. Has been. The connector 40 extends from the connection region with the drain region 16 d to the region where the organic EL element 50 is formed, and is formed on the first planarization insulating layer 18 formed so as to cover the interlayer insulating film 14, the power supply line VL, and the connector 40. The ITO electrode (anode) 52 of the organic EL element 50 is electrically connected through the contact hole.

  In FIG. 10B, only the formation center region of the anode 52 of the organic EL element 50 is opened on the first planarization layer 18, and the edge of the anode 52, the wiring region, and the first and second TFTs are opened. A second planarization insulating layer 61 is formed so as to cover the formation region. A light emitting element layer 51 of the organic EL element 50 is formed on the anode 52 and the second planarization insulating layer 61. A metal electrode 57 common to all pixels is formed on the light emitting element layer 51.

  Next, the relationship between the channel length CL of the second TFT 20 and the moving pitch P of the laser will be described. As described above, it is preferable that the channel length CL of the second TFT 20 is sufficiently long. However, in order to prevent the entire channel region from being annealed by one pulse laser, the laser movement pitch P is set to the channel length. It is preferable that P <CL with respect to CL. The moving pitch P may be adjustable by setting the optical system of the laser annealing apparatus. In such a case, it is preferable to adjust the apparatus so that CL> P. For example, in the case of a display device having a resolution of about 200 dpi, even if the length in the pixel row direction is about 30 μm, about 80 μm can be secured in the column direction. Further, when the laser moving pitch P is 20 μm to 35 μm, the channel length CL can be secured to about 50 μm to 80 μm by arranging the second TFT 20 so that the channel length direction thereof is in the pixel longitudinal direction, and the above relationship is satisfied. it can. In such a relationship, the channel region 16c of the second TFT 20 is always polycrystallized by being irradiated with a plurality of times of pulsed laser, and similarly, the other TFTs that are polycrystallized by the plurality of times of pulsed laser irradiation. It is possible to reduce the difference in characteristics with the second TFT 20.

  In the above description, the single second TFT 20 is formed between the organic EL element 50 and the power supply line VL in one pixel. However, a plurality of second TFTs 20 may be provided in one pixel. FIG. 11 shows an example of a layout when a plurality of second TFTs 20 are connected in parallel between the power supply line 16 and the organic EL element 50 in one pixel. The equivalent circuit of the pixel configuration shown in FIG. 11 is equivalent to the case where the compensation TFT 30 is removed in the circuit of FIG. 6 described above, and the source regions 16sa and 16sb of the two second TFTs 20 are both connected to the power supply line VL. The drain regions 16da and 16db are both connected to the anode 52 of the organic EL element 50 through the contact 40, respectively. By providing a plurality of second TFTs 20 in one pixel as described above, the probability that both of the plurality of second TFTs 20 for one pixel become defective at the same time and current supply to the organic EL element cannot be reduced to at least half. it can.

  As for the arrangement of the two second TFTs 20a and 20b, the channel length direction is substantially parallel to the longitudinal direction of the pixel region (here, also coincides with the extending direction of the data line DL), as in FIG. Deploy. Such an arrangement makes it possible to secure each channel length CL as long as possible while ensuring the maximum light emitting area. Further, the scanning direction of laser annealing is set to be parallel to the channel length direction of the two second TFTs 20a and 20b in FIG. Moreover, both the active layers 16a and 16b are arranged on a straight line. Although it is not essential that the active layers of the plurality of second TFTs 20a and 20b are aligned with each other, the channel regions 16ca and 16cb of the second TFTs 20a and 20b do not completely coincide with each other in the laser scanning direction. Even a slight deviation can more reliably prevent the characteristics of the TFTs 20a and 20b from varying in the same manner. That is, since the channel length directions are shifted from each other in the laser scanning direction, the possibility that the channels of the two TFTs are simultaneously annealed by the same pulse is reduced, and the characteristics of the second TFTs 20a and 20b are set to the same value. The possibility of occurrence of a problem that the two transistors do not operate at the same time or both transistors do not operate at the same time can be greatly reduced, and variations in the total current supplied to the organic EL element 60 for each pixel can be reduced.

  It is desirable that the channel lengths CLa and CLb of the two second TFTs 20a and 20b are both larger than the laser movement pitch P as described above. Furthermore, it is more preferable that the distance L between the channels 16ca and 16cb of the plurality of second TFTs 20a and 20b is larger than the laser movement pitch P. However, when a plurality of second TFTs 20 are arranged in one pixel as shown in FIG. 11, laser annealing is performed if the total channel length of at least two TFTs 20a and 20b and the total distance L is larger than the movement pitch P. As a result, it is possible to prevent the simultaneous failure of the plurality of transistors TFT2a and TFT2b in one pixel or the characteristic shift in the same manner, and an effect of reducing the characteristic variation among the pixels can be obtained.

[Embodiment 3]
Next, as Embodiment 3, a more efficient connection method between the plurality of second TFTs 20 and the corresponding organic EL elements 50 in one pixel will be described. As shown in FIG. 11 of the first and second embodiments described above, providing a plurality of second TFTs 20 between the organic EL element 50 and the power supply line VL in one pixel improves reliability, improves characteristics, and the like. From the viewpoint of When a plurality of second TFTs 20 are provided in one pixel in this way, as shown in FIG. 11, the second TFTs 20a and 20b and the organic EL element 50 are connected to each other to connect the power line VL to the organic EL element 50. The current supply through the second TFT 20 is more reliable. However, in the case of an organic EL element that emits light from the light emitting layer 55 to the outside through the substrate 1 below from the transparent anode 52 as shown in FIG. 10B, the contact portion is often shielded from light. . For example, in FIG. 9C and FIG. 10B, the connection between the organic EL element 50 and the second TFT 20 is made through a wiring layer 40 that is a metal wiring. In the contact portion, the light-shielding wiring layer 40 exists below the anode 52, and light from the light emitting layer 55 cannot pass to the substrate 1 side in this region. Therefore, if the contact portions between the second TFT 20 and the organic EL element 50 are provided in the same number as the number n of the second TFTs 20, the light emission area is reduced in proportion to the number of contacts.

  Therefore, in order to minimize the reduction of the light emitting area, the number of contacts between the second TFT 20 and the organic EL element 50 is n−1 or less with respect to the number n (n ≧ 2) of the second TFT 20 per pixel. It is preferable to do. In FIG. 8 described above and FIGS. 12, 13, and 14 described below, the n second TFTs 20 and the organic EL element 50 are connected with n-1 or less contacts. In each drawing described below, the same reference numerals are given to the same parts as those already described, and the description is omitted.

  FIG. 12 shows a contact method with the organic EL element 50 when two second TFTs 20 a and 20 b are connected in parallel between the power supply line VL and the organic EL element 50. Note that the channel length direction of the two second TFTs 20a and 20b is parallel to the longitudinal direction of the pixel (the extending direction of the data line DL) or the scanning direction of laser annealing, as in FIG. Further, they are arranged so as to deviate from each other, thereby reducing luminance variation between pixels and improving reliability.

  In the example of FIG. 12, a semiconductor layer made of p-Si patterned into a single island shape is used as the active layers 16a and 16b of the two second TFTs 20a and 20b. In this semiconductor pattern, both end sides in the column direction are source regions (in the case of p-ch TFTs) 16sa and 16sb of the second TFTs 20a and 20b, and are connected to the power supply line VL. Also, the drain regions (in the case of p-ch TFTs) 16da and 16db of the two TFTs 20a and 20b near the center of the semiconductor pattern are the single wiring layer 40 disposed between the two TFTs, the interlayer insulating film 14 and They are connected through a common contact hole formed through the gate insulating film 4 (see FIG. 10B).

  The wiring layer 40 extends to the anode formation region of the organic EL element 50, and the organic EL element is connected through one contact hole opened in the first planarization insulating layer 18 similarly to the cross-sectional structure of FIG. 50 anodes 52 are connected. Here, the connection position between the wiring layer 40 and the anode 52 is near the center of the anode 52 in the pixel longitudinal direction in FIG. The contact position is not limited as shown in FIG. 12, but is arranged at a position relatively close to the center of the anode 52 as shown in FIG. An effect of averaging the current density in the region where the anode 52 is formed can be obtained, and the uniformity of the light emission luminance within the light emitting surface of each pixel can be improved.

  In the example shown in FIG. 13, the number of second TFTs 20 is three, and these three TFTs 20-1, 20-2 and 20-3 are connected in parallel between the power supply line VL and the anode 52 of the organic EL element 50. . The active layers 16 of the three second TFTs 20 are integrated, and the channel length direction is set in the row direction in the figure. The channel regions 16c1 to 3 of the second TFTs 20-1 to 20-3 are separated from each other by opening the pattern of the active layer 16 in the channel width direction.

  Here, the three second TFTs 20 are connected to the power supply line VL at one location, and are also connected to the anode 52 of the organic EL element 50 at one location by a single wiring layer 40. The TFT is common, and is configured by a metal wiring electrically connected to the second electrode 8 of the auxiliary capacitor Cs and extending in the column direction from the vicinity of the auxiliary capacitor Cs. In the configuration example of FIG. 13, the three second TFTs 20-1 to 20-3 and the organic EL element 50 are connected by one contact portion, and the proportion of the contact portion in the formation region of the organic EL element 50 can be reduced. The aperture ratio per pixel, that is, the light emission area can be increased.

  In the example illustrated in FIG. 14, the number of second TFTs 20 is four, and these four TFTs 20-1 to 20-4 are electrically connected in parallel between the power supply line VL and the anode 52 of the organic EL element 50. The active layers 16 of the four second TFTs 20 are integrally formed, and the channel length direction of each of the TFTs 20-1 to 20-4 is set parallel to the longitudinal direction of the pixel region or the extending direction of the data line DL, as in FIG. The four are arranged in a substantially straight line.

Here, the four second TFTs 20-1 to 20-4 are connected to the power supply line VL at three locations, and are connected to the anode 52 of the organic EL element 50 at two locations by the first and second wiring layers 40-1 and 40-2. It is connected. In the configuration example of FIG. 14, the source regions 16s ₁ and 16s _{4 of} the TFTs 20-1 and 20-4 located on the outermost side of the single active layer 16 are individually connected to the power supply line VL and located in the center. The source regions 16s ₂ and 16s _{3 of the} TFTs 20-2 and 20-3 are commonly connected to the power supply line VL. The second TFTs 20-1 and 20-2 and the organic EL element 50 have drain regions 16d ₁ and 16d ₂ connected to the first wiring layer 40-1 extending from between the second TFTs 20-1 and 20-2 to the element 50. The first wiring layer 40-1 extends to the formation region of the organic EL element 50 and is connected to the anode 52 of the element. Further, the second TFTs 20-3 and 20-4 and the organic EL element 50 have drain regions 16d ₃ and 16d _{4 in} the second wiring layer 40-2 extending from between the second TFTs 20-3 and 20-4 to the element 50. The second wiring layer 40-2 extends to the region where the organic EL element 50 is formed and is connected to the anode 52 of the element. As described above, only the two second TFTs 20-1 to 20-4 and the organic EL element 50 are connected to each other, and the reduction of the light emitting area due to the provision of the four second TFTs 20-1 to 4 is suppressed.

  In the configuration of FIG. 14, the four second TFTs 20-1 to 20-4 are arranged so that the channel length direction is substantially aligned along the longitudinal direction of the pixel, so that the second TFTs 20-1 to 20-4 are efficient. Therefore, it can be arranged in one pixel.

[Embodiment 4]
Next, a connection structure between the second TFT 20 and the organic EL element 50 will be described with reference to FIGS. As described in the third embodiment, the contact region between the organic EL element 50 and the second TFT 20 is a non-light emitting region in the case of a method of transmitting light from the lower substrate 1 to the outside (bottom emission) through the transparent anode 52. Often. Further, in order to improve the degree of integration in many integrated circuits and the like, and in the case of a display device, it is desirable to reduce the contact area as much as possible. From this point of view, even when the active layer 16 of the second TFT 20 and the anode 52 of the organic EL element 50 are directly connected, a metal connection layer (such as an Al layer or a Cr layer) is not directly connected to improve connection characteristics. 15), the first contact hole 70 of the interlayer insulating film 14 and the second contact hole 72 of the first planarizing insulating layer 18 are preferably formed so as to overlap each other as shown in FIG.

  However, when a plurality of contact holes are formed so as to overlap as shown in FIG. 15A, the contact hole total step (h70 + h72) becomes large, and the surface flatness of the layer formed on the contact hole decreases. Further, in order to prevent a short circuit between the anode 52 and the cathode 57 due to poor coverage of the light emitting element layer 51 in the anode edge region, a second planarization insulating layer 61 covering the edge region of the anode 52 as shown in FIG. In some cases, the second planarization insulating layer 61 is opened in the central region of the anode 52. Therefore, the opening of the second planarization insulating layer 61 is formed in the vicinity of the first and second contact holes 70 and 72, and the formation surface of the light emitting element layer 51 is further formed by the second planarization insulation. The step h74 due to the opening of the layer 61 is also affected.

  On the other hand, the organic EL element 50 causes the light-emitting organic compound contained in the light-emitting layer 55 to emit light by passing an electric current through the light-emitting element layer 51. It is known that electric field concentration is likely to occur in a thinner part than other parts, and dark spots are likely to occur in such a part. The dark spot deteriorates display quality and is often enlarged by driving the element, so that the element life is shortened. Therefore, when forming the organic EL element 50 on the upper layer of the contact region, it is required to increase the flatness of the formation surface of the light emitting element layer 51 as much as possible, and the light emitting element layer 51 is formed on a very uneven surface. The contact structure as shown in FIG. 15 is not preferable from the viewpoint of improving the reliability of the light emitting element layer 51.

  FIG. 16 shows an example of a connection method in which the flatness on the formation surface of the light emitting element layer 51 is improved based on the above. FIG. 16A shows a cross-sectional structure of a contact portion between the active layer 16 of the second TFT 20 and the anode 52 of the organic EL element 50, and FIG. 16B shows a schematic plan structure of the contact portion. The connection structure shown in FIG. 16 has the second planarization insulating layer 61 covering the edge region of the anode 52 and the second TFT shown in FIGS. 8 and 9 described in the first embodiment except that the second TFT is a top gate. In common, the connection position between the wiring layer 40 and the anode 52 is shifted from the connection position between the wiring layer 40 and the active layer 16 of the second TFT 20. By adopting such a layout, in the contact region between the wiring layer 40 and the anode 52, the anode surface, that is, the formation surface of the light emitting element layer 51 is only affected by the step h72 due to the second contact hole 72. As shown in FIG. 15, the step h 70 due to the first contact hole 70 is not affected. Therefore, as can be understood from the comparison between FIG. 15 and FIG. 16, the light emitting element layer forming surface, particularly the light emitting layer 55 is formed, and the flatness of the element layer forming surface in the light emitting region of each pixel is improved.

  FIG. 17 shows a method for further flattening the formation surface of the light emitting element layer in FIG. In the example shown in FIG. 17, as in FIG. 16, the formation position of the second contact hole 72 that connects the wiring layer 40 and the anode 52 of the organic EL element 50 is shifted from the formation position of the first contact hole 70. The second planarization insulating layer 61 covers the second contact hole 72. Therefore, in the region where the light emitting layer 55 is formed, the flatness of the light emitting element layer forming surface can be further improved without being affected by the step due to the second contact hole 72 as well as the first contact hole 70. It has become. Further, since the second planarization insulating layer 61 covers the edge region of the anode 52, a short circuit between the anode 52 and the cathode 57 is reliably prevented.

  Here, the light emitting region of the organic EL element is a region facing the light emitting layer 55 between which the anode 52 and the cathode 57 are disposed, and the second planarization insulation is provided between the anode 52 and the light emitting element layer 51. The region where the layer 61 is formed does not emit light. Therefore, strictly speaking, in the configuration shown in FIG. 17, since the second planarization insulating layer 61 covers not only the edge of the anode 52 but also above the second contact hole 72, the light emitting region decreases accordingly. However, when the light-shielding wiring layer 40 and the like are formed in the lower layer as described above, the formation region of the wiring layer 40 becomes a non-light emitting region when viewed from the outside. Therefore, even if the structure in which the second planarization insulating layer 61 covers the second contact hole 72 as shown in FIG. 17 is adopted, it is possible to suppress a decrease in actual light emission area per pixel.

  The method of covering the contact hole with the second planarization insulating layer 61 can also be achieved by adopting a layout in which the first and second contact holes 70 and 72 are overlapped as shown in FIG. The effect of improving the flatness of the surface is demonstrated. That is, like the cross-sectional structure of the contact portion shown in FIG. 18, the active layer 16 of the second TFT 20 and the anode 52 of the organic EL element 50 are connected by the first and second contact holes 70 and 72 formed in an overlapping manner, A region in which the upper surface of the anode 52 is deeply recessed by the two contact holes is covered with the second planarization insulating layer 61. Therefore, the light emitting element layer formation surface above the contact holes 70 and 72 is a surface with good flatness formed by the second planarization insulating layer 61. In FIG. 18, by forming the two contact holes 70 and 72 at the same position, the element arrangement efficiency in one pixel is high, and it is easy to contribute to the improvement of the light emitting region.

  FIG. 19 illustrates still another method for flattening the light emitting element layer forming surface. The difference from FIG. 17 is that, in the formation region of the second contact hole 72, not the second planarization insulating layer 61 but the buried layer 62 is selectively formed on the anode 52 to fill the depression due to the contact hole. That is. By selectively forming the buried layer 62 on the anode 52 covering the contact hole 72 in this way, even if the second planarization insulating layer 61 or the like is not provided, the light emitting element layer formation surface on the contact hole Can be flattened. Further, as shown in FIG. 20, when the first and second contact holes 70 and 72 are formed to overlap with each other, a buried layer 62 may be employed as in FIG. In FIG. 20, a buried layer 62 is selectively formed on the anode 52 in a region where two contact holes are overlapped, and a deep depression formed by the two contact holes is buried. 19 and 20, the light emitting element layer 51 is formed on the flat surface of the buried layer 62 in the contact hole forming region, and the occurrence of defects in the light emitting element layer in this region is prevented. Can be prevented.

  The material of the second planarization insulating layer 61 and the buried layer 62 may be any material as long as the upper surface is flat. good. For example, polyimide, HMMOS, TOMCAT, TEOS, or the like can be used.

  1 substrate (transparent substrate), 2, 25, 35 gate electrode, 4 gate insulating film, 6, 16 active layer (p-si film), 10 first TFT (switching TFT), 14 interlayer insulating film, 18 flattening insulation Layers 20, 22, 24 Second TFT (element driving TFT), 30, 32, 34 Compensation TFT, 40, 42 Connector (wiring layer), 41 Metal connection layer, 50 Organic EL element, 51 Light emitting element layer, 52 Anode, 53 1st hole transport layer, 54 2nd hole transport layer, 55 organic light emitting layer, 56 electron transport layer, 57 cathode, GL gate line, VL power supply line, DL data line.

Claims (5)

A driven element that operates according to the supplied power;
N (n is an integer of 2 or more) element driving thin film transistors, one end of which is connected to a power supply line, the other end is connected to the driven element, and the power supplied to the driven element is controlled;
A switching thin film transistor for supplying a data signal supplied at the time of selection to the gates of the n element driving thin film transistors and controlling a current flowing through the element driving thin film transistor;
With
One of the source region or drain region of each of the n plurality of element driving thin film transistors is connected to the power supply line, and the other of the source region or drain region is connected to the driven element via a wiring layer , A semiconductor device characterized by being electrically connected by n-1 or less contacts. The semiconductor device according to claim 1,
A semiconductor device, wherein a contact position between the wiring layer and the element driving thin film transistor and a contact position between the wiring layer and the driven element are arranged apart from each other. The semiconductor device according to claim 2,
The driven element is a light emitting element having a light emitting element layer between first and second electrodes, and a contact hole is formed in an insulating layer formed on the wiring layer, and the contact hole The wiring layer is connected to the first electrode of the light emitting element formed on the insulating layer so as to cover the contact hole, and at least the contact hole region of the first electrode is covered with a planarization layer. The semiconductor device is characterized in that the light emitting element layer is formed on the first electrode and the planarizing layer. In the semiconductor device as described in any one of Claims 1-3,
The element driving thin film transistor and the driven element corresponding to each other directly or indirectly in a contact hole formed in an insulating layer separating the layer between the element driving thin film transistor and the driven element formed in a lower layer. The semiconductor is electrically connected, at least a contact hole region of the first electrode is covered with a planarization layer, and the light emitting element layer is formed on the first electrode and the planarization layer. apparatus. In the semiconductor device according to claim 1,
The driven device is an organic electroluminescence device using an organic compound in a light emitting layer.

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