JP5355843B2 - Plasma display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a plasma display device capable of increasing the number of display gradations. <P>SOLUTION: When driving a plasma display panel with display cells, where while being excited by irradiation with electron rays, a magnesium oxide layer containing magnesium oxide crystals which perform cathode luminescence having a peak in a wavelength region of 200 to 300 nm, is formed, writing address discharge is selectively made to occur in each sub-field of a first sub-field group, including a headmost sub-field in a unit display period and a display cell is set to a lighting on state. Next, deletion address discharge is selectively made to occur in only any one sub-field among the sub-field group following the first sub-field group, and thereby, the display cell which is set to the lighting on mode is changed to a lighting off mode. <P>COPYRIGHT: (C)2006,JPO&amp;NCIPI

Description

  The present invention relates to a plasma display device equipped with a plasma display panel.

  In the plasma display apparatus, one field (or one frame) in a video signal is composed of a plurality of subfields each including an address period and a sustain period, so that gradation display is performed. During the address period, each discharge cell corresponding to each pixel of the plasma display panel is selectively discharged based on the input video signal, so that a lighting mode state where wall charges exist and a light-off mode state where wall charges do not exist Set to one of the states. In the sustain period, only the discharge cells set in the lighting mode state are repeatedly subjected to the sustain discharge for the number of times corresponding to the weight of the subfield, and the light emission state associated with the discharge is maintained. A reset period for initializing the state of all discharge cells is provided immediately before the address period of each subfield. In the reset period, first, a write reset discharge for causing wall charges to be formed in all the discharge cells is generated, and then an erase reset discharge for erasing the wall charges formed in all the discharge cells is generated. By doing so, all the discharge cells are initialized to the extinguishing mode. However, the light emission associated with a series of these reset discharges is not related to the display image, and is also generated simultaneously in all discharge cells, so that the contrast of the display image, particularly an image representing a dark scene is being displayed. Dark contrast is reduced. In view of this, there has been proposed a driving method in which the number of reset discharges is reduced to one in one field (or one frame) display period to suppress a reduction in contrast (see, for example, Patent Document 1).

However, if the number of reset discharges is set to one, a discharge delay occurs in the various discharges in the subsequent address period and sustain period. Therefore, various drive pulse pulses applied to the plasma display panel to cause various discharges. It is necessary to widen the width. Therefore, since the address period and the sustain period become longer as the pulse width is increased, it is difficult to increase the number of display gradations by increasing the number of subfields.
JP 11-65517 A

  The present invention has been made to solve such a problem, and an object thereof is to provide a plasma display device capable of increasing the number of display gradations.

According to a first aspect of the present invention, there is provided a plasma display device comprising: a plurality of row electrode pairs; and a plurality of column electrodes arranged intersecting the row electrode pairs and forming display cells at the intersections. On the other hand, a plasma display apparatus that displays an image by configuring a unit display period in an input video signal by a plurality of subfields composed of an address period and a sustain period, and is excited by irradiation of an electron beam and has a wavelength range of 200 to 200. A magnesium oxide crystal that performs cathodoluminescence emission having a peak within 300 nm is formed to be exposed on the surface in contact with the discharge space on the dielectric layer covering the row electrode pair in each of the discharge cells. All by applying a magnesium oxide layer, a reset pulse between the row electrodes constituting the row electrode pair And reset means allowed to rise to reset discharge in the display cell in the address period, a pixel data pulse according to pixel data based on the video signal and applies a scan pulse to one row electrode of the row electrode pairs Address means for selectively generating an address discharge in each of the display cells by applying to the column electrode to set each display cell in one of a lighting mode and a lighting mode, and in the sustain period, Sustaining means for sustaining discharge of the display cell set in the lighting mode by applying a sustaining pulse between the row electrodes constituting the row electrode pair, and the resetting means includes a plurality of continuous units. Only before the first subfield of at least one unit display period in each display period Allowed rise to the reset discharge prior to the address period, the address means selectively write address in the address period of each subfield in the first subfield group including a first subfield in the unit display period The display cell is set to the lighting mode by causing discharge, and the erase address discharge is selectively caused only in one of the subfields in the subfield group subsequent to the first subfield group. The display cell that has been set to the lighting mode is shifted to the state of the extinguishing mode.

  In driving a plasma display panel including a display cell formed with a magnesium oxide layer including a magnesium oxide crystal that is excited by electron beam irradiation and emits cathodoluminescence emission having a peak in a wavelength range of 200 to 300 nm. In each subfield in the first subfield group including the first subfield in the unit display period, the write address discharge is selectively caused to set the display cell in the lighting mode, and the first subfield group includes By selectively causing erase address discharge only in any one subfield in the subsequent subfield group, the display cell set in the lighting mode is changed to the state of the extinguishing mode.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a diagram showing a schematic configuration of a plasma display device according to the present invention.

  As shown in FIG. 1, the plasma display device includes a PDP 50 as a plasma display panel, a row electrode X drive circuit 51, a row electrode Y drive circuit 53, a column electrode drive circuit 55, and a drive control circuit 56.

The PDP 50 includes column electrodes D _{1 to} D _m arranged to extend in the vertical direction (vertical direction) of the two-dimensional display screen, and row electrodes X ₁ to X _m arranged to extend in the horizontal direction (horizontal direction). X _n and row electrodes _Y 1 to Y _n are formed. In this case, row electrode pairs (X ₁ , Y ₁ ), (X ₂ , Y ₂ ), (X ₃ , Y ₃ ),..., (X _n , Y _n ) that are paired with each other adjacent to each other. Are responsible for the first display line to the nth display line in the PDP 50. Each intersection of each display line and the column electrodes D ₁ to D _m, respectively (region surrounded by one-dot chain line in FIG. 1), display cells PC serving as pixels are formed. That is, in the PDP 50, the display cells PC _{1,1 to} PC _{1, m} belonging to the first display line, the display cells PC _{2, 1 to} PC _{2, m} ,... Belonging to the second display line, the nth display. Each of the display cells PCn _{, 1 to} PCn _{, m} belonging to the line is arranged in a matrix.

  FIG. 2 is a front view schematically showing the internal structure of the PDP 50 as viewed from the display surface side.

In FIG. 2, the respective intersections of the column electrodes D _{1 to} D ₃ of the PDP 50, the first display line (Y ₁ , X ₁ ), and the second display line (Y ₂ , X ₂ ) are extracted and shown. Is. 3 is a view showing a cross section of the PDP 50 taken along the line V3-V3 in FIG. 2, and FIG. 4 is a view showing a cross section of the PDP 50 taken along the line W2-W2 in FIG.

As shown in FIG. 2, each row electrode X has a bus electrode Xb extending in the horizontal direction of the two-dimensional display screen and a T provided in contact with a position corresponding to each display cell PC on the bus electrode Xb. And a transparent electrode Xa having a letter shape. Each row electrode Y includes a bus electrode Yb extending in the horizontal direction of the two-dimensional display screen, and a T-shaped transparent electrode Ya provided in contact with a position corresponding to each display cell PC on the bus electrode Yb. Is composed of. The transparent electrodes Xa and Ya are made of a transparent conductive film such as ITO, and the bus electrodes Xb and Yb are made of a metal film, for example. As shown in FIG. 3, the row electrode X composed of the transparent electrode Xa and the bus electrode Xb and the row electrode Y composed of the transparent electrode Ya and the bus electrode Yb are arranged on the back side of the front transparent substrate 10 whose front side is the display surface of the PDP 50. Is formed. At this time, the transparent electrodes Xa and Ya in each row electrode pair (X, Y) extend to the paired row electrode side, and the top sides of the wide portions pass through the discharge gap g1 having a predetermined width. Facing each other. On the back side of the front transparent substrate 10, there is a two-dimensional space between a pair of row electrodes (X ₁ , Y ₁ ) and a row electrode pair (X ₂ , Y ₂ ) adjacent to the row electrode pair. A black or dark light absorbing layer (light shielding layer) 11 extending in the horizontal direction of the display screen is formed. Further, a dielectric layer 12 is formed on the back side of the front transparent substrate 10 so as to cover the row electrode pair (X, Y). As shown in FIG. 3, on the back side of the dielectric layer 12 (the surface opposite to the surface in contact with the row electrode pair), the light absorbing layer 11 and bus electrodes Xb and Yb adjacent to the light absorbing layer 11 are provided. A raised dielectric layer 12A is formed in a portion corresponding to the region where the and are formed. The surface of the dielectric layer 12 and the raised dielectric layer 12A includes a magnesium oxide crystal that is excited by electron beam irradiation and emits cathodoluminescence light having a peak in the wavelength range of 200 to 300 nm. A magnesium oxide layer 13 is formed.

  On the other hand, on the rear substrate 14 arranged in parallel with the front transparent substrate 10, each of the column electrodes D is disposed at a position facing the transparent electrodes Xa and Ya in each row electrode pair (X, Y). , Y). On the back substrate 14, a white column electrode protective layer 15 that covers the column electrode D is further formed. A partition wall 16 is formed on the column electrode protective layer 15. The partition wall 16 includes a horizontal wall 16A extending in the horizontal direction of the two-dimensional display screen at a position corresponding to the bus electrodes Xb and Yb of each row electrode pair (X, Y), and intermediate portions between the column electrodes D adjacent to each other. A ladder wall is formed by the vertical wall 16B extending in the vertical direction of the two-dimensional display screen at the position. A ladder-shaped partition wall 16 as shown in FIG. 2 is formed for each display line of the PDP 50, and a gap SL as shown in FIG. 2 exists between the partition walls 16 adjacent to each other. The ladder-shaped partition 16 partitions the display cell PC including the independent discharge space S and the transparent electrodes Xa and Ya. In the discharge space S, a discharge gas containing xenon gas is enclosed. A phosphor layer 17 is formed on the side surface of the horizontal wall 16A, the side surface of the vertical wall 16B, and the surface of the column electrode protection layer 15 in each display cell PC so as to cover all of these surfaces as shown in FIG. . The phosphor layer 17 is actually composed of three types: a phosphor that emits red light, a phosphor that emits green light, and a phosphor that emits blue light. As shown in FIG. 3, the magnesium oxide layer 13 is closed between the discharge space S and the gap SL of each display cell PC by contacting the horizontal wall 16A. On the other hand, as shown in FIG. 4, since the vertical wall 16B is not in contact with the magnesium oxide layer 13, there is a gap r1 therebetween. That is, the discharge spaces S of the display cells PC adjacent to each other in the horizontal direction of the two-dimensional display screen communicate with each other through the gap r1.

  Here, the magnesium oxide crystal forming the magnesium oxide layer 13 is a single crystal obtained by vapor phase oxidation of magnesium vapor generated by heating magnesium, for example, a wavelength region 200 excited by irradiation with an electron beam. It includes a vapor phase magnesium oxide crystal that performs CL emission having a peak within ˜300 nm (particularly, around 235 nm within 230 to 250 nm). This vapor phase magnesium oxide crystal has a multiple crystal structure in which cubic crystals as shown in the SEM photograph image of FIG. 5A are fitted to each other, or a cubic single crystal structure as shown in the SEM photograph image of FIG. 5B. , A magnesium single crystal having a particle size of 2000 angstroms or more is included. Such a magnesium single crystal is characterized by high purity and fine particles compared to magnesium oxide produced by other methods, and less aggregation of the particles, as will be described later. This contributes to the improvement of the discharge characteristics. In this example, a vapor phase magnesium oxide single crystal having an average particle size measured by the BET method of 500 angstroms or more, preferably 2000 angstroms or more is used. Then, the magnesium oxide layer 13 is formed by adhering such a magnesium oxide single crystal to the surface of the dielectric layer 12 as shown in FIG. 6 by spraying, electrostatic coating or the like. A thin film magnesium oxide layer is formed on the surfaces of the dielectric layer 12 and the raised dielectric layer 12A by vapor deposition or sputtering, and a magnesium oxide single crystal is deposited thereon to form a magnesium oxide layer 13. You may do it.

The row electrode X drive circuit 51 includes a reset pulse generation circuit and a sustain pulse generation circuit. The reset pulse generation circuit of the row electrode X drive circuit 51 generates a reset pulse (to be described later) for initializing each display cell PC of the PDP 50 and applies it to each of the row electrodes X _{1 to} X _n of the PDP 50. A sustain pulse generating circuit of the row electrode X drive circuit 51 generates a sustain pulse (described later) to cause each display cell PC set in a lighting mode (described later) to emit light, and this is generated by the row electrodes X _{1 to} X. _n applied to each.

The row electrode Y drive circuit 53 includes a reset pulse generation circuit, a scan pulse generation circuit, and a sustain pulse generation circuit. The reset pulse generation circuit of the row electrode Y drive circuit 53 generates a reset pulse (to be described later) for initializing each display cell PC of the PDP 50 and applies it to each of the row electrodes Y _{1 to} Y _n of the PDP 50. The scan pulse generation circuit of the row electrode Y drive circuit 53 scans each display cell PC for one display line (to be described later) to be set to a state (lighting mode or light-off mode) corresponding to the input video signal. ) generates, sequentially applies this to row electrodes _Y 1 to Y _n, respectively. A sustain pulse generating circuit of the row electrode Y drive circuit 53 generates a sustain pulse (described later) that should cause each display cell PC set in a lighting mode (described later) to emit light, and this is generated by the row electrodes Y _{1 to} Y. _n applied to each.

The column electrode drive circuit 55 generates a pixel data pulse having a voltage corresponding to a pixel drive data bit (described later) supplied from the drive control circuit 56, and outputs the pixel data pulse for each display line (m). applied to the electrode _D 1 to D _m.

The drive control circuit 56 first converts the input video signal into, for example, 8-bit pixel data representing the luminance level for each pixel, and performs error diffusion processing and dither processing on the pixel data. For example, in the error diffusion process, first, the upper 6 bits of pixel data are used as display data, and the remaining lower 2 bits are used as error data. Then, the weighted addition of each error data of the pixel data corresponding to each peripheral pixel is reflected in the display data. With this operation, the luminance for the lower 2 bits in the original pixel is expressed in a pseudo manner by the peripheral pixels, and therefore, the display data for 6 bits smaller than 8 bits is equivalent to the pixel data for 8 bits. Brightness gradation expression is possible. Then, dither processing is performed on the 6-bit error diffusion processing pixel data obtained by the error diffusion processing. In the dither processing, a plurality of adjacent pixels are set as one pixel unit, and dither coefficients each having a different coefficient value are allocated and added to the error diffusion processing pixel data corresponding to each pixel in the one pixel unit. To obtain dither-added pixel data. According to the addition of the dither coefficients, when viewed in units of one pixel, it is possible to express a luminance corresponding to 8 bits even with only the upper 4 bits of the dither addition pixel data. Therefore, the drive control circuit 56, 12 bit high-order 4 bits of the dither added pixel data as multi-gradation pixel data PD _S, made this the first through twelfth bits in accordance with data conversion table as shown in FIG. 9 To pixel drive data GD. Therefore, pixel data that can represent 256 gradations in 8 bits is converted into 12-bit pixel drive data GD consisting of 13 patterns in total, as shown in FIG. Next, the drive control circuit 56, one screen of pixel drive data GD _{1, 1} to GD _n, for each _m, the separation of these pixel drive data GD _{1, 1} to GD _{n, m} each at the same bit digit with each other By doing
DB1: First bit of each of the pixel drive data GD1 _{, 1 to} GDn _{, m}
DB2: Second bit of each of pixel drive data GD1 _{, 1 to} GDn _{, m}
DB3: The third bit of each of the pixel drive data GD1 _{, 1 to} GDn _{, m}
DB4: 4th bit of each of pixel drive data GD1 _{, 1 to} GDn _{, m}
DB5: 5th bit of each of pixel drive data GD1 _{, 1 to} GDn _{, m}
DB6: 6th bit of each of the pixel drive data GD1 _{, 1 to} GDn _{, m}
DB7: 7th bit of pixel drive data GD1 _{, 1 to} GDn _{, m}
DB8: 8th bit of each of pixel drive data GD1 _{, 1 to} GDn _{, m}
DB9: 9th bit of each of the pixel drive data GD1 _{, 1 to} GDn _{, m}
DB10: 10th bit of each of the pixel drive data GD1 _{, 1 to} GDn _{, m}
DB 11: pixel drive data GD _{1, 1} to GD _n, 11th bit of _m each
DB12: Pixel drive data bit groups DB1 to DB12 such as the 12th bit of the pixel drive data GD1 _{, 1 to} GDn _{, m} are obtained.

  Each of the pixel drive data bit groups DB1 to DB12 corresponds to each of subfields SF1 to SF12 described later. For each subfield, the drive control circuit 56 supplies the pixel drive data bit group DB corresponding to the subfield to the column electrode drive circuit 55 by one display line (m).

  Further, the drive control circuit 56 supplies various control signals for driving the PDP 50 in accordance with a light emission drive sequence employing a subfield method (subframe method) as shown in FIG. 7, the row electrode X drive circuit 51, and the row electrode Y drive circuit 53. , And the column electrode drive circuit 55. In the light emission drive sequence shown in FIG. 7, in the first subfield SF1 in each of the twelve subfields SF1 to SF12 in the unit display period (one field or one frame display period), the reset process R and the address process are performed. Wa and sustain process I are sequentially executed. In each of the subfields SF2 to SF12, the address process Wb and the sustain process I are sequentially executed.

  FIG. 8 is a diagram showing application timings of various drive pulses applied to the column electrodes D and the row electrodes X and Y of the PDP 50 by extracting SF1 and SF2 from the subfields SF1 to SF12.

First, in the reset step R of the subfield SF1, the row electrode Y drive circuit 53 causes the voltage on the row electrode Y to gradually rise with time to reach the positive peak voltage value Vry as shown in FIG. a leading edge that, thereafter, simultaneously applies the reset pulse RP _Y to gently and a rear edge reaching to the voltage value dropped to negative voltage value Vsel to the row electrodes Y ₁ to Y _n. The voltage value Vsel includes the voltage value on the row electrode Y when a negative-polarity scanning pulse (described later) is applied, and the voltage on the row electrode Y when no voltage is applied. The voltage between the values. The peak voltage value Vry is a voltage value larger than the voltage Vsus on the row electrode Y when a sustain pulse described later is applied. The row electrode X drive circuit 51 applies a reset pulse RP _X having a negative voltage as shown in FIG. 8 to the row electrodes X _{1 to} X _n over a period in which the reset pulse RP _Y has a positive voltage. . While the reset pulse RP _X is applied with the reset pulse RP _Y, all the display cells PC _{1, 1} to PC n, weak write reset discharge between the row electrodes X and Y in the _m each is induced. After the end of the write reset discharge, a predetermined amount of wall charges is formed on the surface of the magnesium oxide layer 13 in the discharge space S of each display cell PC. That is, a positive charge is formed in the vicinity of the row electrode X on the surface of the magnesium oxide layer 13, and a negative charge is formed in the vicinity of the row electrode Y. Become. Thereafter, when the voltage of the reset pulse RP _Y go slowly drops from the peak voltage value, during which all the display cells PC _{1, 1} to PC n, weak erasure reset between the row electrodes X and Y in the _m each Discharge occurs. Due to the erase reset discharge, the wall charges formed in all of the display cells PC _{1,1 to} PC _{n, m} disappear. That is, in the reset process R, all of the display cells PC _{1,1 to} PC _{n, m} are initialized to a so-called extinguishing mode in which the amount of wall charges does not reach a predetermined amount.

In the address process Wa of the subfield SF1, the column electrode drive circuit 55 generates a pixel data pulse having a voltage corresponding to the pixel drive data bit. For example, the column electrode driving circuit 55 generates a pixel data pulse having a positive high voltage when a pixel driving data bit having a logic level 1 for setting the display cell PC to the lighting mode is supplied, while turning off the light. When a pixel drive data bit having a logic level 0 to be set to the mode is supplied, a low voltage pixel data pulse is generated. Then, the column electrode driving circuit 55 sequentially applies the pixel data pulses for one display line (m) as the pixel data pulse groups DP ₁ , DP ₂ ,..., DP _n in order of the column electrodes D _{1 to} D _m. Apply to. During this time, the row electrode Y drive circuit 53 sequentially applies negative scan pulses SP as shown in FIG. 8 to the row electrodes Y _{1 to} Y _n in synchronization with the timings of the pixel data pulse groups DP _{1 to} DP _n . Go. At this time, the write address discharge is selectively generated only in the display cell PC to which the scan pulse SP is applied and the high-voltage pixel data pulse is applied, and the magnesium oxide layer 13 in the discharge space S of the display cell PC. A predetermined amount of wall charges are formed on the surface of each of the phosphor layers 17. On the other hand, since the write address discharge as described above is not generated in the display cell PC to which the low-voltage pixel data pulse is applied although the scan pulse SP is applied, the wall charge formation state until just before is maintained. . That is, according to the address process Wa, each display cell PC is set to either a lighting mode state where a predetermined amount of wall charges exists or a light-off mode state where the amount of wall charges does not reach a predetermined amount. .

In the address process Wb of each of the subfields SF2 to SF12, the column electrode drive circuit 55 has a high positive polarity when the pixel drive data bit of the logic level 1 that should set the display cell PC to the light-off mode is supplied. While a pixel data pulse having a voltage is generated, a pixel data pulse having a low voltage is generated when a pixel driving data bit having a logic level 0 is supplied. Then, the column electrode driving circuit 55 sequentially applies the pixel data pulses for one display line (m) as the pixel data pulse groups DP ₁ , DP ₂ ,..., DP _n in order of the column electrodes D _{1 to} D _m. Apply to. During this time, the row electrode Y drive circuit 53 sequentially applies negative scan pulses SP as shown in FIG. 8 to the row electrodes Y _{1 to} Y _n in synchronization with the timings of the pixel data pulse groups DP _{1 to} DP _n . Go. At this time, an erasing address discharge is generated in the display cell PC to which the scanning pulse SP and the high-voltage pixel data pulse DP are simultaneously applied. After the erase address discharge, the wall charges formed in the display cell PC are erased, and the display cell PC is set to the extinguishing mode. On the other hand, since the erase address discharge as described above is not generated in the display cell PC to which the low-voltage pixel data pulse is applied, the wall charge formation state until immediately before is maintained. Therefore, the display cell PC set in the lighting mode maintains the state of the lighting mode and the display cell PC set in the non-lighting mode maintains the state of the light-off mode. In the sustain process I of each of the subfields SF1 to SF12, each of the circuits 51 and the row electrode Y driving circuit 53, alternately applying sustain pulses IP _X and IP _Y to the row electrodes X ₁ to X _n and Y ₁ to Y _n with a positive voltage Vsus as shown in FIG. 8 To do. Incidentally, the number of times of applying the sustain pulses IP _X and IP _Y in each sub-field is dependent on the luminance weighting of the subfield. Each time the sustain pulses IP _X and IP _Y are applied, only the display cell PC set in the lighting mode is sustain-discharged, and the phosphor layer 17 emits light along with this discharge to form an image on the panel surface. Is done.

  The drive shown in FIGS. 7 and 8 as described above is executed based on the 13 types of pixel drive data GD as shown in FIG. According to such driving, except when the luminance level 0 is expressed (first gradation), the write address discharge is generated in each display cell PC in the address process Wa of the first subfield SF1 (double circle). This display cell PC is set to the lighting mode. Thereafter, an erasure address discharge is generated only in the address process Wb of one subfield of each of the subfields SF2 to SF12 (indicated by a black circle), and the display cell PC is set to the extinguishing mode. That is, each display cell PC is set to the lighting mode in each of the continuous subfields corresponding to the intermediate luminance to be expressed, and the light emission associated with the sustain discharge is repeated for the number of times assigned to each of these subfields. Occur (indicated by white circles). At this time, the luminance corresponding to the total number of light emission associated with the sustain discharge generated in one field is visually recognized. Therefore, according to the 13 types of light emission patterns by the 1st to 13th gradation driving as shown in FIG. 9, the middle of 13 gradations corresponding to the total number of sustain discharges generated in each of the subfields indicated by white circles. Luminance is expressed.

  Here, as described above, the vapor-phase magnesium oxide single crystal contained in the magnesium oxide layer 13 formed in each display cell PC is excited by electron beam irradiation and has a wavelength region as shown in FIG. CL light emission having a peak within 200 to 300 nm (particularly, around 235 nm within 230 to 250 nm) is performed. At this time, as shown in FIG. 11, the peak intensity of CL emission increases as the particle diameter of the vapor-phase-process magnesium oxide crystal increases. That is, when forming a vapor phase magnesium oxide crystal, if the magnesium is heated at a temperature higher than usual, the particle size 2000 as shown in FIG. 5A or FIG. A relatively large single crystal of angstroms or more is formed. At this time, since the temperature at which magnesium is heated is higher than usual, the length of the flame in which magnesium and oxygen react with each other also becomes longer. Therefore, the temperature difference between the flame and the surroundings becomes large, and therefore, the group of vapor-phase magnesium oxide single crystals having a large particle size has a higher energy level corresponding to 200 to 300 nm (especially around 235 nm). It is presumed that many single crystals are contained.

  FIG. 12 shows a discharge probability when a magnesium oxide layer is not provided in the display cell PC, a discharge probability when a magnesium oxide layer is constructed by a conventional vapor deposition method, and 200 to 300 nm (particularly 230 to 250 nm) by electron beam irradiation. It is a figure which shows the discharge probability in each case when the magnesium oxide layer containing the gaseous-phase magnesium oxide single crystal which produces CL light emission which has a peak in the vicinity of 235 nm is provided. In FIG. 12, the horizontal axis represents the discharge pause time, that is, the time interval from when a discharge is generated until the next discharge is generated.

  Thus, the oxidation including the vapor-phase magnesium oxide single crystal that emits CL light having a peak at 200 to 300 nm (particularly around 235 nm within 230 to 250 nm) by the electron beam irradiation in the discharge space S of each discharge cell PC. When the magnesium layer 13 is formed, the discharge probability is increased as compared with the case where the magnesium oxide layer is formed by a conventional vapor deposition method. As the above-mentioned vapor-phase magnesium oxide single crystal, as shown in FIG. 13, as the intensity of CL emission having a peak particularly at 235 nm when irradiated with an electron beam increases, it is generated in the discharge space S. The discharge delay can be shortened.

As described above, the probability of discharge in the discharge space S is increased by providing the magnesium oxide layer 13 including a vapor-phase magnesium oxide single crystal in each display cell PC. Thus, to achieve contrast improvement, also be weakened gently on to reset discharge to a voltage transition of the reset pulse RP _Y applied to the row electrodes Y as shown in FIG. 8, in a short time the weak reset discharge It is possible to make it occur stably. In particular, each display cell PC employs a structure in which a discharge is locally generated in the vicinity of the discharge gap between the T-shaped transparent electrodes Xa and Ya. Reset discharge is suppressed and strong erroneous discharge between the column electrode and the row electrode is also prevented.

  In addition, since the discharge probability in each display cell PC is increased, the priming effect by the reset discharge is sustained for a long time. As a result, the reset process R is executed once every one field (or one frame) display period as shown in FIG. 7 or once in a display period of a plurality of fields (or multiple frames) as shown in FIG. It is possible to stably generate the address discharge in the address process (Wa, Wb) of each subfield only by doing. In short, it is only necessary to cause the reset discharge at least once every a plurality of consecutive unit display periods.

Further, since the priming effect by the reset discharge lasts for a long time, the address discharge and the sustain discharge generated in the sustain process I are accelerated. As a result, the pulse width of each of the pixel data pulse DP and the scan pulse SP as shown in FIG. 8 to be applied to the column electrode D and the row electrode Y in order to cause the address discharge can be shortened. Thus, it is possible to reduce the processing time spent in the address process W. Further, it becomes possible to shorten the pulse width of such sustain pulse IP _Y shown in FIG. 8 to be applied to the row electrode Y in order to generate sustain discharge, correspondingly, reduce processing time spent on the sustain process I It becomes possible to make it.

  Therefore, it is possible to increase the number of subfields to be provided in the unit display period (one field or one frame display period) by the amount of reduction in the processing time spent in each of the address process W and the sustain process I. The number of gradations can be increased.

  In the above embodiment, each of the subfields SF2 to SF12 executes the address process Wb that causes the erase address discharge, and the first subfield SF1 executes the address process Wa that causes the write address discharge. Yes. However, the address process Wa may be executed in place of the address process Wb in other subfields other than the first subfield SF1. For example, the address process Wa is executed in each of the subfields SF1 and SF2, and the address process Wb is executed in each of the subfields SF3 to SF12, and driving according to 13 types of light emission patterns as shown in FIG. 15 is performed. In other words, in the second gradation drive that represents one level higher than the luminance level 0, the write address discharge is generated in the address process Wa of the subfield SF2, and the display cell PC is set to the lighting mode. In the address process Wb of the subfield SF3, the erase address discharge is caused to set the display cell PC to the extinguishing mode.

  In short, a drive sequence in which an address process Wa causing an erasure address discharge and an address process Wb causing a write address discharge are mixed in a unit display period is employed. At this time, for example, according to the driving sequence of only the address process Wa, the write discharge must be generated in order to form the wall charge in each subfield, so that the speed is higher than the erase address discharge for erasing the wall charge. It becomes difficult. On the other hand, according to the driving sequence of only the address process Wb, a reset discharge accompanied by a relatively strong light emission must be generated in advance in order to form wall charges in all the display cells. This reset discharge must be generated for all display cells. Therefore, the contrast is lowered as compared with the case where the driving sequence of only the address process Wa is adopted. Therefore, in the drive shown in FIG. 9 or FIG. 15, write address discharge is generated (indicated by white circles) in all the display cells PC in the first subfield SF1 (or SF2) except when black display is performed. Then, all display cells PC are initialized to the lighting mode, and thereafter, the erase address discharge is caused (indicated by black circles) to make the transition to the extinguishing mode. That is, by adopting a drive sequence in which an address process Wa causing an erase address discharge and an address process Wb causing a write address discharge are mixed in a unit display period, the contrast is improved and the address operation is speeded up. This is to achieve both.

In addition, as the PDP 50 in the above embodiment, row electrode pairs (X ₁ , Y ₁ ), (X ₂ , Y ₂ ), (X ₃ , Y ₃ ),..., (X _n , Y _n ) A structure in which the display cell PC is formed between the row electrode X and the row electrode Y that are paired with each other is adopted, but a structure in which the display cell PC is formed between all the adjacent row electrodes is adopted. May be. In short, between the row electrodes X ₁ and Y ₁ , between the row electrodes Y ₁ and X _2, between the row electrodes X ₂ and Y ₂ ,..., Between the row electrodes Y _n−1 and X _n , the row electrode X between _n and Y _n, it is also good to adopt the respective display cell PC is formed structures.

  The PDP 50 in the above embodiment employs a structure in which the row electrodes X and Y are formed on the front transparent substrate 10 and the column electrode D and the phosphor layer 17 are formed on the rear substrate 14. Alternatively, a structure in which the row electrodes X and Y are formed together with the column electrodes D and the phosphor layer 17 is formed on the back substrate 14 may be adopted.

It is a figure which shows schematic structure of the plasma display apparatus by this invention. It is a front view which shows typically the internal structure at the time of seeing PDP5 mounted in the plasma display apparatus of FIG. 1 from the display surface side. It is a figure which shows the cross section on the V3-V3 line | wire shown by FIG. It is a figure which shows the cross section on the W2-W2 line | wire shown by FIG. It is a figure which shows the magnesium oxide crystal | crystallization which has a cubic multiple crystal structure. It is a figure which shows the magnesium oxide single crystal which has a cubic single crystal structure. It is a figure which shows the form at the time of making a magnesium oxide single crystal powder adhere to the surface of a dielectric material layer and a raising dielectric material layer, and forming a magnesium oxide layer. It is a figure which shows an example of the light emission drive sequence employ | adopted in the plasma display apparatus shown by FIG. It is a figure which shows the various drive pulses applied to PDP according to the light emission drive sequence shown in FIG. 7, and its application timing. It is a figure which shows the light emission drive pattern based on the conversion table of pixel data, and the pixel drive data GD obtained by this pixel data conversion table. It is a graph which shows the relationship between the particle size of magnesium oxide single crystal powder, and the wavelength of CL light emission. It is a graph which shows the relationship between the particle size of magnesium oxide single crystal powder, and the intensity | strength of CL light emission of 235 nm. It is a figure which respectively shows the discharge probability when a magnesium oxide layer is not provided in the display cell, the discharge probability when a magnesium oxide layer is constructed by a conventional vapor deposition method, and the discharge probability when a vapor phase magnesium oxide layer is constructed. . It is a figure which shows the correspondence of CL light emission intensity of a 235 nm peak, and discharge delay time. It is a figure which shows another example of the light emission drive sequence employ | adopted in the plasma display apparatus shown by FIG. It is a figure which shows another example of the light emission drive sequence employ | adopted in the plasma display apparatus shown by FIG.

Explanation of symbols

13 Magnesium oxide layer 50 PDP
51 row electrode X drive circuit 53 row electrode Y drive circuit 55 column electrode drive circuit 56 drive control circuit

Claims (9)

A unit display period in an input video signal is addressed to a plasma display panel comprising a plurality of row electrode pairs and a plurality of column electrodes arranged across the row electrode pairs and forming display cells at each intersection. A plasma display device configured to display an image with a plurality of subfields each having a period and a sustain period,
The discharge space on the dielectric layer covering the row electrode pair in each of the discharge cells is a magnesium oxide crystal that is excited by electron beam irradiation and emits cathodoluminescence having a peak in a wavelength range of 200 to 300 nm. A magnesium oxide layer formed exposed on the surface in contact with
Reset means for causing a reset discharge in all the display cells by applying a reset pulse between the row electrodes constituting the row electrode pair;
In the address period, a scan pulse is applied to one row electrode of the row electrode pair, and a pixel data pulse corresponding to pixel data based on the video signal is applied to the column electrode to selectively apply to each display cell. Addressing means for causing address discharge to set each display cell in one of the lighting mode and the extinguishing mode;
Sustaining means for sustaining discharge of the display cell set in the lighting mode by applying a sustain pulse between the row electrodes constituting the row electrode pair in the sustain period;
The reset means generates the reset discharge prior to the address period only in the first subfield of at least one unit display period in each of the plurality of consecutive unit display periods.
The address means selectively causes a write address discharge in the address period of each subfield in the first subfield group including the first subfield in the unit display period to turn on the display cell. The display cell that has been set to the lighting mode by selectively generating an erase address discharge only in any one subfield in the subfield group subsequent to the first subfield group. A plasma display device, wherein a transition to the extinguishing mode is made. 2. The plasma display device according to claim 1 , wherein the reset discharge includes a write discharge for all display cells and an erasure discharge generated immediately after the write discharge . Said row electrode pair row electrodes each constituting a is claim 1, comprising a body portion extending in the row direction, the protrusion protruding in the column direction from the main body portion so as to face each other through a discharge gap The plasma display device described. 4. The plasma display device according to claim 3, wherein the protruding portion of the row electrode has a wide portion near the discharge gap and a narrow portion connecting the wide portion and the main body . The magnesium oxide crystals is, the plasma display apparatus according to claim 1, characterized in that it comprises a single crystal having a particle diameter of 2000 or more angstroms. The plasma display device according to claim 1, wherein the magnesium oxide crystal includes a magnesium oxide single crystal generated by vapor phase oxidation of magnesium vapor generated when magnesium is heated. . 2. The plasma display device according to claim 1, wherein the magnesium oxide crystal emits cathodoluminescence light having a peak in a wavelength range of 230 to 250 nm . The reset pulse has a leading edge that gradually increases with time and reaches a predetermined first voltage value, and a voltage that gradually decreases with time and reaches a predetermined second voltage value. The plasma display device according to claim 1 , further comprising an edge portion . 9. The plasma display apparatus according to claim 8, wherein the first voltage value is larger than a voltage value on the row electrode when the sustain pulse is applied .