JP2006251337A - Method for driving plasma display panel - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for driving a plasma display panel by which an abnormal sound due to vibration of the plasma display panel itself can be removed. <P>SOLUTION: A cycle of subfields is shortened by shortening an address period for transferring each of discharge cells from a state of a lighting mode to a state of a light out mode according to pieces of pixel data by every pixel based on an input video signal in comparison with the case that an average value of luminance levels indicated by the input video signal is larger than a predetermined value when the average value is smaller. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a method for driving a matrix display type plasma display panel (hereinafter referred to as PDP).

  At present, as a thin image display device, a plasma display device on which an AC type (AC discharge type) plasma display panel is mounted has been commercialized (see, for example, FIG. 2 of Patent Document 1).

A PDP 10 as a plasma display panel mounted on such a plasma display device includes column electrodes D _{1 to} D _m as address electrodes, and row electrodes X _{1 to} X _n arranged orthogonal to the column electrodes, and Row electrodes Y _{1 to} Y _n are provided. The PDP 10 has a structure in which a discharge cell corresponding to a pixel is formed at each intersection of a pair of row electrodes X and Y adjacent to each other and a column electrode.

  In this plasma display device, gradation display using the subfield method is performed on the PDP 10 to display an image corresponding to an input video signal (see, for example, FIGS. 3 to 5 of Patent Document 1). That is, in each of the 14 subfields SF1 to SF14 for each one field display period, a pixel data writing process Wc for setting each discharge cell to one of the lighting mode and the extinguishing mode based on the input video signal. Then, the sustain light emission process Ic in which only the discharge cells set in the lighting mode are repeatedly discharged and emitted is performed. Further, the reset process Ic for initializing the states of all the discharge cells is executed only in the first subfield. In the reset process Ic, all discharge cells are initialized to the lighting mode by causing reset discharges to occur in all the discharge cells at once and forming a desired amount of wall charges in each discharge cell. .

  Further, in the pixel data writing step Wc, in order to set each discharge cell to either the lighting mode or the extinguishing mode based on the input video signal, the negative scanning pulse is sequentially applied to each of the row electrodes, and the extinction is performed. A high voltage is applied to the column electrode to which the discharge cell to be set in the mode belongs, and a low voltage pixel data pulse is applied to the column electrode to which the discharge cell to be set in the lighting mode belongs. As a result, only a discharge cell to which a high-voltage pixel data pulse is applied causes a discharge (selective erasure discharge) between the column electrode and the row electrode in the discharge cell. By this selective erasing discharge, wall charges existing in the discharge cell are erased, and the discharge cell is set to the extinguishing mode. On the other hand, since the discharge as described above is not generated in the discharge cell to which the low-voltage pixel data pulse is applied, the state immediately before that is maintained. That is, the discharge cell in which the desired amount of wall charges remains is maintained in the lighting mode and the discharge cell extinction mode in which the wall charge amount is not in the desired amount.

  Here, by causing the selective erasure discharge only in one of the subfields within one field display period, the sustain light emission process of each subfield until the selective erasure discharge is generated. The discharge light emission is continuously performed at Ic, and the luminance corresponding to the total number of the discharge light emission is visually recognized (see, for example, FIG. 5 of Patent Document 1).

  However, in order to set the discharge cell to the extinguishing mode in the pixel data writing process Wc, the selective erasure discharge may not be correctly generated even when a high voltage pixel data pulse is applied to the column electrode to which the discharge cell belongs. It was.

  Therefore, for the discharge cells to be set to the extinguishment mode, the pixel data pulse that causes the selective erasing discharge is repeatedly applied in the pixel data writing process Wc of each successive subfield, whereby the selective erasing discharge opportunity. A driving method has been proposed in which the discharge is surely generated (see, for example, FIG. 29 of Patent Document 1).

However, when a pixel data pulse to cause selective erasure discharge is periodically applied to the column electrode in each of the continuous subfields, depending on the period of each subfield, the rear substrate on which the column electrode is formed (FIG. (Not shown) and a front transparent substrate (not shown) on which row electrodes are formed may vibrate. At this time, there was a problem that an annoying abnormal sound was generated due to the vibration of the front transparent substrate and the rear substrate.
JP 2000-231362 A

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a method for driving a plasma display panel that can remove abnormal noise caused by vibration of the plasma display panel itself. .

  2. The plasma display panel driving method according to claim 1, wherein a discharge cell corresponding to a pixel is formed at each intersection of a plurality of row electrode pairs and a plurality of column electrodes extending in a direction crossing each of the row electrode pairs. A method of driving a plasma display panel in which gradation is driven in N (N is an integer of 2 or more) subfields for each unit display period, wherein each of the subfields is an input An address period for transitioning each of the discharge cells from a lighting mode state to a non-lighting mode state according to pixel data for each pixel based on a video signal, and the discharge set in the lighting mode immediately after the address period A sustain period in which only the cell is repeatedly subjected to a sustain discharge, and the average value of the luminance level indicated by the input video signal is a predetermined value. Shortening the period of the subfield by shortening the address period in comparison with the case of large become if also small.

  The method of driving a plasma display panel according to claim 10 further comprises a discharge cell corresponding to a pixel at each intersection of a plurality of row electrode pairs and a plurality of column electrodes extending in a direction intersecting each of the row electrode pairs. Is a plasma display panel driving method in which gradation is driven in N (N is an integer of 2 or more) subfields for each unit display period, and each of the subfields includes: An address period in which each of the discharge cells is changed from a light-off mode state to a light-on mode state according to pixel data for each pixel based on an input video signal, and the light-on mode is set immediately after the address period. A sustain period in which only the discharge cells are repeatedly sustained, and the average value of the luminance level indicated by the input video signal is predetermined. Shortening the period of the subfield by shortening the address period in comparison with the case made small in the case where it becomes greater than.

  The plasma display panel driving method according to claim 12 is a discharge cell corresponding to a pixel at each intersection of a plurality of row electrode pairs and a plurality of column electrodes extending in a direction intersecting each of the row electrode pairs. A plasma display panel driving method in which gradation is driven in N (N is an integer of 2 or more) subfields for each unit display period, wherein each of the subfields is An address period for transitioning each of the discharge cells from the lighting mode state to the extinguishing mode state or from the extinguishing mode state to the lighting mode state according to pixel data for each pixel based on the input video signal; A sustain period for repeatedly sustaining only the discharge cells set to the lighting mode immediately after the address period, Serial subfields each cycle is less than 66Myusec.

  The average period of the luminance level indicated by the input video signal is lower than a predetermined value during the address period in which each discharge cell is changed from the lighting mode state to the extinguishing mode state according to the pixel data for each pixel based on the input video signal. When it is smaller, the period of the subfield is shortened by making it shorter than when it is larger.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 is a diagram showing a schematic configuration of a plasma display apparatus that drives a plasma display panel (hereinafter referred to as a PDP) to emit light based on a driving method according to the present invention.

In FIG. 1, a PDP 10 as a plasma display panel extends column electrodes D _{1 to} D _m arranged in the vertical direction (vertical direction) of the two-dimensional display screen and extends in the horizontal direction (horizontal direction). Arranged row electrodes X _{1 to} X _n and row electrodes Y _{1 to} Y _n are formed. Note that one display line of the PDP 10 is displayed by a pair of row electrodes X and Y adjacent to each other. A discharge space filled with a discharge gas is provided between the row electrodes X _{1 to} X _n and Y _{1 to} Y _n and the column electrodes D _{1 to} D _m. A discharge cell corresponding to the pixel is formed at each intersection with the column electrode.

  FIG. 2 is a front view schematically showing the internal structure of the PDP 10 as viewed from the display surface side.

In FIG. 2, the crossing portions of each of the column electrodes D _{1 to} D ₃ of the PDP 10 and the first display line (Y ₁ , X ₁ ) and the second display line (Y ₂ , X ₂ ) are extracted and shown. Is. 3 is a view showing a cross section of the PDP 10 taken along the line V3-V3 in FIG. 2, and FIG. 4 is a view showing a cross section of the PDP 10 taken along the line W2-W2 in FIG.

As shown in FIG. 2, each row electrode X has a bus electrode Xb extending in the horizontal direction of the two-dimensional display screen and a T provided in contact with a position corresponding to each discharge cell PC on the bus electrode Xb. And a transparent electrode Xa having a letter shape. Each row electrode Y includes a bus electrode Yb extending in the horizontal direction of the two-dimensional display screen, and a T-shaped transparent electrode Ya provided in contact with a position corresponding to each discharge cell PC on the bus electrode Yb. Is composed of. The transparent electrodes Xa and Ya are made of a transparent conductive film such as ITO, and the bus electrodes Xb and Yb are made of a metal film, for example. As shown in FIG. 3, the row electrode X composed of the transparent electrode Xa and the bus electrode Xb and the row electrode Y composed of the transparent electrode Ya and the bus electrode Yb are arranged on the back side of the front transparent substrate 10 whose front side is the display surface of the PDP 10. Is formed. At this time, the transparent electrodes Xa and Ya in each row electrode pair (X, Y) extend to the paired row electrode side, and the top sides of the wide portions pass through the discharge gap g1 having a predetermined width. Facing each other. On the back side of the front transparent substrate 10, there is a two-dimensional space between a pair of row electrodes (X ₁ , Y ₁ ) and a row electrode pair (X ₂ , Y ₂ ) adjacent to the row electrode pair. A black or dark light absorbing layer (light shielding layer) 11 extending in the horizontal direction of the display screen is formed. Further, a dielectric layer 12 is formed on the back side of the front transparent substrate 10 so as to cover the row electrode pair (X, Y). As shown in FIG. 3, on the back side of the dielectric layer 12 (the surface opposite to the surface in contact with the row electrode pair), the light absorbing layer 11 and bus electrodes Xb and Yb adjacent to the light absorbing layer 11 are provided. A raised dielectric layer 12A is formed in a portion corresponding to the region where the and are formed. The surface of the dielectric layer 12 and the raised dielectric layer 12A includes a magnesium oxide crystal that is excited by electron beam irradiation and emits cathodoluminescence light having a peak in the wavelength range of 200 to 300 nm. A magnesium oxide layer 13 is formed.

  On the other hand, on the rear substrate 14 arranged in parallel with the front transparent substrate 10, each of the column electrodes D is disposed at a position facing the transparent electrodes Xa and Ya in each row electrode pair (X, Y). , Y). On the back substrate 14, a white column electrode protective layer 15 that covers the column electrode D is further formed. A partition wall 16 is formed on the column electrode protective layer 15. The partition wall 16 includes a horizontal wall 16A extending in the horizontal direction of the two-dimensional display screen at a position corresponding to the bus electrodes Xb and Yb of each row electrode pair (X, Y), and intermediate portions between the column electrodes D adjacent to each other. A ladder wall is formed by the vertical wall 16B extending in the vertical direction of the two-dimensional display screen at the position. A ladder-shaped partition wall 16 as shown in FIG. 2 is formed for each display line of the PDP 10, and a gap SL as shown in FIG. 2 exists between the partition walls 16 adjacent to each other. Further, the ladder-shaped partition 16 partitions the discharge cell PC including the independent discharge space S and the transparent electrodes Xa and Ya. In the discharge space S, a discharge gas containing xenon gas is enclosed. A phosphor layer 17 is formed on the side surface of the horizontal wall 16A, the side surface of the vertical wall 16B, and the surface of the column electrode protection layer 15 in each discharge cell PC so as to cover all of these surfaces as shown in FIG. . The phosphor layer 17 is actually composed of three types: a phosphor that emits red light, a phosphor that emits green light, and a phosphor that emits blue light. As shown in FIG. 3, the magnesium oxide layer 13 is closed between the discharge space S and the gap SL of each discharge cell PC by contacting the lateral wall 16A. On the other hand, as shown in FIG. 4, since the vertical wall 16B is not in contact with the magnesium oxide layer 13, a gap r1 exists between them. That is, the discharge spaces S of the discharge cells PC adjacent to each other in the horizontal direction of the two-dimensional display screen communicate with each other through the gap r1.

  The A / D converter 1 samples an analog input video signal, converts it to, for example, 8-bit pixel data PD corresponding to each pixel, and converts this to the average luminance calculation circuit 2 and the pixel drive data generation circuit 3. Supply to each.

  Based on the pixel data PD, the average luminance calculation circuit 2 calculates an average luminance level for each image frame (or one field) based on the input video signal, and drives and controls an average luminance signal APL indicating the average luminance level. Supply to circuit 4.

  The pixel drive data generation circuit 3 performs a multi-gradation process on the pixel data PD, and then sets each discharge cell of the PDP 10 to either the lighting mode or the non-lighting mode for each subfield. Is converted to pixel drive data GD and supplied to the memory 5.

  FIG. 5 is a diagram illustrating an example of the internal configuration of the pixel drive data generation circuit 3.

In FIG. 5, the multi-gradation processing circuit 31 performs error diffusion processing and dither processing on 8-bit pixel data PD. For example, in the error diffusion process, first, the upper 6 bits of the pixel data PD are regarded as display data, and the remaining lower 2 bits are regarded as error data. Then, the weighted addition of each error data of the pixel data PD corresponding to each peripheral pixel is reflected in the display data. With this operation, the luminance for the lower 2 bits in the original pixel is expressed in a pseudo manner by the peripheral pixels, and therefore, the display data for 6 bits smaller than 8 bits is equivalent to the pixel data for 8 bits. Brightness gradation expression is possible. Then, dither processing is performed on the 6-bit error diffusion processing pixel data obtained by the error diffusion processing. In the dither processing, a plurality of adjacent pixels are set as one pixel unit, and dither coefficients each having a different coefficient value are allocated and added to the error diffusion processing pixel data corresponding to each pixel in the one pixel unit. To obtain dither-added pixel data. According to the addition of the dither coefficients, when viewed in units of one pixel, it is possible to express a luminance corresponding to 8 bits even with only the upper 4 bits of the dither addition pixel data. Therefore, the multi-gradation processing circuit 31 supplies the upper 4 bits of the dither addition pixel data to the data conversion circuit 32 as the multi-gradation pixel data PD _S.

Data conversion circuit 32 converts the multi-gradation pixel data PD _S to 14-bit pixel drive data GD according to a data conversion table shown in FIG. The first to fourteenth bits of the pixel drive data GD correspond to subfields SF1 to SF14, which will be described later, respectively.

The memory 5 sequentially writes the pixel drive data GD in accordance with the write signal supplied from the drive control circuit 4. Then, one screen, the pixel drive data GD ₁₁ words corresponding to the pixels of the first row and the first column, up to the pixel driving data GD _nm corresponding to pixels of the n row and m-th column (n × m) When the writing of the pixel drive data GD is completed, the memory 5 performs the following read operation.

First, in the memory 5, pixel drive data GD _{(1,1) to} GD _{(n, m)} written for one screen is divided into pixel bits for each bit digit (1st bit to 14th bit). It is considered as data bits DB1 to DB14. Then, the memory 5 reads the pixel drive data bits DB1 _{(1,1) to} DB1 _{(n, m)} for each display line and supplies them to the address driver 6 in the address process W of the subfield SF1 described later. Further, in the address process W of the subfield SF2, which will be described later, the memory 5 reads the pixel drive data bits DB2 _{(1,1) to} DB2 _{(n, m)} by one display line and supplies them to the address driver 6. Similarly, the memory 5 reads out the pixel drive data bits DB3 to DB14 for one display line and supplies them to the address driver 6 in each address process W of subfields SF3 to SF14 described later.

  The drive control circuit 4 generates a clock signal to be supplied to the A / D converter 1 and a write and read signal to be supplied to the memory 5 in synchronization with the horizontal and vertical synchronization signals in the input video signal. To do. Further, the drive control circuit 4 supplies various timing signals for grayscale driving the PDP 10 according to the light emission drive sequence as shown in FIG. 7 to the address driver 6, the X electrode driver 7, and the Y electrode driver 8. In the light emission driving sequence shown in FIG. 7, driving based on each of the 14 subfields SF1 to SF14 is performed every frame or one field display period (hereinafter referred to as a unit display period). Each of these subfields SF1 to SF14 includes an address process W and a sustain process I, respectively. In the address process W, each discharge cell of the PDP 10 is set to either the lighting mode or the extinguishing mode according to the input video signal. In the sustain process I, only the discharge cells set in the lighting mode are repeatedly subjected to the sustain discharge, and the light emission state associated with the discharge is maintained. Only in the first subfield SF1, immediately before the address process W, a reset process R for initializing all the discharge cells to the lighting mode is executed.

  The address driver 6, the X electrode driver 7, and the Y electrode driver 8 each generate various drive pulses as shown in FIG. 8 in each subfield according to various timing signals supplied from the drive control circuit 4. Applied to electrodes X and Y. In FIG. 8, only SF1 to SF3 are extracted from the subfields SF1 to SF14, and the operation of applying each drive pulse is shown.

First, in the reset process R shown in FIG. 8, the first sustain driver 7 and second sustain driver 8, a reset pulse RP _x and RP with respect PDP10 the row electrodes X ₁ to X _n and Y ₁ to Y _n, respectively _{Apply Y} simultaneously. Depending on the application of the reset pulse RP _x and RP _Y, reset discharge is caused in all the discharge cells of the PDP 10. After the end of the reset discharge, a predetermined amount of wall charges are uniformly formed in each discharge cell, and all the discharge cells in the PDP 10 are initialized to the lighting mode.

In the address process W, the address driver 6 generates a pixel data pulse having a predetermined positive voltage when the pixel drive data bit DB is at logic level 0, and 0 V when the pixel drive data bit DB is at logic level 1. the to the column electrodes D ₁ to D _m by one display line (m bits). For example, in the address step W of the subfield SF1, the address driver 6, first, m pieces of pixel drive data bits DB1 corresponding to the first display line of the PDP10, as shown in FIG. 8 _(1,1) ~DB1 _(1, the m generates pixel data pulses DP1 ₁ according to the logic level of _m) each, simultaneously applied to the respective column electrodes D ₁ to D _m. Then generates m pixel data pulses DP1 ₂ in accordance with the PDP10 logic level of the second display m pixel drive data bits DB1 corresponding to the line _{(2,1) ~DB1 (2, m} ) of each , And simultaneously applied to the column electrodes D _{1 to} D _m , respectively. In the same manner, the address driver 6 applies pixel drive data bits DB1 _{(3,1) to} DB1 _{(3, m)} , DB1 ₍ corresponding to the third, fourth,..., Nth display lines of the PDP 10. _{4,1) to} DB1 _{(4, m)} ,..., DB1 _{(n, 1) to} DB1 _{(n, m)} m pixel data pulse groups DP1 ₃ , DP1 ₄ , corresponding to the respective logic levels. ..., DP1 _n are sequentially applied to the column electrodes D _{1 to} D _m . During this time, the Y electrode driver 8 generates a negative scan pulse SP as shown in FIG. 8 at the same timing as the application timing of each pixel data pulse group DP, and this is applied to the row electrodes Y ₁ to Y _n . Apply sequentially. At this time, discharge (selective erasure discharge) occurs only in the discharge cell at the intersection of the row electrode Y to which the scan pulse SP is applied and the column electrode to which the pixel data pulse having a positive polarity is applied. The wall charge remaining in the cell is erased. Therefore, this discharge cell is set to the extinguishing mode. On the other hand, since the selective erasing discharge is not generated in the discharge cells belonging to the column electrodes to which the pixel data pulse having the positive predetermined voltage as described above is not applied, the discharge cells maintain the state immediately before. That is, a discharge cell in which a predetermined amount of wall charges remains is in the lighting mode, while a discharge cell in which the amount of wall charges is not equal to the predetermined amount remains in the extinguishing mode.

Incidentally, application period T _P in as shown in FIG. 8 pixel data pulse and the scan pulse SP respectively applied to PDP10 in the address stage W is the average luminance level of the image one frame (or one field) for each of the input video signal It is set to the corresponding cycle. For example, the drive control circuit 4 first determines whether or not the average luminance level indicated by the average luminance signal APL is greater than the predetermined luminance level LL. Here, when the average luminance level is higher than the predetermined luminance level LL, the drive control circuit 4 sets the application cycle T _P to the predetermined cycle T _P1, and sequentially applies the pixel data pulse and the scan pulse SP in this cycle T _P1 . A timing signal to be applied to the PDP 10 is supplied to each of the address driver 6, the X electrode driver 7, and the Y electrode driver 8. On the other hand, when the average luminance level is lower than the predetermined luminance level LL, the drive control circuit 4 sets the application cycle T _P to a cycle T _P2 that is smaller than the cycle T _P1 , and sequentially applies pixels in this cycle T _P2 . Timing signals to be applied to the PDP 10 with data pulses and scan pulses SP are supplied to the address driver 6, the X electrode driver 7 and the Y electrode driver 8, respectively.

In the sustain process I, the X electrode driver 7 and the Y electrode driver 8 each have the sustain pulses IP _X and IP _{Y as} shown in FIG. 8 as many as the number corresponding to the luminance weighting value assigned to each subfield as follows. the repeatedly applied to the row electrodes X ₁ to X _n and Y ₁ to Y _n.

SF1: 1
SF2: 3
SF3: 5
SF4: 8
SF5: 10
SF6: 13
SF7: 16
SF8: 19
SF9: 22
SF10: 25
SF11: 28
SF12: 32
SF13: 35
SF14: 39
Then, each time the sustain pulses IP _X and IP _Y are applied, only the discharge cells set in the lighting mode are discharged (sustain discharge), and the light emission state associated with the discharge is maintained.

  Here, whether or not each discharge cell is subjected to the sustain discharge in the sustain process I of each of the subfields SF1 to SF14 is determined according to the pixel drive data GD as shown in FIG.

  That is, as shown in the light emission drive pattern A in FIG. 6, the first selective erasure discharge is generated in the address process W of one subfield (indicated by a black circle) corresponding to the luminance level to be expressed. A pixel data pulse to be applied is applied to the column electrode. Due to such selective erasing discharge, the discharge cells are shifted to the extinguishing mode. Therefore, the discharge cells initialized to the lighting mode in the reset process R of the first subfield SF1 are each subfield (indicated by white circles) existing until the first selective erasure discharge is generated. ) In the lighting mode, and the discharge cells are continuously discharged in each of these subfields.

  At this time, an intermediate luminance corresponding to the total number of sustain discharges generated in the sustain process I of each subfield within the unit display period is visually recognized. That is, one of the 15 types of driving shown by the light emission driving pattern A in FIG. 6 is selectively performed according to the pixel driving data GD.

Thereby, each light emission luminance ratio is
{0, 1, 4, 9, 17, 27, 40, 56, 75, 97, 122, 150, 182, 217, 255}
The intermediate luminance for 15 gradations is expressed.

  Here, in the driving shown in FIG. 6, pixel data pulses for generating the first selective erasing discharge in one subfield (indicated by black circles) corresponding to the luminance gradation level to be expressed are arrayed. Although applied to the electrodes, there was a case where the first selective erasing discharge was not generated even when this pixel data pulse was applied. Therefore, as shown in FIG. 6, after the drive for causing the first selective erasure discharge (indicated by a black circle) is performed, in the address process W of each subfield up to the last subfield SF14. The driving that should cause the second and subsequent selective erasing discharges (indicated by black triangles) is performed.

  However, when a pixel data pulse is periodically applied to the column electrode in each successive subfield to cause the second and subsequent selective erasure discharges, the front transparent substrate and the rear substrate of the PDP 10 vibrate (hereinafter referred to as panel vibration). Sometimes). Therefore, depending on the period of each subfield, there is a problem that an annoying abnormal sound is generated due to the panel vibration. For example, if the period of each subfield is 83 [μs], panel vibration occurs at an audible frequency of 12 [KHz], which becomes an annoying abnormal sound.

Therefore, in the plasma display device shown in FIG. 1, when the average luminance level of the input video signal for one frame of the image is higher than the predetermined luminance level, the pixel data pulse and scanning pulse SP application period T _{P as} shown in FIG. Is set to a cycle T _P1, and when it is low, the cycle is switched to a cycle T _P2 shorter than the cycle T _P1 . In short, compared to a case higher when the average luminance level of the input video signal is low, by shortening the application period T _P of the pixel data pulse and the scan pulse SP, so it reduces the time spent in the address stage W is there.

Thus, for example, as shown in FIG. 9, the average luminance level is a predetermined brightness level period T _b7 through T _b9 subfields SF7~SF9 each case lower than is shorter than the period T _a7 through T _a9 high if . At this time, if each of the periods T _{b7 to} T _b9 is set to be shorter than, for example, 66 [μs], a pixel data pulse to cause selective erasure discharge is applied in the address process W of each of the subfields SF7 to SF9. However, since the frequency of the panel vibration becomes a high frequency of 15 [KHz] or more which is difficult to hear audibly, it is not recognized as an abnormal sound.

  In short, when the luminance level of the input video signal when abnormal noise due to such panel vibration becomes prominent is measured in advance and a video signal having an average luminance level lower than this luminance level is supplied In addition, by shortening the period of each subfield, the frequency at the time of panel vibration is set to a high frequency outside the audible band.

  By the way, if the pulse width of the pixel data pulse and the scanning pulse SP for causing the first selective erasing discharge as shown by the black circles in FIG. 6 is narrowed, the probability that the first selective erasing discharge fails. Becomes higher.

Therefore, when the first selective erasure discharge is caused, the application period of the pixel data pulse and the scan pulse SP is fixed to T _P1 regardless of the average luminance level of the input video signal. That is, when the average luminance level is lower than the predetermined luminance level LL, the pixel data pulse and the scanning pulse SP are applied in the application period T _{P1 in the} subfield indicated by the black circle in FIG. In each of the subsequent subfields, the pixel data pulse and the scan pulse SP are applied at the application period _TP2 . Note that each of the m discharge cells belonging to each display line does not necessarily cause the first selective erasure discharge in the same subfield. For example, on one display line, a discharge cell in which a first selective erasure discharge is generated in the subfield SF4, a discharge cell in which a first selective erasure discharge is generated in SF5, and a first in SF6. There are mixed discharge cells in which the second selective erasing discharge occurs. At this time, since the scan pulse SP is commonly applied to each discharge cell on one display line, the application period of the scan pulse SP cannot be individually changed for each discharge cell. Therefore, in practice, the drive control circuit 4 should first generate the first selective erasure discharge for each discharge cell on this display line based on the pixel drive data GD for each display line. Each subfield is detected. Next, the drive control circuit 4 selects a subfield closest to the last subfield among the subfields in which the first selective erasing discharge is to be performed. Then, the drive control circuit 4 performs control for shortening the application period of the pixel data pulse and the scanning pulse SP for each display line in the address process of each subfield arranged behind the selected subfield. To do it.

  Also, in order to surely cause the first selective erasing discharge as described above, only when the average luminance level of one image frame is low and there is no high luminance area in the one image frame, the pixel data pulse and The application period of the scan pulse SP may be shortened. That is, when displaying an image that is physically dark but has a portion with high brightness, if the application period of the pixel data pulse and the scan pulse SP is shortened, the discharge cell corresponding to the portion with high brightness is displayed. On the other hand, the first selective erasure discharge must be generated by the pixel data pulse having the short pulse width and the scanning pulse SP. Therefore, the drive control circuit 4 first determines whether or not the average luminance level for one image frame in the input video signal is lower than the predetermined luminance level LL, and the predetermined value is included in the input video signal for this one image frame. It is determined whether or not there is a region with a luminance higher than the reference high luminance level. Only when it is determined that there is no region where the average luminance level is lower than the predetermined luminance level LL and there is no high luminance, the application period of the pixel data pulse and the scanning pulse SP is shortened in the address process W of each subfield. The control to be executed is performed.

  Here, as the average luminance level of one image frame is lower, the average luminance level becomes 0 in particular, and at the time of so-called black display, as shown in the light emission drive pattern A in FIG. Since the drive to generate (indicated by black circles and black triangles) is performed, the probability of occurrence of abnormal noise is the highest.

Therefore, while the having a period T _P1 the application period T _P of the pixel data pulse and the scan pulse SP to be applied in the address process W of each subfield when the average luminance level based on the input video signal is other than 0, the average brightness When the level is 0, the application period T _P of the pixel data pulse and the scan pulse SP is set to a period T _P2 shorter than the period T _P1 . That is, only when the average luminance level based on the input video signal is 0, the period of each subfield is shortened as shown in FIG. 9 to suppress the generation of abnormal sound due to panel vibration. At this time, only the address stage W of the first subfield SF1, regardless of the average luminance level of the input video signal, to secure the application period T _P of the pixel data pulse and the scan pulse SP to the period T _P1. In other words, when performing so-called black display in which the average luminance level is 0, if the first selective erasure discharge fails in the first subfield SF1, the discharge cell emits light at least in the sustain process I of SF1. It will not become black display. At this time, since the possibility of discharge failure increases as the pulse width of the pixel data pulse and the scanning pulse SP is narrowed, the application cycle T _{P is set} to a cycle T _P1 larger than the cycle T _P2 only in the first subfield SF1. By fixing, a pulse width capable of surely causing selective erasure discharge is secured. However, if it is possible to secure a pulse width that can surely cause selective erasure discharge, the application period T _P of the pixel data pulse and the scan pulse SP is set to the period T _{P2 in the first} subfield SF1 as in SF2 to SF14. You may make it switch to.

  In the above embodiment, the operation of the present invention has been described by taking as an example the case where the PDP 10 is driven in gray scale based on the light emission drive sequence as shown in FIG. 7. However, when driving based on another light emission drive sequence is performed. Is equally applicable.

  FIG. 10 is a diagram showing another example of the light emission drive sequence used when the PDP 10 shown in FIG.

  In FIG. 10, each of N subfields SF1 to SF (N) provided in the unit display period includes a reset process R, an address process W, and a sustain process I.

  In the reset process R shown in FIG. 10, reset discharge is generated in all the discharge cells of the PDP 10 as in the reset process R shown in FIG. 7, and all the discharge cells are initialized to the lighting mode.

Next, in the address process W, as in the address process W shown in FIG. 7, the address driver 6 generates a pixel data pulse having a voltage corresponding to the logic level of the pixel drive data bit DB, and displays this one display. to the column electrodes D ₁ to D _m as pixel data pulse group DP of each line (m bits). During this time, the Y electrode driver 8 generates a negative scan pulse SP as shown in FIG. 8 at the same timing as the application timing of each pixel data pulse group DP, and this is applied to the row electrodes Y ₁ to Y _n . Apply sequentially. At this time, a selective erasure discharge is generated only in the discharge cell at the intersection of the row electrode Y to which the scan pulse SP is applied and the column electrode to which the pixel data pulse having a predetermined positive voltage is applied. The remaining wall charge is erased. Therefore, this discharge cell is set to the extinguishing mode. On the other hand, since the selective erasing discharge is not generated in the discharge cells belonging to the column electrodes to which the pixel data pulse having the positive predetermined voltage as described above is not applied, the discharge cells maintain the lighting mode.

  Then, in the sustain process I, as in the sustain process I shown in FIG. 7, only the discharge cells set in the lighting mode are repeatedly sustain-discharged by the number corresponding to the luminance weight of each subfield, and the discharge is performed. The light emission state associated with is maintained.

According to the light emission drive sequence shown in FIG. 10, 2 ^N as shown in FIG. 11 corresponding to the combination of subfields in which the discharge cells will sustain discharge in N subfields SF1 to SF (N). Street driving is done. As a result, in the sustain process I of the subfield in which no selective erasure discharge has occurred in the discharge cell, the sustain discharge is generated the number of times corresponding to the luminance weighting of the subfield (indicated by white circles), and the subfields SF1 to SF are generated. An intermediate luminance according to the total number of sustain discharges generated over (N) is visualized. That is, 2 ^N gray levels having different luminance levels can be expressed by 2 ^N driving modes as shown in FIG.

  At this time, the number of subfields in which selective erasing discharge occurs is generated as shown by the black circles in FIG. 11 when the average luminance level for one image frame in the input video signal is low, as compared with the case where the average luminance level is high. Therefore, the probability of occurrence of abnormal noise due to panel vibration increases.

Therefore, when driving the 2 ^N gradation, similarly, when a video signal having an average luminance level lower than a predetermined luminance level is supplied, the address process W of each subfield is performed. By shortening the application period of each of the pixel data pulse and the scan pulse SP, the period of each subfield is shortened. As a result, the frequency at the time of panel vibration can be set to a high frequency outside the audible band, thereby suppressing abnormal sounds.

When black display is performed when driving ^2N gradation as described above, that is, when the average luminance level for one image frame is 0, the period in all subfields is as shown in FIG. Therefore, selective erasing discharge (indicated by black circles) is performed, so that abnormal noise becomes conspicuous. Therefore, only when the average luminance level for one frame of the image in the input video signal is 0, by switching the application period T _P of the pixel data pulse and the scanning pulse SP to a period T _P2 shorter than the period T _P1 , You may make it implement the drive which shortened the period of the subfield as shown in FIG. That is, when the average luminance level for one frame of the image in the input video signal is a value other than 0, the application period T _P of the pixel data pulse and the scan pulse SP is set as the period T _P1 and the period of each subfield is illustrated The extended driving is performed as shown in FIG.

  In the light emission drive pattern A shown in FIG. 6, the drive that should cause the second and subsequent selective erasure discharges (indicated by black triangles) to continue to the last subfield SF14 is performed. However, it is not always necessary to cause the second and subsequent selective erasure discharges continuously until the last subfield is reached. In short, in at least one subfield subsequent to the subfield in which the driving for generating the first selective erasing discharge is performed, the driving for generating the second and subsequent selective erasing discharges for surely generating the discharge. Should be implemented.

  In the above embodiment, when the average luminance level of the input video signal is low, the periods of all the subfields except the first subfield SF1 are shortened as shown in FIG. It is not necessary to shorten the period of all subfields. In short, only the predetermined subfield or subfield group that causes the abnormal sound caused by the panel vibration as described above when the pixel data pulse that causes the second and subsequent selective erasure discharges is applied. As a result, the cycle may be shortened.

  In the above embodiment, as a driving method for gray-scale driving the PDP 10, a predetermined amount of wall charges are formed in advance in all the discharge cells and selectively formed in each discharge cell based on the input video signal. The operation in the case where the so-called selective erasure address method for erasing the wall charges is described. However, the wall charges are erased from all the discharge cells (reset process R), and a discharge (selective writing discharge) is selectively generated in each discharge cell based on the input video signal to form a predetermined amount of wall charges. (Address process W) The case where a so-called selective write address method is adopted can be similarly implemented.

  FIG. 12 is a diagram showing an example of a light emission drive sequence based on the selective write address method. FIG. 13 is a diagram showing a light emission drive pattern by driving based on the light emission drive sequence shown in FIG.

12 and 13, when the average luminance level of the input video signal is lower than the predetermined luminance level LL, the drive control circuit 4 performs the PDP 10 in the address process W as shown in FIG. The application period T _P of the pixel data pulse and the scan pulse SP to be applied to is set to the period T _P1 . On the other hand, when the average luminance level is higher than the predetermined luminance level LL, the application cycle T _P of the pixel data pulse and the scan pulse SP is switched to a cycle T _P2 shorter than the cycle T _P1 . That is, according to the light emission drive pattern as shown in FIG. 13, when expressing high luminance, the number of subfields in which selective write discharge is generated is larger than when expressing low luminance. The probability of occurrence of abnormal noise associated with vibration increases. Therefore, when the average luminance level of the input video signal is higher than a predetermined luminance level is to shorten the period of each subfield by the application period T _P of the pixel data pulse and the scan pulse SP to a small. As a result, the frequency of the panel vibration can be increased to such a level that it cannot be audibly recognized, so that abnormal sounds are suppressed.

  Further, in the above embodiment, the subfield group (SF1 to SF14) for executing the sustain discharge in the subfields continuous in the number corresponding to the gradation luminance level to be expressed is displayed within one frame (one field) display period. Only one is provided. However, the present invention can be similarly applied to a case where a plurality of such specific subfield groups are provided in one frame (one field) display period. That is, in a specific subfield group composed of M (M: integer less than or equal to N) subfields continuously arranged among N (N: integer greater than or equal to 2) subfields within a unit display period. The present invention can be applied in the same manner as long as it is a drive that causes sustain discharge to occur in subfields that are continuous in the number corresponding to the gradation luminance level to be obtained.

  In the above embodiment, the occurrence of abnormal sound is suppressed by shortening the subfield period in accordance with the average luminance level. Occurrence can be prevented. That is, the abnormal sound can be suppressed by including in the magnesium oxide layer 13 of the PDP 10 vapor phase magnesium oxide crystals obtained by vapor phase oxidation of magnesium vapor generated when magnesium is heated. it can. Such a vapor-phase-processed magnesium oxide crystal has a particle size of 2000 angstroms or more, and has a multiple crystal structure in which cubic crystals are fitted to each other as shown in the SEM photograph image of FIG. 14A, or the SEM photograph of FIG. It has a cubic single crystal structure as shown in the image. Further, the vapor phase magnesium oxide crystal is excited by electron beam irradiation and emits CL light having a peak in a wavelength range of 200 to 300 nm (particularly, around 235 nm in 230 to 250 nm) as shown in FIG. It has the property of. Such a magnesium single crystal is characterized by high purity and fine particles compared to magnesium oxide produced by other methods, and less aggregation of particles. As shown in FIG. 16, the peak intensity of CL emission increases as the particle diameter of the vapor-phase-process magnesium oxide crystal increases. That is, when forming a vapor phase magnesium oxide crystal, if magnesium is heated at a temperature higher than usual, the form of the form shown in FIG. 14A or FIG. 14B is obtained together with the vapor phase magnesium oxide single crystal having an average particle size of 500 angstroms. A relatively large single crystal having a particle size of 2000 angstroms or more is formed. At this time, since the temperature at which magnesium is heated is higher than usual, the length of the flame in which magnesium and oxygen react with each other is also increased. Therefore, the temperature difference between the flame and the surroundings becomes large, and therefore, the group of vapor-phase magnesium oxide single crystals having a large particle size has a higher energy level corresponding to 200 to 300 nm (especially around 235 nm). It is presumed that many single crystals are contained. Therefore, the vapor-phase-grown magnesium oxide crystal preferably has an average particle size measured by the BET method of 500 angstroms or more, preferably 2000 angstroms or more.

  FIG. 17 shows a discharge probability when a magnesium oxide layer is not provided in the discharge cell PC, a discharge probability when a magnesium oxide layer is constructed by a conventional vapor deposition method, and 200 to 300 nm (particularly 230 to 250 nm) by electron beam irradiation. It is a figure which shows the discharge probability in each case when the magnesium oxide layer containing the gaseous-phase magnesium oxide single crystal which produces CL light emission which has a peak in the vicinity of 235 nm is provided. In FIG. 17, the horizontal axis represents the discharge pause time, that is, the time interval from when a discharge occurs until the next discharge occurs.

  Thus, the oxidation including the vapor-phase magnesium oxide single crystal that emits CL light having a peak at 200 to 300 nm (particularly around 235 nm within 230 to 250 nm) by the electron beam irradiation in the discharge space S of each discharge cell PC. When the magnesium layer 13 is formed, the discharge probability is increased as compared with the case where the magnesium oxide layer is formed by a conventional vapor deposition method. As shown in FIG. 18, the vapor-phase magnesium oxide single crystal is generated in the discharge space S as the intensity of CL emission having a peak particularly at 235 nm when irradiated with an electron beam increases. The discharge delay can be shortened.

  Accordingly, when the discharge probability is increased (discharge delay is reduced), the priming effect by the write reset discharge and the erase reset discharge in the reset process R is maintained for a long time. This speeds up various discharges such as the address discharge generated in the address process W, the sustain discharge generated in the sustain process I, and the erase discharge generated in the erase process E.

  Therefore, it is possible to shorten the pulse width of each of the pixel data pulse and the scan pulse SP as shown in FIG. 8 applied to the column electrode D and the row electrode Y in order to cause the address discharge, and this address is correspondingly increased. The processing time spent on the process W can be shortened. Therefore, if the period of the subfield is set to a length of 66 μsec or less by shortening the time spent in the address process W of each subfield, the frequency at the time of panel vibration becomes a high frequency outside the audible band, and abnormal sound Is suppressed.

  In the above embodiment, in the address process W included in each subfield, address discharge is performed on the discharge cells belonging to the display line by one display line from the first display line to the nth display line of the PDP 10. However, it is also possible to carry out two display lines at a time. For example, the address driver 6 is provided not only at the upper end of the display screen of the PDP 10 as shown in FIG. 1 but also at the lower end of the display screen. The address driver 6 provided at the upper end of the display screen sequentially applies pixel data pulses for one display line to the discharge cells belonging to the first to (n / 2) display lines of the PDP 10. In parallel with this operation, the address driver 6 provided at the lower end of the display screen applies pixel data pulses sequentially to the discharge cells belonging to each of the [(n / 2) +1] to nth display lines. I do. By adopting such a configuration, the length of the address period is halved, so that the margin is further increased, and the subfield period can be easily set to a period of 66 μsec or less. Therefore, in manufacturing a PDP in which the generation of abnormal noise is suppressed, the margin (margin) is widened and the product yield is improved.

1 is a diagram illustrating a configuration of a plasma display apparatus for driving a plasma display panel by a driving method according to the present invention. It is a front view which shows typically the internal structure at the time of seeing PDP5 mounted in the plasma display apparatus of FIG. 1 from the display surface side. It is a figure which shows the cross section on the V3-V3 line | wire shown by FIG. It is a figure which shows the cross section on the W2-W2 line | wire shown by FIG. It is a figure which shows the internal structure of the pixel drive data generation circuit 3 shown by FIG. It is a figure which shows the data conversion table by the data conversion circuit 3, and the light emission drive pattern within a unit display period. It is a figure which shows an example of the light emission drive sequence at the time of driving PDP10 shown by FIG. It is a figure which shows the application timing of the various drive pulses applied to PDP10 shown by FIG. It is a figure which shows the period of each subfield changed according to an average luminance level. It is a figure which shows another example of the light emission drive sequence. It is a figure which shows the light emission drive pattern based on the light emission drive sequence shown by FIG. It is a figure which shows an example of the light emission drive sequence based on the selective writing address method. It is a figure which shows the data conversion table of the data conversion circuit 32 at the time of employ | adopting the selective writing address method, and the light emission drive pattern. It is a figure which shows the SEM photograph image of the magnesium oxide single crystal which has a multiple crystal structure. It is a figure which shows the SEM photograph image of the magnesium oxide single crystal which has a cubic single crystal structure. It is a graph which shows the relationship between the particle size of a magnesium oxide single crystal body, and the wavelength of CL light emission. It is a graph which shows the relationship between the particle size of a magnesium oxide single crystal, and the intensity | strength of CL light emission of 235 nm. Discharge probability when a magnesium oxide layer is not provided in the discharge cell, discharge probability when a magnesium oxide layer is constructed by a conventional vapor deposition method, and when a magnesium oxide layer containing a vapor-phase magnesium oxide single crystal is provided It is a figure which shows the discharge probability of. It is a figure which shows the correspondence of CL light emission intensity of a 235 nm peak, and discharge delay time.

Explanation of main part codes

2 Average luminance calculation circuit 3 Pixel drive data generation circuit 4 Drive control circuit 10 PDP

Claims (17)

A plasma display panel in which discharge cells corresponding to pixels are formed at each intersection of a plurality of row electrode pairs and a plurality of column electrodes extending in a direction intersecting each of the row electrode pairs is provided for each unit display period. A driving method of a plasma display panel that performs gradation driving in N (N is an integer of 2 or more) subfields,
Each of the subfields includes an address period in which each of the discharge cells is changed from a lighting mode state to a light-off mode state according to pixel data for each pixel based on an input video signal, and the lighting state immediately after the address period. A sustain period in which only the discharge cells set in the mode are repeatedly subjected to a sustain discharge,
When the average value of the luminance level indicated by the input video signal is smaller than a predetermined value, the period of the subfield is shortened by shortening the address period as compared with the case where the average value is large. To drive a plasma display panel. All the discharge cells only immediately before the address period of the first subfield in a specific subfield group consisting of M (2 ≦ M ≦ N) subfields arranged in succession in the N subfields Including a reset period to initialize the lighting mode to the state of the lighting mode,
The first pixel data pulse for changing the discharge cell to the extinguishing mode is applied to the column electrode in an address period of any one of the subfields in the specific subfield group. Item 8. A driving method of a plasma display panel according to Item 1.   A second pixel data pulse having the same polarity as the first pixel data pulse is applied to the column electrode in the address period of a subfield subsequent to the first subfield in the specific subfield group. The method for driving a plasma display panel according to claim 2.   4. The plasma display panel according to claim 2, wherein a cycle of a predetermined subfield in each of the subfields subsequent to the first subfield in the specific subfield group is shortened. 5. Driving method.   4. The plasma display panel according to claim 2, wherein a period of a predetermined subfield in each subfield subsequent to the one subfield in the specific subfield group is shortened. 5. Driving method. A reset period for initializing all the discharge cells to the lighting mode immediately before the address period of each of the N subfields;
2. The plasma display panel according to claim 1, wherein a first pixel data pulse for causing the discharge cells to transition to the extinguishing mode is applied to the column electrodes in the address period of each of the N subfields. Driving method.   The first and second pixel data pulses and the first and second pixels are compared with the case where the average value of the luminance level indicated by the input video signal is smaller than a predetermined value, as compared with the case where the average value is larger. 4. The plasma display panel according to claim 3, wherein the address period is shortened by shortening an application period of each scan pulse applied to one row electrode of the row electrode pair in synchronization with a data pulse. Driving method.   2. The plasma display panel driving method according to claim 1, wherein the predetermined value is a luminance level corresponding to all black display.   6. The method of driving a plasma display panel according to claim 1, wherein the period of the subfield is shortened to a length of 66 [mu] sec or less. A plasma display panel in which discharge cells corresponding to pixels are formed at each intersection of a plurality of row electrode pairs and a plurality of column electrodes extending in a direction intersecting each of the row electrode pairs is provided for each unit display period. A driving method of a plasma display panel that performs gradation driving in N (N is an integer of 2 or more) subfields,
Each of the subfields includes an address period in which each of the discharge cells transitions from a light-off mode state to a light-on mode state according to pixel data for each pixel based on an input video signal, and the light-on mode immediately after the address period. A sustain period in which only the discharge cells that are set to be repeatedly subjected to a sustain discharge,
When the average value of the luminance level indicated by the input video signal is larger than a predetermined value, the period of the subfield is shortened by shortening the address period as compared with a case where the average value is smaller. To drive a plasma display panel.   The method of claim 10, wherein the period of the subfield is shortened to 66 μsec or less. A plasma display panel in which a plurality of discharge cells corresponding to each pixel is formed on each of n display lines is gray-scale driven in N (N is an integer of 2 or more) subfields per unit display period. A driving method of a plasma display panel,
Each of the subfields transitions each of the discharge cells from the lighting mode state to the extinguishing mode state or from the extinguishing mode state to the lighting mode state according to pixel data for each pixel based on the input video signal An address period to be performed, and a sustain period in which only the discharge cells set in the lighting mode immediately after the address period are repeatedly subjected to a sustain discharge,
The method of driving a plasma display panel, wherein a period of each of the subfields is 66 μsec or less.   Each of the discharge cells is provided with a magnesium oxide layer containing a magnesium oxide crystal that is excited by electron beam irradiation and emits cathodoluminescence light having a peak in a wavelength range of 200 to 300 nm. Item 13. A driving method of a plasma display panel according to Item 12.   14. The driving of a plasma display panel according to claim 13, wherein the magnesium oxide crystal includes a magnesium oxide single crystal generated by vapor phase oxidation of magnesium vapor generated when magnesium is heated. Method.   The method for driving a plasma display panel according to claim 13 or 14, wherein the magnesium oxide crystal includes a magnesium oxide single crystal having a particle diameter of 2000 mm or more.   The method of driving a plasma display panel according to any one of claims 13 to 15, wherein the magnesium oxide crystal performs cathodoluminescence emission having a peak in a wavelength range of 230 to 250 nm. At the upper end of the display screen in the plasma display panel, the discharge cells belonging to each of the first to (n / 2) display lines of the plasma display panel according to the pixel data in the address period are in the lighting mode state or A first address driver for sequentially applying pixel data pulses having a voltage to be set in the extinguishing mode for each display line;
At the lower end of the display screen, each of the discharge cells belonging to each of the (1 + n / 2) to nth display lines of the plasma display panel according to the pixel data in the address period is set in the lighting mode or the extinguishing mode. 13. The method of driving a plasma display panel according to claim 12, further comprising a second address driver that sequentially applies pixel data pulses having a voltage to be set to the state of one display line at a time.