KR100956564B1 - Method of driving plasma display panel - Google Patents

Abstract

It is an object of the present invention to provide a method of driving a plasma display panel which can improve dark contrast while preventing erroneous discharge. In the gray scale driving of the plasma display panel including the secondary electron emission material in the phosphor layer in the discharge cell in a plurality of subfields for each unit display period, the following reset steps and address steps are performed in one subfield within the unit display period. Run In the reset step, a first reset discharge is caused in each discharge cell by applying a voltage between the two electrodes of one row electrode of the row electrode pair of the plasma display panel between the anode side and the cathode side. A second reset discharge is caused by applying a first base pulse having a positive potential to the other row electrode while applying a negative potential to the row electrode. In the address step, each discharge cell is selectively discharged in accordance with the input video signal to set it to the ON mode. In addition, during the execution of this address step, a negative second base pulse having a peak potential different from that of the first base pulse is applied to the other row electrode while applying a negative potential to the one row electrode.

Dark contrast, plasma display panel, discharge cell, phosphor layer, secondary electron emission material, reset stroke, address stroke

Description

Driving method of plasma display panel {METHOD OF DRIVING PLASMA DISPLAY PANEL}

The present invention relates to a driving method for driving a plasma display panel.

Currently, as a thin display device, an AC type (AC discharge type) plasma display panel (PDP) is commercialized. In the PDP, two substrates, that is, a front transparent substrate and a back transparent substrate, are disposed to face each other at predetermined intervals. On the inner surface (surface facing the rear transparent substrate) of the front transparent substrate as the display surface, a plurality of row electrode pairs extending in parallel to each other in pairs are formed as sustain electrode pairs. Further, a dielectric layer covering each of the row electrode pairs is formed on the inner surface of the front transparent substrate. On the back substrate, a plurality of column electrodes are formed to extend from the address electrode so as to intersect with the row electrode pairs, and a phosphor is coated. When viewed from the display surface side, display cells corresponding to pixels are formed at the intersections of the row electrode pairs and the column electrodes. To such a PDP, gradation driving using the subfield method is performed so as to obtain the display luminance of the halftone corresponding to the input video signal.

In gradation driving based on the subfield method, display driving is performed on a video signal for one field in each of a plurality of subfields each of which is assigned a number (or period) of light emission. In each subfield, an address stroke and a sustain stroke are executed in sequence. In the addressing step, selective discharge is caused between the row electrodes and the column electrodes in each discharge cell in accordance with the input video signal to form (or erase) a predetermined amount of wall charges. At this time, the discharge cells in which the predetermined amount of wall charges are formed are set to the ON mode, and the discharge cells in which the wall charge amount does not reach the predetermined amount are set to the OFF mode. In the sustaining stroke, only the discharge cells in which the predetermined amount of wall charges are formed, that is, the discharge cells set in the ON mode are repeatedly sustained and the light emission state accompanying the discharge is maintained. In addition, the reset step is executed before the address step in at least the head subfield. In such a reset stroke, in all discharge cells, the reset discharge is caused between paired row electrodes to initialize the amount of wall charge remaining in all the discharge cells, and the all discharge cells are changed to one of the ON mode and the OFF mode. It is in a state.

Here, since the reset discharge is a relatively strong discharge and has nothing to do with the contents of the image to be displayed, there is a problem that the light emission accompanying the discharge lowers the contrast of the image.

Accordingly, a plasma display panel including a plasma display panel is provided in each display cell to provide a magnesium oxide layer containing magnesium oxide crystals excited by irradiation with an electron beam and emitting cathode luminescence emission having a peak within a wavelength of 200 to 300 nm. A rasma display device has been proposed (see, for example, Patent Document 1 and Japanese Patent Laid-Open No. 2006-54160). According to such a plasma display panel, since the discharge delay time caused in the display cell is shortened, it is possible to surely cause reset discharge even when a reset pulse having a relatively low peak potential is applied. Therefore, in this plasma display device, a reset discharge with a low discharge intensity is caused by applying a reset pulse having a relatively low peak potential to each display cell. Thereby, since the light emission luminance accompanying reset discharge falls, it becomes possible to raise the brightness contrast of a display image.

However, as long as the delay time of the discharge is shortened and the discharge is easily caused, there is a problem that a false discharge is caused in the address stroke immediately after the reset discharge.

In addition, a driving method has been proposed in which a reset discharge is not caused only when black display is performed, i.e., when the discharge cell is kept off for one field display period (Patent Document 2, Japanese Patent Laid-Open No. 2001-312244). 9). In such driving, the luminance range from the lowest luminance (black display) to the highest luminance in the 14 subfields is expressed in 15 steps (first to fifteenth gradations). At this time, in the second to fifteenth gradation driving except for the first gradation driving in charge of displaying the lowest luminance (black display), the selective write discharge corresponding to the reset discharge only in the first subfield SF1 (indicated by double circles) To cause each discharge cell to be initialized to the ON mode. Then, by causing the selective erasure discharge (indicated by the black circle) which should cause the discharge cells to transition to the OFF mode in only one of the SFs in the subfields SF2 to SF14, the sustain discharges in each successive SF by the number corresponding to each gray scale ( In circled circles).

By adopting the above-described driving, the opportunity for write discharge to initialize the state of the discharge cell is only the first subfield SF1, and when the black display is performed, the write discharge is not performed, so the contrast is improved.

However, according to this driving, the opportunity to transition the discharge cells from the OFF mode to the ON mode state is only write discharge in the first subfield SF1. Therefore, if the write discharge fails in the subfield SFl, the display becomes black regardless of the input video signal, causing a problem that the image quality deteriorates remarkably.

The present invention has been made to solve such a problem, and an object of the present invention is to provide a method of driving a plasma display panel which can improve dark contrast while preventing erroneous discharge.

In addition, an object of the present invention is to provide a method of driving a plasma display panel that can stably cause write discharges to be selectively shifted from an OFF mode state to an ON mode state on the basis of an input video signal. do.

In the driving method of the plasma display panel according to the first aspect of the present invention, a plurality of row electrode pairs are provided on the front substrate and the front substrate and the rear substrate are disposed to face each other with a discharge space in which discharge gas is enclosed. And a plasma display panel in which discharge cells that are responsible for pixels are formed at respective intersections of a plurality of column electrodes formed on the rear substrate, with a plurality of subfields for each unit display period of an input video signal. A driving method of a plasma display panel for driving, wherein a phosphor layer containing phosphor material and secondary electron emission material is provided on the rear substrate in the discharge cell, and the discharge is performed in one subfield of the unit display period. A reset stroke for initializing the cell to the OFF mode state and according to the input video signal By performing address discharge of all cells selectively, an address step of transitioning the discharge cells to the ON mode is executed. In the reset step, one row electrode of the row electrode pair is the anode side and the column electrode is the cathode side. The first reset discharge is caused between the one row electrode and the column electrode by applying a voltage between the one row electrode and the column electrode, and then the negative electrode potential is subsequently applied to the one row electrode. A second reset discharge is caused by applying a first base pulse having a positive peak potential to the other row electrodes of the row electrode pairs, and a negative potential is applied to the one row electrode during the execution of the addressing step. While applying, a second base pulse having a positive peak potential different from that of the first base pulse is applied to the other row electrode.

By including the secondary electron emission material in the phosphor layer in each discharge cell of the plasma display panel (PDP), it is possible to surely cause a weak reset discharge, and to improve the dark contrast by weakening the reset discharge.

When the PDP is driven in gradation in a plurality of subfields for each unit display period, the following reset steps and address steps are executed in one subfield in the unit display period. First, in the reset step, the first reset discharge is caused in each discharge cell by applying a voltage between the positive electrode and the positive electrode with one row electrode of the row electrode pair of the PDP to the cathode side, and then one row electrode. The second reset discharge is caused by applying the first base pulse having the positive peak potential to the other row electrode while applying the negative potential to the other row electrode. Next, in the address step, each discharge cell is selectively discharged in accordance with the input video signal to set it to the ON mode. Further, during the execution of this address step, a second base pulse having a positive peak potential different from that of the first base pulse is applied to the other row electrode while applying a negative potential to the one row electrode.

At this time, if the peak potential of the first base pulse is set to a higher potential than that of the second base pulse, the second reset discharge becomes a strong discharge, so that the wall charges can be erased, but in the vicinity of one row electrode in each discharge cell. There is a small amount of positive wall charge and a small amount of negative wall charge remains in the vicinity of the other row electrode. As a result, in the state where the negative potential is applied to one row electrode and the second base pulse is applied to the other row electrode in the address stroke, discharge between the row electrodes is less likely to occur, and erroneous discharge is prevented.

On the other hand, if the peak potential of the second base pulse is set to a higher potential than that of the first base pulse, the address discharge is weakly discharged due to the unevenness of the discharge intensity for each discharge cell in the manufacturing phase, and even this discharge cell exists even if the discharge cell exists. It is possible to surely set the cell to the ON mode state.

According to another aspect of the present invention, there is provided a method of driving a plasma display panel, comprising: a plurality of row electrode pairs formed on a first substrate in first and second substrates disposed to face each other with a discharge space filled with discharge gas therebetween; In the video signal, a plasma display panel having a discharge cell including a phosphor layer whose surface is in contact with the discharge gas is formed at each intersection with a plurality of column electrodes formed on the second substrate. A method of driving a gradation drive in a plurality of subfields for each unit display period of the plurality of subfields, wherein each of a first subfield in each of the plurality of subfields in the unit display period and a second subfield subsequent to the first subfield In the video signal, a negative write scan pulse is sequentially applied to one row electrode of the row electrode pair. By applying pixel data pulses corresponding to pixel data for each of the underlying pixels to the column electrode, a write address step of selectively discharging the discharge cells and shifting the discharge cells from the OFF mode to the ON mode In the third subfield subsequent to the second subfield, a negative erase scan pulse is sequentially applied to one of the row electrodes of the row electrode pairs, for each pixel based on the video signal. Performing an erase address step of selectively erasing the discharge cells by applying pixel data pulses corresponding to pixel data to the column electrodes to transition the discharge cells from the ON mode to the OFF mode, and The write scan pulse applied in the write address stroke of the first subfield A peak potential of negative polarity of the stand, the second and higher than the peak potential of negative polarity according to the write scan pulse applied in the writing addressing process of the sub-fields.

In addition, the driving method of the plasma display panel according to another aspect of the present invention includes a plurality of rows formed on the first substrates in the first and second substrates which are disposed to face each other with the discharge space in which the discharge gas is enclosed. A plasma display panel having a discharge cell including a phosphor layer whose surface is in contact with the discharge gas at each intersection of an electrode pair and a plurality of column electrodes formed on the second substrate; A plasma display panel driving method for performing gradation driving in a plurality of subfields for each unit display period in a signal, comprising: a first subfield in each of the plurality of subfields in the unit display period and a first subfield following the first subfield; In each of the two subfields, the negative write scan pulse is sequentially applied to one of the row electrodes of the row electrode pair. Write to discharge the discharge cells selectively by applying pixel data pulses corresponding to pixel data for each pixel based on an image signal to the column electrodes, thereby causing the discharge cells to transition from the OFF mode to the ON mode In each of the pixels based on the video signal, an address stroke is executed, and in the third subfield subsequent to the second subfield, negative erase scan pulses are sequentially applied to one row electrode of the row electrode pair. Performing an erase address step of selectively erasing the discharge cells by applying pixel data pulses corresponding to pixel data of the column data to the column electrodes to transition the discharge cells from the ON mode to the OFF mode, The write scan applied in the write address stroke of the first subfield The pulse width of the pulse is made smaller than the pulse width of the write scan pulse applied in the write address stroke of the second subfield.

In addition, a method of driving a plasma display panel according to another aspect of the present invention includes a plurality of rows formed on a first substrate of first and second substrates that are disposed to face each other with a discharge space filled with discharge gas therebetween. A plasma display panel in which a discharge cell including a phosphor layer whose surface is in contact with the discharge gas is formed at each intersection of an electrode pair and a plurality of column electrodes formed on the second substrate; A plasma display panel driving method which performs gradation driving with a plurality of subfields in each unit display period in a signal, comprising: a first subfield in each of the plurality of subfields in the unit display period and a first subfield following the first subfield; In each of the two subfields, the negative write scan pulse is sequentially applied to one of the row electrodes of the row electrode pair. Write address discharge for selectively writing address discharge the discharge cells to transition the discharge cells from the OFF mode to the ON mode by applying a pixel data pulse corresponding to pixel data for each pixel based on an image signal to the column electrode In the third subfield subsequent to the second subfield, the pixel data for each pixel based on the video signal while applying a negative erase scan pulse sequentially to one row electrode of the row electrode pair. Performing an erase address step of selectively erasing the discharge cells by applying a pixel data pulse to the column electrode to transition the discharge cells from the ON mode to the OFF mode, In the subfield, the row electrode pairs over the execution period of the write address step. Applying a base pulse of a negative polarity to the row electrodes on the other, and the second sub-field is applied to the positive base pulse on the row electrodes on the other throughout the execution period of the writing addressing process.

In each of the first subfield and the subsequent second subfield during the unit display period, the pixel data pulse is applied to the column electrode while the negative write scan pulse is applied to one row electrode of each row electrode pair of the plasma display panel. Thus, a write address discharge is performed to selectively discharge the discharge cells and to transition the discharge cells from the OFF mode to the ON mode. In the third subfield subsequent to the second subfield, the discharge cells are selectively erased by applying a pixel data pulse to the column electrode while applying a negative erase scan pulse to one row electrode of each row electrode pair. An address discharge is performed and an erase address step is executed in which the discharge cells are transitioned from the ON mode to the OFF mode. At this time, the negative peak potential of the write scan pulse applied in the write address stroke of the first subfield is set to the negative peak potential of the write scan pulse applied in the write address stroke of the second subfield. Higher than

The pulse width of the write scan pulse applied in the write address stroke of the first subfield is made smaller than the pulse width of the write scan pulse applied in the write address stroke of the second subfield.

The negative base pulse is applied to the other row electrodes of the row electrode pairs during the execution period of the write address stroke of the first subfield, and the other end of the write address stroke of the second subfield. A positive base pulse is applied to the row electrode.

This driving prevents mis-discharge caused by the row address electrodes caused by the write address discharge caused by the write address stroke of the first subfield, thereby ensuring a write discharge in the write address stroke of the next second subfield. It is possible to cause.

1 is a view showing a schematic configuration of a plasma display apparatus for driving a plasma display panel according to a driving method according to a first embodiment of the present invention.

As shown in Fig. 1, this plasma display device is composed of a PDP 50, an X electrode driver 51, an address driver 55, and a drive control circuit 56 as a plasma display panel.

The PDP 50 has column electrodes D _{1 to} D m arranged in the longitudinal direction (vertical direction) of the two-dimensional display screen, and row electrodes X _{1 to} X _n arranged in the horizontal direction (horizontal direction), respectively, and the rows. Electrodes Y _{1 to} Y _n are formed. At this time, one pair to each other forming a row electrode pair adjacent to each other _{(Y 1, Y n),} (Y 2, X 2), ‥‥, (Y 3, X 3), ‥‥ (Y n, X n) is Each of them is responsible for the first display line to the nth display line in the PDP 50. A discharge cell (display cell) PC in charge of the pixel is formed at each intersection portion (area surrounded by the dashed-dotted line in FIG. 1) between each display line and each of the column electrodes D _{1 to} D _m . That is, in the PDP 50, each of the discharge cells PC _{2 , 1 to} PC _{2 , m} belonging to the first display line, and the discharge cells PC _{n , 1 to} PC _{n , m} belonging to the nth display line are in matrix form. Is arranged.

2 is a front view schematically showing the internal structure of the PDP 50 seen from the display surface side. In Fig. 2, the intersections of three adjacent column electrodes D and two display lines adjacent to each other are shown. 3 is a diagram showing a cross section of the PDP 50 in the V-V line of FIG. 2, and FIG. 4 is a diagram showing a cross section of the PDP 50 in the W-W line of FIG.

As shown in Fig. 2, each row electrode X is a T-shaped transparent provided in contact with a bus electrode Xb extending in the horizontal direction of a two-dimensional display screen and a position corresponding to each discharge cell PC on the bus electrode Xb, respectively. It consists of an electrode Xa. Each row electrode Y is composed of a bus electrode Yb extending in the horizontal direction of a two-dimensional display screen and a T-shaped transparent electrode Ya provided in contact with a position corresponding to each discharge cell PC on the bus electrode Yb, respectively. The transparent electrodes Xa and Ya are made of a transparent conductive film such as indium tin oxide (ITO), for example, and the bus electrodes Xb and Yb are made of a metal film, for example. As shown in Fig. 3, the row electrode X composed of the transparent electrode Xa and the bus electrode Xb, and the row electrode Y composed of the transparent electrode Ya and the bus electrode Yb have a front transparent surface whose front side is the display surface of the PDP 50. It is formed in the back side of the board | substrate 10. FIG. At this time, the transparent electrodes Xa and Ya in each of the row electrode pairs X and Y extend to the side of the row electrodes of the paired pairs, and the positive sides of the wide portions thereof face each other through a discharge gap g1 of a predetermined width. . On the back side of the front transparent substrate 10, a black color extending in the horizontal direction of the two-dimensional display screen between the row electrode pairs X and Y and the row electrode pairs X and Y adjacent to the row electrode pairs. Alternatively, a dark light absorbing layer (shielding layer) 11 is formed. The dielectric layer 12 is formed on the back side of the front transparent substrate 10 so as to cover the row electrode pairs X and Y. On the back side of the dielectric layer 12 (the surface opposite to the surface where the row electrode pairs contact), as shown in Fig. 3, the light absorption layer 11 and the bus electrodes Xb and Yb adjacent to the light absorption layer 11 are shown. A sealed dielectric layer 12A is formed at a portion corresponding to the region where the is formed.

On the surfaces of the dielectric layer 12 and the raised dielectric layer 12A, a magnesium oxide layer 13 is formed. In addition, the magnesium oxide layer 13 is excited by irradiation with an electron beam and performs magnesium oxide as a secondary electron emission material that emits CL (cathode luminescence) light having a peak within a wavelength of 200 to 300 nm, particularly, 230 to 250 nm. It includes a crystal (hereinafter referred to as "CL luminescent MgO crystal"). The CL luminescent MgO crystals are obtained by gas phase oxidation of magnesium vapor generated by heating magnesium, and have, for example, a multi-crystal structure in which the crystals of a cube are sandwiched with each other, or a single crystal structure of a cube. The average particle diameter of CL luminescent MgO crystals is 2000 GPa or more (measurement result by BET method).

In order to form a vapor-phase magnesium oxide single crystal having a large particle size of 2000 kPa or more, it is necessary to increase the heating temperature when generating magnesium vapor. For this reason, as the length of the flame in which magnesium and oxygen react, and the temperature difference between the flame and the temperature increase, the peak wavelength of the CL emission as described above is larger for the vapor phase magnesium oxide single crystal having a larger particle size. , Around 235 nm, within the range of 230 to 250 nm, many energy levels are formed.

In addition, compared with the general vapor phase oxidation method, the vapor phase magnesium oxide single crystal produced by increasing the amount of magnesium evaporated per unit time to increase the reaction region between magnesium and oxygen, and reacting with more oxygen has the peaks of CL emission described above. It has an energy level corresponding to the wavelength.

The magnesium oxide layer 13 is formed by attaching such CL-emitting MgO crystals to the surface of the dielectric layer 12 by a spray method, an electrostatic coating method, or the like. In addition, a thin magnesium oxide layer may be formed on the surface of the dielectric layer 12 by vapor deposition or sputtering, and the magnesium oxide layer 13 may be formed by attaching CL-emitting MgO crystals thereon.

On the other hand, on the back substrate 14 arranged in parallel with the front transparent substrate 10, each of the column electrodes D is positioned at positions facing the transparent electrodes Xa and Ya in each row electrode pair X and Y. It extends in the direction orthogonal to the row electrode pairs (X, Y). On the rear substrate 14, a white column electrode protective layer 15 covering the column electrode D is formed. The partition 16 is formed on the column electrode protective layer 15. The partition wall 16 includes horizontal walls 16A extending in the horizontal direction of the two-dimensional display screen at positions corresponding to the bus electrodes Xb and Yb of each row electrode pair X and Y, and column electrodes adjacent to each other. It is formed in the shape of a ladder by vertical walls 16B extending in the longitudinal direction of the two-dimensional display screen at each intermediate position between D. 2, a ladder-shaped partition wall 16 is formed for each display line of the PDP 50. As shown in FIG. Between partitions 16 adjacent to each other, a gap SL as shown in FIG. 2 exists. Moreover, the discharge cell PC containing independent discharge space S, the transparent electrode Xa, and Ya is partitioned by the ladder-shaped partition wall 16, respectively. In the discharge space S, a discharge gas containing xenon gas is sealed. Phosphor layers 17 are formed on the side surfaces of the horizontal walls 16A, the vertical walls 16B, and the surface of the column electrode protective layer 15 in each discharge cell PC so as to cover all of these surfaces. The phosphor layer 17 is actually composed of three kinds of phosphors that emit red light, phosphors that emit green light, and phosphors that emit blue light.

In addition, the phosphor layer 17 contains MgO crystals (including CL luminescent MgO crystals) as secondary electron emission materials in the form as shown in FIG. 5, for example. At this time, on the surface covering the discharge space S on the surface of the phosphor layer 17, that is, on the surface in contact with the discharge space S, the MgO crystals are exposed from the phosphor layer 17 so as to be in contact with the discharge gas.

Here, the discharge space S and the gap SL of each discharge cell PC are closed with each other as the magnesium oxide layer 13 abuts on the horizontal wall 16A as shown in FIG. As shown in Fig. 4, since the vertical wall 16B does not contact the magnesium oxide layer 13, a gap r is present therebetween. In other words, the discharge spaces S of the discharge cells PC adjacent to each other in the horizontal direction of the two-dimensional display screen communicate with each other through this gap r.

First, the drive control circuit 56 first converts an input video signal into 8-bit pixel data representing all luminance levels of 256 pixels for each pixel, and multi-system consisting of error diffusion processing and dither processing for the pixel data. Harmonization processing is performed. That is, in the error diffusion process, first, the upper 6 bits of the pixel data are the display data and the remaining lower 2 bits are the error data, and the weighted error data of the pixel data corresponding to each of the peripheral pixels is added. By reflecting it in the display data, 6-bit error diffusion processing pixel data is obtained. According to such an error diffusion process, the luminance of the lower two bits in the original pixel is represented pseudo by a peripheral pixel. Therefore, the display data for six bits is smaller than eight bits, so that the pixel data for the eight bits is used. It is possible to express the luminance gradation equivalent to. Next, the drive control circuit 56 performs dither processing on the 6-bit error diffusion processing pixel data obtained by this error diffusion processing. In the dither processing, dither addition is performed by assigning and adding a plurality of pixels adjacent to each other to each other and assigning and adding dither coefficients each having different coefficient values to the staggered error diffusion processing pixel data corresponding to each pixel in the one pixel unit. Get pixel data. According to the addition of the dither coefficients, when viewed in the pixel unit as described above, the luminance equivalent to 8 bits can be expressed only by the upper 4 bits of the dither added pixel data. Thus, the drive control circuit 56 converts the upper four bits of the dither addition pixel data into four bits of multi-gradation pixel data PD _S representing 15 luminance levels as shown in FIG. Therefore, the drive control circuit 56 converts the multi-gradation pixel data PD _S into 14-bit drive data GD in accordance with the data conversion table as shown in FIG. The drive control circuit 56 associates the first to fourteenth bits in the pixel drive data GD with each of the subfields SF1 to SF14 (to be described later), and the pixel of the bit digit corresponding to the subfield SF. One pixel line (m) is supplied to the address driver 55 as drive data bits.

In addition, the drive control circuit 56 supplies various control signals for driving the PDP 50 having the above structure in accordance with the light emission drive sequence shown in Fig. 7 to the X electrode driver 51 and the Y electrode driver 53. And a panel driver comprising an address driver 55. That is, the drive control circuit 56 sequentially drives the drive corresponding to the reset step R, the selective write address step Ww, and the sustain step I in the first subfield SF1 within the one field (one frame) display period as shown in FIG. Supply various control signals to the panel driver. In addition, in each of the subfields SF2~SF14, supplies various control signals to carry out the driving in sequence according to the selective erasing addressing process W _D and the sustaining process I for the panel drivers respectively. In addition, only after the last subfield SF14 within the one-field display period, after execution of the sustain step I, the drive control circuit 56 sends various control signals to the panel driver to sequentially perform the drive according to the erase step E. FIG. Supply.

The panel driver, i.e., the X electrode driver 51, the Y electrode driver 53, and the address driver 55, according to various control signals supplied from the drive control circuit 56, various drive pulses as shown in FIG. Is generated and supplied to the column electrodes D, the row electrodes X and Y of the PDP 50.

In FIG. 8, only the operations in the first subfield SF1, the subsequent subfield SF2 and the last subfield SF14 among the subfields SF1 to SF14 shown in FIG.

First, in the first half of the reset step R of the subfield SF1, the Y electrode driver 53 has a positive reset having a waveform having a gentle transition of potential at the leading edge over time compared to the sustain pulse described later. Pulse RP _Y1 is applied to all the row electrodes Y _{1 to} Y _n . The peak potential of the reset pulse RP _Y1 is higher than that of the sustain pulse. At this time, the address driver 55 sets the column electrodes D _{1 to} D _m in the state of the ground potential (0 V). _Upon application of the reset pulse RP _Y1 , a first reset discharge is caused between the row electrode Y and the column electrode D in each of all the discharge cells PC. That is, in the first half of the reset step R, a voltage is applied between the two electrodes such that the row electrode Y is at the anode side and the column electrode D is at the cathode side, whereby a current flows from the row electrode Y toward the column electrode D (hereinafter, “column on the cathode side”). Discharge ”as the first reset discharge. According to this first reset discharge, wall charges having negative polarity near the row electrode Y in all the discharge cells PC (hereinafter, abbreviated as "negative wall charge") and wall charges having positive polarity near the column electrode D ( Hereinafter, abbreviated as " positive wall charge " Further, in the first half of the resetting process R, the X electrode driver 51, and the same polarity as such a reset pulse RP _Y1, also, prevent the surface discharge from the row electrodes X and Y cross according to the application of the reset pulse RP _Y1 A reset pulse RP _X having a possible peak potential is applied to all of the row electrodes X _{1 to} X _n, respectively.

Next, in the latter half of the reset step R of the subfield SF1, the Y electrode driver 53 has a reset pulse having a negative polarity in which the potential transition at the leading edge part over time elapses (hereinafter, referred to as a "negative polarity reset pulse"). RP _Y2 is generated and applied to all the row electrodes Y _{1 to} Y _n . In the second half of the reset step R, the X electrode driver 51 has the first base pulse BP1 having the first base potential V _B1 as the peak potential of positive polarity while the reset pulse RP _Y2 is applied to the row electrode Y. ⁺ Is applied to each of the row electrodes X _{1 to} X _n . That is, the X-electrode driver 51 applies the first base pulse BP1 ⁺ , which has the highest potential of the pulse as the first base potential V _B1 as shown in FIG. 8, to the preceding electrode X. FIG. With the application of these negative reset pulses RP _Y2 and the positive first base pulse BP1 ⁺ , these second reset discharges cause a second reset discharge between the row electrodes X and Y in all the discharge cells PC. Most of the wall charges formed in the vicinity of each of the row electrodes X and Y in the discharge cell PC are erased. As a result, the pre-discharge cell PC is initialized to a state in which a small amount of negative wall charges near the row electrode X and a small amount of positive wall charges near the row electrode Y are current, that is, in an OFF mode. In addition, with the application of the reset pulse RP _Y2 , a weak discharge is caused also between the row electrode Y and the column electrode D in all the discharge cells PC, and a part of the positive wall charges formed near the column electrode D is erased. do. Thereby, the wall charge remaining in the vicinity of the column electrode D of all the discharge cells PC is adjusted to an amount capable of causing the selective write address discharge correctly in the selective write address step W _W described later.

Further, the voltage applied between the electrodes X and Y by the reset pulse RP2 and the first base pulse BP1 ⁺ takes into account the wall charges formed near each of the row electrodes X and Y in response to the first reset discharge, and thus the row electrode X Is a voltage which can surely cause the second reset discharge between Y and Y. Further, the peak potential of the negative reset pulse RP _Y2 is, it is set to the write scan pulse SP _W is higher than the peak potential of the potential, that is close to the potential 0 V of the negative polarity, which will be described later. That is, when the peak potential of the reset pulse RP _Y2 is lower than the peak potential of the write scan pulse SP _W , strong discharge is caused between the row electrode Y and the column electrode D, and the wall charges formed near the column electrode D are greatly increased. This is because the address discharge in the selective write address step Ww becomes unstable. On the other hand, the peak potential V _B1 of the first base pulse BP1 + is higher than the peak potential V _B2 of the second base pulse BP2 ⁺ described later.

Next, in the selective write address step Ww of the subfield SF1, the Y electrode driver 53 simultaneously applies the base pulse BP ⁻ having the negative peak potential as shown in FIG. 8 to the row electrodes Y _{1 to} Y _n . In addition, the write scan pulse SP _W having the negative peak potential is sequentially applied to each of the row electrodes Y _{1 to} Y _n . At this time, the X electrode driver 51 continuously applies the second base pulse BP2 ⁺ having the second base potential V _B2 as the positive peak potential to the row electrodes X _{1 to} X _n . In other words, the X electrode driver 51 applies the second base pulse BP2 ⁺ whose pulse maximum potential becomes the second base potential V _B2 as shown in Fig. 8 to the preceding electrode X. At this time, the peak potential V _B2 of the second base pulse BP2 ⁺ is lower than the peak potential V _B1 of the first base pulse BP1 ⁺ . The voltage applied between the row electrodes X and Y by the second base pulse BP2 ⁺ and the base pulse BP ⁻ is lower than the discharge start voltage of the discharge cell PC.

Further, in the selective write address step W _W , the address driver 55 first converts the pixel drive data bits corresponding to the subfield SF1 into pixel data pulses DP having pulse voltages corresponding to the logic level. For example, the address driver 55 converts the pixel drive data bits of logic level 1 for setting the discharge cell PC to the ON mode, into pixel data pulses DP having a positive peak potential. On the other hand, the pixel drive data bits of logic level 0 to set the discharge cell PC to the OFF mode are converted to the pixel data pulse DP of the low voltage OV. The address driver 55 then applies such pixel data pulses DP to the column electrodes D _{1 to} D _m in synchronization with the application timing of each write scan pulse SP _W by one display line (m). At this time, a selective write address discharge is caused between the column electrode D and the row electrode Y in the discharge cell PC to which the high voltage pixel data pulse DP to be set in the ON mode is simultaneously applied with the write scan pulse SP _W. In addition, after such selective write address discharge, a weak discharge also occurs between the row electrodes X and Y in the discharge cell PC. That is, after the write scan pulse SPW is applied, a voltage corresponding to the base pulse BP ^- and the second base pulse BP2 ⁺ is applied between the row electrodes X and Y, but this voltage is lower than the discharge start voltage of each discharge cell PC. Since it is set to, only the application of such a voltage does not cause discharge in the discharge cell PC. However, when such selective write address discharge is caused, it is caused by this selective write address discharge, and only the application of voltage by the base pulse BP ^- and the second base pulse BP2 ⁺ causes the discharge between the row electrodes X and Y. . The discharge cell PC has positive wall charges near the row electrode Y, negative wall charges near the row electrode X, and negative wall charges near the column electrode D by the discharge and the selective write address discharge. It is set to the formed state, that is, the ON mode. Meanwhile, as described above, the selective write address discharge is performed between the column electrode D and the row electrode Y in the discharge cell PC to which the low-voltage (0 V) pixel data pulse DP to be set in the OFF mode is simultaneously applied with the write scan pulse SP _W. It is not caused, and therefore, no discharge occurs between the row electrodes X and Y. Therefore, this discharge cell PC maintains the state up to just before, that is, the state of the OFF mode initialized in the reset process R. As shown in FIG.

Next, in the sustain step I of the subfield SF1, the Y electrode driver 53 generates a sustain pulse IP having a positive peak potential by one pulse, and simultaneously applies it to each of the row electrodes Y ₁ to Y _n . . At this time, the X electrode driver 51 sets the row electrodes X _{1 to} X _n to the state of the ground potential (0 V), and the address driver 55 sets the column electrodes D _{1 to} D _m to the ground potential (0 V). Set to). In response to the application of the sustain pulse IP, sustain discharge is caused between the row electrodes X and Y in the discharge cell PC set to the ON mode as described above. The light irradiated from the phosphor layer 17 is irradiated to the outside through the front transparent substrate 1 in accordance with such sustain discharge, so that one display of light emission corresponding to the luminance weight of the subfield SF1 is performed. In addition, according to the application of the sustain pulse IP, discharge is caused even between the row electrode Y and the column electrode D in the discharge cell PC set to the ON mode. By this discharge and the sustain discharge, negative wall charges are formed in the vicinity of the row electrode Y in the discharge cell PC, and positive wall charges are formed in the vicinity of each of the row electrode X and the column electrode D, respectively. After the application of the sustain pulse IP, the Y electrode driver 53, as shown in Fig. 8, has a wall charge control pulse CP having a peak potential of negative polarity in which the potential transition at the leading edge over time elapses. Is applied to the row electrodes Y ₁ to Y _n . As a result of the application of the wall charge adjustment pulse CP, a weak erase discharge is caused in the discharge cell PC causing the sustain discharge as described above, and a part of the wall charges formed therein is erased. Thereby, the amount of wall charges in the discharge cell PC is adjusted to an amount that can cause the selective erase address discharge correctly in the next selective erase address stroke W _D.

Next, in the selective erasing address step Wo of each of the subfields SF2 to SF14, the Y electrode driver 53 applies a base pulse BP ⁺ having a predetermined peak potential of positive polarity to each of the row electrodes Y _{1 to} Y _n . As shown in Fig. 8, the erase scan pulse SP _D having the peak negative polarity is applied sequentially to each of the row electrodes Y _{1 to} Y _n . In addition, the potential of the base pulse BP ⁺ is set to a potential capable of preventing erroneous discharge between the row electrodes X and Y during the execution period of this selective erasing address step Wo. In addition, during the execution of the selective erasing address step Yo, the X electrode driver 51 sets each of the row electrodes X _{1 to} X _n to the ground potential (0 V). Further, in the selective erasing addressing process W _D, the address driver 55 first converts a pixel drive data bit corresponding to the subfield SF into the pixel data pulse DP having a pulse voltage according to logic levels. For example, the address driver 55 converts the pixel drive data bits of logic level 1 for transitioning the discharge cell PC from the ON mode to the OFF mode, into a pixel data pulse DP having a positive peak potential. do. On the other hand, when the pixel drive data bit of logic level 0 which is to maintain the current state of the discharge cell PC is supplied, it is converted into the pixel data pulse DP of low voltage (0V). The address driver 55 applies these pixel data pulses DP to the column electrodes D _{1 to} D _m in synchronization with the application timing of the write erase scan pulse SP _D for each display line (m). At this time, a selective erase address discharge is caused between the column electrode D and the row electrode Y in the discharge cell PC to which the positive pixel data pulse DP is applied at a high voltage at the same time as the erase scan pulse SP _D. By such an erase address discharge, the discharge cell PC is set to a state where positive wall charges are formed in the vicinity of each of the row electrodes Y and X, and negative wall charges are formed in the vicinity of the column electrode D, that is, in the OFF mode. On the other hand, the selective erase address discharge as described above is not caused between the column electrode D and the row electrode Y in the discharge cell PC to which the low voltage (0 V) pixel data pulse DP is applied at the same time as the erase scan pulse SP _D. Therefore, this discharge cell PC maintains the state (ON mode, OFF mode) just before that.

Next, in the sustain step I of each of the subfields SF2 to SF14, the X electrode driver 51 and the Y electrode driver 53 alternately show the luminance of the subfield in the row electrodes X and Y as shown in FIG. The number of times (even number of times) corresponding to the weight is repeated, and a sustain pulse IP having a positive peak potential is applied to each of the row electrodes X _{1 to} X _n and Y _{1 to} Y _n . Each time such a sustain pulse IP is applied, sustain discharge is caused between the row electrodes X and Y in the discharge cell PC set to the ON mode. In response to such sustain discharge, light irradiated from the phosphor layer 17 is irradiated to the outside through the front transparent substrate 10 so that display light emission corresponding to the luminance weight of the subfield SF is performed. At this time, the negative wall charges, the row electrodes X, and the column electrodes D are located near the conduction pole Y in the discharge cell PC in which the sustain discharge is caused in accordance with the sustain pulse IP finally applied in the sustain stroke I of each of the subfields SF2 to SF14. In each vicinity, positive wall charges are formed. After the application of the last sustain pulse IP, the Y electrode driver 53 has a wall charge adjustment pulse CP having a negative peak potential with a slow potential transition at the leading edge as shown in FIG. 8. Is applied to the row electrodes Y _{1 to} Y _n . In response to the application of the wall charge adjustment pulse CP, a weak erase discharge is caused in the discharge cell PC causing the sustain discharge as described above, and a part of the wall charges formed therein is erased. Thereby, the amount of wall charges in the discharge cell PC is adjusted to an amount that can cause the selective erase address discharge correctly in the next selective erase address stroke W _D.

At the end of the final subfield SF14, the Y electrode driver 53 applies the erasing pulse EP having the negative peak potential to all the row electrodes Y _{1 to} Y _n . According to the application of the erase pulse EP, erase discharge is caused only to the discharge cells PC that were in the ON mode. Due to such erase discharge, the discharge cells PC which are in the ON mode state transition to the OFF mode state.

The above driving is executed based on the fifteen pixel driving data GD as shown in FIG. According to this driving, as shown in Fig. 6, except for the case where the luminance level 0 is expressed (first gradation), first, a write address discharge is caused in each discharge cell PC in the first subfield SF1 (2). In the circle), this discharge cell PC is set to the ON mode. Thereafter, a selective erase address discharge is caused (indicated by black circles) only in the selective erase address stroke Wo of one subfield in each of the subfields SF2 to SF14, and the discharge cell PC is then set to the OFF mode. That is, each discharge cell PC is set to the ON mode in each successive subfield by the minute corresponding to the intermediate luminance to be expressed, and repeatedly causes light emission accompanying the sustain discharge by the number of times assigned to each of these subfields. (Indicated by a white circle). At this time, luminance corresponding to the total number of sustain discharges caused in one field (or one frame) display period is observed. Therefore, according to the 15 kinds of light emission patterns by the first to fifteenth gradation driving as shown in Fig. 6, the intermediate luminance of 15 gradations corresponding to the total number of sustain discharges caused in each of the subfields represented by the back circle is Is expressed. According to such driving, since the areas in which the light emission patterns (lighted state, unlit state) invert each other are not mixed in one screen in the first field display period, pseudo contours generated in such a state are prevented.

In the driving as shown in Fig. 8, the number of sustain pulses IP to be applied in the sustain step I of each of the subfields SF2 to SF14 is made even. Therefore, immediately after the end of each sustain step I, negative wall charges are formed in the vicinity of the row electrode Y and positive wall charges are formed in the vicinity of the column electrode D. _{In D} , thermal side anode discharge becomes possible. Therefore, only the positive pulse is applied to the column electrode D, and the high cost of the address driver 55 can be prevented.

In the driving shown in Figs. 7 and 8, after setting each discharge cell PC to the ON mode in the first subfield SF1, each discharge cell PC is applied only to one subfield in each of the following subfields SF2 to SF14. The so-called selective erasing address method is employed to make the transition to the OFF mode.

However, when driving the PDP 50, a light emission driving sequence based on the selective write address method shown in Fig. 9 may be employed instead of the selective erase address method shown in Fig. 7.

At this time, the drive control circuit 56 controls various types of driving according to each of the write address step W _W , the sustain step I and the erase step E in order in each of the subfields SF1 to SF14 as shown in FIG. 9. Supply the signal to the panel driver. In addition, the drive control circuit 56 supplies the panel driver with various control signals for sequentially performing the drive according to the reset step R before the selective write address step W _W only in the first subfield SF1.

The panel driver (X electrode driver 51, Y electrode driver 53, and address driver 55) generate various drive pulses as shown in FIG. 10 in accordance with various control signals supplied from the drive control circuit 56 to generate the PDP 50. Are supplied to the column electrodes D, the row electrodes X and Y.

In FIG. 10, only the operations in the first subfield SF1, the subsequent subfield SF2, and the last subfield SF14 in the subfields SF1 to SF14 shown in FIG. 9 are shown. In Fig. 10, the operations in each of the reset step R and the selective write address step W _W of the subfield SF1 are the same as those shown in Fig. 8, and thus description thereof is omitted.

First, in the sustain step of the leading subfield SF1, the Y electrode driver 53 generates a sustain pulse IP having a positive peak potential by one pulse and applies it to each of the row electrodes Y _{1 to} Y _n simultaneously. At this time, the X electrode driver 51 sets the row electrodes X _{1 to} X _n to the state of the ground potential (0 V), and the address driver 55 sets the column electrodes D ₁ to D _m to the ground potential (0 V). Set to). In response to the application of the sustain pulse IP, sustain discharge is caused between the row electrodes X and Y in the discharge cell PC set to the ON mode. In response to such sustain discharge, light irradiated from the phosphor layer 17 is irradiated to the outside through the front substrate 10, whereby one display of light emission corresponding to the luminance weight of the subfield SF1 is performed. In addition, in response to the application of the sustain pulse IP, discharge occurs between the row electrode Y and the column electrode D in the discharge cell PC set to the ON mode. This discharge and the sustain discharge form negative wall charges in the vicinity of the row electrode Y in the discharge cell PC, and positive wall charges in the vicinity of each of the row electrode X and the column electrode D, respectively.

Next, in the erasing stroke E of each of SF1 to SF14, the Y electrode driver 53 carries out a negative erasing pulse EP having the same waveform as the reset pulse RP _Y2 applied in the second half of the reset stroke R. _It is applied to _1- Y _n . At this time, the X electrode driver 51 applies the base pulse BP ⁺ having a predetermined peak potential of positive polarity to each of all the row electrodes X _{1 to} X _n , similarly to the second half of the reset step R. FIG. According to this erase pulse EP and base pulse BP ⁺ , a weak erase discharge is caused in the discharge cell PC in which such sustain discharge is caused. This erase discharge erases a part of the wall charges formed in the discharge cell PC, and the discharge cell PC transitions to the OFF mode state. Further, with the application of the erase pulse EP, a weak discharge is caused also between the column electrode D and the row electrode Y in the discharge cell PC. With such a positive wall charge-discharge is formed around the column electrodes D, it is adjusted into a quantity capable of causing the in selective write address discharge correctly in the next selective writing addressing process W _W of.

Next, in the sustain step I of each of the subfields SF2 to SF14, the X electrode driver 51 and the Y electrode driver 53 alternately show the luminance of the subfield in the row electrodes Y and X, as shown in FIG. The number of times corresponding to the weight is repeated, and a sustain pulse IP having a positive peak potential V _SUS and a pulse width W _b is applied to the row electrodes Y _{1 to} Y _n and X _{1 to} X _n . Each time such a sustain pulse IP is applied, sustain discharge is caused between the row electrodes X and Y in the discharge cell PC set to the ON mode. In response to the sustain discharge, light emitted from the phosphor layer 17 is irradiated to the outside through the front transparent substrate 10, thereby displaying display light for the number of times corresponding to the luminance weight of the subfield SF. The total number of sustain pulses IP applied in each sustain step I is odd. That is, in each sustain step I, the first sustain pulse IP and the last sustain pulse IP are applied to the row electrode Y together. Therefore, immediately after the end of each sustain step I, negative wall charges are formed in the vicinity of the row electrode Y in the discharge cell PC where the sustain discharge is caused, and positive wall charges are formed in the vicinity of each of the row electrode X and the column electrode D, respectively. Thereby, the formation state of the wall charge in each discharge cell PC becomes the same as just after completion | finish of the 1st reset discharge in reset stroke R. As shown in FIG. Therefore, in the erasing step E performed immediately thereafter, the state of all the discharge cells PC is turned off by applying the erasing pulse EP having the same waveform as the reset pulse RP _Y2 applied in the second half of the reset step R to the row electrode Y. You can transition to the state of the mode.

Then, by causing the selective write address discharge in the selective write address process Ww for each of the consecutive subfields from the beginning, the (N + 1) gray scale (N: subfield within the one-field display period is the same as the driving shown in FIG. Is displayed. That is, the intermediate luminance display for 15 gradations is performed by the 14 subfields SF1 to SF14 as shown in FIG.

Further, according to the driving based on the selective write address method as shown in Figs. 9 and 10, ^2N gradation is performed by the combination method of the subfields causing the selective write address discharge in all the subfields within one field display period. Intermediate luminance of minutes (N: number of subfields in one field display period) can be expressed. That is, in the 14 subfields SF1 to S14, since there are 2 ¹⁴ combination patterns of the subfields causing the selective write address discharge, intermediate luminance display of 16384 gray levels is possible.

In addition, according to the driving shown in Fig. 10, since the reset pulse RP _Y2 applied to the row electrode Y in the reset step R and the erase pulse EP applied to the row electrode Y in the erase step E are the same waveform, both are common. Can be generated as a circuit. Further, the sub-fields in each of the SF1~SF14 due to the selective writing addressing process W _W About one embodiment, a circuit for generating a scan pulse and sufficient for one system, Each of the selective writing addressing process W _W, the column electrode side It is sufficient to cause a general thermal side anode discharge as the anode.

Therefore, in driving the PDP 50, when driving based on the selective write address method as shown in Figs. 9 and 10 is adopted, driving based on the selective erase address method shown in Figs. In comparison with the case, it is possible to construct a panel driver for generating various drive pulses at low cost.

In the driving shown in Figs. 7 and 8 or 9 and 10, in the first subfield SF1, first, all discharge cells PC are reset and initialized to OFF mode to perform black display (luminance level 0). Except in the case, a write address discharge is caused for each discharge cell PC and is made to transition to the ON mode. At this time, when black display is performed by such driving, the discharge caused through one field display period becomes only the reset discharge in the first subfield SF1. Accordingly, the number of discharges caused within one field display period is compared with the case of employing a drive that causes the selective discharge address discharge to reset all the discharge cells and initialize them to the ON mode and then transition them to the OFF mode. Becomes less. Therefore, according to such driving, it becomes possible to improve contrast, so-called dark contrast, when displaying a dark image.

In the driving shown in Figs. 7 and 8 or 9 and 10, the voltage between the two electrodes is applied by applying a voltage having the column electrode D as the cathode side and the row electrode Y as the anode side in the reset step R of the first subfield SF1. The column-side cathode discharge, in which current flows from the row electrode Y toward the column electrode D, is caused as the first reset discharge. Therefore, during the first reset discharge, when the cation in the discharge gas is directed to the column electrode D, it collides with the MgO crystal as the secondary electron emission material contained in the phosphor layer 17 as shown in FIG. Secondary electrons are emitted from the MgO crystals. In particular, in the PDP 50 of the plasma display device shown in FIG. 1, by exposing the MgO crystals to the discharge space as shown in FIG. 5, the probability of collision with the cation is increased, and the secondary electrons are efficiently released into the discharge space. I'm going to let you. Therefore, since the discharge start voltage of the discharge cell PC becomes low by the priming action | action by such secondary electrons, it becomes possible to generate relatively weak reset discharge. Therefore, since the light emission luminance according to the discharge decreases due to the weakening of the reset discharge, display with improved dark contrast is possible.

In the driving shown in Fig. 8 or 10, the first reset discharge is formed on the side of the row electrode Y and the back substrate 14 formed on the front transparent substrate 10 side as shown in Fig. 3. It is caused between the column electrodes D. Therefore, as compared with the case where reset discharge is caused between the row electrodes X and Y formed on the front transparent substrate 10 side, discharge light emitted to the outside from the front transparent substrate 10 side is reduced, Furthermore, the cancer contrast can be improved.

In the drive shown in Fig. 8 or 10, following the first reset discharge, each discharge cell is applied by applying the first base pulse BP1 ⁺ to the previous electrode X while applying the reset pulse RP _Y2 to the previous electrode Y. The second reset discharge for erasing the wall charges in the PC is caused, and all the discharge cells PC are initialized to the OFF mode state. At this time, the peak potential V _B1 of the first base pulse BP1 ⁺ applied to the row electrode X to cause such a second reset discharge is applied to the row electrode X at the selective write address step W _W immediately after the reset step R. The electric potential is higher than the peak potential V _B2 of the second base pulse BP2 ⁺ . That is, the voltage applied between the row electrodes X and Y by the first base pulse BP1 ⁺ and the reset pulse RP _Y2 becomes a relatively high voltage, and the discharge intensity of the second reset discharge becomes large. Therefore, according to the application of these first base pulses BP1 ⁺ and the reset pulse RP _Y2 , a second reset discharge is caused as a discharge for erasing wall charges, but there is a small amount of negative polarity in the vicinity of the row electrode X in all the discharge cells PC. A small amount of positive wall charge remains in the wall charge and in the vicinity of the row electrode Y.

Therefore, in the selective write address step Ww immediately after the reset step R, as shown in Fig. 8 or 10, the positive second base pulse BP2 ⁺ is applied to the row electrode X and the negative base pulse BP− ^. In the state where it is applied to the row electrode Y, it is difficult to cause a discharge between the row electrodes X and Y. Thus, when the pixel data pulse DP of 0 V is applied to the column electrode D while applying the negative write scan pulse SP _W to the row electrode Y so that the discharge cell PC is set to the OFF mode in the selective write address step Ww. In this case, erroneous discharge between the row electrodes X and Y is prevented.

In the driving shown in Fig. 8 or 10, in the sustain step I of the subfield SF1 having the smallest luminance weight, the sustain pulse IP is applied only once, so that the number of sustain discharges is made only once and the low luminance image is applied. To improve the display reproducibility. Furthermore, after the end of the sustain discharge caused by this one sustain pulse IP, negative wall charges are formed in the vicinity of the row electrode Y, and positive wall charges are formed in the vicinity of the column electrode D, respectively. Thus, when driving shown in Fig. 8, in the selective erasing address step W _W of the subfield SF2, the discharge is made with the column electrode D on the anode side between the column electrode D and the row electrode Y (hereinafter referred to as “column side anode”. Discharge ”) as a selective erase address discharge.

In addition, in the PDP 50 shown in FIG. 1, not only in the magnesium oxide layer 13 formed on the front transparent substrate 10 side in each discharge cell PC but also on the back substrate 14 side. In the magnesium layer 17, CL-emitting MgO crystals as secondary electron emission materials are also included.

Hereinafter, the effect by employing such a configuration will be described with reference to FIGS. 11 and 12.

FIG. 11 shows a reset pulse as shown in FIG. 8 in a so-called conventional PDP in which the CL-emitting MgO crystals are included only in the magnesium oxide layer 13 in each of the magnesium oxide layer 13 and the phosphor layer 17 as described above. It is a figure which shows the change of the discharge intensity in the thermal side cathode discharge which arises when RP _Y1 is applied.

On the other hand, Fig. 2 shows a column-side cathode caused when a reset pulse RPY1 is applied to the PDP 50 according to the present invention in which the CL luminescent MgO crystals are included in both the magnesium oxide layer 13 and the phosphor layer 17. It is a figure which shows the change of the discharge intensity in discharge.

As shown in Fig. 11, according to the conventional PDP, relatively strong thermal side cathode discharge continues over 1 [ms] in accordance with the application of the reset pulse RP _Y1 , but according to the PDP 50 according to the present invention, As shown in Fig. 6, the thermal cathode discharge ends within 0.04 [ms]. That is, compared with the conventional PDP, the discharge delay time in the column-side cathode discharge can be significantly shortened.

Therefore, if the potential transition in the rising period as shown in Fig. 8 causes reset-side pulse RP _Y1 having a gentle waveform to the row electrode Y of the PDP 50 to cause column-side cathode discharge, then the potential of the reset pulse RP _Y1 is increased. The discharge ends before the peak potential is reached. Therefore, the column-side cathode discharge is terminated at the stage where the voltage applied between the row electrode and the column electrode is low, and as shown in FIG. 12, the discharge intensity is significantly lower than in the case of FIG.

In other words, for example, the reset pulse RP _Y1 having a gentle waveform of rising potential, as shown in Fig. 8, includes the CL-emitting MgO crystals in the phosphor layer 17 as well as the magnesium oxide layer 13. By applying to the PDP 50, the heat-side cathode discharge, which further weakens the discharge intensity, is caused. Therefore, since the side-side cathode discharge, which is extremely weak in discharge intensity, can be caused as a reset discharge, it is possible to increase the contrast of the image, especially the dark contrast when displaying a dark image.

The waveform at the time of rising in the reset pulse RP _Y1 is not limited to the one with a constant tendency as shown in FIG. 8, and may change gradually over time as shown in FIG. 13, for example.

In the reset step R shown in FIG. 8 or 10, reset discharges are caused to all pixel cells at once, but the reset discharges may be distributed in time for each pixel self block composed of a plurality of pixel cells. .

In the embodiment shown in Fig. 5, MgO crystals are included in the phosphor layer 17 provided on the back substrate 14 side of the PDP 50. However, as shown in Fig. 14, the particles are made of phosphor particles. The phosphor layer 17 may be formed by stacking the phosphor particle layer 17a and the secondary total emission layer 18 made of the secondary electron emission material. At this time, as the secondary electron emission layer 18, a crystal made of a secondary electron emission material (for example, MgO crystal including CL light-emitting MgO crystal) may be formed on the entire surface of the phosphor particle layer 17a. The secondary electron emission material may be formed by thin film formation.

[Example 2]

Fig. 15 is a diagram showing a schematic configuration of a plasma display device for driving a plasma display panel according to the driving method according to the second embodiment of the present invention.

The PDP 50 of the plasma display device shown in Fig. 15 is the same as the PDP 50 of the plasma display device shown in Fig. 1, that is, has a structure as shown in Figs. In addition, the X electrode driver 51, the Y electrode driver 53, and the address driver 55 of the plasma display apparatus shown in FIG. 15 also perform the same operations as those shown in FIG. However, in the plasma display device shown in FIG. 15, the driving method of the PDP 50 implemented by the drive control circuit 560 is different from that shown in FIG.

That is, the drive control circuit 560 shown in Fig. 15 uses the 4-bit multi-gradation pixel data PD _S obtained by performing the above-described error diffusion processing and dither processing on 8-bit pixel data for each pixel, According to the data conversion table as shown in Fig. 16, conversion is made to 14-bit pixel drive data GD. The drive control circuit 560 associates the first to fourteenth bits in the pixel drive data GD with each of the subfields SF1 to SF14, respectively, and uses the number of bit digits corresponding to the subfield SF as the pixel drive data bits. It is supplied to the address driver 55 by one display line (m pieces).

In addition, the drive control circuit 560 supplies various control signals for driving the PDP 50 having the above structure in accordance with the light emission drive sequence as shown in Fig. 17 to the X electrode driver 51 and the Y electrode driver 53. And address driver 55, respectively. That is, the drive control circuit 560 drives the drive according to each of the first reset step R1, the first selective write address step W1 _W and the micro light emission step LL in the first subfield SF1 in one field (one frame) display period. Various control signals to be executed sequentially are supplied to the panel driver. In SF2 subsequent to this subfield SF1, the panel driver is supplied with various control signals for sequentially driving in accordance with the second reset step R2, the second selective write address step W2 _W, and the sustain step I, respectively. In addition, supplies various control signals to the respective sub-fields SF3~SF14, so as to carry out driving according to the selective erasing addressing process W _D and the sustaining process I, respectively in sequence to the panel driver. In addition, only after the last subfield SF14 in one field display period, after execution of the sustain step I, the drive control circuit 560 supplies the panel driver with various control signals for driving in accordance with the erase step E. FIG.

The panel driver, i.e., the X electrode driver 51, the Y electrode driver 53, and the address driver 55, generate various drive pulses as shown in Fig. 18 in accordance with various control signals supplied from the drive control circuit 56. It generates and supplies to the column electrodes D, the row electrodes X and Y of the PDP 50.

In FIG. 18, only the operation | movement in SF1-SF3 and the last subfield SF14 among the subfields SF1-SF14 shown in FIG.17 is shown and shown.

First, in the first half of the first reset step R1 of the subfield SF1, the Y-electrode driver 53 receives a positive reset pulse RP1 _Y1 having a waveform having a gentle transition in the leading edge over time as compared with the sustain pulse. It is applied to all the row electrodes Y ₁ ~Y _n. 18, the peak potential at the reset pulse RP1 _Y1 is higher than the peak potential of the sustain pulse. At this time, the address driver 55 sets the column electrodes D _{1 to} D _m in the state of the ground potential (0 V). Upon application of the reset pulse RP1 _Y1 , a first reset discharge is caused between the row electrode Y and the column electrode D in each of all the discharge cells PC. That is, in the first half of the first reset step R1, a current flows from the row electrode Y toward the column electrode D by applying a voltage between the two electrodes such that the row electrode Y is at the anode side and the column electrode D is at the cathode side (hereinafter, “ Thermal side cathode discharge ”) as the first reset discharge. According to this first reset discharge, negative wall charges are formed in the vicinity of the row electrode Y in all the discharge cells PC, and positive wall charges are formed in the vicinity of the column electrode D. FIG.

In addition, in the first half of the first resetting process R1, the X electrode driver 51, and the same polarity as such a reset pulse RP1 _Y1, In addition, the reset pulse RP1 surface discharge between the row electrodes X and Y in accordance with the application of _Y1 A reset pulse RP _X having a peak potential that can be prevented is applied to all of the row electrodes X _{1 to} X _n, respectively.

In the second half of the first reset step R1 of the subfield SF1, the Y electrode driver 53 has a pulse waveform that gradually decreases in potential over time and reaches a negative peak potential as shown in FIG. A reset pulse RP1 _Y2 is generated and applied to all the row electrodes Y ₁ to Y _n . At this time, according to the application of the reset pulse RP1 _Y2 , a second reset discharge is caused between the row electrodes X and Y in all the discharge cells PC. In addition, the peak potential of the reset pulse RP1 _Y2 considers the wall charges formed near each of the row electrodes X and Y in accordance with the first reset discharge, thereby causing the second reset discharge certainly between the row electrodes X and Y. It is the lowest potential that can be made. In addition, the peak potential of the reset pulse RP1 _Y2 is set to a potential higher than the peak potential of the negative write scan pulse SP _W described later, that is, a potential close to 0V. That is, when the peak potential of the reset pulse RP1 _Y2 is lower than the peak potential of the write scan pulse SP _W , strong discharge is caused between the row electrode Y and the column electrode D, and the wall charges formed near the column electrode D are largely erased. This is because the address discharge in the first selective write address step W1 _W described later becomes unstable. By the second reset discharge caused in the second half of the first reset step R1, the wall charges formed near each of the row electrodes X and Y in each discharge cell PC are erased, and all the discharge cells PC are initialized to the OFF mode. do. In addition, a weak discharge also occurs between the row electrode Y and the column electrode D in all the discharge cells PC according to the application of the reset pulse RP1 _Y2 , and part of the positive wall charge formed near the column electrode D is caused by this discharge. is erased, the amount is adjusted to that it is possible to cause the selective write address discharge correctly in the first selective writing addressing process W1 _W.

Next, in the first selective writing addressing process W1 _W of the sub-field SF1, Y electrode driver 53 applies the base pulse BP having a predetermined peak potential of negative polarity as shown in Figure 18 ^- the row electrodes Y ₁ ~ While simultaneously being applied to Y _n , it is sequentially applied to each of the write scan pulse SP _W row electrodes Y _{1 to} Y _n having a negative peak potential in sequence. At this time, the X electrode driver 51 applies a voltage of 0 V to each of the row electrodes X _{1 to} X _n . Further, in the first selective write address step W1 _W , the address driver 55 first generates a pixel data pulse DP corresponding to the logic level of the pixel drive data bit corresponding to the subfield SF1. For example, the address driver 55 generates a pixel data pulse DP having a positive peak potential when a pixel drive data bit of logic level 1 for setting the discharge cell PC to the ON mode is supplied. On the other hand, the pixel data pulse DP of low voltage (0 V) is generated in accordance with the pixel drive data bit of logic level 0 to set the discharge cell PC to the OFF mode. The address driver 55 then applies such pixel data pulses DP to the column electrodes D _{1 to} D _m in synchronization with the application timing of each write scan pulse SP _W by one display line (m). At this time, a selective write address discharge is caused between the column electrode D and the row electrode Y in the discharge cell PC to which the high-voltage pixel data pulse DP to be set to the ON mode is simultaneously applied with the write scan pulse SP _W. Further, just after such selective write address discharge, a weak discharge is also caused between the row electrodes X and Y in this discharge cell PC. That is, after the write scan pulse SP _W is applied, a voltage according to the base pulse BP ⁻ is applied between the row electrodes X and Y, but since this voltage is set to a voltage lower than the discharge start voltage of each discharge cell PC, The application of such a voltage alone does not cause discharge in the discharge cell PC. However, when the selective write address discharge is caused, it is caused by the selective write address discharge, and the discharge is caused between the row electrodes X and Y only by application of the voltage by the base pulse BP ⁻ . By this discharge and the selective write address discharge, the discharge cell PC has positive wall charges near the row electrode Y, negative wall charges near the row electrode X, and negative wall charges near the column electrode D. It is set to each formed state, that is, ON mode. On the other hand, at the same time as the write scan pulse SP _W , the selective write address as described above is provided between the column electrode D and the row electrode Y in the discharge cell PC to which the low-voltage (0 V) pixel data pulse DP to be set in the OFF mode is applied. No discharge is caused, and therefore, no discharge occurs between the row electrodes X and Y. Therefore, this discharge cell PC maintains the state up to just before, that is, the state of the OFF mode initialized in the reset process R. As shown in FIG.

Next, in the microluminescence stroke LL of the subfield SF1, the Y electrode driver 53 applies a microluminescence pulse LP having a predetermined peak potential of positive polarity to each of the row electrodes Y _{1 to} Y _n as shown in FIG. do. In response to the application of the microluminescence pulse LP, a discharge (hereinafter referred to as "micro-emitting discharge") is caused between the column electrode D and the row electrode Y in the discharge cell PC set to the ON mode. That is, in the microluminescence stroke LL, discharge is caused between the row electrodes Y and the column electrodes in the discharge cell PC, but is set to the ON mode by applying a potential to the row electrodes Y that does not cause the discharge between the row electrodes X and Y. The micro luminescence discharge is caused only between the column electrode D and the row electrode Y in the discharge cell PC. At this time, the peak potential of the minute light emission pulse LP is a potential lower than the peak potential of the sustain pulse IP applied in the sustain step I after the subfield SF2 described later. For example, the row electrode Y in the selective erasing address step W _D described later. It is equal to the potential applied to. As shown in Fig. 18, the rate of change over time in the rising section of the potential in the micro-light emitting pulse LP is higher than the rate of change in the rising section in the reset pulses RP1 _Y1 and RP2 _Y1 . That is, by making the potential transition in the leading edge of the micro light emitting pulse LP steeper than the potential transition in the leading edge of the reset pulse, a stronger discharge is caused than the first reset discharge caused by the first reset stroke R1. Here, as described above, the sustain discharge caused between the row electrodes X and Y is because the discharge is caused by the micro-emitting pulse LP whose column potential is lower than that of the sustain pulse IP, as described above. Luminous luminance due to the discharge is lower than that described later. That is, in the micro-light emission stroke LL, the discharge is accompanied by light emission at a higher luminance level than the first reset discharge, but the discharge is lower than the sustain discharge, which is lower in luminance level, that is, microscopic light emission that can be used for display. This causes the accompanying discharge as a micro luminescent discharge. At this time, the selective write address discharge is caused between the column electrode D and the marching pole Y in the discharge cell PC in the first selective write address step W1 _W performed just before the micro light emission stroke LL. Therefore, in the subfield SF1, the luminance corresponding to the gradation higher in luminance by one level than the luminance level 0 is expressed by the light emission accompanying the selective write address discharge and the light emission associated with the micro light emission discharge.

Further, after the light emission discharge, negative wall charges are formed near the row electrode Y, and positive wall charges are formed near the column electrode D, respectively.

Next, in the first half of the second reset step R2 of the subfield SF2, the Y electrode driver 53 has a positive reset pulse having a waveform having a gentle transition in the leading edge over time as compared with the sustain pulse described later. RP2 _Y1 is applied to all the row electrodes Y _{1 to} Y _n . 18, the peak potential of reset pulse RP2 _Y1 is higher than the peak potential of reset pulse RP1 _Y1 . At this time, the address driver 55 sets the column electrodes D _{1 to} D _m in the state of the ground potential (0 V), and the X electrode driver 51 applies the row electrodes X and the row in response to the application of the reset pulse RP2 _Y1 . A positive reset pulse RP2 _X having a peak potential capable of preventing surface discharge between Y is applied to each of the row electrodes X _{1 to} X _n . If no surface discharge occurs between the row electrodes X and Y, the X electrode driver 51 applies all the row electrodes X _{1 to} X _n to the ground potential (0) instead of applying the reset pulse RP2 _X. V) may be set. In response to the application of the reset pulse RP2 _Y1 , between the row electrode Y and the column electrode D in the discharge cell PC in which no column-side cathode discharge is caused in the microluminescence stroke LL in each of the discharge cells PC, A first reset discharge, which is weaker than the column side cathode discharge, is caused. That is, in the first half of the second reset step R2, the voltage of the two electrodes is applied between the two electrodes such that the row electrode Y is at the anode side and the column electrode D is at the cathode side. Cause as 1 reset discharge. On the other hand, in the discharge cell PC in which the micro light emission discharge is already caused in the micro light emission stroke LL, even if the reset pulse RP2 _Y1 is applied, no discharge is caused. Thus, the end of the first half of the second reset step R2 Thereafter, negative wall charges are formed in the vicinity of the row electrode Y in all the discharge cells PC, and positive wall charges are formed in the vicinity of the column electrode D. FIG.

In the second half of the second reset step R2 of the subfield SF2, as shown in Fig. 18, the Y electrode driver 53 has a pulse waveform that gradually decreases in potential over time and reaches a negative peak potential. The reset pulse RP2 _Y2 is applied to the row electrodes Y _{1 to} Y _n . In the second half of the second reset step R2, the X electrode driver 51 has a first base potential V _B1 as the peak potential of positive polarity while the reset pulse RP2 _Y2 is being applied to the row electrode Y. The base pulse BP1 ⁺ is applied to each of the row electrodes X _{1 to} X _n . That is, the X-electrode driver 51 applies the first base pulse BP1 ⁺ , which is the first base potential V _B1 , to the previous electrode X as shown in FIG. 18. Application of these negative reset pulses RP2 _Y2 and positive first base pulse BP1 ⁺ causes a second reset discharge between the row electrodes X and Y in all the discharge cells PC. By this second reset discharge, the placenta of wall charges formed in the vicinity of each of the row electrodes X and Y in all the discharge cells PC is erased. As a result, the pre-discharge cell PC is initialized to a state in which a small amount of negative wall charges remain near the row electrode X, and a small amount of positive wall charges remain near the row electrode Y, that is, in the OFF mode. In addition, with the application of the reset pulse RP2 _Y2 , a weak discharge is caused also between the row electrode Y and the column electrode D in all the discharge cells PC, and part of the positive wall charges formed near the column electrode D is erased. . As a result, the wall charges remaining around the column electrodes D in the vicinity of the discharge cell PC, the is adjusted into a quantity capable of causing the in selective write address discharge correctly in the second selective writing addressing process W2 _W.

In addition, the voltage applied between the row electrodes X and Y by the reset pulse RP2 _Y2 and the first base pulse BP1 ⁺ is determined in consideration of the wall charges formed near each of the row electrodes X and Y in response to the first reset discharge. It is the voltage that can surely cause the second reset discharge between the electrodes X and Y. The negative peak potential at the reset pulse RP2 _Y2 is set to a potential higher than the peak potential of the negative write scan pulse SP _W described later, that is, a potential close to 0V. That is, when the peak potential of the reset pulse RP2 _Y2 is lower than the peak potential of the write scan pulse SP _W , strong discharge is caused between the row electrode Y and the column electrode D, and the wall charges formed near the column electrode D are greatly increased. is erased, the second selective write address discharge in the address process W2 _W becomes unstable due to the. In addition, the peak potential V _B1 of the first base pulse BP1 ⁺ is higher than the peak potential V _B2 of the second base pulse BP2 ⁺ described later.

Next, in the subfield SF2 of the second selective writing addressing process W2 _W In, Y electrode driver 53 applies the base pulse BP having a predetermined peak potential of negative polarity as shown in Figure 18 ^- the row electrodes Y ₁ ~ While simultaneously applying to Y _n , the write scan pulse SP _W having the negative peak potential is sequentially applied to each of the row electrodes Y _{1 to} Y _n . At this time, the X electrode driver 51 continues to apply the second base pulse BP2 ⁺ having the second base potential V _B2 as the positive peak potential to the row electrodes X ₁ to X _n . That is, the X-electrode driver 51 applies the second base pulse BP2 ⁺ , which is the second base potential V _B2 , to the preceding electrode X as shown in FIG. 18. The peak potential V _B2 of the second base pulse BP2 ⁺ is lower than the peak potential V _B1 of the first base pulse BP1 ⁺ . The row electrode is formed by the second base pulse BP2 ⁺ and the base pulse BP ⁻ . The voltage applied between X and Y is lower than the discharge start voltage of the discharge cell PC. Further, in the second selective write address step W2 _W , the address driver 55 first generates a pixel data pulse DP having a peak potential corresponding to the logic level of the pixel drive data bit corresponding to the subfield SF2. For example, the address driver 55 generates a pixel data pulse DP having a positive peak potential when a pixel drive data bit of logic level 1 for setting the discharge cell PC to the ON mode is supplied. On the other hand, the pixel data pulse DP of low voltage (0 V) is generated in accordance with the pixel drive data bit of logic level 0 to set the discharge cell PC to the OFF mode. The address driver 55 then applies such pixel data pulses DP to the column electrodes D _{1 to} D _m in synchronization with the application timing of each write scan pulse SP _W by one display line (m pieces). At this time, a selective write address discharge is caused between the column electrode D and the row electrode Y in the discharge cell PC to which the high-voltage pixel data pulse DP to be set to the ON mode is simultaneously applied with the write scan pulse SP _W. Further, just after such selective write address discharge, a weak discharge is also caused between the row electrodes X and Y in this discharge cell PC. That is, after the write scan pulse SP _W is applied, a voltage corresponding to the base pulse BP ⁻ and the second base pulse BP 2 ⁺ is applied between the row electrodes X and Y, but this voltage is the discharge start voltage of each discharge cell PC. Since the voltage is set lower than this, the application of such a voltage alone does not cause discharge in the discharge cell PC. However, if the selective write address discharge is caused, the selective write address discharge is caused to cause a base pulse BP ^- and Discharge is caused between the row electrodes X and Y only by applying the voltage by the second base pulse BP2 ⁺ . The discharge cell PC has positive wall charges near the row electrode Y, negative wall charges near the row electrode X, and negative wall charges near the column electrode D by the discharge and the selective write address discharge. It is set to the formed state, that is, the ON mode. On the other hand, as described above, between the column electrode D and the row electrode Y in the discharge cell PC to which the low-voltage (0 V) pixel data pulse DP to which the write scan pulse SP _W is set to the OFF mode is applied, as described above. No discharge is caused, and therefore, no discharge occurs between the row electrodes X and Y. Therefore, this discharge cell PC maintains the state up to just before, ie, the OFF mode initialized in the 2nd reset process R2.

Next, in the sustain step I of the subfield SF2, the Y electrode driver 53 generates a sustain pulse IP having a positive peak potential by one pulse and applies it to each of the row electrodes Y ₁ to Y _n simultaneously. At this time, the X electrode driver 51 sets the row electrodes X _{1 to} X _n to the state of the ground potential (0 V), and the address driver 55 sets the column electrodes D _{1 to} D _m to the ground potential (0 V). Set to). In response to the application of the sustain pulse IP, sustain discharge is caused between the row electrodes X and Y in the discharge cell PC set to the ON mode. In response to such sustain discharge, light irradiated from the phosphor layer 17 is irradiated to the outside through the front transparent substrate 10, whereby one display of light emission corresponding to the luminance weight of the subfield SF1 is performed. In addition, according to the application of the sustain pulse IP, discharge is caused even between the row electrode Y and the column electrode D in the discharge cell PC set to the ON mode. By such discharge and sustain discharge, negative wall charges are formed in the vicinity of the row electrode Y in the discharge cell PC, and positive wall charges are formed in the vicinity of each of the row electrode X and the column electrode D, respectively.

Next, in the selective erasing address step Wo of each of the subfields SF3 to SF14, the Y electrode driver 53 applies a base pulse BP ⁺ having a predetermined peak potential of positive polarity to each of the row electrodes Y ₁ to Y _n . An erase scan pulse SP _D having a negative peak potential as shown in FIG. 18 is sequentially applied to each of the row electrodes Y _{1 to} Y _n . In addition, the peak potential of the base pulse BP ⁺ is set to a potential capable of preventing mis-discharge between the row electrodes X and Y during the execution period of this selective erasing address step Wo. In addition, during the execution period of the selective erasing address step Wo, the X electrode driver 51 sets each of the row electrodes X _{1 to} X _n to the ground potential (0 V). Further, in the selective erasing addressing process W _D, the address driver 55 first converts a pixel drive data bit corresponding to the subfield SF into the pixel data pulse DP having a peak potential corresponding to logic levels of . For example, the address driver 55 converts the pixel drive data bits of logic level 1, which should cause the discharge cell PC to transition from the ON mode to the OFF mode, to a pixel data pulse DP having a positive peak potential. do. On the other hand, when a pixel drive data bit of logic level 0 to maintain the current state of the discharge cell PC is supplied, it is converted into a pixel data pulse DP of low voltage (0 V). The address driver 55 then applies such pixel data pulses DP to the column electrodes D _{1 to} D _m in synchronization with the application timing of each erase scan pulse SP _{D for} each display line (m). At this time, at the same time as the erase scan pulse SP _D , a selective erase address discharge is caused between the column electrode D and the row electrode Y in the discharge cell PC to which the high voltage pixel data pulse DP is applied. By this selective erasing address discharge, the discharge cell PC is set to the OFF mode in a state where positive wall charges are formed near each of the row electrodes Y and X, and negative wall charges are formed near the column electrode D, respectively. On the other hand, the selective erase address discharge as described above is not caused between the column electrode D and the row electrode Y in the discharge cell PC to which the low-voltage (0 V) pixel data pulse DP is applied at the same time as the erase scan pulse SP _D. Therefore, this discharge cell PC maintains the state (ON mode, OFF mode) just before that.

In the sustain step I of each of the subfields SF3 to SF14, the X electrode driver 51 and the Y electrode driver 53 alternately show the row weights Y and X of the luminance weight of the subfield, as shown in FIG. Is repeated a number of times corresponding to, and a sustain pulse IP having a positive peak potential is applied to the row electrodes Y _{1 to} Y _n and X _{1 to} X _n . Each time such a sustain pulse IP is applied, sustain discharge is caused between the row electrodes X and Y in the discharge cell PC set to the ON mode. Light emitted from the phosphor layer 17 is irradiated to the outside through the front transparent substrate 10 in response to such sustain discharge, so that display light emission for the number of times corresponding to the luminance weight of the subfield SF is performed.

After the end of the sustain step I of the final subfield SF14, the Y electrode driver 53 applies the erasing pulse EP having the negative peak potential to all the row electrodes Y _{1 to} Y _n . With the application of the erase pulse EP, erase discharge is caused only in the discharge cell PC in the ON mode state. By such erase discharge, the discharge cells PC in the ON mode state transition to the OFF mode state.

The above driving is executed based on the 16 pixel drive data GD as shown in FIG.

First, as shown in Fig. 16, the discharge cell PC is set to ON mode only in SF1 in the subfields SF1 to SF14 as shown in Fig. 16 in the second gradation that shows higher brightness by one step than one gradation that expresses black display (luminance level 0). Causes the selective write address discharge to be discharged, and the discharge cell PC set to the ON mode is caused to emit a small light emission (indicated by?). At this time, the luminance level at the time of light emission according to these selective write address discharges and the micro-emission discharge is lower than the luminance level at the time of light emission according to one sustain discharge. Therefore, when the luminance level observed by the sustain discharge is set to "1", the luminance corresponding to the luminance level "α" lower than the luminance level "1" is expressed in the second tone.

Next, in the third gradation which exhibits higher luminance by one step than the second gradation, selective write address discharge is caused to set the discharge cell PC to ON mode only in SF2 in the subfields SF1 to SF14 (indicated by double circles). In the next subfield SF3, a selective erase address discharge for causing the discharge cell PC to transition to the OFF mode is caused (indicated by a black circle). Therefore, in the third gradation, light emission is performed according to the sustain discharge for one time only in the sustaining stroke I of SF2 in the subfields SF1 to SF14, and the luminance corresponding to the luminance level "1" is expressed.

Next, in the fourth gradation that exhibits higher luminance by one step than the third gradation, first, in the subfield SF1, the selective write address discharge for setting the discharge cell PC to ON mode is caused, and thus the gradation is set to this ON mode. The discharge cell PC is micro-light discharged (indicated by?).

Further, in the fourth gradation, the selective write address discharge for setting the discharge cell PC to ON mode is caused only in SF2 of the subfields SF1 to SF14 (indicated by double circles), and the discharge cell PC in the next subfield SF3. Causes a selective erase address discharge to transition to the OFF mode (indicated by black circles). Therefore, in the fourth gray scale, light emission of the luminance level "α" is performed in the subfield SF1, and sustain discharge accompanied with light emission of the luminance level "1" is performed in SF2 by one time, so that the luminance level "α" + The luminance corresponding to "1" is expressed.

Further, in each of the fifth to sixteenth grayscales, a selective write address discharge for setting the discharge cell PC to the ON mode is generated in the subfield SF1, and the discharge cell PC set to the ON mode is caused to emit light emission (in?). Display). Then, only one subfield corresponding to the gray level generates a selective erase address discharge for transitioning the discharge cell PC to the OFF mode (indicated by black circles). Therefore, in each of the fifth to sixteenth gradations, the micro-luminescent discharge is caused in the subfield SF1, and a sustain discharge is caused once in SF2, and then each successive subfield by the number corresponding to the gradation (white Sustain discharge is caused by the number of times assigned to the subfield. Thereby, in each of the fifth to sixteenth tones, the luminance corresponding to the luminance level "α" + "the total number of sustain discharges caused in the display period of one field (or one frame)" is observed. Therefore, according to the driving shown in Figs. 16 to 18, the luminance range of the luminance levels "0" to "255 + α" can be represented in 16 steps as shown in Fig.16.

At this time, in the driving shown in Figs. 16 to 18, the discharge contributes to the display image in the subfield SF1 having the smallest luminance weight, so that the micro-luminescence discharge is caused instead of the sustain discharge. Since the micro luminescent discharge is a discharge caused between the column electrodes D and the row electrodes Y, the luminance level at the time of light emission according to the discharge is lower than that of the sustain discharge caused between the row electrodes X and Y. Therefore, in the case where high brightness is exhibited (second gradation) by one level from the black display (luminance level 0) by such micro luminescence discharge, the luminance difference from the luminance level 0 is smaller than that in the case of displaying it by the sustain discharge. Therefore, the gradation expression ability at the time of expressing a low brightness image becomes high. In addition, in the second gradation, since no reset discharge is caused in the second reset step R2 of SF2 subsequent to the subfield SF1, the decrease in dark contrast due to this reset discharge is suppressed. Further, in the driving shown in Fig. 16, even in each of the gradations after the fourth gradation, the micro luminescence discharge accompanying light emission of the luminance level? Is caused in the subfield SF1, but in the gradations after the third gradation, the micro luminescence is performed. You may not cause a discharge. That is, since the light emission accompanying the micro-luminescence discharge is extremely low luminance (luminance level α), the luminance of the luminance level α is used in the gradation after the fourth gradation in which the combination with the sustain discharge accompanied with high luminance emission is performed. This is because the increase may not be visualized, and at this time, the meaning of causing the micro luminescent discharge is lost.

Here, in driving the PDP 50, a light emission driving sequence based on the selective write address method shown in FIG. 19 may be employed instead of the selective erase address method shown in FIG.

At this time, the drive control circuit 560, in the subfield SF1 at the head of the one-field (frame) display period as shown in Fig. 19, has a first reset step R1, a first selective write address step W1 _W, and a minute light emission step. The panel driver is supplied with various control signals for sequentially driving the respective LLs. Further, in the second selective writing addressing process W2 _W, sustain process I and erase process E to the panel drivers for sequentially various control signals to carry out driving according to each method, the subfields SF2~SF14 each drive control circuit 560 Supply. In addition, the drive control circuit 560, in the sub-field SF2, the supplies various control signals to carry out the driving in sequence according to the second resetting process R2 prior to the second selective writing addressing process W2 _W to the panel driver.

The panel driver, i.e., the X electrode driver 51, the Y electrode driver 53, and the address driver 55, according to various control signals supplied from the drive control circuit 560, show various drive pulses as shown in FIG. Is generated and supplied to the column electrodes D, the row electrodes X and Y of the PDP 50.

In FIG. 20, only the operations in the first subfield SF1, followed by the subfield SF2 and the last subfield SF14, are shown in the subfields SF1 to SF14 shown in FIG. 20, operations in the first reset step R1 of the subfield SF1, the first selective write address step W1 _W, and the micro light emission step LL, respectively, and the second reset step R2 of the SF2, the second selective write address step. Since the operations in W2 _W and the sustain stroke I are the same as those shown in Fig. 18, the description is omitted.

In the erasing stroke E of each of the subfields SF2 to SF14, the Y electrode driver 53 has a negative waveform having the same waveform as the reset pulse RP1 _Y2 or RP2 _Y2 applied in the second half of the first reset stroke R1 or the second reset stroke R2. The polarization erase pulse EP is applied to the row electrodes Y ₁ to Y _n . At this time, the X electrode driver 51 applies the base pulse BP ⁺ having a predetermined peak potential of positive polarity to each of all the row electrodes X _{1 to} X _n , similarly to the second half of the second reset step R2. According to this erase pulse EP and base pulse BP ⁺ , a weak erase discharge is caused in the pixel cell PC where the sustain discharge is caused as described above. By such erase discharge, a part of the wall charges formed in the pixel cell PC is erased, and the pixel cell PC transitions to the OFF mode state. Further, with the application of the erase pulse EP, a weak discharge is caused also between the column electrode D and the row electrode Y in the pixel cell PC. With such a positive wall charge-discharge is formed around the column electrodes D, it is adjusted into a quantity capable of causing the next second selective writing addressing process in the selective write address discharge correctly in the W2 _W. In each of the subfields SF3 to SF14, the second selective write address step W2 _W is performed instead of the selective erase address step W _D.

In the sustain step I of each of the subfields SF3 to SF14 shown in Fig. 20, the number of times the X electrode driver 51 and the Y electrode driver 53 alternately correspond to the luminance weight of the subfield in the row electrodes Y and X alternately. Repeating as many times as described above, a sustain pulse IP having a positive peak potential V _sus and a pulse width W _b is applied to the row electrodes Y _{1 to} Y _n and X _{1 to} X _n . Each time such a sustain pulse IP is applied, sustain discharge is caused between the row electrodes X and Y in the pixel cell PC set to the ON mode. In response to such sustain discharge, light irradiated from the phosphor layer 17 is irradiated to the outside through the front transparent substrate 10, so that display light emission for the number of times corresponding to the luminance weight of the subfield SF is performed. The total number of sustain pulses IP applied in each sustain step I is odd. That is, in each sustain step I, both the first sustain pulse IP and the last sustain pulse IP are applied to the row electrode Y. Therefore, immediately after the end of each sustain step I, negative wall charges are formed in the vicinity of the row electrode Y in the pixel cell PC where the sustain discharge is caused, and positive wall charges are formed in the vicinity of each of the row electrode X and the column electrode D, respectively. . As a result, the state of formation of the wall charges in each of the recovery cells PC becomes the same as immediately after the end of the first reset discharge in the first reset step R1 or the second reset step R2. Therefore, in the erasing step E performed immediately thereafter, the erasing pulse EP having the same waveform as the reset pulse RP1 _Y2 or RP2 _Y2 applied in the second half of the first reset step R1 or the second reset step R2 is applied to the row electrode Y. By applying, the state of all the pixel cells PC can be shifted to the state of OFF mode.

19 and 20, when the second gradation that is higher in brightness by one step than the first gradation that represents the black display (luminance level 0) is displayed, it is selected and written only in SF1 among the subfields SF1 to SF14. Cause an address discharge. As a result, the microluminescence discharge is caused as the discharge which is associated with the display image only in SF1 in each of SF1 to SF14. In addition, when the third gradation which is higher in brightness by one step than the second gradation is displayed, the selective write address discharge is caused only in SF2 in the subfields SF1 to SF14. As a result, one sustain discharge is caused as the discharge related to the display image only in SF2 in each of the subfields SF1 to SF14. After the fourth gradation, the selective write address is caused in each of the subfields SF1 and SF2, and the selective write address is caused in each successive subfield by the number corresponding to the gradation. As a result, as the discharges involved in the display image, first, micro-luminescent discharges are caused in the subfield SF1, and then sustain discharges are caused in each successive subfield by the number corresponding to the gray level. According to such driving, intermediate luminance display of 16 gradations as shown in Fig. 16 is enabled.

At this time, according to the driving shown in Figs. 19 and 20, the reset pulse RP1 _Y2 or RP2 _Y2 applied to the row electrode Y in the first reset step R1 or the second reset step R2 and the row electrode Y in the erase step E are applied. Since the erase pulse EP is the same waveform, both can be generated by a common circuit. In each of the subfields SF1 to SF14, as a method for setting the state (ON mode, OFF mode) of the pixel cell PC, only an address stroke is used for selective writing, and only one circuit is sufficient for generating a scanning pulse. . In addition, in this selective write address process, a general column side anode discharge with the column electrode side as the anode is caused.

Therefore, in the case of driving the PDP 50, the case of adopting the selective write address method as shown in Figs. 19 and 20 is compared with the case of employing the selective erase address method as shown in Figs. This makes it possible to construct a panel driver for generating various driving pulses at low cost.

In the drive shown in Fig. 17 or 19, in the first reset step R1 of the leading subfield SF1, a row electrode is applied between two electrodes by applying a voltage having the column electrode D as the cathode side and the row electrode Y as the anode side. A column-side cathode discharge flowing from Y to the column electrode D is caused as the first reset discharge. Therefore, in the first reset room display, when the cation in the discharge gas is directed to the column electrode D, the MgO crystal as the secondary electron emission material contained in the phosphor layer 17 as shown in FIG. Emit secondary electrons from the crystals. In particular, in the PDP 50, by exposing the MgO crystals to the discharge space as shown in Fig. 5, the collision probability with the cation is increased, and secondary electrons are efficiently discharged into the discharge space. That is, since the discharge start voltage of the discharge cells P is lowered by the priming action by the secondary electrons, it is possible to cause relatively weak reset discharge. Therefore, since the light emission luminance due to the discharge decreases due to the weakening of the reset discharge, display with improved dark contrast is possible.

In the driving shown in Fig. 17 or 19, the reset discharge is formed between the row electrode Y formed on the front transparent substrate 10 side as shown in Fig. 3 and the column electrode D formed on the rear substrate 14 side. Is causing. Therefore, compared with the case where the reset discharge is caused between the row electrodes X and Y formed on the front transparent substrate 10 side, the discharge discharged to the outside from the front transparent substrate 10 side is less. The contrast can be improved.

In the PDP 50 shown in Fig. 15, not only the magnesium oxide layer 13 formed on the front transparent substrate 10 side in each discharge cell PC but also the phosphor layer formed on the rear substrate 14 side. Also in (17), as shown in FIG. 5 or FIG. 14, the CL luminescent MgO crystal as a secondary electron emission material is included.

Therefore, it is possible to terminate the weak discharge in a short time as compared with the column-side cathode discharge (shown in FIG. 11) in the discharge cell in which the CL oxide light-emitting MgO crystal is included only in the magnesium oxide layer 13 (shown in FIG. 12). . Therefore, since the side-side cathode discharge having a very low discharge intensity can be caused as a reset discharge, it is possible to increase the contrast of the image, especially the dark contrast when displaying a dark image.

In the driving shown in Figs. 17 and 18 or 19 and 20, in the first subfield SF1, the discharge cell PC is initialized to the OFF mode first by resetting discharge, and black display (luminance level 0) is performed. Except in the case, a write address discharge is generated for each discharge cell PC so as to transition it to the ON mode. At this time, when black display is performed by such driving, the discharge caused through one field display period becomes only the reset discharge in the first subfield SF1. Therefore, compared with the case of employing a drive that causes a selective erase address discharge to reset all discharge cells to reset discharge, initialize it to the ON mode, and then transition it to the OFF mode state, it is caused within one field display period. The number of discharges is small. Therefore, according to such driving, it becomes possible to improve the contrast, so-called dark contrast, when displaying a dark image.

In the drive shown in Figs. 17 and 18 or 19 and 20, a voltage is applied between the two electrodes with the column electrode D as the cathode side and the row electrode Y as the anode side in the reset step R1 of the leading subfield SF1. A column-side cathode discharge through which current flows from the row electrode Y toward the column electrode D is caused as the first reset discharge. Therefore, during the first reset discharge, when the cations in the discharge gas are directed to the column electrode D, they collide with MgO crystals as secondary electron emission materials contained in the phosphor layer 17 as shown in FIG. Secondary electrons are emitted from the MgO crystals. In particular, in the PDP 50 of the plasma display device shown in FIG. 15, the collision probability with the cation is increased by exposing the MgO crystals to the discharge space as shown in FIG. That is, since the discharge start voltage of the discharge cell PC becomes low by the priming action by such secondary electrons, it becomes possible to cause relatively weak reset discharge. Therefore, since the light emission luminance due to the discharge decreases due to the weakening of the reset discharge, display with improved dark contrast is possible.

18 or 20, the first reset discharge is formed on the row electrode Y formed on the front transparent substrate 10 side and on the back substrate 14 side as shown in FIG. It is caused to occur between the column electrodes D. Therefore, compared with the case where the reset discharge is caused between the row electrodes X and Y formed on the front transparent substrate 10 side, the discharge light emitted from the front transparent substrate 19 side to the outside becomes smaller. The cancer contrast can be improved.

18 or 20, in the second reset step R2 of the subfield SF2, after the first reset discharge is caused, the reset pulse RP2 _Y2 is applied to the previous electrode Y while applying the first pulse to the previous electrode X. By applying the base pulse BP1 ⁺ , a second reset discharge for erasing the wall charges in each discharge cell PC is caused, thereby initializing all the discharge cells PC in the OFF mode. At this time, the peak potential V _B1 of the first base pulse BP1 ⁺ applied to the row electrode X so as to cause such a second reset discharge is at the second selective write address step W2 _W immediately after the second reset step R2. The electric potential is higher than the peak potential V _B2 of the second base pulse BP2 ⁺ applied to the row electrode X. That is, the voltage applied between the row electrodes X and Y by the first base pulse BP1 ⁺ and the reset pulse RP2 _Y2 becomes a relatively high voltage, and the discharge intensity of the second reset discharge becomes large. Therefore, according to the application of these first base pulses BP1 ⁺ and the reset pulse RP2 _Y2 , a second reset discharge is caused as a discharge for erasing the wall charges, but there is a small amount of negative polarity near the row electrodes X in all the discharge cells PC. In the vicinity of the wall charge and the row electrode Y, a small amount of positive wall charge remains.

Thus, in the second selective writing addressing process W2 _W, Fig. 18 or, is positive the second base pulses BP2 ⁺ is to the row electrodes X are also the base pulse BP - of negative polarity as shown in Figure 20 ^- to the row electrode Y In the applied state, it is difficult to cause a discharge between the row electrodes X and Y. Thereby, the pixel data pulse DP of 0 V is applied to the column electrode D while applying the negative write scan pulse SP _W to the row electrode Y so as to set the discharge cell PC to the OFF mode in the second selective write address step W2 _W. In this case, erroneous discharge between the row electrodes X and Y is prevented.

In the driving shown in Fig. 18 or 20, in the sustaining stroke of the subfield SF1 having the smallest luminance weight, the sustain pulse IP is applied only once, so that the number of sustain discharges is set only once, so that the display reproducibility for the low luminance image is reduced. It is raising. Furthermore, after the end of the sustain discharge caused by this one sustain pulse IP, negative wall charges are formed in the vicinity of the row electrode Y, and positive wall charges are formed in the vicinity of the column electrode D, respectively. Thus, when driving shown in Fig. 18, in the selective erasing address step W _D of the subfield SF2, the discharge with the column electrode D on the anode side between the column electrode D and the row electrode Y (hereinafter referred to as "column side anode discharge"). May be caused as a selective erase address discharge. At this time, in the drive shown in Fig. 18, in the sustain step I of each of the subfields SF2 to SF14, the number of application of the sustain pulse IP is even. Therefore, immediately after the end of each sustain stroke I, the negative wall charges are formed in the vicinity of the row electrode Y and the positive wall charges are formed in the vicinity of the column electrode D. Therefore, the selective erasure address stroke performed after each sustain step I is performed. in W _D, the column side anode discharge is possible. Therefore, only the positive pulse is applied to the column electrode D, and the high cost of the address driver 55 can be avoided.

Example 3

Fig. 21 is a diagram showing a schematic configuration of a plasma display device for driving a plasma display panel according to the driving method according to the third embodiment of the present invention.

The PDP 50 of the plasma display device shown in Fig. 21 is the same as the PDP 50 of the plasma display device shown in Fig. 1, that is, has a structure as shown in Figs. 21, the operation of each of the Y electrode driver 53, the address driver 55, and the drive control circuit 56 in the plasma display device is the same as that shown in FIG. That is, the drive control circuit 56 controls various kinds of control signals for driving the PDP 50 in accordance with the light emission drive sequence shown in FIG. 7 when the selective erasing address method is employed and when the selective writing address method is adopted. Are supplied to the panel driver (X electrode driver 51a, Y electrode driver 53, address driver 55).

When the selective erase address method is adopted, the panel driver generates various drive pulses as shown in FIG. 22 for each of the subfields SF1 to SF14 in accordance with the light emission drive sequence shown in FIG. D, row electrodes X and Y. On the other hand, when the selective write address method is adopted, the panel driver generates various drive pulses as shown in FIG. 23 for each of the subfields SF1 to SF14 in accordance with the light emission drive sequence shown in FIG. To column electrodes D, row electrodes X and Y.

In Fig. 22, the applying operation in each of the subfields SF2 to SF14, and the applying operation in the first half of the reset step R and the sustain step I of the subfield SF1 are the same as those shown in Fig.8. 23, the application operation in each of the subfields SF2 to SF14 and the first half of the reset step R of the subfield SF1, the sustain step I and the erasing step E are the same as those shown in FIG.

That is, in Fig. 22 (or Fig. 23), the first base pulses BP1a ⁺ and SF1 applied to the row electrodes X at the second half of the reset step R of the subfield SF1 are applied to the row electrodes X in the selective writing address step Ww of SF1. The other driving pulses except for the two base pulses BP2a ⁺ are the same as those shown in Fig. 8 (or Fig. 10).

Therefore, in Fig. 22 (or Fig. 23), only the driving pulse applied to each of the second half of the reset step R of SF1 and the selective write address step Ww of SF1 will be described, and the operation thereof will be described.

In the second half of the reset step R, the Y electrode driver 53 _applies all of the row electrodes to the negative reset pulse RP _Y2 having a slow potential transition at the leading edge portion as time elapses, as shown in FIG. 22 or FIG. Applies to Y. At this time, the X electrode driver 51a applies the first base pulse BP1a ⁺ having the positive peak potential as the highest potential of the pulse to the preceding electrode X. Application of these first base pulses BP1a ⁺ and reset pulse RP _Y2 causes a second reset discharge in all the discharge cells. By this second reset discharge, all the discharge cells are initialized to the OFF mode. Further, according to the application of the reset pulse RP _Y2 , a weak discharge is caused also between the row electrode Y and the column electrode D in all the discharge cells PC, and a part of the positive wall charges formed near the column electrode D is erased. do. As a result, the wall charge remaining in the vicinity of the column electrode D of all the discharge cells PC is adjusted to an amount that can cause the selective write address discharge correctly in the selective write address step Vw.

Then, over the execution period of the selective write address step Ww immediately after the reset step R, the X electrode driver 51a is the first base pulse BP1a of qualitative as the highest potential of the pulse as shown in FIG. 22 or FIG. The second base pulse BP2a ⁺ having a positive peak potential higher than ⁺ is applied to the previous electrode X. Further, in this selective write address step Ww, the Y electrode driver 53 simultaneously applies the base pulse BP ⁻ having the negative peak potential as shown in Fig. 22 or 23 to the row electrodes Y _{1 to} Y _n . In addition, the write scan pulse SP _W having the negative peak potential is sequentially applied to each of the row electrodes Y _{1 to} Y _n . At this time, the address driver 55 generates the pixel data pulse DP of positive voltage with respect to the discharge cell PC to be set to the ON mode, the pixel data pulse DP of 0 V with respect to the discharge cell PC to be set to the OFF mode, This is applied to the column electrode D by one display line in synchronization with the application timing of the write scan pulse SP _W. At this time, a selective write address discharge is caused between the column electrode D and the row electrode Y in the discharge cell PC to which the high voltage pixel data pulse DP to which the high voltage pixel data pulse DP is set to be in the ON mode simultaneously with the write scan pulse SP _W. Further, just after such selective write address discharge, a weak discharge is also caused between the row electrodes X and Y in this discharge cell PC. That is, after the write scan pulse SP _W is applied, a voltage corresponding to the base pulse BP ^- and the second base pulse BP2a ⁺ is applied between the row electrodes X and Y, but this voltage is higher than the discharge start voltage of each discharge cell PC. Since it is set to a low voltage, application of such a voltage alone does not cause discharge in the discharge cell PC. However, when the selective write address discharge is caused, it is caused by the selective write address discharge, and only a slight discharge is caused between the row electrodes X and Y only by applying the voltage by the base pulse BP ⁻ and the second base pulse BP2a ⁺ . Due to such a weak discharge and the selective write address discharge, the discharge cell PC has positive wall charges near the row electrode Y, negative wall charges near the row electrode X, and negative wall charges near the column electrode D. Are respectively formed, that is, set to the ON mode.

Here, in the driving shown in Fig. 22 or 23, the second base pulse BP2a ⁺ having a peak potential higher than the first base pulse BP1a ⁺ so as to surely cause the weak discharge as described above immediately after the selective write address discharge. Is applied to the row electrode X.

That is, in a high resolution PDP, i.e., a PDP having a large number of pixels in one screen, an unevenness in discharge intensity between each pixel compared to a PDP having a small number of pixels, in particular, a counter discharge between the row electrodes Y and the column electrodes D in each discharge cell. The nonuniformity of discharge intensity becomes large. Therefore, depending on the nonuniformity of discharge intensity for each discharge cell, there may be a discharge cell PC in the PDP 50 which causes selective write address discharge with a low discharge intensity. In such a discharge cell PC, it is difficult to surely cause the weak discharge as described above immediately after the selective write address discharge.

Thus, the selective writing address discharge is generated by applying the FIG. 22 or the driving as shown in Figure 23, the selective write address step Ww second base pulse BP2a ⁺ row electrodes X the above classic than that of the first base pulse BP1a ⁺ throughout the execution period The discharge cells which become weak discharges are surely caused to have weak discharges.

Example 4

Fig. 24 is a diagram showing a schematic configuration of a plasma display device for driving a plasma display panel according to the driving method according to the fourth embodiment of the present invention.

The PDP 50 of the plasma display device shown in Fig. 24 has the same structure as that of the PDP 50 of the plasma display device shown in Fig. 15, that is, as shown in Figs. The operations of the Y electrode driver 53, the address driver 55, and the drive control circuit 560 in the plasma display device shown in FIG. 24 are also the same as those shown in FIG. That is, the drive control circuit 560 controls various kinds of controls for driving the PDP 50 in accordance with the light emission drive sequence shown in FIG. 17 when the selective erasing address method is adopted and FIG. 19 when the selective write address method is employed. The signal is supplied to the panel driver (X electrode driver 51b, Y electrode driver 53, address driver 55).

When the selective erase address method is adopted, the panel driver generates various drive pulses as shown in FIG. 25 for each of the subfields SF1 to SF14 in accordance with the light emission drive sequence shown in FIG. 17, and generates the column electrodes of the PDP 50. D, row electrodes X and Y. On the other hand, when the selective write address method is adopted, the panel driver generates various drive pulses as shown in FIG. 26 for each of the subfields SF1 to SF14 in accordance with the light emission drive sequence shown in FIG. 19, and the PDP 50 To column electrodes D, row electrodes X and Y.

25, the application operation in each of the subfields SF1 and SF3 to SF14, the first half of the second reset step R2 of the subfield SF2, and the application operation in the sustain step I are the same as those shown in FIG. In FIG. 26, the application operation in each of the subfields SF1 and SF3 to SF14 and the first half of the second reset step R2, the sustain step I and the erasing step E of the subfield SF2 are the same as those shown in FIG. same.

In Fig. 25 (or Fig. 26), the first base pulse BP1b ⁺ applied to the row electrode X at the second half of the second reset step R2 of SF2 and the second selective write address step W2 _W of SF2 are applied to the row electrode X. The other driving pulses except for the second base pulse BP2b ⁺ are the same as those shown in Fig. 18 (or Fig. 20).

In the following, only the driving pulses applied to each of the second half of the second reset step R2 of SF2 and the second selective write address step W2 _W of SF2 will be described, and the application operation thereof will be described.

In the second half of the second reset step R2 of the subfield SF2, as shown in FIG. 25 or 26, the Y electrode driver 53 has a negative reset pulse having a slow potential transition at the leading edge over time. RP2 _Y2 is applied to the row electrode Y. At this time, the X electrode driver 51b applies the first base pulse BP1b ⁺ having the positive peak potential as the highest potential of the pulse to the previous electrode X. Application of these first base pulses BP1b ⁺ and reset pulse RP2 _Y2 causes a second reset discharge in all the discharge cells. By this second reset discharge, all the discharge cells are initialized to the OFF mode. Further, according to the application of the reset pulse RP2 _Y2 , a weak discharge is caused also between the row electrode Y and the column electrode D in all the discharge cells PC, and the part of the positive wall charges formed near the column electrode D is erased. do. As a result, it is adjusted to the available amount of the wall charge amount remaining in the vicinity of column electrodes D in the discharge cells PC, causing the second selective writing addressing process in the selective write address discharge correctly in the W2 _W.

Then, over the execution period of the second selective write address step W2 _W immediately after the second reset step R2, the X electrode driver 51b has a peak potential higher than that of the first base pulse BP1b ⁺ . As shown in Fig. 26, the second base pulse BP2b ⁺ having a positive peak potential as the highest potential of the pulse is applied to the preceding electrode X. Further, in the second selective write address step W2 _W , the Y electrode driver 53 applies a base pulse BP ^- having a negative peak potential as shown in FIG. 25 or 26 to the row electrodes Y _{1 to} Y _n . While simultaneously applying, the write scan pulse SP _W having the negative peak potential is sequentially applied to the conducting poles Y ₁ to Y _n . At this time, the address driver 55 generates the pixel data pulse DP of positive voltage with respect to the discharge cell PC to be set to the ON mode, the pixel data pulse DP of 0 V with respect to the discharge cell PC to be set to the OFF mode, This is applied to the column electrode D by one display line in synchronization with the application timing of the write scan pulse SP _W. At this time, a selective write address discharge is caused between the column electrode D and the row electrode Y in the discharge cell PC to which the high-voltage pixel data pulse DP to be set to the ON mode is simultaneously applied with the write scan pulse SP _W. Further, immediately after such selective write address discharge, a weak discharge is also caused between the row electrodes X and Y in the discharge cell PC. That is, after the write scan pulse SP _W is applied, a voltage corresponding to the base pulse BP ^- and the second base pulse BP2b ⁺ is applied between the row electrodes X and Y, but this voltage is lower than the discharge start voltage of each discharge cell PC. Since the voltage is set, the application of this voltage alone does not cause discharge in the discharge cell PC. However, when the selective write address discharge is caused, it is caused by the selective write address discharge, and a weak discharge is caused even between the row electrodes X and Y only by application of the voltage by the base pulse BP ⁻ and the second base pulse BP 2 ⁺ . . By the weak discharge and the selective write address discharge, the discharge cell PC has positive wall charges near its row electrode Y, negative wall charges near its row electrode X, and negative wall charges near its column electrode D. It is set to each formed state, that is, ON mode.

Here, in the driving shown in FIG. 25 or FIG. 26, in the second selective write address administration W2 _W , higher than the first base pulse BP1b ⁺ so as to surely cause the weak discharge as described above immediately after the selective write address discharge. A second base pulse BP2b ⁺ having a peak potential is applied to the row electrode X.

That is, high resolution PDP. That is, in the PDP having a large number of pixels in one screen, the nonuniformity of the discharge intensity between each pixel, in particular, the nonuniformity of the discharge intensity in the counter discharge between the row electrode Y and the column electrode D in each discharge cell in comparison with the PDP having a small number of pixels. Will grow. Therefore, there is a case where there is a discharge cell PC in the PDP 50 that causes a selective write address discharge with a low discharge strength to be caused by the variation in discharge intensity for each discharge cell. In such a discharge cell PC, it is difficult to reliably cause the weak discharge as described above immediately after the selective write address discharge.

Therefore, in the driving as shown in Fig. 25 or Fig. 26, in the second selective writing addressing process, selected by applying the first base pulse BP1b ⁺ than the high potential second base pulse BP2b ⁺ throughout the execution period of W2 _W of the row electrodes X The discharge cells in which the write address discharges become weak discharges can be surely caused.

In the first reset step R1 shown in Figs. 18, 20, 25 and 26, respectively, the reset pulse RP1 _Y1 is applied to the row electrodes Y _{1 to} Y _n in the _first half to cause the first reset discharge as the column-side cathode discharge. Although it is supposed to, it may be omitted.

For example, instead of the first reset step R1 shown in Figs. 18, 20, 25 and 26, the first reset step R1 is adopted as shown in Fig. 27. That is, as shown in Fig. 27, in the first half of the first reset step R1, the row electrodes Y _{1 to} Y _n are fixed to the ground potential. That is, the purpose of the column-side cathode discharge from the row electrode Y to the column electrode D in the first half of the first reset step R1 is to discharge charged particles for stabilizing the write discharge in the first selective write address step W1 _W. . However, in the case where a structure including MgO crystals containing CL-emitting MgO crystals as disclosed in FIG. 5 or 14 in the phosphor layer is employed, the write scan discharge is more stable than in the case where such a structure is not employed. . Therefore, in the first half of the first reset step R1, it is possible to adopt a configuration that does not cause column-side cathode discharge, in which both the row electrode Y and the column electrode D are at ground potentials. In this case, the row electrode X is also set to the ground potential level as shown in FIG. Also in this case, after the end of the first reset step R1, all the discharge cells are turned off by the discharge by the erase pulse EP in the erase step E of the field immediately before the discharge and the discharge by the application of the reset pulse RP1 _Y2 . do. At this time, the column-side cathode discharge by application of the reset pulse RP2 _Y1 in the first half of the second reset step R2 shown in Figs. 18, 20, 25 and 26, respectively, is emitted by this reset discharge. The charged particles mainly act to stabilize the write discharge in the second selective write address stroke W2 _W. Therefore, if the column-side negative electrode discharge due to the application of the reset pulse RP2 _Y1 is omitted in the first half of the second reset step R2, when a write failure occurs in the second reset step R2, the sustain is performed in all subfields after the subfield SF2. It cannot be caused to discharge. Therefore, it is preferable to perform column side cathode discharge by application of reset pulse RP2 _Y1 in the first half part of 2nd reset process R2. This also applies to the first half of the reset step R shown in Figs. 8, 10, 22, and 23, respectively.

Next, another Example of this invention is described. The plasma display device for driving the plasma display panel according to the driving method according to the fifth embodiment is the same as that of the plasma display device shown in Fig. 15, and the driving control circuit 560 shown in Fig. 16 is selected according to the data conversion table shown in Fig. 16. Generates the bit conversion driving data GD. In addition, the drive control circuit 560 supplies various drive control signals for driving the PDP 50 having the above structure in accordance with the light emission drive sequence, as shown in Fig. 17, for the X electrode driver 51 and the Y electrode driver 53. And the address driver 55.

The panel driver, i.e., the X electrode driver 51, the Y electrode driver 53, and the address driver 55, according to various control signals supplied from the drive control circuit 560, show various drive pulses as shown in FIG. Is generated and supplied to the column electrodes D, the row electrodes X and Y of the PDP 50.

28 shows only the operation | movement in SF1-SF3 and the last subfield SF14 among the subfield SF1-SF14 shown in FIG.

First, in the first half of the first reset step R1 of the subfield SF1, the Y electrode driver 53 has a positive reset pulse RP1 having a waveform having a gentle transition in the leading edge over time as compared with the sustain pulse described later. _Y1 is applied to all the row electrodes Y _{1 to} Y _n . The peak potential of the reset pulse RP1 _Y1 is higher than the peak potential of the sustain pulse and is lower than the peak potential of the reset pulse RP2 _Y1 described later. At this time, the address driver 55 sets the column electrodes D _{1 to} D _m in the state of the ground potential (0 V). At this time, X-electrode driver 51, and the same polarity as such a reset pulse RP1 _Y1, The peak capable of preventing a surface discharge between the row electrodes X and Y, which due to application of the reset pulse RP1 _Y1 A reset pulse RP1 _X having a potential is applied to all of the row electrodes X _{1 to} X _n, respectively. At this time, if no surface discharge occurs between the row electrodes X and Y, the X electrode driver 51 applies all the row electrodes X _{1 to} X _n to the ground potential (0 V) instead of applying the reset pulse RP1 _X. () May be set. Here, in the first half of the first reset step R1, according to the application of the reset pulse RP1 _Y1 as described above, the first reset discharge is caused between the row electrode Y and the column electrode D in each of all the discharge cells PC. That is, in the first half of the first reset step R1, a voltage is applied between the two electrodes such that the row electrode Y is at the anode side and the column electrode D is at the cathode side, so that a current flows from the row electrode Y toward the column electrode D (hereinafter, “ Thermal side cathode discharge ”) as the first reset discharge. According to this first reset discharge, negative wall charges are formed in the vicinity of the row electrode Y in all the discharge cells PC, and positive wall charges are formed in the vicinity of the column electrode D. FIG.

Next, in the second half of the first reset step R1 of the subfield SF1, the Y-electrode driver 53 generates a negative reset pulse RP1 _Y2 having a gentle potential transition at the leading edge over time, It is applied to the row electrodes Y _{1 to} Y _n . The negative peak potential in the reset pulse RP1 _Y2 is set to a potential higher than the peak potential of the negative write scan pulse SP _W described later, that is, a potential close to 0V. That is, when the peak potential of the reset pulse RP _Y2 is lower than the peak potential of the write scan pulse SP _W , strong discharge is caused between the row electrode Y and the column electrode D, and the wall charges formed near the column electrode D are greatly increased. the discarded are erased, the first selective write address discharge in the address administration W1 _W is because the unstable. At this time, the X electrode driver 51 sets all of the row electrodes X _{1 to} X _n to the ground potential (0 V). In addition, the peak potential of the reset pulse RP1 _Y2 is the lowest potential that can surely cause vibration between the row electrodes X and Y in consideration of the wall charges formed near the row electrodes X and Y in accordance with the first reset discharge. Here, in the second half of the first reset step R1, according to the application of the reset pulse RP1 _Y2 as described above, the second reset discharge is caused between the row electrodes X and Y in all the discharge cells PC. That is, in the second half of the first reset step R1, a current flows from the column electrode D to the row electrode Y by applying a voltage between the two electrodes such that the row electrode Y is at the cathode side and the column electrode D is at the anode side (hereinafter, “ Column side anode discharge ”) as the second reset discharge. By this second reset discharge, wall charges formed near each of the row electrodes X and Y in each discharge cell PC are erased, and all the discharge cells PC are initialized to the OFF mode. Further, according to the application of the reset pulse RP1 _Y2 , weak discharge is caused between the row electrode Y and the column electrode D in all the discharge cells PC. Due to this weak discharge, part of the positive wall charges formed near the column electrode D is erased and adjusted to an amount that can cause the selective write address discharge correctly in the first selective write address step W1 _W described later. .

In this manner, in the first reset step R1, the first and second reset discharges are discharged in each discharge cell by successively applying the reset pulse RP1 _Y1 as the reset head pulse and the reset pulse RP1 _Y2 as the reset tail pulse to the preceding electrode Y. It causes sequentially, and initializes all the discharge cells to OFF mode.

Next, in the first selective write address step W1 _W of the subfield SF1, the Y electrode driver 53 supplies the base pulses BP ^- having a predetermined potential of negative polarity as shown in FIG. 28 to the row electrodes Y _{1 to} Y _n. At the same time, the write scan pulse SP _W having the negative peak potential is sequentially applied to each of the row electrodes Y _{1 to} Y _n . At this time, the address driver 55 first converts the pixel drive data bit corresponding to the subfield SF1 into a pixel data pulse DP having a pulse voltage corresponding to the logic level. For example, the address driver 55 converts the pixel drive data bits of logic level 1 for setting the discharge cell PC to the ON mode, into pixel data pulses DP having a positive peak potential. On the other hand, for the pixel drive data bit of logic level 0 which causes the discharge cell PC to be set to the OFF mode, it is converted into a pixel data pulse DP of low voltage (0 V). The address driver 55 then applies such pixel data DP to the column electrodes D _{1 to} D _m in synchronization with the application timing of each write scan pulse SP _{W for} each display line (m). At this time, a selective write address discharge is caused between the column electrode D and the row electrode Y in the discharge cell PC to which the high voltage pixel data pulse DP to be set to the ON mode is simultaneously applied with the write scan pulse SP _W. At this time, a voltage corresponding to the write scan pulse SP _W is also applied between the row electrodes X and Y. In this step, since all the discharge cells PC are in the OFF mode, that is, the wall charge is erased, such write scan pulse SP _{W is applied.} The application of does not cause discharge between the row electrodes X and Y. Therefore, in the first selective write address step W1 _W of the subfield SF1, the selective write address discharge is made only between the column electrodes D and the row electrodes Y in the discharge cell PC in response to the application of the write-order pulse SP _W and the high-voltage pixel data pulse DP. This is caused. As a result, wall charges do not exist near the row electrode X in the discharge cell PC, but positive wall charges are formed near the row electrode Y, and negative wall charges are formed near the column electrode D, respectively. On the other hand, the selective write address discharge as described above is performed between the column electrode D and the row electrode Y in the discharge cell PC to which the low-voltage (0 V) pixel data pulse DP to be set in the OFF mode is simultaneously applied with the write scan pulse SP _W. It is not caused. Therefore, this discharge cell PC maintains the state in the OFF mode initialized in the first reset step R1, that is, no discharge occurs in any of the row electrodes Y and the column electrodes D and between the row electrodes X and Y. .

Next, in the micro light emission step LL of the subfield SF1, the Y electrode driver 53 simultaneously applies the micro light emission pulse LP having a predetermined peak potential of positive polarity to the row electrodes Y _{1 to} Y _n as shown in FIG. do. In response to the application of the microluminescence pulse LP, a discharge (hereinafter referred to as "micro-emitting discharge") occurs between the column electrode D and the row electrode Y in the discharge cell PC set to the ON mode. That is, in the micro light emission stroke LL, discharge is caused between the row electrode Y and the column electrode D in the discharge cell PC, but is applied to the row electrode Y by applying a potential to the row electrode Y between the row electrodes X and Y to cause the discharge. The micro light emission discharge is caused only between the column electrodes D and the row electrodes Y in the set discharge cell PC. In this case, the peak potential of the minute light emission pulse LP is, and is lower than the peak potential of the sustain pulse IP applied in the sustaining process I after the later sub-field SF2 potential, for example, a row in the later selective erasing addressing process W _D It is equal to the base potential applied to the electrode Y. As shown in Fig. 8, the rate of change with the passage of time in the rising section of the potential in the micro-light emitting pulse LP is higher than the rate of change in the rising section in the reset pulses RP1 _Y1 and RP2 _Y1 . . That is, by making the steeper than the potential transition in the leading edge of the micro light emitting pulse LP, a discharge stronger than the first reset discharge caused by the first reset step R1 and the second reset step R1 and the second reset step R2 is generated. Here, since the discharge is a heat-side cathode discharge as described above, and is a discharge caused by the micro-luminescence pulse LP whose pulse voltage is lower than that of the sustain pulse IP, the sustain discharge generated between the row electrodes X and Y ( Luminous luminance accompanying the discharge is lower than that described later). That is, in the micro-luminescence stroke LL, discharges with light emission with a luminance level higher than that of the first reset discharges or discharges with a lower luminance level different from those discharges with sustain discharges, i.e., microscopic light emission that can be used for display are used. The accompanying discharge is caused as a micro luminescent discharge. At this time, the selective write address discharge is caused between the column electrode D and the row electrode Y in the discharge cell PC in the first selective write address step W1 _W performed just before the micro light emission step LL. Therefore, in the subfield SF1, the luminance corresponding to the gradation higher in luminance by one level than the luminance level 0 is expressed by the light emission accompanying the selective write address discharge and the light emission associated with the microluminescence discharge.

After the microluminescence discharge, negative wall charges are formed near the row electrode Y, and positive wall charges are formed near the column electrode D, respectively.

Next, in the first half of the second reset step R2 of the subfield SF2, the Y-electrode driver 53 receives a positive reset pulse RP2 _Y1 having a slow potential transition at the leading edge over time compared to the sustain pulse described later. It is applied to all the row electrodes Y ₁ ~Y _n. In addition, the peak potential of the reset pulse RP2 _Y1 is higher than the peak potential of the reset pulse RP1 _Y1 . At this time, the address driver 55 sets the column electrodes D _{1 to} D _m at the state of the ground potential (0 V), and the X electrode driver 51 performs the row electrodes according to the application of the reset pulse RP2 _Y1 . A positive reset pulse RP2 _X having a peak potential capable of preventing surface discharge between X and Y is applied to all of the row electrodes X _{1 to} X _n, respectively. If no surface discharge occurs between the row electrodes X and Y, the X electrode driver 51 sets all the row electrodes X ₁ to X _n to the ground potential (0 V) instead of applying the reset pulse RP2 _X. You may do so. In response to the application of the reset pulse RP2 _Y1 , between the row electrode Y and the column electrode D in the discharge cell PC in which no column-side cathode discharge is caused in the microluminescence stroke LL in each of the discharge cells PC, in this microluminescence stroke LL The first reset discharge which is weaker than the thermal side negative electrode discharge is caused. That is, in the first half of the second reset step R2, a voltage is applied between the two electrodes such that the row electrode Y is at the anode side and the column electrode D is at the cathode side, whereby the column-side cathode discharge flowing from the row electrode Y toward the column electrode D is recalled. This is caused by the first reset discharge. On the other hand, in the discharge cell PC in which the micro luminescent discharge has already been caused in the micro luminescent stroke LL, even when the reset pulse RP2 _Y1 is applied, no discharge is caused. Therefore, immediately after the end of the first half of the second reset step R2, negative wall charges are formed in the vicinity of the row electrode Y in all the discharge cells PC, and positive wall charges are formed in the vicinity of the column electrode D.

Next, in the subfield SF2 of the second in the second half of the resetting process R2, Y electrode driver 53, over time, performing a reset pulse RP2 _Y2 of negative polarity which the potential transition at the leading edge gradually electrodes Y ₁ ~ Is applied to Y _n . At this time, the negative peak potential of the reset pulse RP2 _Y2 is lower than the negative peak potential of the reset pulse RP1 _Y2 applied to the preceding electrode Y in the first reset step R1, as shown in FIG. It is also higher than the negative peak potential of the write scan pulse SP _W applied to the row electrode Y in the first selective write address step W1 _W. FIG.

In the second half of the second reset step R2, the X electrode driver 51 applies a base pulse BP ⁺ having a predetermined potential of positive polarity to each of the row electrodes X _{1 to} X _n . At this time, according to the application of these negative reset pulses RP2 _Y2 and the positive base pulse BP ⁺ , a second reset discharge is caused between the row electrodes X and Y in all the discharge cells PC. That is, in the second half of the second reset step R2, voltage is applied between the two electrodes such that the row electrode Y is at the cathode side and the column electrode D is at the anode side, whereby the column-side anode discharge in which current flows from the column electrode D to the row electrode Y is described. This is caused by the second reset discharge. In addition, the potentials of the reset pulses RP2 _Y2 and the base pulses BP ⁺ are certainly defined between the row electrodes X and Y in consideration of the wall charges formed near the row electrodes X and Y by the first reset discharge. 2 Lowest potential that can cause reset discharge. The negative peak potential in the reset pulse RP2 _Y2 is set to a potential higher than the peak potential of the negative write scan pulse SP _W , that is, a potential close to 0V. That is, when the peak potential of the reset pulse RP2 _Y2 is lower than the peak potential of the write scan pulse SP _W , strong discharge is caused between the row electrode Y and the column electrode D, and the wall charges formed near the column electrode D are greatly increased. it is erased, because the address discharge in the second selective writing addressing process W2 _W becomes unstable. Here, by the second reset discharge caused in the second half of the second reset step R2, the wall charges formed near each of the row electrodes X and Y in each discharge cell PC are erased, and all the discharge cells PC are turned off. The mode is initialized. In addition, the application of the reset pulse RP2 _Y2 causes a weak discharge to occur between the row electrode Y and the column electrode D in all the discharge cells PC, and the positive wall charges formed near the column electrode D are caused by such discharge. part of is erased, the amount of which is adjusted to be awoken in the selective write address discharge correctly in the second selective writing addressing process W2 _W.

In this manner, in the second reset step R2, the first and second reset discharges are discharged in each discharge cell by successively initializing the reset pulse RP2 _Y1 as the reset head pulse and the reset pulse RP2 _Y2 as the reset tail pulse to the preceding electrode Y. It causes sequentially, and initializes all the discharge cells to OFF mode.

Next, in the second selective write address step W2 _W of the subfield SF2, the Y electrode driver 53 supplies the base pulse BP ^- having the predetermined potential of negative polarity as shown in FIG. 28 to the row electrodes Y _{1 to} Y _n. At the same time, the write scan pulse SP _WW having the negative peak potential is sequentially applied to each of the row electrodes Y ₁ to Y _n . Further, as shown in Fig. 8, the negative peak potential in the write scan pulse SP _WW is negative in the write scan pulse SP _W applied to each row electrode Y in the first selective write address step W1 _W. As shown in FIG. It is lower than the peak potential of polarity. X electrode driver 51 continues even in the base pulse BP ⁺ is applied to the row electrodes X ₁ ~X _n in the second half of the resetting process R2, the second selective writing addressing process W2 _W applied to the row electrodes X ₁ ~X each _n do. The potentials of the base pulses BP ⁻ and the base pulses BP ⁺ are each set at a potential such that the voltage between the row electrodes X and Y in the non-application period of the write scan pulse SP _WW is lower than the discharge start voltage of the discharge cell PC. It is set. Further, in the second selective write address step W2 _W , the address driver 55 first converts the pixel drive data bits corresponding to the subfield SF2 into pixel data pulses DP having a pulse voltage corresponding to the logic level thereof. For example, the address driver 55 converts the pixel drive data bits of logic level 1 for setting the discharge cell PC into the ON mode, into pixel data pulses DP having a positive peak potential. On the other hand, the pixel drive data bits of logic level 0 to set the discharge cell PC to the OFF mode are converted into pixel data pulses DP of low voltage (0 V). The address driver 55 then applies such pixel data pulses DP to the column electrodes D _{1 to} D _m in synchronization with the application timing of each write scan pulse SP _{WW for} each one display line (m). At this time, a selective write address discharge is caused between the column electrode D and the row electrode Y in the discharge cell PC to which the high voltage pixel data pulse DP to which the high voltage pixel data pulse DP is set to be in the ON mode simultaneously with the write scan pulse SP _WW . Further, immediately after such selective write address discharge, a weak discharge is also caused between the row electrodes X and Y in the discharge cell PC. That is, after the write scan pulse SP _WW is applied, the base pulse BP ^{− −} is applied between the row electrodes X and Y. And the voltage according to the base pulse BP ⁺ is applied, but since this voltage is set to a voltage lower than the discharge start voltage of each discharge cell PC, the application of such voltage alone does not cause discharge in the discharge cell PC. However, when the selective write address discharge is caused, this selective write address discharge is caused to cause a discharge between the row electrodes X and Y only by applying the voltage by the base pulse BP ⁻ and the base pulse BP ⁺ . Such discharge does not occur in the first selective write address step W1 _W in which the base pulse BP ⁺ is not applied to the row electrode X. This discharge and the selective write address discharge cause the discharge cell PC to have positive wall charges near its row electrode Y, negative wall charges near its row electrode X, and negative wall charges near its column electrode D, respectively. It is set to the formed state, that is, the ON mode. On the other hand, the selective writing as described above is performed between the column electrodes D and the row electrodes Y in the discharge cell PC to which the low-voltage (0 V) pixel data pulse DP to which the write scan pulse SP _WW is set in the OFF mode is applied. No address discharge is caused, and therefore, no discharge occurs even between the row electrodes X and Y. Therefore, this discharge cell PC maintains the state up to just before, that is, the state of the OFF mode initialized in the 2nd reset process R2.

Next, in the sustain step I of the subfield SF2, the X electrode driver 53 generates a sustain pulse IP having a positive peak potential by one pulse and applies it to each of the row electrodes Y ₁ to Y _n simultaneously. At this time, the X electrode driver 51 sets the row electrodes X _{1 to} X _n at the state of the ground potential (0 V), and the address driver 55 sets the column electrodes D _{1 to} D _m at the ground potential (0 V). Set to). In response to the application of the sustain pulse IP, sustain discharge is caused between the row electrodes X and Y in the discharge cell PC set to the ON mode as described above. In response to such sustain discharge, light irradiated from the phosphor layer 17 is irradiated to the outside through the front transparent substrate 10, thereby emitting light corresponding to the luminance weight of the subfield SF1. In addition, according to the application of the sustain pulse IP, discharge is caused even between the row electrode Y and the column electrode D in the discharge cell PC set to the ON mode. This discharge and the sustain discharge form negative wall charges in the vicinity of the row electrode Y in the discharge cell PC, and positive wall charges in the vicinity of each of the row electrode X and the column electrode D, respectively. After the application of the sustain pulse IP, the Y electrode driver 53 supplies the wall charge adjustment pulse CP having a negative peak potential with a slow potential transition at the leading edge as shown in FIG. It is applied to the row electrodes Y _{1 to} Y _n . In response to the application of the wall charge adjustment pulse CP, a weak erase discharge is caused in the discharge cell PC caused by the sustain discharge as described above, and part of the wall charges formed therein is erased. Thereby, the amount of wall charges in the discharge cell PC is adjusted to an amount that can cause the selective erase address discharge correctly in the next selective erase address stroke W _D.

Next, in the selective erasing address step Wo of each of the subfields SF3 to SF14, the Y electrode driver 53 applies a base pulse BP ⁺ having a predetermined positive potential to each of the row electrodes Y _{1 to} Y _n , and FIG. 28. An erase scan pulse SP _D having a negative peak potential as shown in Fig. 2 is alternatively sequentially applied to each of the row electrodes Y _{1 to} Y _n . Further, the peak potential of the base pulse BP ⁺ is, throughout the execution period of the selective erasing addressing process W _O, is set to a potential capable of preventing erroneous discharges between the row electrodes X and Y. In addition, during the execution period of the selective erasing address step Wo, the X electrode driver 51 sets each of the row electrodes X _{1 to} X _n to the ground potential (0 V). Further, in the selective erasing addressing process W _D, the address driver 55 first converts a pixel drive data bit corresponding to the subfield SF into the pixel data pulse DP having a pulse voltage according to logic levels. For example, the address driver 55 converts the pixel drive data bits of logic level 1 which will cause the discharge cell PC to transition from the ON mode to the OFF mode, into a pixel data pulse DP having a positive peak potential. do. On the other hand, when the pixel drive data bit of logic level 0 is maintained to maintain the current state of the discharge cell PC, it is converted into a pixel data pulse DP of low voltage (0 V). The address driver 55 then applies such pixel data pulses DP to the column electrodes D _{1 to} D _m in synchronization with the application timing of each erase scan pulse SP _{D for} each display line (m). At this time, at the same time as the erase scan pulse SP _D , a selective erase address discharge is caused between the column electrode D and the row electrode Y in the discharge cell PC to which the high voltage pixel data pulse DP is applied. By this selective erasing address discharge, the discharge cell PC is set to a state where positive wall charges are formed in the vicinity of each of the row electrodes Y and X, and negative wall charges are formed in the vicinity of the column electrode D, that is, in the OFF mode. do. On the other hand, the selective erase address discharge as described above does not occur between the column electrode D and the row electrode Y in the discharge cell PC to which the low-voltage (0 V) pixel data pulse DP is applied at the same time as the erase scan pulse SP _D. Therefore, this discharge cell PC maintains the state (ON mode, OFF mode) just before that.

Next, in the sustain step I of each of the subfields SF3 to SF14, the X electrode driver 51 and the Y electrode driver 53 alternately show the luminance of the subfield in the row electrodes X and Y as shown in FIG. repeatedly by a number of minutes (even number) corresponding to the weight, and applies the sustain pulse IP X to the row electrodes Y ₁ and _{n 1} ~X ~Y _n each having a positive peak potential. Each time such a sustain pulse IP is applied, sustain discharge is caused between the row electrodes X and Y in the discharge cell PC set to the ON mode. The light emitted from the phosphor layer 17 is irradiated to the outside through the front transparent substrate 10 in accordance with the sustain discharge, thereby performing display light emission for the number of times corresponding to the luminance weight of the subfield SF. At this time, the negative wall charges, the row electrodes X, and the column electrodes D are located near the row electrodes Y in the discharge cells PC in which sustain discharges are caused in accordance with the sustain pulses IP finally applied in the sustain steps I of each of the subfields SF2 to SF14. In each vicinity, positive wall charges are formed. After the application of the last sustain pulse IP, the Y electrode driver 53 carries out a wall charge adjustment pulse CP having a negative peak potential with a slow potential change over time, as shown in FIG. _It is applied to _1- Y _n . In response to the application of the wall charge adjustment pulse CP, a weak erase discharge occurs in the discharge cell PC in which the sustain discharge is caused as described above, and part of the wall charges formed therein is erased. Thereby, the amount of wall charges in the discharge cell PC is adjusted to an amount that can cause the selective erase address discharge correctly in the next selective erase address stroke W _D.

After the end of the sustain step I of the final subfield SF14, the Y electrode driver 53 applies the erasing pulse EP having the negative peak potential to all the row electrodes Y _{1 to} Y _n . According to the application of the erase pulse EP, erase discharge is caused only to the discharge cells PC in the ON mode. Due to such erase discharge, the discharge cells PC which are in the ON mode state transition to the OFF mode state.

The above driving is executed based on the 16 kinds of pixel driving data GD as shown in FIG.

First, in the second gradation which shows brightness higher by one level than the first gradation which expresses black display (luminance level 0), as shown in FIG. 16, the discharge cell PC is set to ON mode only in SF1 of the subfields SF1 to SF14. To cause the selective write address discharge to be made, the discharge cell PC set to this ON mode is caused to emit a small light emission (indicated by?). At this time, the luminance level at the time of light emission according to these selective write address discharges and the micro-emission discharge is lower than the luminance level at the time of light emission according to one sustain discharge. Therefore, when the luminance level observed by the sustain discharge is set to "1", the luminance corresponding to the luminance level "α" lower than the luminance level "1" is expressed in the second tone.

Next, in the third gradation which shows brightness higher by one level than the second gradation, the selective write address discharge for setting the discharge cell PC to ON mode is caused only in SF2 among the subfields SF1 to SF14 (indicated by double circles). In the following subfield SF3, a selective erase address discharge for causing the discharge cell PC to transition to the OFF mode is caused (indicated by black circles). Therefore, in the third gradation, light emission associated with one sustain discharge is performed only in the sustain stroke I of SF2 in the subfields SF1 to SF14, and the luminance corresponding to the luminance level "1" is expressed.

Next, in the fourth gradation that shows higher luminance by one step than the third gradation, first, the selective write address discharge for setting the discharge cell PC to the ON mode in the subfield SF1 is caused, and the discharge set to this ON mode is caused. The cell PC is subjected to micro luminescence discharge (indicated by?). In this fourth gradation, the selective write address discharge for setting the discharge cell PC to the ON mode only in SF2 of the subfields SF1 to SF14 is caused (indicated by the double circles), and the discharge cell PC is turned off in the next subfield SF3. Causes selective erase address discharge to transition to mode (indicated by black circles). Therefore, in the fourth gradation, light emission of the luminance level "α" is performed in the subfield SF1, and sustain discharge accompanied with light emission of the luminance level "1" is performed in SF2 by one time, so that the luminance level "α" + The luminance corresponding to "1" is expressed.

Further, in each of the fifth to sixteenth gradations, the selective write address discharge for setting the discharge cell PC to the ON mode is caused in the subfield SF1, and the discharge cell PC set to the ON mode is caused to emit light emission (in?). Display). Then, only one subfield corresponding to the gray level generates a selective erase address discharge for transitioning the discharge cell PC to the OFF mode (indicated by black circles). Therefore, in each of the fifth to sixteenth grayscales, the micro-luminescent discharge is caused in the subfield SF1, and a sustain discharge for one time is caused in the SF2, and then each successive subfield by the number corresponding to the grayscales (white Sustain discharge is caused by the number of times assigned to the subfield. Thus, in each of the fifth to sixteenth gradations, luminance corresponding to the luminance level " α " + " the total number of sustain discharges caused in one field (or one frame) display period "

That is, with the driving as shown in Fig. 16, it is possible to indicate the luminance range that becomes the luminance level " 0 " to " 255 + alpha " in 16 steps as shown in Fig.

According to such driving, since the areas in which the light emission patterns (lighting state, off state) are inverted in one field display period do not mix in one screen, pseudo contours generated in such a state are prevented. do.

Here, in the driving shown in Fig. 28, in each of the first reset step R1 of the subfield SF1 and the second reset step R2 of the SF2, the voltage between the two electrodes is set to the cathode side and the row electrode Y to the anode side. The application causes a column-side cathode discharge, in which current flows from the row electrode Y toward the column electrode D, as the first reset discharge. Therefore, during such first reset discharge, when the cation in the discharge gas is directed to the column electrode D, it collides with the MgO crystal as the secondary electron emission material contained in the phosphor layer 17 as shown in FIG. Secondary electrons are emitted from the MgO crystals. In particular, in the PDP 50 of the plasma display device shown in Fig. 1, the MgO crystals are exposed to the discharge space as shown in Fig. 5, thereby increasing the probability of collision with the cations and efficiently discharging secondary electrons into the discharge space. I'm trying to. That is, since the discharge start voltage of the discharge cell PC becomes low by the priming action by such secondary electrons, it becomes possible to cause relatively weak reset discharge. Therefore, since the light emission luminance accompanying the discharge decreases due to the weakening of the reset discharge, the display in which the contrast, the so-called dark contrast when the dark image is displayed, can be improved.

In the driving shown in Fig. 28, the first reset discharge is formed between the row electrode Y formed on the front transparent substrate 10 side as shown in Fig. 3 and the column electrode D formed on the rear substrate 14 side. Is causing. Therefore, compared with the case where reset discharge is caused between the row electrodes X and Y formed on the front transparent substrate 10 side, discharge light emitted from the front transparent substrate 10 side to the outside becomes smaller. The cancer contrast can be improved.

In the driving shown in Figs. 16, 17 and 28, the discharge cell PC in this OFF mode state is caused in the first subfield SF1 after causing a reset discharge to initialize all the discharge cells PC to the OFF mode state. Causes a selective write address discharge to transition to the ON mode. Then, in one subfield in each of the subfields SF3 to SF14 subsequent to SF2, the selective erase address method for causing the selective write address discharge to cause the discharge cell PC in the ON mode state to transition to the OFF mode state is adopted. It is to drive. Therefore, when black display (luminance level 0) is performed by driving according to the first gradation as shown in Fig. 16, the discharge caused through the one-field display period becomes only the reset discharge in the first subfield SF1. Therefore, in the subfield SF1, one field display period is compared with the case in which a reset discharge for initializing all the discharge cells PC to the ON mode state is caused, and then a drive for causing the selective erase address discharge to transition to the OFF mode state is adopted. The number of discharges caused by Therefore, it becomes possible to improve dark contrast.

In the driving shown in Figs. 16, 17, and 28, in the subfield SF1 having the smallest luminance weight, the microluminescence discharge, not the sustain discharge, is caused as the discharge that contributes to the display image. At this time, since the micro-luminescent discharge is a discharge caused between the column electrode D and the row electrode Y, the luminance level at the time of light emission accompanying the discharge is lower than that of the sustain discharge caused between the row electrode X and Y. Therefore, in the case where high brightness is exhibited by one level (second grayscale) from the black display (luminance level 0) by such micro-luminescent discharge, the luminance difference from the luminance level 0 is smaller than that by the sustain discharge. Therefore, the gradation expression ability at the time of expressing a low brightness image becomes high. In the second gradation, since the reset discharge is not caused in the second reset step R2 of SF2 subsequent to the subfield SF1, the decrease in the dark contrast caused by the reset discharge is suppressed.

In the driving shown in Fig. 28, the peak potential of the reset pulse RP1 _Y1 applied to the row electrode Y to cause the first reset discharge in the first reset step R1 of the subfield SF1 is set in the second reset step R2 of SF2. It is lower than the peak potential of the reset pulse RP2 _Y1 applied to the row electrode Y to cause the first reset discharge. As a result, in the first reset step R1 of the subfield SF1, light emission when all the discharge cells PC are reset and discharged at the same time is weakened, thereby reducing the dark contrast.

In the driving shown in Figs. 16, 17, and 28, in the sustain step I of the subfield SF2 in which the luminance weight is the second, the gray scale when expressing the low luminance image is caused by causing the sustain discharge only once. To increase the expressive power. Further, in the sustain stroke I of the subfield SF2, since the sustain pulse IP applied to cause the sustain discharge is only one time, after the end of the sustain discharge caused by this one-time sustain pulse IP, near the row electrode Y In this case, negative wall charges are formed, and positive wall charges are formed in the vicinity of the column electrode D, respectively. Thus, in the selective erasing address step W _D of the next subfield SF3, the discharge (hereinafter referred to as "column side positive electrode discharge") with the column electrode D on the anode side between the column electrode D and the row electrode Y is referred to as the selective erasing address discharge. It is possible to cause as. On the other hand, in the sustain step I of each of the following subfields SF3 to SF14, the number of application of the sustain pulse IP is even. Therefore, immediately after the end of each sustain step I, the negative wall charges are formed in the vicinity of the row electrode Y and the positive wall charges are formed in the vicinity of the column electrode D. Therefore, the selective erasing address step performed after each sustain step I is performed. in W _D, the column side anode discharge is possible. Therefore, only the positive pulse is applied to the column electrode D, and the high cost of the address driver 55 is suppressed.

In the PDP 50 shown in Fig. 1, the phosphor layer 17 formed on the back substrate 14 side as well as the magnesium oxide layer 13 formed on the front transparent substrate 10 side in each discharge cell PC. ), CL-emitting MgO crystals as secondary electron emission materials are included.

Below, the effect by employ | adopting such a structure is demonstrated with reference to FIG. 11 and FIG.

Therefore, as shown in Fig. 18, when the potential transition in the rising section causes reset-side pulse RP1 _Y1 or RP2 _Y1 having a gentle waveform to the row electrode Y of the PDP 50, the column-side cathode discharge is caused. The discharge ends before the potential reaches the peak potential of the pulse. Therefore, since the column-side cathode discharge ends at the stage where the voltage applied between the row electrode and the column electrode is low, as shown in FIG. 12, the discharge intensity is significantly lower than in the case of FIG.

That is, the CL-emitting MgO crystals are included in both the magnesium oxide layer 13 and the phosphor layer 17 in the reset pulses RP1 _Y1 or RP2 _Y1 as shown in FIG. By applying to the PDP 50, thermal side cathode discharge with weak discharge intensity is caused. Therefore, since the side-side cathode discharge having a very low discharge intensity can be caused as a reset discharge, it is possible to increase the contrast of the image, especially the dark contrast when displaying a dark image.

In the drive shown in Fig. 18, the write scan pulse SP _W applied to the row electrode Y in the selective write address stroke W1 _W of the subfield SF1 and the write applied to the row electrode Y in the selective write address stroke W2 _W of the subfield SF2 The negative peak potential in each of the scanning pulses SP _WW ,

SP _WW <SP _W

, First and in the second selective writing addressing process W2 _W to surely cause the selective writing address discharge is generated by a size relationship is to.

The reason why the selective write address discharge is surely caused by setting the negative peak potentials in each of the write scan pulses SP _W and SP _WW in the above-described magnitude relationship is described below.

According to the driving shown in Fig. 28, in the first selective write address step W1 _W of the subfield SF1, selective writing is performed between the column electrode D and the row electrode Y in response to the application of the high voltage pixel data pulse DP and the write scan pulse SP _W. Address discharge is caused. At this time, in order to prevent erroneous discharge between the row electrodes X and Y, the row electrode X is set to the ground potential as shown in FIG. On the other hand, in the second selective write address step W2 _W of the sustain pulse SF2, the selective write address discharge is caused between the column electrode D and the row electrode Y in response to the application of the high voltage pixel data pulse DP and the write scan pulse SP _WW . Further, in the second selective write address step W2 _W , the discharge is caused not only between the column electrodes D and the row electrodes Y, but also between the row electrodes X and Y, so that the state of formation of the wall charges in the discharge cells corresponds to the ON mode. As shown in Fig. 28, a positive base pulse BP ⁺ is applied to the row electrode X so as to transition to the state.

Here, in the first selective write address step W1 _W of the subfield SF1, when the negative peak potential of the write scan pulse SP _W is low, the voltage between the row electrodes X and Y increases, so that the selective write address There is a possibility that weak false discharge occurs between the row electrodes X and Y due to the discharge. As a result of this misdischarge, the positive wall charges present in trace amounts are erased in the vicinity of the row electrode X, and the negative wall charges are charged on the contrary. In the first half of the second reset step R2 of the subsequent subfield SF2, the reset pulses RP2 _Y1 and RP2 having the same polarity to each of the row electrodes Y and X are prevented so as to prevent erroneous discharge between the row electrodes X and Y. _Y2 ) is applied. Therefore, no discharge is caused in the row electrode X, and the next second selective writing address step W2 _W must be executed with the regular wall charge erased in the vicinity of the row electrode X. FIG.

As described above, when the negative peak potential of the write scan pulse SP _W is low, erroneous discharge is caused between the row electrodes X and Y, and according to this erroneous discharge, an anisotropic wall charge is formed near the row electrode X. This is not an ideal state. Therefore, in the second selective write address step W2 _W of SF2 in this state, there is a possibility that no discharge is caused between the row electrodes X and Y, that is, the write discharge is not caused correctly. At this time, the address process of each subfield in the subfield SF3 is later, all of which are selective erasing addressing process W _D for transitioning the state of the discharge cells from the ON mode to the OFF mode. Therefore, the discharge cells in which the selective write address discharge failed in the step of SF2 do not cause sustain discharge in each sustain step I after SF3, resulting in a black display state, which significantly deteriorates the display quality.

Therefore, as shown in Fig. 28, the negative peak potential of the write scan pulse SPW applied to the row electrode Y in the first selective write address step W1 _W of SF1 is set to the row electrode in the second selective write address step W2 _W of SF2. It is set higher than the negative peak potential of the write scan pulse SP _WW applied to Y. That is, in the first selective write address step W1 _W , even when the selective write address discharge is caused, the write scan pulse SP _W having raised the negative peak potential to such a degree that the discharge is caused and no erroneous discharge is caused between the row electrodes X and Y. Is applied to the row electrode Y. On the other hand, in the second selective write address step W2 _W , the negative peak potential of the write scan pulse SP _WW is lower than the negative peak potential of the write scan pulse SP _W so that discharge is surely caused between the row electrodes X and Y. .

Therefore, since the erroneous discharge caused by the selective write address discharge in the first selective write address step W1 _W and caused by the row electrodes X and Y is prevented, the state of forming ideal wall charges is maintained in the discharge cell, in the second selective writing addressing process W2 _W it is possible to surely cause the selective write address discharge.

Also Also, in the write scan pulse, as all, to increase the negative peak potential of the SP _W having the negative polarity writing for the peak voltage scan pulse SP _WW, the first reset pulse in the reset step R1 RP1 _Y2 as described above, the unit Consideration is required in setting the polar peak potential. That is, when the negative peak potential of the reset pulse RP1 _Y2 as the reset tail pulse is lower than the negative peak potential of the reset pulse RP2 _Y2 as the reset head pulse, the following problem occurs.

In other words, each of the reset pulses RP1 _Y2 and RP2 _Y2 as the reset tail pulses is applied to stably adjust the amount of wall charges for stably causing the selective write address discharge in the write address steps W1 _W and W2 _W immediately after that. .

However, as described above, since the negative peak potential of the write scan pulse SP _W is set high in the first selective write address step W1 _W of SF1, the reset pulse RP1 in the immediately preceding step (second half of R1). _{If a} relatively strong discharge is caused by _Y2 , there is a high possibility that the selective write address discharge fails.

Thus, the portion set to be higher the negative peak potential of the reset pulse RP1 to weaken the discharge generated under the application of _Y2, the reset pulse RP1 _Y2. Specifically, the negative peak potential of the reset pulse RP1 _Y2 in the first reset step R1 of SF1 and the negative peak potential of the reset pulse RP2 _Y2 in the second reset step R2 of SF2 are RP2 _Y2 ≤ RP1 _Y2 . We do in big and small relations.

As a result, as shown in FIG. 28, even when the negative peak potential of the write scan pulse SP _W in the first selective write address step W1 _W is set relatively high, the selective write discharge can be surely caused. Further, by setting the reset pulse RP1 _Y2 of negative polarity peak voltage to the reset pulse RP2 _Y2 of negative polarity than the peak potential higher, fading is also a discharge which is caused in accordance with the impression of the reset pulse RP1 _Y2, it is possible to further increase dark contrast .

By the way, when the negative peak potentials of the reset pulses RP1 _Y2 and RP2 _Y2 are lower than the negative peak potentials of each of the write scan pulses SP _W and SP _WW , the write address discharge is surely selected in the write address steps W1 _W and W2 _W. Cannot be caused.

In view of this, therefore, in the drive shown in Fig. 28, the negative polarities of the reset pulse RP1 _Y2 and the write scan pulse SP _W in the subfield SF1, the reset pulse RP2 _Y2 and the write scan pulse SP _WW in the subfield SF2, respectively. and so the peak _{voltage, SP WW <SP W ≤ RP2} , the second selective writing addressing process surely cause the selective writing address discharge in the W2 _W by a size relationship is to ≤RP1 _{Y2 Y2.}

Further, in the above embodiment, the write scan pulse scan writing the negative peak potential of the SP _W pulse higher than the negative peak potential of SP _WW. However, as shown in Fig. 29, similar to the negative peak potential of the two and , the write scan pulse SP _W of the scan pulse SP _W may be written to the pulse width T1 smaller than a pulse width T2. At this time, the negative peak potentials of the reset pulses RP1 _Y2 , RP2 _Y2 , the write scan pulses SP _W , and SP _WW each have a magnitude relationship such that SP _WW = SP _W ≦ _{RP 2 Y 2} ≦ _{RP 1 Y 2} .

By such driving as shown in FIG. 29, similarly to the case of employing the driving method shown in FIG. 28, the erroneous discharge caused by the selective write address discharge and caused between the row electrodes X and Y is prevented.

In addition, as shown in Fig. 30, the write scan pulse SP _W in the portion at the same time be higher than the negative peak potential of the scan pulse SP _WW enter the negative peak potential of the write scan pulse write scan pulse width T1 of the SP _W pulse SP _W May be smaller than the pulse width T2.

As shown in Fig. 31, the negative peak potentials of each of the write scan pulses SP _W and SP _WW are equal to each other and both pulse widths are the same, and during the execution period of the first selective write address step W1 _W , In addition to the row electrodes Y _{1 to} Y _n , a negative base pulse BP ⁻ may be applied to each of the row electrodes X _{1 to} X _n . That is, the misdischarge between the row electrodes X and Y is prevented by applying a base pulse having the same polarity as the base pulses BP ⁻ applied to the row electrodes Y _{1 to} Y _n to the row electrodes X _{1 to} X _n .

As shown in Fig. 31, driving for applying the negative base pulse BP ^- to each of the row electrodes X ₁ to X _n during the execution period of the first selective writing address step W1 _W is shown in Figs. 28, 29 or It may be performed in combination with the driving shown in FIG.

In other words, the negative base pulse BP ⁻ is applied to each of the row electrodes X ₁ to X _n during the execution period of the first selective write address step _W 1 _W , _and the negative polarity of the write scan pulse SP _W is shown in FIG. writing a peak potential scan pulse to be higher than the negative peak potential of SP _WW, or may be a drive smaller than the pulse width of the even write scan pulse SP _W of the scan pulse SP _WW write pulse widths as shown in the 29 embodiment.

In the above embodiment, in the pulse rising (or falling) period of each of the reset pulses RP1 _X , RP2 _X , RP1 _Y1 , RP1 _Y2 , RP2 _Y1 , and RP2 _Y2 , the change in potential over time is constant. As shown in the figure, the amount of change in potential may gradually change with time.

In the first reset step R1 shown in Figs. 28 and 29 to 31, respectively, the reset pulse RP1 _Y1 is applied to the row electrodes Y _{1 to} Y _n in the _first half thereof to cause the first reset discharge as the column-side cathode discharge. It is also possible to omit it.

For example, instead of the first reset step R1 shown in Figs. 28 and 29 to 31, the first reset step R1 shown in Fig. 27 is adopted. As shown in Fig. 27, in the first half of the first reset step R1, the row electrodes Y _{1 to} Y _n are fixed to the ground potential. That is, the purpose of the column-side cathode discharge from the row electrode Y to the column electrode D in the first half of the first reset step R1 is to discharge charged particles for stabilizing the write discharge in the first selective write address step W1 _W. . Here, as the structure of the PDP, for example, when included in the MgO crystal containing the CL luminescent MgO crystal as shown in Fig. 5, the write discharge is stabilized as compared with the case where such a structure is not employed. Therefore, in the first half of the first reset step R1, it is possible to adopt a configuration in which the row electrode Y and the column electrode D are both at ground potentials and do not cause column side cathode discharge. In this case, the row electrode X is also set to the ground potential level as shown in FIG.

In the above embodiment, the reset steps R1 and R2 and the selective write address steps W1 _W and W2 _W are sequentially executed only in the first subfield SF1 and the second subfield SF2. The same operation may be performed in the third and subsequent subfields.

In addition, in the first reset step R1 and the second reset step R2 shown in Figs. 28 and 29 to 31, reset discharge is caused to all discharge cells at the same time. However, each of the discharge cell blocks each includes a plurality of discharge cells. Each time, reset discharge may be dispersed in time.

In the above embodiment, only the first subfield SF1 is configured to perform the light emission step LL instead of the sustain step I as the step of performing light emission related to the display image. However, in the subfields other than the first subfield or a plurality of subfields including the first subfield, the light emission stroke LL is substituted for the sustain step I.

May be executed.

Further, in the driving shown in Fig. 16, even in the gradations after the fourth gradation, the micro luminescence stroke LL of the subfield SF1 causes the micro luminescence discharge accompanying the emission of the luminance level?, But after the third gradation In gradation, this micro-luminescence discharge may not be caused. That is, since the light emission due to the microluminescence discharge is extremely low luminance (luminance level α), when used together with the sustain discharge accompanied with high luminance emission, that is, in the gradation after the third gradation, the "luminance level α This is because it is not necessary to cause this micro luminescent discharge when the luminance increase of "

Incidentally, in the embodiments shown in Figs. 28 and 29 to 31, the micro light emitting pulse LP and the reset pulse RP2 _Y1 are connected and applied to the row electrode Y. However, as shown in Fig. 33, both are dispersed in time. It may be applied sequentially to the row electrode Y.

In addition, in the example shown in FIG. 5, MgO crystals are included in the phosphor layer 17 provided on the back substrate 14 side of the PDP 50. As shown in FIG. 17, the phosphor layer 17 You may provide the secondary electron emission layer 18 which consists of a secondary emission material so that the surface of () may be coat | covered. At this time, as the secondary electron emission layer 18, a crystal (for example, MgO crystal including CL-emitting MgO crystal) made of a secondary electron emission material may be formed on the entire surface of the phosphor layer 17, Alternatively, the secondary electron emission material may be formed by thin film formation.

This application is based on Japanese Patent Application Nos. 2007-055557 and 2007-109650, which are incorporated herein by reference.

1 is a view showing a schematic configuration of a plasma display apparatus for driving a plasma display panel according to a driving method according to a first embodiment of the present invention.

2 is a front view schematically showing the internal structure of the PDP 50 as viewed from the display surface side.

FIG. 3 is a diagram showing a cross section on the V-V line shown in FIG.

FIG. 4 is a diagram showing a cross section on the W-W line shown in FIG.

FIG. 5 is a diagram schematically showing MgO crystals contained in the phosphor layer 17. FIG.

FIG. 6 is a diagram showing an example of a light emission pattern for each gray scale in the plasma display device shown in FIG.

FIG. 7 is a diagram showing an example of a light emission drive sequence employed in the plasma display device shown in FIG.

FIG. 8 is a diagram showing various drive pulses applied to the PDP 50 in accordance with the light emission drive sequence shown in FIG.

FIG. 9 is a diagram showing another example of the light emission drive sequence employed in the plasma display device shown in FIG.

FIG. 10 is a diagram showing various drive pulses applied to the PDP 50 in accordance with the light emission drive sequence shown in FIG.

FIG. 11 is a view showing the transition of the discharge intensity in the thermal side cathode discharge caused when the reset pulse RPY1 is applied to a conventional PDP in which the CL luminescent MgO crystals are included only in the magnesium oxide layer 13.

Fig. 12 shows the transition of the discharge intensity in the thermal side cathode discharge caused when the reset pulse RPY1 is applied to the PDP 50 containing the CL luminescent MgO crystals in both the magnesium oxide layer 13 and the phosphor layer 17. Figs. It is a figure which shows.

Fig. 13 shows another waveform of the reset pulse RPY1.

FIG. 14 is a diagram schematically showing a form in which the secondary electron emission layer 18 is laminated on the surface of the phosphor particle layer 17a to form the phosphor layer 17. As shown in FIG.

Fig. 15 is a diagram showing a schematic configuration of a plasma display device for driving a plasma display panel in accordance with a discharge method according to a second embodiment of the present invention.

FIG. 16 is a diagram showing an example of a light emission pattern for each gray scale in the plasma display device shown in FIG.

FIG. 17 is a diagram showing an example of a light emission drive sequence employed in the plasma display device shown in FIG.

FIG. 18 is a diagram showing various drive pulses applied to the PDP 50 in accordance with the light emission drive sequence shown in FIG.

FIG. 19 is a diagram showing another example of the light emission drive sequence employed in the plasma display device shown in FIG.

FIG. 20 is a diagram showing various drive pulses applied to the PDP 50 in accordance with the light emission drive sequence shown in FIG.

Fig. 21 is a diagram showing a schematic configuration of a plasma display device for driving a plasma display panel according to the driving method according to the third embodiment of the present invention.

FIG. 22 is a diagram showing an example of a light emission drive sequence employed in the plasma display device shown in FIG.

FIG. 23 is a diagram showing an example other than the light emission drive sequence employed in the plasma display device shown in FIG.

Fig. 24 is a diagram showing a schematic configuration of a plasma display device for driving a plasma display panel according to the driving method according to the fourth embodiment of the present invention.

FIG. 25 is a diagram showing an example of a light emission drive sequence employed in the plasma display device shown in FIG.

FIG. 26 is a diagram showing another example of the light emission drive sequence employed in the plasma display device shown in FIG.

27 is a diagram showing another application method of the reset pulse in the first reset step R1.

FIG. 28 is a diagram showing various drive pulses applied to the PDP 50 in accordance with the light emission drive sequence shown in FIG.

FIG. 29 is a diagram showing another example of various drive pulses applied to the PDP 50 in accordance with the light emission drive sequence shown in FIG.

30 is a diagram showing another example of various drive pulses applied to the PDP 50 in accordance with the light emission drive sequence shown in FIG.

FIG. 31 is a diagram showing another example of various drive pulses applied to the PDP 50 in accordance with the light emission drive sequence shown in FIG.

32 shows waveforms of the reset pulse RP.

33 is a diagram showing another example of the application timing of each of the light emitting pulse LP and the reset pulse RP2Y1.

Claims (25)

The intersection of the plurality of row electrode pairs formed on the first substrate in the first and second substrates disposed opposite to each other with the discharge space filled with the discharge gas interposed therebetween, and the plurality of column electrodes formed on the second substrate. A plasma display panel in which a discharge cell including a phosphor layer whose surface is in contact with the discharge gas is formed, is gradally driven to a plurality of subfields for each unit display period of a video signal. With driving method, In each of the first subfield in each of the plurality of subfields in the unit display period and the second subfield subsequent to the first subfield, sequentially writing negative write scan pulses are applied to one row electrode of the row electrode pair. By applying a pixel data pulse corresponding to the pixel data for each pixel based on the video signal to the column electrode while selectively applying, the discharge cells are selectively write-address discharged to bring the discharge cells from the OFF mode to the ON mode. Executes the write address process of transitioning, In a third subfield subsequent to the second subfield, a pixel data pulse corresponding to pixel data for each pixel based on the video signal while sequentially applying an erase scan pulse to one row electrode of the row electrode pair Is applied to the column electrode to selectively erase address discharge the discharge cells, thereby performing an erase addressing step of transitioning the discharge cells from the ON mode to the OFF mode, The negative peak potential in the write scan pulse applied in the write address stroke of the first subfield is negative in the write scan pulse applied in the write address stroke of the second subfield. A driving method of a plasma display panel which is made higher than the peak potential. The pulse width of the write scan pulse applied in the write address stroke of the first subfield is smaller than the pulse width of the write scan pulse applied in the write address stroke of the second subfield. A driving method of the plasma display panel. A plurality of row electrode pairs formed on the first substrate in the first and second substrates disposed to face each other with a discharge space filled with discharge gas therebetween, and a plurality of column electrodes formed on the second substrate. A plasma display panel in which a discharge cell including a phosphor layer whose surface is in contact with the discharge gas is formed at a cross section, and is grayscale-driven in a plurality of subfields for each unit display period of a video signal. By the driving method of, In each of the first subfield in each of the plurality of subfields in the unit display period and the second subfield subsequent to the first subfield, sequentially writing negative write scan pulses are applied to one row electrode of the row electrode pair. By applying a pixel data pulse corresponding to the pixel data for each pixel based on the video signal to the column electrode while selectively applying the discharge cells, the discharge cells are selectively erased and addressed so that the discharge cells are switched from the OFF mode to the ON mode. Executes the write address erase address step of transitioning, In a third subfield subsequent to the second subfield, a pixel data pulse corresponding to pixel data for each pixel based on the video signal while applying a sequential negative erase scan pulse to one row electrode of the row electrode pair Is applied to the column electrode to selectively erase address discharge the discharge cells, thereby performing an erase address step of transitioning the discharge cells from the ON mode to the OFF mode, In each of the first and second subfields, one row of reset tail pulses causes a reset discharge having the column electrode to the anode side between the column electrode and the one row electrode immediately before the write address stroke. A reset step applied to the electrode, and each of the subfields following the third subfield and the third subfield does not include the reset step, In the plasma display panel, the pulse width of the write scan pulse applied in the write address stroke of the first subfield is smaller than the pulse width of the write adverb pulse applied in the write address stroke of the second subfield. Driving method. The negative peak potential of the write scan pulse applied in the write address stroke of the first subfield, and the write scan pulse applied in the write address stroke of the second subfield. A method of driving a plasma display panel in which the peak potentials of negative polarities in the same manner are set equally. The plasma display panel driving method according to claim 1 or 3, wherein the erasing address step is executed in each of all subfields subsequent to the third subfield. 4. The first and second subfields of claim 1 or 3, wherein in each of the first and second subfields, a reset discharge is performed between the column electrode and one of the row electrodes immediately before the write address stroke. A reset step of applying a reset tail pulse to be applied to said one row electrode, The peak potential of negative polarity in the reset tail pulse applied in the first subfield is a potential higher than or equal to the negative peak potential in the reset tail pulse applied in the second subfield. Driving method The method of driving a plasma display panel according to claim 1 or 3, wherein the phosphor layer contains a phosphor material and a secondary electron emission material. The method of driving a plasma display panel according to claim 7, wherein the secondary electron emission material is made of magnesium oxide. The method of driving a plasma display panel according to claim 8, wherein the magnesium oxide includes magnesium oxide crystals which are excited by an electron beam and emit cathode luminescence emission having a peak within a wavelength range of 200 to 300 nm. The method of driving a plasma display panel according to claim 7, wherein the secondary electron emission material is in contact with the discharge gas in the discharge space. The method of driving a plasma display panel according to claim 6, wherein in the reset step, all of the discharge cells are initialized in the OFF mode. The said one row electrode and the said column of Claim 6 in the reset process of the said 2nd subfield, The voltage which made the said one row electrode into the anode side, and said column electrode into the cathode side immediately before application of the said reset pulse was carried out. A method of driving a plasma display panel which causes reset discharge between the one row electrode and the column electrode by applying a reset head pulse to be caused between electrodes to the one row electrode. 7. In the reset step of each of the first and second subfields, immediately before the reset tail pulse is applied, a voltage having the one row electrode as the anode side and the column electrode as the cathode side is the row electrode. And applying a reset head pulse to be caused between the column electrodes to the one row electrode, thereby causing a reset discharge between the one row electrode and the column electrode. The method of driving a plasma display panel according to claim 12, wherein in the reset step, a potential for preventing discharge between the other row electrode and the one row electrode of the row electrode pair is applied to the other row electrode. . The method of driving a plasma display panel according to claim 13, wherein in the reset step, a potential for preventing discharge between the other row electrode and the one row electrode of the row electrode pair is applied to the other row electrode. . The plasma display panel according to claim 1 or 3, wherein the first subfield is a first subfield in the unit display period, and the second subfield is a subfield provided immediately after the first subfield. Driving method. The method of driving a plasma display panel according to claim 13, further comprising the reset step only in the first subfield and the second subfield among the subfields in the unit display period. The method of driving a plasma display panel according to claim 12, wherein in the reset step, the potential of the leading edge of the reset head pulse is gradually increased over time. The driving method of the plasma display panel according to claim 13, wherein in the reset step, the potential of the leading edge of the reset head pulse is gradually increased over time. The method of claim 12, wherein the reset head pulse has a positive peak potential, In the reset step, the plasma display panel driving method applies a positive potential to the other row electrode while applying the reset head pulse to the one row electrode. The method of claim 13, wherein the reset head pulse has a positive peak potential, In the reset step, the plasma display panel driving method applies a positive potential to the other row electrode while applying the reset head pulse to the one row electrode. 4. The first subfield according to claim 1 or 3, wherein a voltage having one row electrode of the row electrode pair as the anode side and the column electrode as the cathode side is set between the one row electrode and the column electrode. The method of driving a plasma display panel by applying a micro luminescent discharge stroke to cause micro luminescent discharge between the column electrode and the one row electrode in the discharge cell set to the ON mode state by applying. 23. The method for driving a plasma display panel according to claim 22, wherein the minute light emitting discharge is a discharge accompanied by light emission corresponding to a grayscale having a higher luminance by one step than the luminance level 0. 4. A negative base pulse according to claim 1 or 3, wherein in the first subfield, a negative base pulse is applied to the other row electrodes of the row electrode pairs during the execution period of the write address stroke, In the second subfield, during the execution period of the write address stroke. A method of driving a plasma display panel, wherein a positive base pulse is applied to the other row electrode. A plurality of row electrode pairs formed on the first substrate in the first and second substrates disposed to face each other with a discharge space filled with discharge gas therebetween, and a plurality of column electrodes formed on the second substrate. A plasma display for gradually driving a plasma display panel in which a discharge cell including a phosphor layer whose surface is in contact with the discharge gas is formed at a cross section in a plurality of subfields for each unit display period of the video signal; By the driving method of the panel, In each of the first subfield in each of the plurality of subfields in the unit display period and the second subfield subsequent to the first subfield, sequentially writing negative write scan pulses are applied to one row electrode of the row electrode pair. By applying a pixel data pulse corresponding to the pixel data for each pixel based on the video signal to the column electrode while applying, selectively discharge address the discharge cells to transition the discharge cells from the OFF mode to the ON mode. Executes a write address stroke, In a third subfield subsequent to the second subfield, a pixel data pulse corresponding to pixel data for each pixel based on the video signal while applying a sequential negative erase scan pulse to one row electrode of the row electrode pair Is applied to the column electrode to selectively erase address discharge the discharge cells, thereby performing an erase address step of transitioning the discharge cells from the ON mode to the OFF mode, In the first subfield, a negative base pulse is applied to the other row electrodes of the row electrode pairs over the execution period of the write address stroke, and in the second subfield, in the execution period of the write address stroke. A method of driving a plasma display panel, wherein a positive base pulse is applied to the other row electrode.

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