JP2008122684A - Plasma display device and driving method of display panel - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suitably control a wall charge distribution in a discharge cell while improving a dark-place contrast. <P>SOLUTION: A plasma display device sets initial selection cells except discharge cells to provide luminance display of black level in a light emittable state in an address period Tw of a subfield SF<SB>1</SB>, makes the initial selection cells emit light by applying a discharge sustain pulse the odd number of times allocated to the subfield SF<SB>1</SB>in a light emission period T1 of the subfield SF<SB>1</SB>, sets the initial selection cells selectively in a non-light-emission state in address periods Te of following subfields SF<SB>1</SB>to SF<SB>N</SB>by selectively generating erasure discharges of the initial selection cells, makes charge adjustments in charge adjustment periods Ta of the following subfields SF<SB>1</SB>to SF<SB>N</SB>, and makes the discharge cells in the light emittable state emit light in light emission periods T<SB>2</SB>to T<SB>N</SB>of the following subfields SF<SB>1</SB>to SF<SB>N</SB>. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a plasma display device that decomposes each field of a video signal into a plurality of subfields and displays a multi-gradation image by a combination of subfields, and a driving technique thereof.

  The plasma display has a display panel composed of a plurality of discharge cells each having a phosphor layer applied and arranged in a matrix. When displaying an image, the plasma display causes a gas discharge in a selected discharge cell among the discharge cells to generate ultraviolet rays. This ultraviolet light excites the phosphor layer in the discharge cell and causes the phosphor layer to emit light. A multi-tone image can be displayed by controlling the number of gas discharges generated in the discharge cells per unit time.

Generally, as a gradation control method of a plasma display, each field corresponding to one image is decomposed into a plurality of subfields, and a luminance weight proportional to the light emission period is assigned to each subfield. A subfield method is employed in which multi-gradation image display is performed by a combination of the above. Since the plurality of subfields are sequentially displayed along the time axis, the human eye integrates the light emission patterns of the plurality of subfields and visually perceives them as one image. For example, the luminance weights to be assigned to the eight subfields constituting one field are 2 ⁰ : 2 ¹ : 2 ² : 2 ³ : 2 ⁴ : 2 ⁵ : 2 ⁶ : 2 ⁷ (= 1: 2), respectively. : 4: 8: 16: 32: 64: 128), it is possible to display 256 gradation images by combining subfields. For example, Patent Document 1 (Japanese Patent Laid-Open No. 2003-29698) and Patent Document 2 (US Patent Application Publication No. 2003/011543) disclose this type of gradation control technique based on the subfield method.

  However, in the plasma display using the gradation control technique disclosed in Patent Document 1, it is known that an observer visually observes noise called a dynamic pseudo contour in a display image. For example, Patent Document 3 (Japanese Patent Laid-Open No. 2000-231362) and Patent Document 4 (US Patent Application Publication No. 2002-054000) disclose a gradation control technique for preventing the occurrence of this kind of moving image pseudo contour. Has been. This gradation control technique is based on the subfield method, but does not generate a moving image pseudo contour in principle.

FIG. 1 shows an example of the light emission pattern of each discharge cell by the gradation control technique disclosed in Patent Document 3. In FIG. 1, when one field is composed of 15 subfields SF _{1 to} SF ₁₅ , gradation levels “0” to “15” of the video signal and light emission patterns corresponding to the gradation levels are shown. It is shown. In the figure, a symbol “◯” means that a gas discharge (sustain discharge) for gradation display occurs in the discharge cell, and a symbol “●” indicates that the wall charge in the discharge cell is selectively erased. This means that gas discharge (selective erasure discharge) occurs. Although not clearly shown in FIG. 1, in the display period of the first subfield SF ₁ , first, a reset discharge that sets all the discharge cells to an emissive state occurs, and wall charges are accumulated in all the discharge cells. Let As shown in FIG. 1, except for the light emission pattern of the gradation level “0” indicating the black level, the discharge cell is brought into a non-light emitting state from any of the display periods of the subfields SF _{2 to} SF _15. Until the selective erasing discharge set to the non-emissive state is generated, the light emission sustaining discharge is generated in each display period of the temporally continuous subfield, and visible light is emitted to the discharge cell. Since the discharge cell displaying the gradation level “0” is set from the light emitting state to the non-light emitting state in the display period of the _first subfield SF ₁ , the discharge is performed in the display period of all the subfields SF _{1 to} SF _15. The light emission sustain discharge does not occur in the cell.

In the case of the gradation control technique of FIG. 1, as described above, it is necessary to cause a reset discharge in all the discharge cells in the display period of the _first subfield SF1, but the light (background light emission) generated by this reset discharge is displayed. There is a problem in that the contrast of the image, particularly the dark room contrast, is lowered, thereby degrading the image quality. Here, in general, the “dark place contrast” is a ratio (= Lg / Lb) between the light emission luminance (= Lg) at the time of white level image display and the background light emission luminance (= Lb) at the time of black level image display. Is defined as Dark place contrast is one of the parameters that determines the superiority or inferiority of the image quality particularly when displaying a low-luminance image. Patent Document 5 (Japanese Patent Laid-Open No. 2001-31244) and Patent Document 6 (US Patent Application Publication No. 2002/018030) disclose a gradation control technique that can improve dark place contrast. In this gradation control technique, in order to improve dark room contrast, in the _first subfield SF ₁ , a discharge discharge that should be displayed with a black level luminance is not caused to generate a reset discharge, but is selectively applied only to other discharge cells. This causes a reset discharge.
JP 2003-29698 A US Patent Application Publication No. 2003/011543 (publication publication of US patent application based on patent application relating to Patent Document 1 on which priority is claimed) JP 2000-231362 A US Patent Application Publication No. 2002/054000 (publication publication of a US patent application based on a patent application relating to Patent Document 3 on which priority is claimed) JP 2001-31244 A US Patent Application Publication No. 2002/018030 (publication publication of US patent application based on patent application based on patent document 5 based on priority claim)

As described above, the gradation control technique disclosed in Patent Document 3 causes all discharge cells to emit light during the display period of the _first subfield SF ₁ and causes all discharge cells to emit light. To do. Therefore, there is an advantage that the distribution of the wall charge amount in the discharge cell can be controlled relatively easily in the display period of the subsequent subfields SF _{2 to} SF ₁₅ subsequent to the _first subfield SF ₁ . On the other hand, in the gradation control technique disclosed in Patent Document 5, the discharge discharge is selectively caused in the discharge cells during the display period of the _first subfield SF1, and only specific discharge cells are set in a light emission enabled state. The discharge cells are kept in a non-light emitting state. For this reason, in the display period of the subsequent subfields SF _{2 to} SF ₁₅ , it is relatively difficult to control the wall charge distribution in the discharge cell. For example, an unexpected erroneous discharge occurs in the discharge cell or the wall charge is increased. There is a problem that the image quality is deteriorated due to failure to delete the image.

  In view of the above, the main object of the present invention is to improve the dark place contrast by selectively setting the discharge cells to the light-emissionable state during the display period of the first subfield, while increasing the contrast in the discharge cells during the display period of the subsequent subfield. It is intended to provide a plasma display apparatus and a display panel control method capable of optimally controlling the wall charge distribution of the display and thereby improving the image quality.

  In order to achieve the above-mentioned object, the invention according to claim 1 includes a front substrate, a back substrate having an opposing surface spaced apart from one surface of the front substrate, and a plurality of surfaces formed on one surface of the front substrate. A row electrode pair, a plurality of column electrodes formed on opposite surfaces of the back substrate, and a plurality of row electrode pairs and a plurality of column electrodes formed between the front substrate and the back substrate, respectively. A display panel driving method in which a discharge gas is enclosed in each discharge cell and a phosphor layer is provided, and (a) a plurality of fields of an input video signal are provided. (B) assigning a luminance weight to each of the subfields; and (c) a plurality of periods including at least an address period and a light emission period. And sequentially displaying the plurality of subfields on the display panel in each of the plurality of periods, wherein the step (c) includes (c-1) a first sub-field of the subfields. In a field address period, scan pulses are sequentially applied to the scan electrodes of the plurality of row electrode pairs, and write pulses synchronized with the scan pulses are applied to the column electrodes to selectively write to the discharge cells. The write-in discharge is caused between the scan electrode and the column electrode only in the initial selection cell except for the discharge cell to be displayed with black level luminance among the discharge cells. (C-2) In the light emission period after the address period of the first subfield, discharge is performed on the scan electrode and the common electrode of each row electrode pair. Applying a sustain pulse an odd number of times assigned to the first subfield, thereby causing a sustain discharge to occur between the scan electrode and the common electrode of the row electrode pair only in the initial selected cell, thereby causing the phosphor layer to emit light (C-3) In the address period of each subsequent subfield excluding the first subfield among the subfields, a scan pulse is sequentially applied to the scan electrodes and a selective erase pulse synchronized with each scan pulse is applied. Selectively setting the initial selected cell to a non-light emitting state by selectively applying to the column electrode and selectively causing an erasing discharge in the initial selected cell; and (c-4) each subsequent In the charge adjustment period set immediately after the subfield address period, the adjustment pulses are respectively applied to the scan electrode and the common electrode of each row electrode pair. (C-5) In the light emission period after the charge adjustment period of each subsequent subfield, a discharge sustain pulse is alternately applied to the scan electrode and the common electrode of each row electrode pair. And causing the phosphor layer to emit light by causing a sustain discharge between the scan electrode and the common electrode only in the discharge cells in the light emission enabled state by applying the number of times assigned to the discharge cell. .

  According to a twenty-third aspect of the present invention, there is provided a front substrate, a rear substrate having a facing surface separated from one surface of the front substrate, a plurality of row electrode pairs formed on one surface of the front substrate, and the rear surface. A plurality of column electrodes formed on opposing surfaces of the substrate, and a plurality of discharge cells respectively formed in intersection regions of the plurality of row electrode pairs and the plurality of column electrodes between the front substrate and the back substrate. A display panel including a display panel in which a discharge gas is sealed in each discharge cell and a phosphor layer is provided, wherein each field of an input video signal is decomposed into a plurality of subfields A weight assignment unit for assigning luminance weights to the subfields, a panel drive unit for driving the display panel, and a display period of each subfield at least in an address period And a drive control unit that divides the display unit into a plurality of periods including a light emission period and controls the panel driving unit in each of the plurality of periods to sequentially display the plurality of subfields on the display panel. (A) In the address period of the first subfield of the subfields, a scan pulse is sequentially applied to the scan electrodes of the row electrode pair, and a write pulse synchronized with each scan pulse is applied to the column electrodes. By applying a write discharge selectively to the discharge cells by applying, only the initial selected cells except for the discharge cells that should display the black level of luminance among the discharge cells are arranged between the scan electrodes and the column electrodes. A write operation for causing the write discharge to set the initially selected cell in a light-emission enabled state; and (b) in a light emission period after an address period of the first subfield, A sustain discharge is applied between the scan electrode and the common electrode of the row electrode pair only in the initial selected cell by applying a discharge sustain pulse to the scan electrode and the common electrode of each row electrode pair only an odd number of times assigned to the first subfield. A light emitting operation for causing the phosphor layer to emit light, and (c) sequentially applying scan pulses to the scan electrodes in the address period of each subsequent subfield excluding the first subfield of the subfields, and An erasure that selectively sets the initial selected cell to a non-light-emitting state by selectively applying a selective erasing pulse synchronized with each scanning pulse to the column electrode to selectively cause an erasing discharge in the initial selected cell. (D) In the charge adjustment period set immediately after the address period of each subsequent subfield, the scan electrode of each row electrode pair And (e) in the light emission period after the charge adjustment period of each subsequent subfield, the discharge is alternately maintained on the scan electrode and the common electrode of each row electrode pair. A light emission operation for causing the phosphor layer to emit light by causing a sustain discharge between the scan electrode and the common electrode only in the discharge cells in the light emission enabled state by applying a pulse for the number of times assigned to each subsequent subfield. It is characterized by executing.

  Hereinafter, various embodiments according to the present invention will be described.

  FIG. 2 is a diagram showing a schematic configuration of the plasma display apparatus 1 according to the embodiment of the present invention. The plasma display device 1 includes a display panel 2 that is a PDP (plasma display panel), and further includes a column electrode driving unit 15 that drives discharge cells CL,..., CL in the display panel 2, and first row electrode driving. Part 16A and second row electrode driving part 16B. The column electrode driving unit 15, the first row electrode driving unit 16A, and the second row electrode driving unit 16B may constitute a “panel driving unit” according to the present invention.

  In addition, the plasma display device 1 includes a controller 10, a gradation adjustment unit 12, a drive data generation unit 13, and a memory circuit 14 as a signal processing unit that processes a video signal to be displayed on the display panel 2. The controller 10 performs signal processing on the input video signal VSi, which is a digital signal, to generate a video signal VSa, and transfers the video signal VSa to the gradation adjustment unit 12. Further, the controller 10 includes a weight assignment unit 10A and a cell detection unit 10B as processing blocks. The weight assigning unit 10A has a function of calculating an average luminance level of the input video signal VSi and assigning a luminance weight corresponding to the average luminance level to each subfield constituting each field of the input video signal VSi. The cell detector 10B has a function of detecting a discharge cell having a light emission pattern that matches a predetermined condition from the discharge cells CL,..., CL based on the input video signal VSi. Details of the function of the cell detector 10B will be described later. The controller 10 has a function of controlling the operation of the drive control unit 11 using a synchronization signal (including a horizontal synchronization signal and a vertical synchronization signal) and a clock signal supplied from an external signal source (not shown). Have.

  All or part of the processing blocks 10 to 13 may be realized by a hardware circuit configuration, or may be realized by a program or program code recorded on a recording medium such as a nonvolatile memory or an optical disk. Good. Such a program or program code causes a processor such as a CPU to execute all or part of the processing of the processing blocks 10 to 13.

  The gradation adjusting unit 12 performs an error diffusion process and a dither process on the video signal VSa input from the controller 10 to generate a gradation adjustment signal VSb. For example, the gradation adjusting unit 12 can obtain a 6-bit signal by performing error diffusion that diffuses the lower 2 bits of the pixel data of the 8-bit video signal VSa into the upper 6 bits of the peripheral pixel data. Further, the gradation adjusting unit 12 can obtain the upper 4-bit gradation adjustment signal VSb by performing bit shift after adding the elements of the dither matrix to the 6-bit signal obtained by error diffusion, for example. .

  The drive data generation unit 13 has a function of converting the gradation adjustment signal VSb into the drive data signal DD in accordance with a conversion table corresponding to the subfield method drive sequence. The memory circuit 14 temporarily stores a drive data signal DD that is an output of the drive data generation unit 13. At the same time, the memory circuit 14 reads the stored data in units of subfields and transfers the read data signal DDa to the column electrode driver 15 under the control of the drive controller 11. In this way, the drive data generation unit 13 and the memory circuit 14 cooperate to exhibit a function of decomposing each field of the gradation adjustment signal VSb into a plurality of subfields and generating a data signal DDa representing these subfields. .

The column electrode driver 15, an address pulse generated based from the memory circuit 14 to the transfer data signal DDa, the column electrode D ₁ of the display panel 2 these address pulse at a predetermined timing, ..., D _m (m is (Integer of 2 or more).

The display panel 2 includes a plurality of discharge cells CL,..., CL arranged in a plane and in a matrix, and m column electrodes (that is, address electrodes) D extending from the column electrode driving unit 15 in the column direction. ₁ ,..., D _m , n common electrodes X ₁ ,..., X _n extending in the row direction from the first row electrode driving unit 16A and the second row electrode driving unit 16B. N scanning electrodes Y ₁ ,..., Y _n extending in the row direction. The common electrode X _j (j is a positive integer) and the corresponding scan electrode Y _j constitute one row electrode pair. Discharge cells in the intersection region between the row electrode pair X _j , Y _j and the column electrode D _k (k is a positive integer), in other words, the region corresponding to the intersection point between the row electrode pair X _j , Y _j and the column electrode D _k CL is formed. The electrode pair X _j , Y _j and the column electrode D _k are separated from each other in the thickness direction of the substrate of the display panel 2, and the discharge space in each discharge cell CL has the electrode pair X _j , Y _j and the column electrode. It is formed between _Dk .

  FIG. 3 is a plan view showing an example of the configuration of the display panel 2. 4 is a cross-sectional view taken along the line V3-V3 of the display panel 2 shown in FIG. 3, and FIG. 5 is a cross-sectional view taken along the line W2-W2 of the display panel 2 shown in FIG.

As shown in FIGS. 4 and 5, the display panel 2 includes a transparent substrate (front substrate) 22 and a back substrate 24. On the inner surface of the transparent substrate 22, row electrode pairs X _j , Y _j and X _{j + 1} , Y _{j + 1} are formed. Each common electrode X _j includes a first transparent electrode Xa and a first bus electrode Xb connected to the first transparent electrode Xa, and each scanning electrode Y _j includes a second transparent electrode Ya and the second transparent electrode Ya. The second bus electrode Yb is connected to the second bus electrode Yb. The first and second transparent electrodes Xa and Ya are made of a transparent electrode material such as ITO (indium tin oxide) or SnO ₂ , and the first and second bus electrodes Xb and Yb are row electrode pairs X _j and Y _j. In order to reduce the impedance of X _{j + 1} and Y _{j + 1} , it is made of a conductive material having a relatively low electric resistance such as Cr (chromium) or Cu (copper). A black or dark light absorption layer (black stripe) 21 is formed on the inner surface of the transparent substrate 22 between the row electrode pair X _j , Y _j and the row electrode pair X _{j + 1} , Y _{j + 1.} ing.

A dielectric layer 23 is formed as a protective layer covering the common electrodes X _j and X _{j + 1} , the scanning electrodes Y _j and Y _{j + 1} and the light absorption layer 21. The dielectric layer 23 may be composed of, for example, a single layer or a plurality of layers of a dielectric film made of a glass material and a protective film that covers the dielectric film. Examples of the protective film include an alkaline earth metal oxide film (for example, an MgO film). As shown in FIG. 3, the first bus electrodes Xb of the common electrodes X _j and X _{j + 1} extend in the row direction, and the first transparent electrode Xa protrudes from the first bus electrode Xb in the column direction and is T-shaped. The tip has a shape. Similarly, the second bus electrode Yb of the scan electrodes Y _j and Y _{j + 1} extends in the row direction, the second transparent electrode Ya protrudes from the second bus electrode Yb in the column direction, and the first transparent electrode Xa It has a T-shaped tip that faces the T-shaped tip. The light absorption layer 21 interposed between the row electrode pair X _j , Y _j and the row electrode pair X _{j + 1} , Y _{j + 1} extends in the row direction and reduces the external light reflectance. To improve contrast.

On the other hand, as shown in FIGS. 3 to 5, column electrodes D _k , D _{k + 1} and D _{k + 2} extending in the column direction are formed on the opposing surface of the back substrate 24. A protective layer 25 made of a white dielectric covering these column electrodes D _k , D _{k + 1} , D _{k + 2} is formed. On the protective layer 25, the partition 20 which forms the discharge space DS which each discharge cell CL has is provided. As shown in FIG. 3, each partition wall 20 includes a pair of partition walls 20A and 20A extending in the row direction and a plurality of partition walls 20B and 20B extending in the column direction so as to connect the pair of partition walls 20A and 20A. It is composed of ... As shown in FIGS. 4 and 5, a phosphor layer 26 is applied to the side wall of the partition wall 20 and the upper surface of the protective layer 25 below the electrode pairs X _j , Y _j and X _{j + 1} , Y _{j + 1.} ing. Each region surrounded by the barrier rib 20, the phosphor layer 26, and the dielectric layer 23 forms a discharge space DS. The discharge space DS, a discharge gas is enclosed, such as xenon, the discharge gas may be any potential difference between the common electrode X _j and the scanning electrode Y _j or the common electrode X _j and the scanning electrode Y _j, The potential difference between the _one and the column electrode D _{k + 1} causes gas discharge by an electric field formed in the discharge space DS, and generates ultraviolet rays. The ultraviolet rays excite excitons (for example, electrons and holes) of the phosphor layer 26 and cause the phosphor layer 26 to emit visible light of the emission color (red, green, or blue) of the phosphor layer 26.

  One pixel cell includes a plurality of display cells CL,. For example, one pixel cell may be constituted by the red light emitting display cell CL, the green light emitting display cell CL, and the blue light emitting display cell CL.

  6 and 7 are cross-sectional views showing other examples of the configuration of the display panel 2. 6 is a cross-sectional view taken along the line V3-V3 of the display panel 2 shown in FIG. 3, and FIG. 7 is a cross-sectional view taken along the line W2-W2 of the display panel 2 shown in FIG. In the display panel 2 of FIGS. 6 and 7, an electron emission layer 30 is formed so as to cover the dielectric layer 23. The configuration excluding the electron emission layer 30 is substantially the same as the configuration of FIGS. The electron emission layer 30 can be formed by an electron beam evaporation method or a sputtering method.

  The electron emission layer 30 is irradiated with ions to emit secondary electrons (Ion-Induced Secondary Electron) with a high secondary electron emission rate (γ value), and receives an electric field to generate electrons (hereinafter referred to as “initial electrons”). .) Is included. When the discharge cell CL is miniaturized in order to realize high definition of the plasma display device 1, there is a problem that the discharge delay is increased and the discharge delay is increased. Secondary electrons and initial electrons improve the discharge delay by causing a priming effect that lowers the discharge start voltage. In particular, when a magnesium oxide crystal is used as the electron emission material, the discharge delay can be improved. This magnesium oxide crystal can be obtained by a process in which magnesium oxide vapor and oxygen are subjected to a gas phase oxidation reaction to generate crystal nuclei, and the generated crystal nuclei are grown.

  From the viewpoint of greatly improving the discharge delay, it is preferable to use a material containing a cathode luminescence material having an emission peak in the wavelength range of 200 to 300 nanometers as the magnesium oxide crystal, particularly 230 to 250 nanometers. It is preferred to use a material comprising a cathodoluminescent material having an emission peak in the meter wavelength range. Such a magnesium oxide crystal has not only a high secondary electron emission rate (γ value) but also a high initial electron emission rate, and thus has an effect of increasing the priming effect.

In order to improve the discharge delay, a thin film made of the electron emission material may be formed on the phosphor layer 26, or crystal particles made of the electron emission material are exposed to the discharge space DS. The phosphor layer 26 may be mixed in a state. FIG. 8 is a diagram schematically showing an electron emission film 26a formed on the phosphor layer 26. FIG. 9 shows crystal particles 26e, 26e, FIG. As shown in FIG. 9, the crystal particles 26e,... Constitute the phosphor layer 26 together with the phosphor particles 26p, 26p,. When the electron emission film 26a of FIG. 8 and the crystal particles 26e of the electron emission material of FIG. 9 are used, a pulse having a negative voltage polarity is applied to the column electrode _Dk , and the common electrode _Xj or the scan electrode _Yj is positive. When a counter discharge is generated in the discharge space DS by applying a voltage polarity pulse, secondary electrons and initial electrons (priming particles) are emitted from the electron emission film 26a and the crystalline particles 26e, thereby causing a priming effect. Improve discharge delay. This priming effect will be described later.

  Various operations of the plasma display apparatus 1 having the above configuration will be described below.

<First embodiment>
FIG. 10 is a diagram schematically showing an example of a drive sequence according to the first embodiment of the present invention. In the drive sequence shown in FIG. 10, one field of the video signal is divided into N subfields SF ₁ ,..., SF _N that are successively arranged in the display order (N is an integer of 2 or more). The plasma display device 1 displays the subfields SF ₁ ,..., SF _N on the display panel 2 in order to make one multi-tone image visible to the human eye.

Referring to FIG. 10, the display period of the _first subfield SF ₁ is divided into an initial adjustment period Tr, a selective writing period (address period) Tw, and a light emission period T ₁ . Further, the display period of the subsequent subfield SF _q (q is an integer of 2 to N−1) subsequent to the _first subfield SF ₁ is divided into a selective erasing period (address period) Te, a charge adjustment period Ta, and a light emission period T _q . Has been. The display period of the last subfield SF _N which is the last subsequent subfield is divided into a selective erasure period (address period) Te, a charge adjustment period Ta, a light emission period _TN, and an erasure period Tb. 2 assigns a positive integer luminance weight W (1) to the _first subfield SF ₁ , and each of the subsequent subfields SF ₂ ,..., SF _N has a positive integer luminance weight W (2 ),..., W (N) is assigned. The lengths of the light emission periods T ₁ ,..., T _N of the subfields SF ₁ ,..., SF _N are controlled to have time lengths proportional to the luminance weights W (1),. Is done. In this embodiment, the luminance of the weight W (1), ..., W (N) , respectively, the sub-fields SF _1, ..., the light-emitting period T ₁ of the SF _N, ..., the sustaining pulses to be applied to T _N Or a value substantially proportional to this number.

FIG. 11 is a timing chart schematically illustrating a waveform of a drive signal according to the drive sequence of FIG. 11 is a signal waveform applied to column electrodes D ₁ to D _n, the signal waveform applied to the common electrode X ₁ to X _n, and the scanning electrodes Y _1, ..., signals to be respectively applied to Y _n The waveform is shown.

  Hereinafter, the drive sequence of FIG. 10 will be described with reference to the signal waveforms of FIG.

In the initial adjustment period Tr in the display period of the first subfield SF _1, the column electrode driver 15 of FIG. 2, as shown in FIG. 11, the voltage of the GND level (ground level) to the column electrodes D ₁ to D _m Is applied. The first row electrode driver 16A of FIG. 2 applies the initial adjustment pulse Pxr of positive polarity having a gentle voltage gradient whose voltage level gradually increases from the GND level to the common electrode X ₁ to X _n. At the same time, the second row electrode driver 16B in FIG. 2, positive initial adjustment pulse Pyr with gentle voltage gradient whose voltage level gradually increases from the GND level, ..., the Pyr, respectively, scan electrodes Y _1, ... , Y _n . Thereby, positive ion particles are accumulated on the wall surface of the dielectric layer 23 (FIG. 4) near the common electrodes X _{1 to} X _n , and positive ions are accumulated on the wall surface of the dielectric layer 23 near the scan electrodes Y _{1 to} Y _n. Particles are accumulated, and negative ion particles are accumulated on the wall surface of the phosphor layer 26 (FIG. 4) close to the column electrodes D _{1 to} D _m .

  In the present specification, the “positive polarity” pulse means a pulse having a voltage level higher than a predetermined reference level (eg, GND level). The “negative polarity” pulse means a pulse having a voltage level lower than the reference level.

Next, the first subfield SF ₁ selective write period Tw, initially, the first row electrode driver 16A has a negative voltage gradient is a voltage level gradually decreases from the GND level as shown in FIG. 11 A wedge-shaped adjustment pulse Pxc is applied to the common electrodes X _{1 to} X _n . At the same time, the second row electrode driver 16B is a wedge-shaped adjustment pulse Pyc with a negative voltage gradient is a voltage level gradually decreases from the GND level, ..., respectively the scanning electrodes Y ₁ to Pyc, ..., is applied to the Y _n . At this time, the column electrode driver 15 applies a GND level voltage to the column electrodes D _{1 to} D _m .

Subsequently, the second row electrode driver 16B sequentially applies a negative scan pulse Ps to the scan electrodes Y ₁ ,..., Y _n . At the same time, the column electrode driver 15, the write pulse group Dw ₁ positive polarity, ..., the column electrodes D ₁ to synchronize each Dw _n to each scanning pulse Ps, ..., is applied to the D _m. For example, while a scanning pulse Ps to the first scanning electrode Y ₁ is applied, the write pulse group Dw ₁ synchronized with the scanning pulse Ps is the column electrodes D _1, ..., it is applied to the D _m. While subsequently second scan electrode Y ₂ in the scanning pulse Ps is applied, the write pulse group Dw ₂ synchronized with the scanning pulse Ps is the column electrodes D _1, ..., is applied to the D _m. Generally, while a scanning pulse Ps to the j-th scanning electrode Y _j is applied, the column electrodes D ₁ write pulse group Dw _j synchronized with the scanning pulse Ps is, ..., is applied to the D _m. As a result, the write discharge is selectively generated in the discharge cells CL,..., CL of the display panel 2, and only the initially selected cells CL excluding the specific discharge cells to be displayed with the black level luminance can emit light. Set to

More specifically, referring to FIG. 4, while the negative scan pulse Ps is applied to the scan electrode Y _j , the positive pulse of the write pulse group Dw _j synchronized with the scan pulse Ps is selectively used. when applied to the column electrode D _{k + 1,} the gas discharge due to the potential difference between the column electrode D _{k + 1} is a scanning electrode Y _j and the anode is a cathode in the discharge space DS (i.e. write discharge) is Is generated, thereby generating ionic particles. Among the generated ion particles, positive ion particles are attracted to the wall surface of the dielectric layer 23 near the cathode Y _j , and negative ion particles are attracted to the wall surface of the phosphor layer 26 near the anode D _{k + 1} . Then, the discharge voltage is lowered and the writing discharge is stopped. At the time of occurrence of the write discharge, an offset pulse Pop having a polarity (that is, positive polarity) opposite to the voltage polarity (that is, negative polarity) of the scan electrode Y _j is applied to all the common electrodes X _{1 to} X _n . Negative ion particles are accumulated on the wall surface of the dielectric layer 23 close to the common electrode X _j . As a result, ion particles having different charge polarities, that is, wall charges, are accumulated on the wall surface close to the common electrode X _j and the wall surface close to the scanning electrode Y _j . The discharge cell CL having such a wall charge distribution is set in a light emission enabled state.

On the other hand, when the write pulse synchronized with the scan pulse Ps is not applied to the column electrode D _{k + 1} while the negative scan pulse Ps is applied to the scan electrode Y _j , the gas discharge is performed in the discharge space DS. Does not occur. Therefore, ion particles having the same charge polarity are accumulated on the wall surface close to the common electrode X _j and the wall surface close to the scanning electrode Y _j . The discharge cell CL having such a wall charge distribution is set to a non-light emitting state.

As described above, immediately before the scanning pulse Ps and the offset pulse Pop is applied, the wedge-shaped adjustment pulse Pxc, Pyc is applied to the common electrode X ₁ to X _n and the scan electrodes Y ₁ to Y _n. These adjustment pulses Pxc and Pyc optimize the wall charge distribution in the discharge space DS in order to stably generate the write discharge, and are strong enough to reverse the charge polarity of the wall surface near each electrode. It does not cause discharge.

Next, in the light emission period T ₁ (FIG. 10) of the _first subfield SF ₁ , the second row electrode driver 16B applies a positive voltage pulse to each row electrode pair as a discharge sustaining pulse. The sustaining pulse is applied only an odd number of times assigned to the _first subfield SF1. In the example of FIG. 11, a GND level voltage is applied to the column electrodes D _{1 to} D _m . At this time, one positive sustaining pulse P ⁺ is applied to each of the scan electrodes Y _{1 to} Y _n , and at the same time, a GND level voltage pulse P ⁻ is applied to each of the common electrodes X _{1 to} X _n. Is done. Immediately before the application of the sustaining pulse, in the initially selected cell CL set to the light emission enabled state, the negative ion particles accumulated on the wall surface near the common electrode X _j and the positive ion accumulated on the wall surface near the scanning electrode Y _j. The ion particles form a weak electric field in the discharge space DS. In this state, if a discharge sustaining pulse P ⁺ is applied to the scan electrode Y _j and a voltage pulse P ⁻ is applied to the common electrode X _j , the electric field formed in the discharge space DS by these pulses P ⁺ and P ⁻ is generated. Superposed on existing weak electric field. The superimposed electric field causes a strong gas discharge (that is, a sustain discharge), thereby generating ion particles. Among the generated ion particles, negative ion particles are attracted to the scanning electrode Y _j, positive since ion particles are attracted to the common electrode X _j, the common electrode X _j and the wall surface of the charge polarity close to the scanning electrode Y _j The polarity of the charge on the wall near is reversed. The ultraviolet rays generated by the sustain discharge excite the excitons of the phosphor layer 26 to emit visible light.

Here, in the example of FIG. 11, for improving image quality in a low luminance region, it has been applied one discharge sustaining pulse P ⁺ to each of the scan electrodes Y ₁ to Y _n, being limited thereto Absent. The sustaining pulse P ⁺ may be applied alternately to the scanning electrode Y _j and the common electrode X _j of each row electrode pair. In this case, the number of sustaining pulse P ⁺ is applied to the scanning electrode Y _j of each row electrode pair to the light-emitting period T _1, the sum of the corresponding discharge sustaining pulse P ⁺ the number of which is applied to the common electrode X _j It is adjusted to be an odd number.

Next, in the selective erasing period Te (FIG. 10) of the subsequent subfield SF ₂ , first, the first row electrode driver 16 </ _b > A has a negative voltage at which the voltage level gradually decreases from the GND level as shown in FIG. 11. A wedge-shaped adjustment pulse Pxc having a gradient is applied to the common electrodes X _{1 to} X _n . At the same time, the second row electrode driver 16B is a wedge-shaped adjustment pulse Pyc with a negative voltage gradient is a voltage level gradually decreases from the GND level, ..., respectively the scanning electrodes Y ₁ to Pyc, ..., is applied to the Y _n . At this time, the column electrode driver 15 applies a GND level voltage to the column electrodes D _{1 to} D _m . Similar to the adjustment pulses Pxc and Pyc applied in the selective writing period Tw of the _first subfield SF ₁ , these adjustment pulses Pxc and Pyc are the wall charge distribution in the discharge space DS in order to stably cause the selective erasure discharge. Is to optimize.

Subsequently, the second row electrode driver 16B sequentially applies a negative scan pulse Ps to the scan electrodes Y ₁ ,..., Y _n . At the same time, the column electrode driving unit 15, the selective erase pulse group De ₁ of positive polarity, ..., the column electrodes D ₁ to synchronize the respective De _n to each scanning pulse Ps, ..., is applied to the D _m. For example, while a scanning pulse Ps to the first scanning electrode Y ₁ is applied, the selective erase pulse group De ₁ synchronized with the scanning pulse Ps is the column electrodes D _1, ..., it is applied to the D _m. While subsequently second scan electrode Y ₂ in the scanning pulse Ps is applied, selective erasure pulse group De ₂ synchronized with the scanning pulse Ps is the column electrodes D _1, ..., it is applied to the D _m. In general, the scan pulse selects the erase pulse group De _j synchronized with Ps column electrodes D ₁ while the scanning pulse Ps to the j-th scanning electrode Y _j is applied, ..., it is applied to the D _m. As a result, gas discharge (that is, selective erasure discharge) is selectively generated in the initially selected cells CL,. The

More specifically, referring to FIG. 4, while the negative scan pulse Ps is applied to the scan electrode Y _j , the positive pulse of the selective erasing pulse group De _j synchronized with the scan pulse Ps is selectively used. when applied to the column electrode D _{k + 1,} the discharge space DS in selective erase discharge of the scan electrode Y _j and the anode a is the column electrode D _k due to the potential difference between the _{+ 1} initial selection cell CL is cathode Is generated, thereby generating ionic particles. Among the generated ion particles, positive ion particles are attracted to the wall surface near the cathode Y _j , and negative ion particles are attracted to the wall surface near the anode D _{k + 1.} Stop. Since the offset pulse Pom having the same polarity (that is, negative polarity) as the voltage polarity (that is, negative polarity) of the scanning electrode Y _j is applied to all the common electrodes X _{1 to} X _n when the selective erasing discharge is generated. Positive ion particles are accumulated on the wall surface near the electrode X _j . As a result, ion particles having the same charge polarity are accumulated on the wall surface close to the common electrode X _j and the wall surface close to the scanning electrode Y _j , and the discharge cell CL in which the selective erasing discharge has occurred is set to a non-light emitting state.

On the other hand, in the initial selected cell CL in which the selective erasing discharge does not occur, ion particles having different charge polarities are accumulated on the wall surface close to the common electrode X _j and the wall surface close to the scanning electrode Y _j . The state of the discharge cell CL having such a wall charge distribution is maintained in a light emission enabled state.

Then, the subsequent subfields SF ₂ charge adjustment period Ta, as shown in FIG. 11, the first row electrode driver 16A applies a positive polarity adjusting pulse Pxa to the common electrode X ₁ to X _n. At the same time, the second row electrode driver 16B applies an adjustment pulse Pya having the same polarity as the voltage polarity of the adjustment pulse Pxa to each of the scan electrodes Y _{1 to} Y _n . These adjustment pulse Pxa, the voltage level of Pya is controlled to a voltage substantially the same level of the sustaining pulse applied to the light-emitting period T _2.

In the emission period T ₂ of the immediately following charge adjustment period Ta, a second row electrode driver 16B applies alternately a positive polarity sustaining pulse P ⁺ of each row electrode pair to the scan electrode Y _j and the common electrode X _j. Here, when the sustaining pulse P ⁺ is applied to the scan electrode Y _j of each row electrode pair, a voltage pulse P ⁻ of the reference potential (GND level) is applied to the corresponding common electrode X _j , and each row electrode pair When the discharge sustaining pulse P ⁺ is applied to the common electrode X _j , the reference potential voltage pulse P ⁻ is applied to the corresponding scanning electrode Y _j . A sustaining pulse P ⁺ the number of which is applied to the scanning electrode Y _j of each row electrode pair to the light-emitting period T _2, the sum of the corresponding discharge sustaining pulse P ⁺ the number of which is applied to the common electrode X _j, the discharge cells wall charge distribution within CL is adjusted to be an even number so as not to substantially change before and after the emission period T _2.

Referring to FIG. 11, a GND level voltage is applied to the column electrodes D _{1 to} D _m during the light emission period T ₂ . At this time, the sustaining pulse P ⁺ is alternately applied to the scanning electrode _Yj of each row electrode pair and the corresponding common electrode _Xj . Thus each row electrode pair X _j, Y _j voltage pulse applying a potential difference P ^+, P ^- by is applied, the discharge space DS of the discharge cells CL emission enable state, and the common electrode X _j scan electrodes Sustain discharge repeatedly occurs between _Yj . The ultraviolet rays generated by the sustain discharge excite excitons of the phosphor layer 26 to emit visible light.

Here, in the signal waveform of FIG. 11, as shown in the partially enlarged view of FIG. 12A, the first row electrode driving unit 16A applies the adjustment pulse Pxa to the common electrodes X _{1 to} X _n in the charge adjustment period Ta. after applying the second row electrode driver 16B is applied to the sustaining pulse P ⁺ to the common electrode X ₁ to X _n. Therefore, adjustment pulse Pxa the sustaining pulse P ⁺ and are applied to the common electrode X ₁ to X _n temporally continuously adjusted pulse Pxa sustaining pulse P before the voltage level falls to GND level ⁺ Is applied, but instead, as shown in FIG. 12B, after the voltage level of the adjustment pulse Pxa completely falls to the GND level, the discharge sustaining pulse P ⁺ is applied. Good.

In the display period of the subsequent subfields SF _{3 to} SF _N , the same operation as that in the display period of the subsequent subfield SF ₂ is performed.

The display period of the last subfield SF _N has selective erase period Te, in addition to the charge adjusting period Ta and the light-emitting period T _N, the erase period Tb that is set immediately after the light-emitting period T _N. In the erasing period Tb, the first row electrode driver 16A and the second row electrode driver 16B apply a GND level voltage to the scan electrode Y _j of each row electrode pair and simultaneously apply to the corresponding common electrode X _j . applies a narrow pulse Pe1 high positive voltage than the potential of the scan electrodes Y _j. Subsequently, the first row electrode driver 16A and the second row electrode driver 16B apply positive voltage pulses Pe2 and Pe simultaneously to the common electrode X _j and the scan electrode Y _j of each row electrode pair, respectively.

As described above, the discharge cells CL in which the selective erasure discharge does not occur in the selective erasure period Te of the subsequent subfields SF _{2 to} SF _N are continuously set in the light emission enabled state until immediately before the erasure period Tb. In this discharge cell CL, at the end of the light emission period T _N of the final subfield SF _N , positive ion particles are accumulated on the wall surface near the common electrode X _j and negative ion particles are accumulated on the wall surface near the scan electrode Y _j . Has wall charge distribution. In this state, the erase period Tb, when the voltage pulse of the GND level is applied to the common electrode X _j positive pulse Pe1 narrow is applied to and the scanning electrode Y _j, each row electrode pair X _j, between Y _j A weak discharge is generated in the discharge space DS. Subsequently, positive voltage pulses Pe2 and Pe are simultaneously applied to the row electrode pairs _Xj and _Yj , respectively, so that negative ion particles in the discharge space DS are in the vicinity of the row electrode pairs _Xj and _Yj . The positive ion particles are attracted to the wall surface and are attracted to the wall surface in the vicinity of each column electrode D _k to which a GND level voltage is applied.

On the other hand, the discharge cells CL in which no write discharge occurs in the selective write period Tw of the top subfield SF ₁ are set to the non-light-emitting state throughout. In this discharge cell CL, at the end of the light emission period T _N of the final subfield SF _N , negative ion particles are accumulated on the wall surface near the common electrode X _j and negative ion particles are accumulated on the wall surface near the scan electrode Y _j . Has wall charge distribution. Therefore, the charge polarity (negative polarity) on the wall surface close to the common electrode X _j does not change before and after the erasing period Tb, and the charge polarity (negative polarity) on the wall surface close to the scanning electrode Y _j does not change.

On the other hand, before reaching the light emission period T _N of the final subfield SF _N , the discharge cell CL does not emit light in the selective erasure period Te of any subsequent subfield SF _p (p is any one of 2 to N). When set to the state, the discharge cell CL is formed on the wall surface near the scanning electrode Y _j where negative ion particles are accumulated on the wall surface near the common electrode X _j at the end of the light emission period T _N of the final subfield SF _N. It has a wall charge distribution in which negative ion particles are accumulated. Therefore, the charge polarity (negative polarity) on the wall surface close to the common electrode X _j does not change before and after the erasing period Tb, and the charge polarity (negative polarity) on the wall surface close to the scanning electrode Y _j does not change.

FIG. 13 illustrates a light emission pattern of the discharge cell CL that can be realized when the drive sequence of FIG. 10 is employed. FIG. 13 shows the relationship between the gradation level of the video signal and the corresponding emission pattern when each field of the video signal is decomposed into ₁₂ subfields SF _{1 to} SF ₁₂ . FIG. 13 shows the relationship between the gradation level and the value of the gradation adjustment signal VSb corresponding to the gradation level, and the relationship (conversion table) between the value of the gradation adjustment signal VSb and the value of the drive data signal DD. It is shown. In FIG. 13, the symbol “◎” means that the write discharge is selectively generated in the selective write period Tw of the _first subfield SF ₁ and the sustain discharge is generated in the light emission period T ₁ . Further, the symbol "○" means that the sustain discharge in one of the light-emitting period T ₂ through T ₁₂ subfields SF ₂ - SF ₁₂ occurs, the symbol "●" is subfields SF ₂ - SF ₁₂ This means that selective erasure discharge occurs in any of the selective erasure periods Te.

  When the luminance of the gradation level g of the video signal is represented by L (g), the luminance L (g) is given by the following equation.

Here, N is the total number of subfields SF _{1 to} SF _{N. In} the case of FIG. 13, N = 12. B (g; i) takes a value “1” when the discharge cell CL is in a light emitting state in the i-th subfield SF _i with respect to the luminance level g, and a value “0” when the discharge cell CL is in a non-light emitting state. Take. W (i) is a luminance weight assigned to the i-th subfield SF _i as described above. For example, W (1) = 1, W (2) = 2, W (3) = 4, W (4) = 8, W (5) = 12, W (6) = 16, W (8) = 22 , W (9) = 28, W (10) = 34, W (11) = 40, W (12) = 46, W (13) = 42. The luminance L (g) shown in the table is realized.

According to the light emission pattern shown in FIG. 13, the state change of the discharge cell CL in the display period of one field can be classified into the following three types of patterns. That is, 1) after the state of the discharge cell CL is set from the non-light emitting state (“black” state) to the light emitting enabled state (“white” state) by the write discharge in the selective writing period Tw of the _first subfield SF _1. The first pattern corresponding to the maximum gradation level “N” maintained in the light emission enabled state (“white” state) until immediately before the erasing period Tb of the final subfield SF _N and 2) the state of the discharge cell CL After setting from the non-light emitting state (“black” state) to the light emitting enabled state (“white” state) by the write discharge in the selective writing period Tw of the _first subfield SF ₁ , the subsequent subfields SF _{2 to} SF _{N− A} second pattern corresponding to gradation levels “1” to “N−1” set to a non-light emitting state (“black” state) by selective erasing discharge in any one of selective erasing periods Te; and 3) The discharge cell CL is in a non-light emitting state (“black” state) ) And the third pattern corresponding to the gradation level “0” ending in the non-light emitting state (“black” state).

FIGS. 14A, 14B, and 14C show transitions of wall charge distributions corresponding to the first, second, and third patterns, respectively. In each of FIGS. 14A, 14B, and 14C, the discharge cell CL has a wall surface close to the common electrode _Xj in the erasing period Tb of the immediately preceding field with respect to the current field (current field). Negative ion particles are accumulated, negative ion particles are accumulated on the wall surface close to the scan electrode Y _j , and positive ion particles are accumulated on the wall surface close to the column electrode D _k , ie, a “black” state (that is, a non-black state). (Light emission state).

After the initial adjustment period Tr of the _first subfield SF ₁ ends, the state of the discharge cell CL is negative on the wall surface near the common electrode X _j as shown in FIGS. The ion particles are accumulated, the negative ion particles are accumulated on the wall surface close to the scanning electrode Y _j , and the “black” state representing the wall charge distribution in which the positive ion particles are accumulated on the wall surface close to the column electrode D _k .

In this initial adjustment period Tr, as shown in FIG. 11, a GND level voltage is applied to the column electrodes D _{1 to} D _m , and a positive initial adjustment pulse Pxr is applied to the common electrodes X _{1 to} X _n . A positive initial adjustment pulse Pyr is applied to the scan electrodes Y _{1 to} Y _n . Through this initial adjustment period Tr, initialization is performed so that the wall charge distribution in the discharge cell CL becomes the optimum distribution. That is, when the wall charge distribution in the discharge cell CL is not the optimum distribution, the ion particles are moved by the electric field formed in the discharge space DS by the initial adjustment pulses Pxr and Pyr, or a minute discharge is caused to cause the wall charge distribution. Is adjusted. When a micro discharge is generated, the intensity of the micro discharge is weak and cannot reverse the charge polarity of ion particles on the wall surface near the electrodes X _j , Y _j , and D _k . For this reason, the visible light emitted from the phosphor layer 26 by such a minute discharge hardly contributes to the background light emission luminance, and hardly reduces the dark place contrast.

The first pattern shown in FIG. 14A will be described below. The first subfield SF ₁ selective write period Tw, as shown in FIG. 11, the offset pulse Pop having a positive polarity is applied to the common electrode X _j, a negative polarity scan pulse Ps is applied to the scanning electrode Y _j Then, a positive writing pulse synchronized with the scanning pulse Ps is applied to the column electrode _Dk . As a result, a write discharge is generated in the discharge space DS between the column electrode D _k and the scan electrode Y _j . As a result, as shown in FIG. 14A, after the selective writing period Tw ends, positive ion particles are accumulated on the wall surface near the scanning electrode Y _j , and negative ion particles are accumulated on the wall surface near the common electrode X _j. And negative ion particles are accumulated on the wall surface close to the column electrode D _k . The common electrode X _j for offset pulse Pop having a positive polarity is applied, the negative ion particles are attracted to the wall surface closer to the common electrode X _j, it can exist stably. Accordingly, the discharge cell CL is set to a “white” state (that is, a light emission enabled state) of the wall charge distribution in which ion particles having opposite charge polarities are accumulated on the wall surfaces close to the electrodes X _j and Y _j .

Thereafter, in the light emission period T _{1 of the first} subfield SF ₁ , as shown in FIG. 11, the column electrode D _k has a negative polarity lower than the voltage of the sustaining pulse P ⁺ applied to the scan electrode Y _j. Side voltage (GND level voltage) is applied. Further, the sustaining pulse P ⁺ is applied to the scan electrode Y _j , and at the same time, the voltage pulse P ⁻ is applied to the common electrode X _j . Thus, the row electrode pairs X _j, sustain discharge in the discharge space DS between Y _j is occurring, opposed discharge in the discharge space DS between the column electrode D _k is a scanning electrode Y _j and the cathode an anode Is born. As a result, as shown in FIG. 14A, after the end of the light emission period T ₁ , positive ion particles are accumulated on the wall surface near the common electrode X _j and negative ion particles are accumulated on the wall surface near the scanning electrode Y _j. And positive ion particles are accumulated on the wall surface close to the column electrode _Dk .

In the case of the first pattern, since the selective erasing pulse synchronized with the scanning pulse Ps is not applied to the column electrode D _k in the selective erasing period Te of the subsequent subfields SF _{2 to} SF _N , the wall charge distribution in the discharge cell CL Hardly changes. Further, in the charge adjustment period Ta following the selective erasing period Te, positive ion particles are accumulated on the wall surface close to the column electrode _Dk , so that no gas discharge is generated in the discharge space DS.

Further, in the light emission period T _p (p is an integer of 2 to N) following the charge adjustment period Ta, as shown in FIG. 11, the discharge is alternately maintained on the scan electrode Y _j and the common electrode X _j of each electrode pair. Pulse P ⁺ is applied. At this time, the sum of the number of sustaining pulses P ⁺ applied to the scan electrode _Yj and the number of sustaining pulses P ⁺ applied to the corresponding common electrode _Xj is adjusted to be an even number. . Thereby, a sustain discharge is repeatedly generated in the discharge space DS between the pair of row electrodes X _j and Y _j , and the phosphor layer 26 is excited to emit visible light. As a result, as shown in FIG. 14A, after the light emission period T _p ends, positive ion particles are accumulated on the wall surface near the common electrode X _j , and negative ion particles are accumulated on the wall surface near the scanning electrode Y _j. In addition, positive ion particles are accumulated on the wall surface close to the column electrode D _k .

In the erase period Tb of the final subfield SF _N , as shown in FIG. 11, a narrow and positive erase pulse Pe1 is applied to the common electrode X _j , and at the same time, a GND level voltage is applied to the scan electrode Y _j. Since it is applied, a weak discharge is generated in the discharge space DS between the row electrode pair X _j , Y _j . Subsequently, since the positive pulses Pe2 and Pe are applied to the common electrode _Xj and the scanning electrode _Yj , respectively, negative ion particles are attracted to the wall surface close to the common electrode _Xj, and to the wall surface close to the scanning electrode _Yj. Negative ion particles are attracted. As a result, as shown in FIG. 14A, after the erasing period Tb ends, negative ion particles are accumulated on the wall surface near the common electrode X _j , and negative ion particles are accumulated on the wall surface near the scanning electrode Y _j. In addition, positive ion particles are accumulated on the wall surface close to the column electrode D _k .

Next, the second pattern shown in FIG. 14B will be described below. The first subfield SF ₁ selective write period Tw, writing discharge in the discharge space DS between the case of the first pattern as well as the column electrode D _k and scan electrode Y _j is induced. As a result, as shown in FIG. 14B, after the selective writing period Tw ends, positive ion particles are accumulated on the wall surface near the scanning electrode Y _j , and negative ion particles are accumulated on the wall surface near the common electrode X _j. Are accumulated, and negative ion particles are accumulated on the wall surface close to the column electrode D _k . Accordingly, the discharge cell CL is set to the “white” state.

Thereafter, in the light emission period T ₁ of the subfield SF ₁ , the discharge sustaining pulse P ⁺ is applied to the scan electrode Y _j and the GND level voltage is applied to the column electrode D _k as in the case of the first pattern. The Thus, the row electrode pairs X _j, sustain discharge in the discharge space DS between Y _j is occurring, opposed discharge in the discharge space DS between the column electrode D _k is a scanning electrode Y _j and the cathode an anode Is born. As a result, as shown in FIG. 14B, positive ion particles are accumulated on the wall surface near the common electrode X _j and negative ion particles are accumulated on the wall surface near the scanning electrode Y _j after the end of the light emission period T _1. And positive ion particles are accumulated on the wall surface close to the column electrode _Dk . In the example of FIG. 11, the number of sustaining pulses P ⁺ applied to the scan electrode Y _j is only one. However, the number is not limited to this, and the scan electrode Y _j and the common electrode X _j of each row electrode pair are alternately arranged. By applying the sustaining pulse P ⁺ , the sum of the number of sustaining pulses P ⁺ applied to the scan electrode _Yj and the number of sustaining pulses P ⁺ applied to the common electrode _Xj is set to an odd number. Good. The reason why the total sustaining pulse P ⁺ and odd number, in the selective erase period Te of the subsequent subfields, the cathode scanning electrode Y _j and the column electrode D _k and the anode between the scanning electrodes Y _j and the column electrode D _k This is to form a wall charge distribution that can cause a counter discharge.

In the case of the second pattern, as shown in FIG. 11, in the selective erasing period Te of any of the subsequent subfields SF _{2 to} SF _N , a negative offset pulse Pom is applied to the common electrode X _j , and the scan electrode A negative scan pulse Ps is applied to Y _j , and a positive selective erase pulse synchronized with this scan pulse Ps is applied to the column electrode D _k . As a result, a selective erasure discharge is generated between the column electrode D _k and the scan electrode Y _j with the column electrode D _k as an anode and the scan electrode Y _j as a cathode. As a result, as shown in FIG. 14B, after the selective erasing period Te is completed, positive ion particles are accumulated on the wall surface near the scanning electrode Y _j , and negative ion particles are accumulated on the wall surface near the column electrode D _k. Is done. Because the common electrode X _j of the negative polarity of the offset pulse Pom is applied, the wall closer to the common electrode X _j positive ion particles are attracted, can exist stably.

In the charge adjustment period Ta following the selective erasing period Te, as shown in FIG. 11, a positive adjustment pulse Pxa is applied to the common electrode X _j , and at the same time, a positive adjustment pulse Pya is applied to the scan electrode Y _j. Is applied. As a result, a counter discharge is generated between the common electrode X _{j serving} as the anode and the column electrode D _{k serving} as the cathode, and at the same time, a counter discharge is generated between the scanning electrode Y _{j serving} as the anode and the column electrode D _{k serving} as the cathode. Discharge occurs. As a result, as shown in FIG. 14B, after the end of the charge adjustment period Ta, negative ion particles are accumulated on the wall surface near the common electrode X _j , and negative ion particles are accumulated on the wall surface near the scan electrode Y _j. In addition, positive ion particles are accumulated on the wall surface close to the column electrode D _k . Accordingly, the discharge cell CL is set to the “black” state. As described above, since the counter discharge is generated between the common electrode X _j and the column electrode D _{k and} between the scan electrode Y _j and the column electrode D _k immediately after the selective erasing period Te, the counter discharge can be stably generated. Can do.

Thereafter, no gas discharge is generated in the discharge space DS in the erasing period Tb of the final subfield SF _N.

Next, for the third pattern shown in FIG. 14C, no gas discharge is generated in the discharge space DS after the initial adjustment period Tr of the _first subfield SF1 ends. Therefore, after the initial adjustment period Tr of the _first subfield SF ₁ ends, the discharge cell CL continues to be set to the “black” state over the display period of all the subfields SF _{1 to} SF _N.

As described above, the gradation control method according to the first embodiment can emit light only from the initial selected cells CL excluding the discharge cells that should display the luminance at the black level in the selective writing period Tw of the _first subfield SF _1. Since the state is set, the background light emission luminance that does not contribute to the display luminance L (g) is suppressed in the selective writing period Tw, and the dark place contrast can be improved.

In the light emission period T ₁ following the selective writing period Tw, since an odd number of sustaining pulses are applied in order to cause the sustaining discharge in the initial selected cell CL, any one of the subsequent subfields SF _{2 to} SF _N is applied. In the selective erasing period Te, a wall charge distribution capable of causing a counter discharge between the scanning electrode Y _j and the column electrode D _k can be formed. For example, as shown in FIGS. 14A and 14B, after the light emission period T ₁ of the _first subfield SF ₁ ends, negative ion particles are placed on the wall surface close to the scan electrode Y _j and close to the common electrode X _j . Positive ion particles can be accumulated on the wall surface, and positive ion particles can be accumulated on the wall surface close to the column electrode _Dk .

Furthermore, the gradation control method according to the first embodiment causes a selective erasure discharge between the scan electrode Y _j and the column electrode D _{k in} the selective erasure period Te in any of the subsequent subfields SF _{2 to} SF _N. Immediately after this, a counter discharge is generated between the scanning electrode Y _j and the column electrode D _{k and} between the common electrode X _j and the column electrode D _{k in} the charge adjustment period Ta, so that the wall surface near the common electrode X _j and the scanning electrode Y _j It is possible to obtain a non-light emitting discharge cell CL having a wall charge distribution in which ion particles of the same polarity are accumulated on a wall surface close to. Since these counter discharges are stably generated, an optimal wall charge distribution can be stably realized. For example, as shown in FIG. 14B, after the charge adjustment period Ta of the subsequent subfields SF _{2 to} SF _N ends, negative ion particles are placed on the wall surface near the scanning electrode Y _j, and the wall surface near the common electrode X _j. Thus, a non-light emitting discharge cell CL in which negative ion particles and positive ion particles are accumulated on the wall surface close to the column electrode D _k is obtained.

  By realizing such a wall charge distribution, the plasma display apparatus 1 according to the first embodiment can improve image quality by suppressing the occurrence of an unexpected erroneous discharge while improving the contrast in the dark place. It is.

<First Modification>
The drive sequence (FIG. 10) according to the first embodiment may be applied to the display panel 2 having the structure shown in FIGS. 4 and 5, or the display having the structure shown in FIGS. It may be applied to the panel 2. Furthermore, the present invention can be applied to the display panel 2 having the structure shown in FIGS.

  As described above, the initial adjustment period Tr shown in FIGS. 10 and 11 is a period provided for adjusting the wall charge distribution in the discharge cell CL. The panel structure of FIGS. 6 and 7 improves the discharge delay by improving the priming effect by the initial electrons and secondary electrons, so that a wide margin (margin) of the drive voltage can be ensured. If the structures of FIGS. 6 and 7 and the structures of FIGS. 8 and 9 are used in combination, further improvement in discharge delay and a wide driving voltage margin can be realized. Therefore, if the panel structure of FIGS. 6 to 9 is employed, the initial adjustment period Tr can be omitted, and the dark place contrast can be greatly improved.

<Second embodiment>
Next, a second embodiment of the present invention will be described. FIG. 15 is a diagram schematically illustrating an example of a drive sequence according to the second embodiment. The drive sequence of FIG. 15 is the same as the drive sequence of FIG. 10 except that it does not have the erase period Tb of the last subfield SF _N shown in FIG. In addition, the waveform of the drive signal to be applied to the display panel 2 in each period constituting one field also does not have the signal waveform of the erase period Tb of the final subfield SF _N , except that Same as waveform.

In this case, as shown in FIG. 15, immediately after the light emission period T _N of the last subfield SF _N , the display period of the _first subfield SF ₁ of the next field is started. In each field, after the light emission period T _N of the final subfield SF _N ends, the light emission enabled state of the discharge cell CL cannot be switched to the non-light emission state, and thus the light emission enabled state (“white” state) is set. The discharge cell CL may exist immediately before the _first subfield SF1 of the next field. On the other hand, in the light emission pattern of the first embodiment shown in FIG. 14, in the erase period Tb of the final subfield SF _N , the light emission enabled state of the discharge cell CL is always switched to the non-light emission state. Only the discharge cell CL in the non-light emitting state (“black” state) may exist immediately before the field SF ₁ .

Therefore, in the driving sequence according to the second embodiment, the state change of the discharge cell CL in the display period of one field can be classified into the following six types of patterns. That is, 1) a first pattern in which the state of the discharge cell CL starts from the “white” state and ends in the “white” state, as shown in FIG. 16A, and 2) as shown in FIG. First, after the discharge cell CL starts from the “white” state and is set to the “white” state by the write discharge in the selective write period Tw of the _first subfield SF ₁ , the subsequent subfields SF _{2 to} SF _N− a second pattern set in "black" state by selective erasure discharge in the _first one of the selective erase period Te, 3) as shown in FIG. 16 (C), the state of the discharge cell CL "white" A third pattern starting from the state and set to the “black” state after the initial adjustment period Tr and the selective writing period Tw of the _first subfield SF ₁ and ends in the “black” state, and 4) FIG. As shown in the figure, the state of the discharge cell CL is “black”. It begins state after being set by the writing discharge in the first subfield SF ₁ selective write period Tw in the "white" state, a fourth pattern ending in "white" state, 5) in FIG. 17 (B) As shown, after the discharge cell CL starts from the “black” state and is set to the “white” state by the write discharge in the selective writing period Tw of the _first subfield SF ₁ , the subsequent subfields SF ₂ to SF ₂ . A fifth pattern which is set to a “black” state by selective erasing discharge in any selective erasing period Te of SF _N−1 , and 6) as shown in FIG. 17C, the state of the discharge cell CL is And a sixth pattern starting from the “black” state and ending in the “black” state.

In each of FIGS. 16A, 16B, and 16C, the discharge cell CL has a wall surface close to the common electrode X _j after the display period of the immediately preceding field with respect to the current field (current field). Is set to a “white” state representing a wall charge distribution in which positive ion particles are accumulated, negative ion particles are accumulated on the wall surface near the scanning electrode Y _j , and positive ion particles are accumulated on the wall surface near the column electrode D _k. The

In such a case, after the initial adjustment period Tr of the _first subfield SF ₁ ends, as shown in FIGS. 16A, 16B, and 16C, the state of the discharge cell CL is close to the common electrode X _j . Negative ion particles are accumulated on the wall surface, negative ion particles are accumulated on the wall surface close to the scanning electrode Y _j , and positive ion particles are accumulated on the wall surface close to the column electrode D _k , which is in a “black” state. . In this initial adjustment period Tr, as shown in FIG. 11, a GND level voltage is applied to the column electrodes D _{1 to} D _m , and a positive initial adjustment pulse Pxr is applied to the common electrodes X _{1 to} X _n . A positive initial adjustment pulse Pyr is applied to the scan electrodes Y _{1 to} Y _n . As a result, the electric charge formed in the discharge space DS by the initial adjustment pulses Pxr, Pyr moves the ion particles or causes a slight discharge to adjust the wall charge distribution. As a result, after the initial adjustment period Tr ends, the wall charge distribution shown in FIGS. 16A, 16B, and 16C is generated.

The first pattern shown in FIG. 16A will be described below. In this case, the first subfield SF ₁ selective write period Tw, as shown in FIG. 11, the offset pulse Pop having a positive polarity is applied to the common electrode X _j, a negative polarity scan pulse to the scan electrodes Y _j Ps is applied, and a positive writing pulse synchronized with the scanning pulse Ps is applied to the column electrode _Dk . As a result, a counter discharge is generated in the discharge space DS between the scan electrode Y _j and the column electrode D _k . As a result, as shown in FIG. 16A, after the selective writing period Tw ends, positive ion particles are accumulated on the wall surface near the scanning electrode Y _j , and negative ion particles are accumulated on the wall surface near the common electrode X _j. Accumulated negative ion particles are accumulated on the wall surface close to the column electrode _Dk . The common electrode X _j for offset pulse Pop having a positive polarity is applied, the negative ion particles are attracted to the wall surface closer to the common electrode X _j, it can exist stably. Therefore, the discharge cell CL is set to the “white” state of the wall charge distribution in which ion particles having opposite charge polarities are accumulated on the wall surfaces close to the electrodes X _j and Y _j .

Thereafter, during the light emission period T _{1 of the first} subfield SF ₁ , as shown in FIG. 11, a GND level voltage is applied to the column electrode D _k , and a positive discharge sustaining pulse P ⁺ is applied to the scan electrode Y _j. At the same time, a voltage pulse P ⁻ at the GND level is applied to the common electrode X _j . Thus, the row electrode pairs X _j, sustain discharge in the discharge space DS between Y _j is occurring, opposed discharge in the discharge space DS between the column electrode D _k is a scanning electrode Y _j and the cathode an anode Is born. As a result, as shown in FIG. 16A, after the end of the light emission period T ₁ , positive ion particles are accumulated on the wall surface near the common electrode X _j , and negative ion particles are accumulated on the wall surface near the scanning electrode Y _j. And positive ion particles are accumulated on the wall surface close to the column electrode D _k .

In the case of the first pattern, since the selective erasing pulse synchronized with the scanning pulse Ps is not applied to the column electrode D _k in the selective erasing period Te of the subsequent subfields SF _{2 to} SF _N , the wall charge distribution in the discharge cell CL Hardly changes. Further, in the charge adjustment period Ta following the selective erasing period Te, positive ion particles are accumulated on the wall surface close to the column electrode _Dk , so that no gas discharge is generated in the discharge space DS.

In the light emission period T _p (p is an integer of 2 to N) subsequent to the charge adjustment period Ta, as shown in FIG. 11, the discharge sustain pulse P ⁺ is alternately applied to the scan electrode Y _j and the common electrode X _j. However, the sum of the number of sustaining pulses P ⁺ applied to the scan electrode _Yj and the number of sustaining pulses P ⁺ applied to the common electrode _Xj is adjusted to be an even number. Thereby, a sustain discharge is repeatedly generated in the discharge space DS between the pair of row electrodes X _j and Y _j , and the phosphor layer 26 is excited to emit visible light. As a result, as shown in FIG. 16A, after the end of the light emission period T _p , positive ion particles are accumulated on the wall surface near the common electrode X _j , and negative ion particles are accumulated on the wall surface near the scanning electrode Y _j. In addition, positive ion particles are accumulated on the wall surface close to the column electrode D _k .

Next, the second pattern shown in FIG. 16B will be described below. In this case, the first subfield SF ₁ selective write period Tw, writing discharge in the discharge space DS between the case of the first pattern as well as the column electrode D _k and scan electrode Y _j is occurring Is done. Subsequently, during the light emission period T ₁ , as in the case of the first pattern, a sustain discharge is generated in the discharge space DS between the row electrode pair X _j and Y _j , and the scan electrode Y _j that is an anode A counter discharge is generated in the discharge space DS between the cathode and the column electrode _Dk . As a result, as shown in FIG. 16B, positive ion particles are accumulated on the wall surface near the common electrode X _j and negative ion particles are accumulated on the wall surface near the scanning electrode Y _j after the end of the light emission period T _1. Then, positive ion particles are accumulated on the wall surface close to the column electrode _Dk .

In the case of the second pattern, as shown in FIG. 11, in the selective erasing period Te of any of the subsequent subfields SF _{2 to} SF _N , a negative offset pulse Pom is applied to the common electrode X _j , and the scan electrode A negative scan pulse Ps is applied to Y _j , and a positive selective erase pulse synchronized with this scan pulse Ps is applied to the column electrode D _k . As a result, a selective erasure discharge is generated between the column electrode D _k and the scan electrode Y _j with the column electrode D _k as an anode and the scan electrode Y _j as a cathode. As a result, as shown in FIG. 16B, after the selective erasing period Te ends, positive ion particles are accumulated on the wall surface near the scanning electrode Y _j , and negative ion particles are accumulated on the wall surface near the column electrode D _k. Is done. Because the common electrode X _j of the negative polarity of the offset pulse Pom is applied, the wall closer to the common electrode X _j positive ion particles are attracted, can exist stably.

In the charge adjustment period Ta following the selective erasing period Te, as shown in FIG. 11, a positive adjustment pulse Pxa is applied to the common electrode X _j , and at the same time, a positive adjustment pulse Pya is applied to the scan electrode Y _j. Is applied. As a result, a counter discharge is generated between the common electrode X _{j serving} as the anode and the column electrode D _{k serving} as the cathode, and at the same time, a counter discharge is generated between the scanning electrode Y _{j serving} as the anode and the column electrode D _{k serving} as the cathode. Discharge occurs. As a result, as shown in FIG. 16B, after the end of the charge adjustment period Ta, negative ion particles are accumulated on the wall surface near the common electrode X _j , and negative ion particles are accumulated on the wall surface near the scan electrode Y _j. In addition, positive ion particles are accumulated on the wall surface close to the column electrode D _k . Accordingly, the discharge cell CL is set to the “black” state. As described above, since the counter discharge is generated between the common electrode X _j and the column electrode D _{k and} between the scan electrode Y _j and the column electrode D _k immediately after the selective erasing period Te, the counter discharge can be stably generated. Can do.

Next, the third pattern shown in FIG. 16C will be described below. In this case, no gas discharge is generated in the discharge space DS after the initial adjustment period Tr of the _first subfield SF ₁ ends. Therefore, after the initial adjustment period Tr of the _first subfield SF ₁ ends, the discharge cell CL continues to be set to the “black” state over the display period of all the subfields SF _{1 to} SF _N.

Next, the fourth pattern shown in FIG. 17A will be described below. In this case, the first subfield SF ₁ selective write period Tw, as shown in FIG. 11, the offset pulse Pop having a positive polarity is applied to the common electrode X _j, a negative polarity scan pulse to the scan electrodes Y _j Ps is applied, and a positive writing pulse synchronized with the scanning pulse Ps is applied to the column electrode _Dk . As a result, a counter discharge is generated in the discharge space DS between the scan electrode Y _j and the column electrode D _k . As a result, as shown in FIG. 17A, after the end of the selective writing period Tw, positive ion particles are accumulated on the wall surface near the scanning electrode Y _j , and negative ion particles are accumulated on the wall surface near the column electrode D _k. Accumulated. The common electrode X _j for offset pulse Pop having a positive polarity is applied, the negative ion particles are attracted to the wall surface closer to the common electrode X _j, it can exist stably. Therefore, the discharge cell CL is set to the “white” state of the wall charge distribution in which ion particles having opposite charge polarities are accumulated on the wall surfaces close to the electrodes X _j and Y _j .

Thereafter, in the light emission period T _{1 of the first} subfield SF ₁ , as shown in FIG. 11, a GND level voltage is applied to the column electrode D _k , and a positive discharge sustaining pulse P ⁺ is applied to the scan electrode Y _j. At the same time, a GND level voltage P ⁻ is applied to the common electrode X _j . Thus, the row electrode pairs X _j, sustain discharge in the discharge space DS between Y _j is occurring, opposed discharge in the discharge space DS between the column electrode D _k is a scanning electrode Y _j and the cathode an anode Is born. As a result, as shown in FIG. 17A, after the light emission period T ₁ ends, positive ion particles are accumulated on the wall surface near the common electrode X _j , and negative ion particles are accumulated on the wall surface near the scanning electrode Y _j. And positive ion particles are accumulated on the wall surface close to the column electrode _Dk .

In the case of the fourth pattern, since the selective erasing pulse synchronized with the scanning pulse Ps is not applied to the column electrode _Dk in the selective erasing period Te of the subsequent subfields SF _{2 to} SF _N , the wall charge distribution in the discharge cell CL Hardly changes. Further, in the charge adjustment period Ta following the selective erasing period Te, positive ion particles are accumulated on the wall surface close to the column electrode _Dk , so that no gas discharge is generated in the discharge space DS. In the light emission period T _p (p is an integer of 2 to N) following the charge adjustment period Ta, as shown in FIG. 11, the discharge sustaining pulse P ⁺ is alternately applied to the scan electrode Y _j and the common electrode X _j. Is done. The number of sustaining pulses P ⁺ applied at this time is adjusted to be an even number. Thereby, a sustain discharge is repeatedly generated in the discharge space DS between the pair of row electrodes X _j and Y _j , and the phosphor layer 26 is excited to emit visible light. As a result, as shown in FIG. 17A, after the emission period T _p ends, positive ion particles are accumulated on the wall surface near the common electrode X _j , and negative ion particles are accumulated on the wall surface near the scanning electrode Y _j. In addition, positive ion particles are accumulated on the wall surface close to the column electrode D _k .

Next, the fifth pattern shown in FIG. 17B will be described below. In this case, in the selective writing period Tw of the _first subfield SF ₁ , the writing discharge is generated in the discharge space DS between the column electrode D _k and the scanning electrode Y _j as in the case of the fourth pattern. Is done. Subsequently, in the light emission period T ₁ , as in the case of the fourth pattern, a sustain discharge is generated in the discharge space DS between the row electrode pair X _j and Y _j , and the scan electrode Y _j that is an anode A counter discharge is generated in the discharge space DS between the column electrode _Dk which is a cathode. As a result, as shown in FIG. 17B, after the light emission period T ₁ ends, positive ion particles are accumulated on the wall surface near the common electrode X _j , and negative ion particles are accumulated on the wall surface near the scanning electrode Y _j. Then, positive ion particles are accumulated on the wall surface close to the column electrode _Dk .

In the case of the fifth pattern, a negative offset pulse Pom is applied to the common electrode X _j in the selective erasing period Te of any of the subsequent subfields SF _{2 to} SF _N , as shown in FIG. A negative scan pulse Ps is applied to Y _j , and a positive selective erase pulse synchronized with this scan pulse Ps is applied to the column electrode D _k . As a result, a selective erasure discharge is generated between the column electrode D _k and the scan electrode Y _j with the column electrode D _k as an anode and the scan electrode Y _j as a cathode. As a result, as shown in FIG. 17B, after the selective erasing period Te is completed, positive ion particles are accumulated on the wall surface near the scan electrode Y _j , and negative ion particles are accumulated on the wall surface near the column electrode D _k. Is done. Because the common electrode X _j of the negative polarity of the offset pulse Pom is applied, the wall closer to the common electrode X _j positive ion particles are attracted, can exist stably.

In the charge adjustment period Ta following the selective erasing period Te, as shown in FIG. 11, a positive adjustment pulse Pxa is applied to the common electrode X _j , and at the same time, a positive adjustment pulse Pya is applied to the scan electrode Y _j. Is applied. As a result, a counter discharge is generated between the common electrode X _{j serving} as the anode and the column electrode D _{k serving} as the cathode, and at the same time, a counter discharge is generated between the scanning electrode Y _{j serving} as the anode and the column electrode D _{k serving} as the cathode. Discharge occurs. As a result, as shown in FIG. 17B, after the end of the charge adjustment period Ta, negative ion particles are accumulated on the wall surface near the common electrode X _j , and negative ion particles are accumulated on the wall surface near the scanning electrode Y _j. In addition, positive ion particles are accumulated on the wall surface close to the column electrode D _k . Accordingly, the discharge cell CL is set to the “black” state. As described above, since the counter discharge is generated between the common electrode X _j and the column electrode D _{k and} between the scan electrode Y _j and the column electrode D _k immediately after the selective erasing period Te, the counter discharge can be stably generated. Can do.

Next, the sixth pattern shown in FIG. 17C will be described below. In this case, no gas discharge is generated in the discharge space DS after the initial adjustment period Tr of the _first subfield SF ₁ ends. Therefore, after the initial adjustment period Tr of the _first subfield SF ₁ ends, the discharge cell CL continues to be set to the “black” state over the display period of all the subfields SF _{1 to} SF _N.

As described above, the gradation control method according to the second embodiment is similar to the gradation control method according to the first embodiment in the scanning electrode Y during the selective erasing period Te in one of the subsequent subfields SF _{2 to} SF _{N. A} selective erasure discharge is generated between _j and the column electrode D _k, and a counter discharge is generated between the scan electrode Y _j and the column electrode D _{k and} between the common electrode X _j and the column electrode D _{k in} the charge adjustment period Ta immediately after this. By waking up, it is possible to obtain a non-light emitting discharge cell CL having a wall charge distribution in which ion particles of the same polarity are accumulated on the wall surface close to the common electrode X _j and the wall surface close to the scanning electrode Y _j . Since these counter discharges are stably generated, an optimal wall charge distribution can be stably realized. For example, as shown in FIGS. 16B and 17B, after the charge adjustment period Ta of the subsequent subfields SF _{2 to} SF _N ends, negative ion particles are commonly used on the wall surface near the scan electrode Y _j. A non-light emitting discharge cell CL is obtained in which negative ion particles are accumulated on the wall surface near the electrode X _j and positive ion particles are accumulated on the wall surface near the column electrode D _k .

By realizing such a wall charge distribution, the gradation control method according to the second embodiment can improve the image quality by suppressing the occurrence of unexpected false discharge while improving the contrast in the dark place. It is. Further, as shown in FIG. 15, since the final subfield SF _N does not have the erasing period Tb according to the first embodiment, the background light emission luminance that does not contribute to the display luminance L (g) is suppressed, and the dark place contrast is reduced. Improvement is possible.

<Third embodiment>
Next, a third embodiment of the present invention will be described. FIG. 18 is a diagram schematically illustrating an example of a drive sequence according to the third embodiment. The drive sequence of FIG. 18 does not have the erase period Tb of the _Nth subfield SF _N shown in FIG. 10, but has the (N + 1) th subfield SF _{N + 1} except that it has the erase period Tb. Same as sequence. The (N + 1) th subfield SF _{N + 1} has only the selective erasing period Te.

In the selective erasing period Te of the subfield SF _{N + 1} , as in the selective erasing period Te (FIG. 11) of the subfield SF ₂ , a wedge-shaped adjustment pulse Pxc is applied to the common electrodes X _{1 to} X _n and simultaneously. wedge-shaped adjustment pulse Pyc, ..., the scan electrodes Y ₁ Pyc respectively, ..., is applied to the Y _n. Subsequently, scan electrodes Y _1, ..., the scanning pulse Ps having a negative polarity is sequentially applied to the Y _n, the selective erase pulse group De ₁ of positive polarity, ..., each of De _n columns in synchronism with the scanning pulse Ps Applied to the electrodes D ₁ ,..., D _m . As a result, all the discharge cells CL in the display panel 2 in the light emission enabled state are set to the non-light emission state.

FIG. 19 illustrates a light emission pattern of the discharge cell CL that can be realized when the drive sequence of FIG. 18 is adopted. FIG. 19 shows the relationship between the gradation level of the video signal and the corresponding light emission pattern when each field of the video signal is decomposed into ₁₃ subfields SF _{1 to} SF ₁₃ . FIG. 19 shows the relationship between the gradation level and the value of the gradation adjustment signal VSb corresponding to the gradation level, and the relationship (conversion table) between the value of the gradation adjustment signal VSb and the value of the drive data signal DD. It is shown. In FIG. 19, the symbol “◎” means that a write discharge is selectively generated in the selective write period Tw of the _first subfield SF ₁ and a sustain discharge is generated in the light emission period T ₁ . The symbol “◯” means that a sustain discharge occurs in any one of the light emission periods T _{2 to} T ₁₂ of the subfields SF _{2 to} SF ₁₂ , and the symbol “●” denotes the subfields SF _{2 to} SF _13. This means that selective erasure discharge occurs in any of the selective erasure periods Te.

  Similarly to the first embodiment, the plasma display device 1 according to the third embodiment can improve the image quality by suppressing the occurrence of an unexpected erroneous discharge while improving the dark place contrast. .

<Second Modification>
Next, a second modification of the first to third embodiments will be described. FIG. 20A is a diagram showing a wall charge distribution when the selective erasure discharge is normally generated in the selective erasure period Te of the subfield SF _k (k is an integer of 2 or more), and FIG. a diagram illustrating the distribution of wall charges when the selective erasure discharge in the selective erase period Te of subfield SF _k did not occur normally.

As shown in FIG. 20A, in the selective erasing period Te of the subfield SF _k , a negative scanning pulse Ps is applied to the scanning electrode Y _j , and a selective erasing pulse group De _j synchronized with the scanning pulse Ps. _Are applied to the column electrode _Dk . As a result, a counter discharge is generated in the discharge space DS between the scan electrode Y _j and the column electrode D _k . In the subsequent charge adjustment period Ta, positive adjustment pulses Pxa and Pya are applied to the electrodes X _j and Y _j , respectively. As a result, a counter discharge is generated between the common electrode X _j and the column electrode D _k , and at the same time, a counter discharge is generated between the scan electrode Y _j and the column electrode D _k , and the discharge cell CL is set to a non-light emitting state. . Therefore, in the subsequent light emission period T _k , no sustain discharge occurs in the discharge cell CL, and no visible light is emitted.

However, as shown in FIG. 20 (B), sub-field when the selective erasure discharge in SF _k selective erase period Te has not occurred normally, charge adjusting period Ta even discharge cell CL light emission ends It may be set to possible state. In such a case, in the light emission periods T _k , T _{k + 1} , T _{k + 2} ,..., A sustain discharge, that is, an erroneous discharge occurs in the discharge cell CL, thereby degrading the image quality.

To reliably suppress the occurrence of such an erroneous discharge, a plasma display device 1, in the discharge cells CL to cause selective erasure discharge in the subfields SF _k selective erase period Te, the subsequent subfields SF k _{+ 1} A selective erasing discharge can be generated in the selective erasing period Te. As shown in FIG. 21, even when the selective erasure discharge in the selective erase period Te of subfield SF _k is not occur correctly, the scanning electrode Y _j in the subsequent subfields SF k _{+ 1} of the selective erase period Te If a selective erasing discharge is generated between the column electrodes D _k , it is possible to prevent erroneous discharge during the light emission periods T _{k + 1} ,.

FIG. 22 illustrates a light emission pattern of the discharge cell CL according to the second modification. FIG. 22 shows the relationship between the gradation level of the video signal and the corresponding emission pattern when each field of the video signal is decomposed into ₁₂ subfields SF _{1 to} SF ₁₂ . In FIG. 22, the symbol “◎” means that the write discharge is selectively generated in the selective write period Tw of the _first subfield SF ₁ and the sustain discharge is generated in the light emission period T ₁ . The symbol “◯” means that the sustain discharge is generated in any one of the light emission periods T _{2 to} T ₁₁ of the subfields SF _{2 to} SF ₁₂ . Further, the symbol “●” shown in FIG. 22 indicates that the selective erasure discharge is generated in any of the selective erasure periods Te of the subfields SF _{2 to} SF ₁₂ . The symbol “Δ” indicates that the selective erasing discharge may or may not occur in any of the selective erasing periods Te of the subfields SF _{4 to} SF ₁₂ .

As shown in FIG. 22, when the drive control unit 11 of the plasma display device 1 displays a luminance of any one of the gradation levels “1” to “10” on a certain display cell CL, continuous arranged two subfields _{SF k, SF k + 1 (} k is an integer of 2 to 11) selective erase period Te, the driving circuit 15,16A so as to generate respective selective erasure discharge in Te, control 16B To do. Thus, even when the selective erasure discharge is not normally generated in the selective erasure period Te of the subfield SF _k , the drive control unit 11 performs the selective erasure discharge in the subsequent selective erasure period Te of the subfield SF _{k + 1.} It can be generated to prevent erroneous discharge. In order to prevent erroneous discharge more reliably, the drive control unit 11 performs sub-field SF _{k + 1} following the sub-field SF _{k + 1} as shown in the light emission patterns corresponding to the gradation levels “1” to “9” in FIG. A selective erasing discharge may be generated in at least one selective erasing period Te of the field SF _{k + 2} ,.

<Third Modification>
Next, a third modification of the first to third embodiments will be described. FIG. 23 is a diagram for explaining a third modification. Referring to FIG. 23, a plurality of fields F _1, F ₂ temporally consecutive, ..., when the discharge cell CL over the display period F _P forms a luminance display of a black level, a gas discharge in the discharge cells CL Therefore, the amount of priming particles is remarkably reduced as compared with other discharge cells CL. Thus, when the discharge cell CL in which the amount of priming particles is reduced performs luminance display of a light emission level (gradation level other than the black level) in the display period of the field _{FP + 1} , the discharge cell CL is discharged as compared with other discharge cells CL. There is a problem that a delay may occur.

  In order to solve such a problem, the plasma display device 1 shown in FIG. 2 includes a cell detector that detects a non-light emitting cell CL to be displayed with a black level luminance over a predetermined number of temporally continuous fields. 10B.

Drive control unit 11 according to the detection result by the cell detection section 10B, selection of the first subfield SF ₁ of the last field F _P of the temporally more fields F ₁ consecutive, F _2, ..., F _P In the write period Tw, a write discharge is generated in the non-light emitting cell CL, and the non-light emitting cell CL is set in a light emission enabled state. Therefore, in the light emission period T ₁ following the selective writing period Tw, a sustain discharge is generated between the common electrode X _j and the scan electrode Y _j . Thereafter, the drive control unit 11, in a subsequent subfield SF ₂ selective erase period Te, the non-light emitting cell CL in to rise to the selective erase discharge to set the non-light emitting cell CL to a non-emission state.

As described above, by causing discharge in the non-light emitting cell CL, the amount of priming particles is supplemented, and it becomes possible to improve the discharge delay in the display period of the field _{FP + 1} shown in FIG.

It is a figure which shows an example of the light emission pattern of a discharge cell. It is a figure which shows schematic structure of the plasma display apparatus based on the Example of this invention. It is a top view which shows the structure of the display panel of a plasma display apparatus. It is a figure which shows an example of the cross section in the V3-V3 cutting line of the display panel shown by FIG. It is a figure which shows an example of the cross section in the W2-W2 cutting line of the display panel shown by FIG. FIG. 5 is a diagram showing another example of a cross section taken along the line V3-V3 of the display panel shown in FIG. FIG. 4 is a diagram showing another example of a cross section taken along the line W2-W2 of the display panel shown in FIG. It is a figure which shows roughly the electron emission film | membrane formed into a film on the fluorescent substance layer of a discharge cell. It is a figure which shows roughly the crystal grain of the electron emission material scattered in the fluorescent substance layer of a discharge cell. It is a figure which shows roughly the example of the drive sequence which concerns on 1st Example of this invention. 11 is a timing chart schematically illustrating a waveform of a drive signal according to the drive sequence of FIG. 10. (A) is a figure which shows the waveform of the adjustment pulses Pxa and Pya shown by FIG. 10 as an example, (B) is a figure which shows the other example of the waveform of the adjustment pulses Pxa and Pya shown by FIG. is there. It is a figure which illustrates the light emission pattern implement | achieved by the drive sequence of FIG. (A) shows the charge in the discharge cell when the state of the discharge cell transitions in the order of black state (non-light-emitting state), white state (light-emitting state), and white state (light-emitting state) in accordance with the driving sequence of FIG. (B) is an explanatory diagram showing a change in the charge distribution in the discharge cell when the state of the discharge cell transitions in the order of black state, white state, black state, C) is an explanatory diagram showing a change in charge distribution in the discharge cell when the state of the discharge cell transitions in the order of black state, black state, and black state. It is a figure which shows schematically the example of the drive sequence which concerns on 2nd Example of this invention. (A) is an explanatory diagram showing a change in charge distribution in the discharge cell when the state of the discharge cell transitions in the order of white state, white state, and white state according to the drive sequence of FIG. It is explanatory drawing showing the change of the electric charge distribution in a discharge cell when the state of a discharge cell changes in order of a white state, a white state, and a black state, (C) is the state of a discharge cell being a white state, a black state, It is explanatory drawing showing the change of the electric charge distribution in the discharge cell in case of changing in order of a black state. (A) is an explanatory view showing the change in the charge distribution in the discharge cell when the state of the discharge cell transitions in the order of black state, white state, and white state according to the drive sequence of FIG. 15, (B) It is explanatory drawing showing the change of the electric charge distribution in a discharge cell when the state of a discharge cell changes in order of a black state, a white state, and a black state, (C) is the state of a discharge cell being a black state, a black state, It is explanatory drawing showing the change of the electric charge distribution in the discharge cell in case of changing in order of a black state. It is a figure which shows schematically the example of the drive sequence which concerns on 3rd Example of this invention. It is a figure which illustrates the light emission pattern implement | achieved by the drive sequence of FIG. It is a figure for demonstrating the gradation control which concerns on the 2nd modification of the 1st-3rd Example of this invention. It is a figure for demonstrating the gradation control which concerns on a 2nd modification. It is a figure which illustrates the light emission pattern which concerns on a 2nd modification. It is a figure for demonstrating the gradation control which concerns on the 3rd modification of the 1st-3rd Example of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Plasma display apparatus 2 Display panel 10 Controller 10A Weight assignment part 10B Cell detection part 11 Drive control part 12 Gradation adjustment part 13 Drive data generation part 14 Memory circuit 15 Column electrode drive part 16A 1st row electrode drive part 16B 2nd line Electrode driver

Claims (23)

A front substrate, a rear substrate having a facing surface spaced apart from one surface of the front substrate, a plurality of row electrode pairs formed on one surface of the front substrate, and formed on the facing surface of the rear substrate; A plurality of column electrodes; and a plurality of discharge cells respectively formed in intersection regions of the plurality of row electrode pairs and the plurality of column electrodes between the front substrate and the back substrate; A display panel in which a discharge gas is sealed and a phosphor layer is provided,
(A) decomposing each field of the input video signal into a plurality of subfields;
(B) assigning a luminance weight to each of the subfields;
(C) dividing the display period of each subfield into a plurality of periods including at least an address period and a light emission period, and sequentially displaying the plurality of subfields on the display panel in each of the plurality of periods. ,
The step (c)
(C-1) In the address period of the first subfield among the subfields, a scan pulse is sequentially applied to the scan electrodes of the plurality of row electrode pairs, and a write pulse synchronized with each scan pulse is applied to the column. The scan electrode and the column electrode are applied only to the initial selected cells except for the discharge cells to be displayed with black level luminance among the discharge cells by selectively applying an address discharge to the discharge cells. Causing the write discharge in between to set the initially selected cell in a light-emission enabled state;
(C-2) In the light emission period after the address period of the first subfield, a discharge sustain pulse is applied to the scan electrode and the common electrode of each row electrode pair only an odd number of times assigned to the first subfield, Causing the phosphor layer to emit light by causing a sustain discharge between the scan electrode and the common electrode of the row electrode pair only in the initial selection cell;
(C-3) In the address period of each subsequent subfield excluding the first subfield among the subfields, a scan pulse is sequentially applied to the scan electrode and a selective erase pulse synchronized with the scan pulse is applied to the column. Selectively setting the initial selected cell to a non-light-emitting state by selectively applying an electrode and causing an erasing discharge selectively in the initial selected cell;
(C-4) simultaneously applying adjustment pulses to the scan electrode and the common electrode of each row electrode pair in the charge adjustment period set immediately after the address period of each subsequent subfield;
(C-5) In the light emission period after the charge adjustment period of each subsequent subfield, a discharge sustain pulse is alternately applied to the scan electrode and the common electrode of each row electrode pair for the number of times assigned to each subsequent subfield. And causing the phosphor layer to emit light by causing a sustain discharge between the scan electrode and the common electrode only in the discharge cells in the light emission enabled state,
A driving method comprising: The driving method according to claim 1, comprising:
During the light emission period of the first subfield, a positive voltage pulse is applied to the scan electrode as the final pulse of the sustaining pulses, and at the same time, a voltage lower than the voltage of the final pulse is applied to each column electrode. Applied,
In the charge adjustment period, a positive voltage pulse is applied to each row electrode pair as the adjustment pulse, and at the same time, a voltage lower than the voltage of the adjustment pulse is applied to each column electrode.
A driving method characterized by that.   3. The driving method according to claim 1, wherein only one discharge sustaining pulse is applied to the scan electrode of each row electrode pair during the light emission period of the first subfield. 4.   3. The driving method according to claim 1, wherein, during the light emission period of the first subfield, scanning of each row electrode pair is performed by the number of times that a positive voltage pulse is assigned to the first subfield as the discharge sustain pulse. A driving method characterized in that the sum of the number of sustaining pulses applied to the scanning electrode and the number of sustaining pulses applied to the common electrode is an odd number applied alternately to the electrodes and the common electrode. .   5. The driving method according to claim 1, wherein the adjustment pulse is applied to the scan electrode and the common electrode immediately before the light emission period of each subsequent subfield. Driving method.   6. The driving method according to claim 1, wherein a positive voltage pulse is assigned to each subsequent subfield as the sustaining pulse during the light emission period of each subsequent subfield. The number of discharge sustain pulses applied to the scan electrodes and the number of sustain discharge pulses applied to the common electrodes are alternately applied to the scan electrodes and the common electrodes of each row electrode pair by the given number of times. The drive method characterized by making it into a piece.   5. The driving method according to claim 1, wherein the step (c) applies the discharge sustaining pulse in each address period of the head subfield and the subsequent subfield. 6. Immediately before the operation, the method further comprises the step of applying a wedge-shaped pulse having the same polarity as the voltage polarity of the scan pulse to the scan electrode and the common electrode. The driving method according to any one of claims 1 to 4, wherein:
The step (c)
In the address period of the first subfield, applying the scan pulse to the scan electrode and simultaneously applying an offset pulse having a polarity opposite to the voltage polarity of the scan pulse to the common electrode;
In the address period of each subsequent subfield, applying the scan pulse to the scan electrode and simultaneously applying an offset pulse having the same polarity as the voltage polarity of the scan pulse to the common electrode;
A driving method comprising:   9. The driving method according to claim 1, wherein the step (c) includes performing each row in an erasing period set after a light emission period of a final subfield of the subfields. Applying a pulse having a voltage higher than the potential of the scan electrode paired to the common electrode of the electrode pair, and immediately applying a positive voltage pulse to the common electrode and the scan electrode of each of the row electrode pairs. The driving method further comprising:   9. The driving method according to claim 1, wherein the display period of the first subfield of the next field is started immediately after the light emission period of the last subfield of the subsequent subfields. A driving method comprising steps.   9. The driving method according to claim 1, wherein in step (c), scanning pulses are sequentially applied to the scanning electrodes in a display period of a final subfield of the subfields. And applying a selective erasing pulse selectively to the column electrodes in synchronization with the respective scanning pulses to selectively cause an erasing discharge in the discharge cells, so that all the discharge cells in the light-emission enabled state are made non-conductive. A driving method, further comprising a step of executing an erasing operation for setting to a light emitting state.   12. The driving method according to claim 1, wherein the step (c) is performed in an address period of a k-th subfield (k is a positive integer) of the subsequent subfields. In the initial selected cell to which the scan pulse and the selective erase pulse are supplied, the erase discharge is generated by supplying the scan pulse and the selective erase pulse in the address period of the (k + 1) th subfield following the kth subfield. The driving method further comprising a step. The driving method according to any one of claims 1 to 10, wherein:
(D) detecting a non-light-emitting cell that should display a black level luminance over a predetermined number of temporally continuous fields based on the input video signal. And
The step (c) is performed in the address period of the first subfield among the subfields belonging to the last field among the predetermined number of fields that are temporally continuous according to the detection result of the step (d). The driving method further comprising: causing the write discharge in a non-light emitting cell and causing the erasing discharge in the non-light emitting cell in an address period of a subsequent subfield subsequent to the leading subfield.   14. The driving method according to claim 1, wherein each discharge cell includes an electron emission material that emits secondary electrons to the discharge space upon receiving ion irradiation. Driving method.   15. The driving method according to claim 14, wherein the electron emission material is a material that receives an electric field and emits electrons to the discharge space.   16. The driving method according to claim 14, wherein each discharge cell includes a dielectric layer formed on one surface of the front substrate so as to cover the row electrode pair, and the electron emission material. A driving method comprising: an electron emission layer covering the dielectric layer.   16. The driving method according to claim 14, wherein each of the discharge cells includes an electron emission layer made of the electron emission material and covering the phosphor layer.   16. The driving method according to claim 14, wherein the crystal particles of the electron emission material are scattered in the phosphor layer in a state of being exposed to the discharge space.   19. The driving method according to claim 14, wherein the electron emission material is made of a magnesium oxide crystal.   20. The driving method according to claim 19, wherein the magnesium oxide crystal includes a cathode luminescent material having an emission peak in a wavelength range of 200 to 300 nanometers.   21. The driving method according to claim 20, wherein the emission peak of the cathode luminescent material exists in a wavelength range of 230 to 250 nanometers.   The driving method according to any one of claims 19 to 21, wherein particles produced by a gas phase oxidation reaction between metal magnesium vapor and oxygen are used as the magnesium oxide crystal. A driving method characterized by the above. A front substrate, a rear substrate having a facing surface spaced apart from one surface of the front substrate, a plurality of row electrode pairs formed on one surface of the front substrate, and formed on the facing surface of the rear substrate; A plurality of column electrodes; and a plurality of discharge cells respectively formed in intersection regions of the plurality of row electrode pairs and the plurality of column electrodes between the front substrate and the back substrate; A plasma display device including a display panel in which a discharge gas is sealed and a phosphor layer is provided,
A signal processing unit that decomposes each field of the input video signal into a plurality of subfields;
A weight assignment unit for assigning luminance weights to the subfields;
A panel driver for driving the display panel;
Driving in which the display period of each subfield is divided into a plurality of periods including at least an address period and a light emission period, and the panel driving unit is controlled in each of the plurality of periods to sequentially display the plurality of subfields on the display panel. A control unit,
The panel drive unit is
(A) In the address period of the first subfield of the subfields, a scan pulse is sequentially applied to the scan electrodes of the row electrode pair, and a write pulse synchronized with each scan pulse is applied to the column electrodes. By selectively generating a write discharge in the discharge cells, only the initial selected cells except for the discharge cells that should display a black level of luminance among the discharge cells, the write electrodes are arranged between the scan electrodes and the column electrodes. A write operation for causing a discharge and setting the initially selected cell in a light-emission enabled state;
(B) In the light emission period after the address period of the first subfield, the discharge sustain pulse is applied to the scan electrode and the common electrode of each row electrode pair only an odd number of times assigned to the first subfield, thereby A light emitting operation for causing the phosphor layer to emit light by causing a sustain discharge between the scan electrode and the common electrode of the row electrode pair only in the selected cell;
(C) In the address period of each subsequent subfield excluding the first subfield among the subfields, a scan pulse is sequentially applied to the scan electrode and a selective erase pulse synchronized with the scan pulse is applied to the column electrode. An erasing operation for selectively setting the initial selected cell to a non-light-emitting state by selectively applying and selectively causing an erasing discharge in the initial selected cell;
(D) In a charge adjustment period set immediately after the address period of each subsequent subfield, a charge adjustment operation in which adjustment pulses are simultaneously applied to the scan electrode and the common electrode of each row electrode pair;
(E) In the light emission period after the charge adjustment period of each subsequent subfield, a discharge sustain pulse is alternately applied to the scan electrode and the common electrode of each row electrode pair for the number of times assigned to each subsequent subfield. A light emission operation for causing the phosphor layer to emit light by causing a sustain discharge between the scan electrode and the common electrode only in the discharge cell in the light emission enabled state;
The plasma display apparatus characterized by performing.

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