JP5348912B2 - Semiconductor device drive circuit - Google Patents

Description

  The present invention relates to a semiconductor element driving circuit, and more particularly to suppression of surge voltage.

  A hybrid vehicle has a configuration in which a battery, a motor, and an inverter are added to an engine. The size of the inverter depends on the loss in the inverter, and the larger the loss, the larger the size of the inverter. Therefore, reducing the loss of the inverter not only increases the conversion efficiency of the inverter, but also contributes to the downsizing of the inverter, leading to a reduction in size and weight of the hybrid vehicle and an improvement in fuel consumption. The inverter loss can be divided into DC loss and switching loss.

  In order to reduce the switching loss of the semiconductor element in the inverter, an element (high-speed IGBT or MOSFET) having a high-speed switching characteristic may be driven at high speed. However, when the IGBT and MOSFET are switched at a high speed, a large surge voltage is generated, and in some cases, element destruction or damage to equipment connected to the inverter may occur.

  Thus, conventionally, a method of switching the gate resistance has been proposed as a technique for reducing the switching loss while suppressing the surge voltage. A configuration in which a capacitor is added between the gate and emitter of the IGBT has also been proposed.

JP 2002-125363 A JP 2006-222593 A JP-A-11-330935 JP 2000-333441 A Japanese Patent Laid-Open No. 11-234103 Japanese Patent Laid-Open No. 2004-23880

  However, in the conventional method of switching the gate resistance, the gate resistance is switched during the switching operation of the element. Since the recent high-speed IGBT has a fast switching time, the gate resistance can be switched at an optimal timing during switching. There is a problem that is substantially impossible from the operation time of the control circuit. Adding a capacitance between the gate and the emitter has a certain effect for preventing malfunction of the gate, but from the viewpoint of reducing the switching loss, there is almost no effect in the conventional IGBT.

  An object of the present invention is to provide a semiconductor element driving circuit that reduces a switching loss while suppressing a surge voltage.

The present invention is a circuit for driving a thin plate type IGBT or SiCMOSFET semiconductor element having a substrate thickness of 50 μm to 200 μm, a driver for applying a voltage to the gate of the semiconductor element, and a gate connected to the gate of the semiconductor element A resistor, a capacitor connected between the gate and emitter of the semiconductor element or between the gate and source, and a diode connected in series with the capacitor between the gate and emitter of the semiconductor element or between the gate and source;
It characterized that you chromatic connected thereto and a capacitor charging resistor between the capacitance and the driver.

  If the gate resistance is reduced at the turn-off time of the semiconductor element, the rise of the element voltage can be accelerated and the switching loss can be reduced, but at the same time the attenuation rate of the element current is increased, so that the surge voltage increases. Therefore, by adding a capacitance between the gate and the emitter or between the gate and the collector, it is possible to suppress the increase in surge voltage by reducing the decay rate of the device current while maintaining the rapid rise of the device voltage. Further, when the semiconductor element is turned on, the time constant is determined by the product of the gate resistance and the gate capacitance, and the surge voltage is determined. On the other hand, if the gate resistance is reduced, the device voltage falls faster, so that switching loss can be reduced. Therefore, by adding a capacitor and setting the capacitor to a value that can obtain a desired time constant, the gate resistance can be set small as a result, thereby suppressing a switching voltage while suppressing a surge voltage. descend.

  In another embodiment of the present invention, the driver has an on terminal for applying an on voltage to the gate and an off terminal for applying an off voltage, and the capacitor charging resistor is connected to the on terminal of the driver. And a second gate resistor connected between the ON terminal of the driver and the gate of the semiconductor element.

  In another embodiment of the present invention, the semiconductor device further includes a second capacitor connected between the gate and the emitter of the semiconductor element.

  According to the present invention, the surge voltage can be suppressed and the switching loss can be reduced.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  First, the basic principle of the semiconductor element driving circuit in the present embodiment will be described by taking an IGBT (insulated gate bipolar transistor) element as an example of the semiconductor element. Of course, it is not limited to IGBT, and may be MOSFET.

  First, the turn-off side of the IGBT element will be described. As shown in FIG. 14, the IGBT element is normally driven on and off by supplying voltages (for example, 15 V and 0 V) output from the drive circuit to the gate via the gate resistor Rg. Differences in characteristics due to the magnitude of the gate resistance Rg will be described. When the two types of gate resistances are R1 and R2 (R1> R2), R2 has a faster rise of the voltage Vce of the IGBT element at the time of turn-off, and the current attenuation factor di / dt is also large. FIG. 1 shows time variations of the element voltage Vce and the element current Ice. In the figure, the solid line is the characteristic when R1 and the broken line is the characteristic when R2. In either case, a surge voltage is generated at the time of turn-off. However, since the surge voltage is given by di / dt × Lp with the inductance of the parasitic component as Lp, the surge voltage is larger in R2.

Next, it is assumed that a capacitor Cge1 (capacitor) is added between the gate and emitter of the IGBT element in addition to R2. FIG. 2 shows temporal changes in the element voltage Vce and the element current Ice in this case. The addition of R2 and the capacitor CGE1, the rise of the principle on the element voltage Vce is the same as the case of R 2, attenuation rate di / dt of the current decreases. Therefore, to set the capacity Cge1 as when the current decay rate is driven by R1 are the same, by adding such a capacity Cge 1 in R2, the rise of the element voltage Vce with the same surge voltage as R1 Can be made faster. That is, the turn-off loss can be reduced with the same surge voltage.

Next, the turn-on side will be described. The sum of the gate resistance Rg, the gate additional capacitance C1, and the gate-emitter parasitic capacitance Cd of the IGBT element, that is, the gate capacitance Cge = C1 + Cd is used as an index Rg × Cge. Two types of resistors R1 and R2 and two types of gate capacitances Cge (1) and Cge (2) are used.
R1 × Cge (1) = R2 × Cge (2)
Set to be. Here, R1> R2 and Cge (1) <Cge (2). When the product of the gate resistance and the gate capacitance is the same, the time constant is the same, so the rate of increase in the gate voltage is the same. Since the device current of the IGBT element is controlled by the gate voltage, the same switching waveform is obtained until the voltage between the emitter and the collector of the IGBT element changes and the gate voltage starts to be affected via the feedback capacitance. As switching proceeds, the voltage of the IGBT element starts to decrease, and when the gate voltage is affected, the influence of the gate resistance begins to appear. In the case of turn-on, the fall of the voltage Vce of the IGBT element is earlier as the gate resistance is smaller. For this reason, in the turn-on waveform, the fall of Vce is earlier in R2 and Cge (2). FIGS. 3 and 4 show temporal changes in the device current Ice and the voltage Vce, respectively. As a result, the combination of R2 and Cge (2) also reduces the turn-on loss.

  In this way, the IGBT element is not driven by a single gate resistor, but by adding capacitance in addition to the gate resistance to reduce the gate resistance, switching loss is reduced on both the turn-on side and the turn-off side with the same surge voltage. Can be made. The method of adding a capacitance between the gate and the emitter of the IGBT element is known as prevention of gate malfunction as described above, but the reduction of the switching loss is not discussed, and the switching loss of the conventional IGBT is not discussed. There is almost no lowering effect. On the other hand, in this embodiment, the switching loss can be reduced by reducing the gate resistance while maintaining the product of the gate resistance and the capacitance constant. More specifically, the substrate thickness is 400 μm, which is a normal thickness. The switching loss can be reduced by applying it to a so-called thin substrate type high-speed IGBT element having a substrate thickness of about 50 μm-200 μm in order to make the P-type layer on the collector side as thin as 50 μm or less, compared to a conventional IGBT element of the order The present applicant has found. It is not limited to an IGBT element, but may be a high-speed element using SiC or GaN.

  On the other hand, when a capacitance is added to the gate resistance, vibration may occur in the switching waveform. For this reason, a damping resistor may be further added between the gate resistor and the capacitor.

  FIG. 5 shows a configuration of the semiconductor element driving circuit of the present embodiment. In the configuration in which the gate voltage is applied to the gate of the IGBT element 10 from the driver, the gate resistance R1 is added to the gate, the capacitance C1 is added between the gate and the emitter, and the gate resistance R1 and the capacitance C1 are further connected. A damping resistor Rd is added. Here, R1> Rd. By adding the capacitor C1 and setting the gate resistance R1 small, the switching loss can be reduced while suppressing the surge voltage.

  As described above, there is a restriction that the product of gate resistance and gate capacitance is constant on the turn-on side, but there is no such restriction on the turn-off side. This means that in a circuit configuration in which the turn-off side and the turn-on side are driven by the same gate resistance, optimization of the gate resistance and gate capacitance is defined by the conditions on the turn-on side, and the turn-off side is not necessarily optimized. It will be.

  Therefore, as shown in FIG. 6, a configuration in which the relationship between the gate resistance and the gate capacitance is optimized on the turn-off side and the turn-on side may be employed. In FIG. 6, the gate resistance for driving is composed of R3 on the on side and R1 on the off side, and the gate capacitance is composed of C2 on the on side and C1 + C2 on the off side. A diode D1 is disposed so that the capacitance is switched between the on side and the off side, and a charging resistor R2 is disposed for charging the capacitor C1. More specifically, the on-side terminal of the driver is connected to the gate of the IGBT element 10 via the gate resistor R3. Further, it is connected to the gate via a charging resistor R2 and capacitors C1 and C2. A connection point P between the gate resistor R3 and the gate and a connection point Q between the gate resistor R2 and the capacitor C1 are connected by a diode D1. The driver's OFF terminal is connected to the connection point P via the gate resistor R1. The diode D1 and the capacitor C1 are connected in series between the gate and emitter of the IGBT element 10. The charging resistor R2 of the capacitor C1 is connected between the driver and the capacitor C1. The gate resistance R3 and the gate capacitance C2 are effective on the ON side, and the gate resistance R1 and the gate capacitance C1 + C2 are effective on the OFF side, which can be optimized on the turn-on side and the turn-off side.

  Further, as shown in FIG. 7, a configuration in which the capacitor C2 is omitted in FIG. The gate resistance R3 is on the on side, and the gate resistance R1 and the gate capacitance C1 are on the off side.

  Further, as shown in FIG. 8, the same resistance R1 may be used on the on side and the off side. The driver is connected to the gate of the IGBT element 10 via the gate resistor R1, and the resistor R2 and the gate capacitor C1 are connected in series between the connection point S between the driver and the gate resistor and the emitter, and the gate resistor R1 A diode D1 is connected between a connection point T between the gate and the gate capacitor C1. The gate resistance R1 is on the on side, and the gate resistance R1 and the gate capacitance C1 are on the off side.

  If the configuration excluding the damping resistor Rd from FIG. 5 is a basic configuration, FIG. 8 adds a diode D1 in series with the capacitor C1 between the gate and the emitter, and further between the driver and the capacitor C1. In this configuration, a capacitor charging resistor R2 is added. FIG. 7 shows a configuration in which the capacitor charging resistor R2 is connected to the on-terminal of the driver in the configuration of FIG. 8, and a gate resistor R3 is connected between the on-terminal of the driver and the gate. FIG. 6 shows a configuration in which a second gate capacitor C2 is further added between the gate and the emitter in the configuration of FIG.

  Hereinafter, specific application examples of the present embodiment will be described.

  FIG. 9 shows an application example on the turn-off side, that is, an application example in the configuration of FIG. 5 (however, the damping resistance Rd is ignored). This is a case where the gate capacitance is added to be 3 times the reference, and the gate resistance is 1/2 the reference value. In the figure, the conventional case is indicated by a solid line, and the embodiment is indicated by a broken line. The conventional gate resistance is 22Ω, the gate resistance of the embodiment is 10Ω, and the gate additional capacitance is 66 nF. The parasitic capacitance Cd is 33 nF. In the embodiment, the surge voltage (maximum value of Vce) at the time of turn-off and the device current Ice remain substantially the same, and the rise of the device voltage Vce can be accelerated, and the turn-off loss can be reduced by 19.3%.

  FIG. 10 shows an application example on the turn-on side. It is a time change of the element voltage Vce. This is a case where the gate resistance is 6.9Ω and the gate additional capacitance is 22 nF. It is difficult to make the product of the gate resistance and the gate capacitance the same as the conventional one. In the embodiment, the product of the gate resistance and the gate capacitance is slightly larger than the conventional one, and the loss is increased. By setting / 3, the fall of the element voltage Vce is accelerated, and the turn-on loss can be reduced by 4%. FIG. 11 shows the time change of the device current Ice. The current change rate di / dt is also smaller in the embodiment, and the surge characteristics are also improved.

  FIG. 12 shows an application example in which the gate resistance and the gate capacitance are optimized on the turn-on side and the turn-off side, that is, an application example in the configuration of FIG. Compared to the conventional case where the gate resistance is 20 Ω alone, the off-side gate resistance is 5 Ω, the gate additional capacitance is 80 nF (20 nF + 60 nF), the on-side gate resistance is 7 Ω, and the gate additional capacitance is 20 n. When compared with FIG. 6, R1 = 5Ω, R3 = 7Ω, C1 = 60 nF, C2 = 20 nF, and 12 corresponds to the driver. FIG. 13 summarizes the results. Rg is the value of the gate resistance, Eoff is the loss energy when off, and Eon is the loss energy when on. Compared with the conventional switching loss per turn, 23.11 / 27.94 = 0.527 on the turn-off side and 6.58 / 10.48 = 0.628 on the turn-on side. Realized. The improvement rate is 37% on the on side and 17% on the off side. FIG. 13 also shows the result in the case of FIG. This is a case where R1 = 7Ω and gate additional capacitance C1 = 80 nF. On the off side, the loss is improved by 12%, but on the contrary, the loss increases. This indicates that it is effective in the case of a semiconductor device in which a surge countermeasure at the turn-off is necessary but a surge countermeasure at the turn-on is not particularly necessary. For example, in an arm configuration in which two pairs of switching elements and Si fast recovery diodes are connected in series, it is necessary to take measures against surges at the turn-on time and turn-off time of the IGBT element, but SBD (Schottky barrier diode) or the like is used as a free wheel diode. When an element without reverse recovery current is used, a surge countermeasure on the turn-on side of the IGBT element is not necessarily required, and it is necessary to reduce surge on the turn-off side and improve turn-off loss. 7 and 8 are effective in the case of such an element. In this embodiment, the gate capacitance is connected between the gate and the emitter, but may be connected between the gate and the source.

It is a principle explanatory view (turn-off side) of an embodiment. It is a principle explanatory view (turn-off side) of an embodiment. It is a principle explanatory view (turn-on side) of an embodiment. It is a principle explanatory view (turn-on side) of an embodiment. It is a circuit block diagram of an embodiment. It is another circuit block diagram of embodiment. It is another circuit block diagram of embodiment. It is another circuit block diagram of embodiment. It is a voltage-current characteristic figure at the time of turn-off which shows the example of application of embodiment. It is a voltage characteristic figure at the time of turn-on which shows the example of application of an embodiment. It is a current characteristic figure at the time of turn-on which shows the example of application of an embodiment. It is a circuit diagram which shows the other example of application of embodiment. It is a characteristic table figure in the structure of FIG. It is a circuit diagram of the conventional drive circuit.

Explanation of symbols

  10 IGBT element, 12 Driver including power supply.

Claims (3)

A circuit for driving a thin plate type IGBT or SiCMOSFET semiconductor element having a substrate thickness of 50 μm to 200 μm,
A driver for applying a voltage to the gate of the semiconductor element;
A gate resistor connected to the gate of the semiconductor element;
A capacitance connected between the gate and emitter of the semiconductor element or between the gate and source;
A diode connected in series with the capacitor between the gate and emitter of the semiconductor element or between the gate and source;
A capacitor charging resistor connected between the driver and the capacitor;
The semiconductor element drive circuit according to claim that you have a. The circuit of claim 1, wherein
The driver has an on terminal for applying an on voltage to the gate and an off terminal for applying an off voltage,
The capacitor charging resistor is connected to an on terminal of the driver, and
A semiconductor element driving circuit, comprising: a second gate resistor connected between an ON terminal of the driver and a gate of the semiconductor element . The circuit of claim 2, further comprising:
A second capacitor connected between the gate and emitter of the semiconductor element or between the gate and source.
A semiconductor element driving circuit comprising:

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