JP5345649B2 - Variable gate field effect transistor (FET) and electrical and electronic device comprising this FET - Google Patents

Abstract

Provided are a variable field effect transistor (FET) designed to suppress a reduction of current between a source and a drain due to heat while decreasing a temperature of the FET, and an electrical and electronic apparatus including the variable gate FET. The variable gate FET includes a FET and a gate control device that is attached to a surface or a heat-generating portion of the FET and is connected to a gate terminal of the FET so as to vary a voltage of the gate terminal. A channel current between the source and drain is controlled by the gate control device that varies the voltage of the gate terminal when the temperature of the FET increases above a predetermined temperature.

Description

  The present invention relates to a field effect transistor (FET), and more particularly, by changing a gate voltage of an FET using a metal-insulator transition (MIT) element or a thermistor element, thereby stabilizing the field effect transistor (Field Effect Transistor: FET). The present invention relates to a high-efficiency and low-heat-generating FET that can operate at high speed.

  A representative switch among electronic components is a transistor which is a three-terminal element, and the transistor is classified into a bipolar transistor using a pn junction principle and an FET using a capacitor. The high-speed signal amplification FET is used as an element for RF signal amplification, a DC-DC converter, and a DC switching at the front end-front end (Front-End) of an electrical and electronic apparatus (Electrical and Electronic Apparatus). A typical problem with such FETs is that heat is generated in the source and drain conductive layers during high-speed switching, and that heat is transferred to the gate insulator to reduce the channel current between the source and drain. As pointed out.

  Due to such a problem, the FET cannot perform high-speed signal amplification. Therefore, peripheral elements such as a temperature sensor, a memory, a DA (Digital-to-Analog) converter, and a microprocessor for controlling such peripheral elements are required for high-speed amplification of the FET. In order to operate such a peripheral device, a complicated system concept program is required.

  The problem to be solved by the present invention is to effectively solve the problem of current reduction between the source and drain of the FET due to heat, and to reduce the temperature of the FET, and a variable gate FET (variable gate FET) and the FET An electrical and electronic device comprising:

  In order to solve the above-described problems, the present invention provides an FET and a gate control that is attached to the surface of the FET or a heat generating portion and is connected to the gate terminal of the FET in terms of circuit and changes the voltage of the gate terminal. The gate control element controls the channel current between the source and drain of the FET by changing the voltage of the gate terminal when the temperature of the FET is higher than a predetermined temperature. A variable gate FET is provided.

  In one embodiment of the present invention, the gate control device may include an MIT device that generates a metal-insulator transition (MIT) at a critical temperature. The MIT element includes an MIT thin film that causes an abrupt MIT at the critical temperature, and two electrode thin films that are in contact with the abrupt MIT thin film, and one of the two electrode thin films. The first electrode thin film is connected to the gate terminal, and the other second electrode thin film is connected to a control voltage source or ground. Meanwhile, a driving voltage source is connected to the drain electrode of the FET, a driving element is connected to the source electrode of the FET, and a gate voltage source and the MIT element are commonly connected to the gate of the FET.

  In one embodiment of the present invention, the gate control element includes a thermistor element whose resistance decreases with increasing temperature. One of the two terminals of the thermistor element is connected to the gate of the FET, and the other is connected to a control voltage source or ground.

  In one embodiment of the present invention, the FET and the gate control element may be packaged in one chip. The variable gate FET includes a heat transfer medium that transfers heat generated from the FET, the FET and the gate control element are packaged, and the packaged FET and gate control element are They are coupled to transfer heat through a heat transfer medium.

  In order to solve the above-mentioned problems, the present invention also includes a drive element, and at least one variable gate FET connected to the drive element and controlling a current supplied to the drive element. I will provide a.

  In one embodiment of the present invention, the gate control element includes an MIT thin film that causes an abrupt MIT at the critical temperature, and two electrode thin films that are in contact with the abrupt MIT thin film. The first electrode thin film, which is one of the thin films, is connected to the gate terminal, and the other second electrode thin film is connected to a control voltage source or ground.

  In one embodiment of the present invention, there are a plurality of the variable gate FETs, and each of the plurality of the variable gate FETs is arranged in an array structure to constitute an FET array element, and each of the FET array elements The gate control element is connected to the FET.

  In one embodiment of the present invention, the electrical and electronic device includes an RF signal amplification element, a DC-DC switching element, a power supply switching element, a microprocessor high-speed signal processing switching element, in which the variable gate FET is used. Electronic device power control switching device, lithium ion charging switching device, LED control switching device, display pixel control switching device, memory cell control switching device, acoustic and audio signal amplification switching device for audio equipment, photo At least one of a relay and an optical switch is included.

  The variable gate FET of the present invention and the electric / electronic device including the FET use a MIT element or a thermistor element to change the voltage applied to the gate of the FET by the heat generated in the FET, and thereby the source and drain of the FET. The operation of the FET can be stably maintained by increasing the current between them and decreasing the temperature of the FET.

  Accordingly, the variable gate FET of the present invention is a high-speed, high-power and low-heat switching element, which is an RF signal amplification element, a DC-DC switching element, a power supply switching element, and a microprocessor for high-speed signal processing switching. Switching element for power control of electronic devices, switching element for lithium ion charging, switching element for LED control, switching element for display pixel control, switching element for memory cell control, switching element for acoustic and audio signal amplification in acoustic equipment, It can be used for a switching element such as a photo relay and an optical switch, and can be effectively used for all electric and electronic devices such as a mobile phone, a notebook computer, a computer, and a memory including the switching element.

It is a basic circuit diagram for demonstrating operation | movement of N type FET. In the circuit of FIG. 1 is a graph showing the drain current _{I D} with respect to the source and drain voltage _{V DS} by the gate voltage _{V GS.} 2 is a graph showing a surface temperature T of an FET with respect to a source and drain current I _DS by a gate voltage V _{GS in} the circuit of FIG. 1. 1 is a circuit diagram of an electrical and electronic device including a variable gate FET according to an embodiment of the present invention. 1 is a circuit diagram of an electrical and electronic device including a variable gate FET according to an embodiment of the present invention. FIG. 6 is a cross-sectional view of an MIT element used for the variable gate FET of FIG. 4 or 5. FIG. 6 is a cross-sectional view of an MIT element used for the variable gate FET of FIG. 4 or 5. FIG. 6B is a plan view of the horizontal MIT element of FIG. 6B. Is a graph showing a resistance characteristic against temperature embodied been MIT device using vanadium oxide (VO _2). FIG. 5 is a modified circuit diagram of FIG. 4 used to measure a change in output voltage with respect to a sine wave input. It is a signal waveform diagram which shows the input voltage and output voltage which were measured with the circuit diagram of FIG. It is a signal waveform diagram which shows the input voltage and output voltage which were measured with the circuit diagram of FIG. FIG. 9 is a graph showing the maximum and minimum values of the output voltage due to the _VMIT change measured in the circuit diagram of FIG. 8. FIG. 9 is a graph showing the maximum and minimum values of the output voltage measured by the _RMIT change measured in the circuit diagram of FIG. 8. FIG. 9 is a signal waveform diagram showing an output voltage after passing through a capacitor in the circuit diagram of FIG. 8. FIG. 9 is a signal waveform diagram showing an output voltage after passing through a capacitor in the circuit diagram of FIG. 8. FIG. 6 is a circuit diagram of an electrical and electronic device including a variable gate FET according to another embodiment of the present invention. FIG. 6 is a circuit diagram of an electrical and electronic device including a variable gate FET according to another embodiment of the present invention. In FIG. 13 or FIG. 14, it is sectional drawing about the thermistor element utilized for variable gate FET. In FIG. 13 or FIG. 14, it is sectional drawing about the thermistor element utilized for variable gate FET. It is a graph which shows the resistance characteristic with respect to the temperature of a thermistor element. It is a top view which shows the aspect by which the variable gate FET by one Embodiment of this invention was packaged in one package. It is sectional drawing which shows the aspect by which the gate variable element and FET of variable gate FET by one Embodiment of this invention were respectively packaged and couple | bonded. It is a top view which shows the aspect by which the gate variable element and FET of variable gate FET by one Embodiment of this invention were packaged and couple | bonded.

  Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. When it is described that a component in the following description is present on top of another component, this may also be directly above the other component, with a third component interposed therebetween. is there. In the drawings, the thickness and size of each component are exaggerated for convenience of description and clarity, and portions not related to the description are omitted. The same reference numerals in the drawings denote the same elements. On the other hand, the terms used are merely used to describe the present invention, and are not used to limit the scope of the present invention described in the meaning limitation or the claims. Further, in describing the present invention, if it is determined that a specific description of a related known function or configuration can unnecessarily obscure the spirit of the present invention, a detailed description thereof will be given. Omitted.

  FIG. 1 is a basic circuit diagram for explaining the operation of an N-type FET.

Referring to FIG. 1, the FET 10 (hereinafter, “FET”) is generally a three-terminal switch, and the voltage applied to the gate G from the gate voltage source V _G is adjusted to adjust the source S of the FET 10. In addition, by turning on and off the channel between the drain D and the drain D, the function of supplying the current from the driving voltage source V _D to the driving element (not shown) is exhibited. The FET 10 is classified into an N-type FET and a P-type FET, and the N-type FET is illustrated in this drawing.

  In the FET 10, a gate voltage is applied to the gate, and a charge induced by the voltage is caused to flow by the source and drain voltages to supply a current to the driving element. Such an FET 10 can be used as a power FET by increasing the source and drain voltages and flowing a large current. The FET 10 may be used as a high-speed switching element that performs high-speed switching by applying an appropriate gate voltage to a low source and drain voltage.

  However, the FET 10 generates heat in the source and drain channel layers during high-speed switching, and the heat is transmitted to the gate insulator to reduce the channel current between the source and drain, thereby driving elements (FIG. (Not shown). Here, A surrounded by a circle is an ammeter connected to the FET 10 instead of the driving element.

FIG. 2 is a graph showing the drain current _ID with respect to the source and drain voltage V _DS by the gate voltage V _{GS in} the circuit of FIG. 1, and is a graph obtained by using the N-MOS IRF 640 as the FET.

Referring to FIG. 2, it can be seen that the drain current _ID increases as the source and drain voltage _VDS increases. It can also be seen that the higher the gate voltage V _GS , the higher the rate of increase of the drain current _ID , that is, the slope of the corresponding graph. On the other hand, from above the gate voltage 5.5V despite the increase in the gate voltage V _GS, the rate of increase of the drain current I _D is substantially the same. On the graph, when the source and drain voltage V _DS is about 3.7 V, a portion where the drain current _ID is 2 A is indicated by an arrow.

FIG. 3 is a graph showing the surface temperature T of the FET with respect to the source and drain current I _DS by the gate voltage V _{GS in} the circuit of FIG. 1, and is also a graph obtained by using the N-MOS IRF 640 as the FET. Here, the source and the drain current I _DS is may be regarded the same as the drain current I _D of FIG. 2.

Referring to FIG. 3, it can be seen that the surface temperature T of the FET increases as the source and drain current _IDS increases. Further, it can be confirmed that the surface temperature T graph moves to the right side as the gate voltage V _GS is higher, but this can be interpreted that the surface temperature of the FET can be lowered by increasing the gate voltage V _GS . That is, when the black arrow drawn along the X axis near 70 ° C. on the Y axis is observed, the surface temperature T of the FET is constant despite the increase in the source and drain currents I _DS due to the increase in the gate voltage V _GS. It is.

For example, when the gate voltage _{V GS} is the graph A is 5.0V, the surface temperature of the FET is seen to become more 100 ° C. in partial source and drain current _{I DS} is about 2.0A. However, when the gate voltage V _GS is increased (a graph in which the gate voltage V _GS is 5.5 V or more), the surface temperature of the FET may be lowered to about 60 ° C. with the same 2.0 A source and drain current I _DS. I can confirm. On the other hand, in FIG. 2, despite the increase of the gate voltage _{V GS} from 5.5V or more gate voltage _{V GS,} the same context as the rate of increase of the drain current _{I D} is not increased, 5.5V or more gate voltage The surface temperature graph of the FET from V _GS does not move to the right side but is maintained substantially the same.

Eventually, based on the graph of FIG. 3, by increasing the voltage applied to a gate electrode of the FET, it is possible to increase the source and drain current I _DS, also can be seen to lower the surface temperature of the FET with it.

  FIG. 4 is a circuit diagram of an electrical and electronic device including a variable gate FET according to an embodiment of the present invention.

  Referring to FIG. 4, the electrical / electronic device of the present embodiment may include a variable gate FET 1000 and a driving element 300. The variable gate FET 1000 can include an FET 100 and an MIT element 200 coupled to the gate G of the FET 100.

The driving voltage source V _D may be connected to the drain D of the FET 100, and the driving element 300 may be connected to the source S. Further, the gate voltage source V _G and the MIT device 200 may be connected to the gate G of the FET 100 through the contact A. One terminal of the MIT element 200 may be connected to the gate G of the FET 100, and the other terminal may be connected to the control voltage source _VMIT .

Meanwhile, a resistance element 400 for voltage drop and protection of the FET 100 may be connected between the drain D of the FET 100 and the driving voltage source V _D. In addition, although not shown, a resistance element may be connected between the gate voltage source V _G and the gate G, and between the control voltage source V _MIT and another terminal. Furthermore, it goes without saying that other resistive elements may be added or omitted in each required part in the electrical and electronic device.

  The MIT element 200 is a two-terminal element, maintains the characteristics as an insulator below the critical temperature, and has a characteristic as a metal by rapidly transitioning above the critical temperature. The specific structure and features of the MIT element 200 will be described in more detail in the description of FIGS. 6A to 7.

The operation of the variable gate FET 1000 in the electric / electronic device according to the present embodiment will be described. As described above, if the FET 100 is switched at high speed, heat is accumulated in the source and drain channel layers. As well as reducing the drain channel current. However, the heat generated at this time is transmitted to the MIT element 200, and the MIT element 200 transitions to metal by heat, so that the voltage of the control voltage source V _MIT is applied to the gate G of the FET 100 through the contact A, The gate voltage of the FET 100 is increased.

  If the gate voltage of the FET 100 increases, the source and drain currents increase as confirmed by the graph of FIG. As a result, the current decreased due to heat generation is compensated for by the increased current due to the increase in the gate voltage, so that there is no substantial decrease in the current supplied to the driving element 300, thereby stably operating the driving element 300. Can be made. On the other hand, as the source and drain currents increase, the temperature of the source and drain channel layers also tends to decrease. This is the same principle as described in the graph of FIG. 3 in that the temperature is kept constant regardless of the increase in the source and drain currents due to the increase in the gate voltage indicated by the black arrow at 70 ° C. on the Y axis. It is.

The experimentally measured results of the circuit designed as shown in FIG. Here, using the IRF640 as FET 100, the resistance value of the resistance element 400 between the drive voltage source _{V D} and FET 100 is 5 [Omega, heat added through heat gun MIT device 200 (Heat Gun).

In Table 1, V _G represents the gate voltage of the FET 100, V _D represents the drain voltage of the FET 100, I _DS represents the source and drain current, and V _MIT represents the control voltage source connected to the MIT element 200. Represents the voltage of Temp. Represents the surface temperature of the FET 100.

  As can be seen from Table 1, before applying heat to the MIT device 200 through a heat gun, the surface temperature of the FET 100 was 136 ° C., and the source and drain currents were 0.6 A. After applying heat to the MIT device 200, the gate voltage of the FET 100 is increased from 4V to 4.7V, thereby increasing the source and drain currents from 0.6A to 1.0A. The temperature decreased from 136 ° C to 70 ° C. Such a result is exactly consistent with the operating principle of the variable gate FET 1000.

  On the other hand, based on the principle of operation of the variable gate FET 1000 as described above, the MIT element 200 can be attached to the surface of the FET 100 or a portion where heat generation often occurs. For example, the MIT element 200 can be attached to a portion close to the channel layer, the gate electrode, and the like of the FET 100 where heat generation often occurs so that the generated heat is effectively transmitted.

  FIG. 5 is a circuit diagram of an electrical and electronic device including a variable gate FET according to an embodiment of the present invention.

  Referring to FIG. 5, the electrical / electronic device of the present embodiment has a similar structure to that of FIG. 4, but only the MIT element 200 portion is different. That is, one terminal of the MIT element 200 can be connected to the gate G of the FET 100 through the contact A, and the other terminal can be connected to the ground instead of the control voltage source.

  By connecting the ground to the MIT element 200 in this way, the source and drain currents of the FET 100 can be reduced. For example, when the source and drain currents need to be reduced after the source and drain currents rise through the structure as shown in FIG. 4, the source and drain currents are reduced by connecting the ground to the MIT device 200. be able to.

  Meanwhile, although the circuit structure in which one MIT element is connected to one FET has been described so far, the present invention is not limited thereto, and the variable gate FET according to the embodiment of the present invention is an FET array in which a plurality of FETs are arranged in an array structure. It goes without saying that the element can be expanded to a circuit structure in which one MIT element is connected to each FET in the FET array element.

  6A and 6B are a plan view and a plan view of an MIT element used in the variable gate FET of FIG. 4 or 5, and FIG. 6A is a plan view of an MIT element 200 having a stacked structure. 6B is a plan view of the MIT element 200a having a horizontal structure, and FIG. 6C is a plan view of the horizontal MIT element of FIG. 6B.

  Referring to FIG. 6A, the stacked MIT device 200 may include a substrate 210, a buffer layer 220, a transition thin film 230, and an electrode thin film 240.

The substrate 210 is made of SrTiO doped with Si, SiO ₂ , GaAs, Al ₂ O ₃ , plastic, glass, V ₂ O ₅ , PrBa ₂ Cu ₃ O ₇ , YBa ₂ Cu ₃ O ₇ , MgO, SrTiO ₃ , and Nb. ₃ and SOI (Silicon On Insulator).

The buffer layer 220 is formed on the substrate 210 and has a role of relaxing lattice mismatch between the substrate 210 and the first electrode thin film 241. When the lattice mismatch between the substrate 210 and the first electrode thin film 241 is very small, the buffer layer 220 can be omitted. Such a buffer layer 220 can be formed including a SiO ₂ or Si ₃ N ₄ film.

The electrode thin film 240 may include a first electrode thin film 241 below the transition thin film 230 and a second electrode thin film 243 above. The first electrode thin film 241 is formed on the buffer layer 220. In the case of the buffer layer 220, the first electrode thin film 241 can be formed immediately on the substrate 210. The electrode thin film 240 is made of W, Mo, W / Au, Mo / Au, Cr / Au, Ti / W, Ti / Al / N, Ni / Cr, Al / Au, Pt, Cr / Mo / Au, YBa ₂ Cu. ₃ O _7-d , Ni / Au, Ni / Mo, Ni / Mo / Au, Ni / Mo / Ag, Ni / Mo / Al, Ni / W, Ni / W / Au, Ni / W / Ag and Ni / It can be formed of W / Al containing at least one substance. The electrode thin film 240 can be formed by using at least one vapor deposition method from a sputtering vapor deposition method, a vacuum vapor deposition method, and an E-beam vapor deposition method.

The transition thin film 230 may be formed on the first electrode thin film 241. The transition thin film 230 includes an inorganic compound semiconductor to which low-concentration holes containing oxygen, carbon, a semiconductor element (III-V group, II-VI group), a transition metal element, a rare earth element, and a lanthanum element are added, and an insulator. Including at least one of an organic semiconductor and an insulator to which a low-concentration hole is added, a semiconductor to which a low-concentration hole is added, and an oxide semiconductor and an insulator to which a low-concentration hole is added Can do. Here, the concentration of the added holes is about 3 × 10 ¹⁶ cm ⁻³ . In addition, the transition thin film 230 may be formed to include an n-type semiconductor and an insulator having a very large resistance.

  The electrical characteristics of the MIT element 200 change rapidly due to various changes in physical characteristics such as voltage, temperature, and electromagnetic waves. For example, the MIT device 200 exhibits the characteristics of an insulator below the critical temperature, and the discontinuous MIT occurs above the critical temperature to have the characteristics of a metallic material.

  Referring to FIG. 6B, the horizontal MIT element 200a may include a substrate 210, a buffer layer 220, a transition thin film 230a, and an electrode thin film 240a, similar to the stacked MIT element 200.

  The transition thin film 230a is formed on the buffer layer 220 and can be formed immediately on the substrate 210 when the lattice mismatch with the substrate 210 is small. In addition, the first electrode thin film 241a and the second electrode thin film 243a of the electrode thin film 240a are formed on the buffer layer 220, but may be formed to face each other on both sides of the transition thin film 230a. In addition, the first electrode thin film 241a and the second electrode thin film 243a can be formed to cover a part of the upper surface of the transition thin film 230a as shown in the drawing.

  On the other hand, it goes without saying that the substrate 210, the buffer layer 220, the transition thin film 230a, and the electrode thin film 240a of the horizontal MIT element 200a can be formed of the same material as described in FIG. 6A.

  Referring to FIG. 6C, the buffer layer 220, the transition thin film 230a, and the first and second electrode thin films 241a and 243a of the horizontal MIT device 200a are illustrated. As shown in the figure, in the horizontal MIT element 200a, each of the first electrode thin film 241a and the second electrode thin film 243a can have a first width W, and between the first electrode thin film 241a and the second electrode thin film 243a. There may be a first interval d between them.

  The stacked or horizontal MIT elements 200 and 200a can be manufactured in a small size of μm, and can be manufactured at an extremely low cost from an economical viewpoint. Further, the critical temperatures of the MIT elements 200 and 200a can be changed by changing the structure itself, for example, by changing the first interval d and the first width W of the electrode thin film in FIG. 6C.

FIG. 7 is a graph showing resistance characteristics with respect to temperature of an MIT element made of vanadium dioxide (VO ₂ ), and a predetermined voltage is applied to the MIT element.

Referring to FIG. 7, the MIT element has a resistance value of 10 ⁵ Ω or more when it is less than 340K, and represents a characteristic as an insulator. Represents the characteristics as a metal with When referring to this graph, since the MIT device used in the experiment causes discontinuous MIT at 340K, the critical temperature can be regarded as about 340K.

  Although not shown in the drawing, in the case of the voltage-current curve graph of the MIT element, it can be seen that the current rapidly increases through the discontinuous jump and the voltage decreases at the critical temperature. Here, the generation of MIT due to temperature has been described. In general, an MIT element can generate MIT due to various physical characteristics such as pressure, voltage, electric field, and electromagnetic waves in addition to temperature. However, since there is a gist and distance of the present invention, a detailed description of the occurrence of MIT due to other physical characteristics is omitted.

On the other hand, the MIT element used in this experiment was manufactured using an MIT thin film formed of VO ₂ , but is not limited to VO ₂ and has discontinuous jump characteristics due to the various physical characteristics described above. Needless to say, an MIT thin film can be manufactured using a new material or material that can be used. The MIT thin film can also be manufactured in the form of a ceramic thin film or a single crystal thin film.

Figure 8 is a modified circuit diagram of FIG. 4 were used to measure the change in output voltage with respect to sinusoidal input, the input voltage V _IN is applied to the gate terminal V _G which is connected to one terminal of the capacitor The first output voltage V _OUT1 is measured at the drain terminal of the FET, and the second output voltage V _OUT2 is measured at the other terminal of the capacitor C1.

  Referring to FIG. 8, the variable gate FET used in this experiment has an RC circuit in which a capacitor C1 is connected to the gate of the FET. Such an RC circuit may be the same circuit as FIG. 4 except for the capacitor C1. On the other hand, the used FET is a MOS (Metal Oxide Semiconductor) FET, and may be, for example, KTK919S.

In such RC circuits by applying a 15MHz high frequency sine-wave input voltage _{V IN} to the gate terminal _{V G,} the change of the voltage _{V MIT} applied to the resistor _{R MIT} variations and MIT device MIT device at the drain terminal of the FET The two types of output waveforms with respect to the first output voltage _VOUT1 are observed. Further, at the other end of the capacitor, due to the change in resistance _{R MIT} in the MIT device, observing the output waveform for the second output voltage _{V OUT2.}

The RC circuit is regarded as a high-pass filter, and the ratio of the output voltage to the input voltage is increased when the frequency is high according to the following expression 1.

Table 1 is the RC circuit diagram of FIG. 8 and shows the first output voltage V _OUT1 when the voltage V _MIT applied to the MIT element is changed.

In Table 2, V _G represents a voltage applied to the gate terminal, V _D represents a voltage applied to the drain terminal of the FET, and Freq. Is a frequency of the input voltage, the unit is Mhz, C represents the capacitance of the capacitor C1, R ₁ represents a resistance value for the resistance element R1 connected to the drain terminal of the FET.

If Table 2 is analyzed,
a. The first output voltage V _OUT1 before VMIT is applied is 230 mV. After V _MIT can be applied, the first output voltage V _OUT1 increases to a maximum of 900 mV, and is amplified to 2 to 4 times the first output voltage V _OUT1 before V _MIT is applied.
b. An offset occurs in the positive sine wave after the V _MIT voltage of 1 V or more is applied. The maximum value of the first output voltage V _OUT1 is increased by the voltage increase of V _MIT , but the minimum value is constant from V _MIT = 2V to −700 mV.

  9A and 9B are signal waveform diagrams showing the input voltage and the output voltage measured in the circuit diagram of FIG. 8, and FIG. 9A shows the waveform of the first output voltage when the MIT element is not connected. FIG. 9B is a waveform diagram for the first output voltage when a voltage of 4 V is applied to the MIT element.

Waveform diagram of FIG. 9A, the top of the conditions in Table 2, i.e., the input voltage _{V IN} is _5Sin2paift, showing a case _{where R MIT} and _{V MIT} is not connected. In such a case, it can be seen that the first output voltage is as small as 230 mV. On the other hand, ch1 5V at the bottom of FIG. 9A means that the scale unit on the graph of the input voltage portion is 5V, and ch2 200mV means that the scale unit of the output voltage portion is 200 mV.

The waveform diagram of FIG. 9B shows the condition at the bottom of Table 2, that is, the case where the input voltage _VIN is 5 sin 2πft, R _MIT is 30Ω, and V _MIT is 4V. In such a case, it can be seen that the first output voltage increases to about 900 mV, and that the minimum value is −700 mV and an offset of about 200 mV occurs. _{Consequently,} the _{V MIT} increases, it can be seen that the first output voltage is amplified from previous _{V MIT} connected. For example, it can be confirmed that when the V _MIT is 4 V, the first output voltage is amplified by about 4 times compared to before the V _MIT connection.

FIG. 10 is a graph showing the maximum and minimum values of the first output voltage _VOUT1 due to the change in _VMIT measured in the circuit diagram of FIG.

As can be seen from FIG. 10, the first output voltage at the portion where V _MIT is not connected is shown, and it can be seen that the first output voltage increases as V _MIT increases. On the other hand, considering the aspect of the maximum value and the minimum value of the first output voltage, the first output voltage continues to increase as V _MIT increases, but the minimum value is constant from V _MIT = 2V to −700 mV. I understand that. Thereby, it can be seen that the offset generated from V _MIT = 1V or higher continues to increase.

Table 3 shows the first output voltage V _OUT1 due to the _RMIT change measured in the circuit diagram of FIG.

  The meanings of the variables shown in Table 3 are as described in Table 1.

If Table 3 is analyzed,
a. The first output voltage _{V OUT1} as the resistance of R _MIT increases is reduced. That is, it is not well amplified.
b. R _MIT = 30Ω, and the absolute value difference between the maximum value and the minimum value of V _OUT1 is 200 mV. That is,
| 900 | − | −700 | = 200 [mV]
c. When R _MIT = 100 kΩ, the absolute value difference between the maximum value and the minimum value of V _OUT1 is 50 mV, and the offset decreases as the resistance increases. That is,
| 450 | − | −400 | = 50 [mV]

FIG. 11 is a graph showing the maximum and minimum values of the first output voltage _VOUT1 due to the _RMIT change measured in the circuit diagram of FIG.

Referring to FIG. 11, when R _MIT = 30Ω, the first output voltage offset is the largest at 200 mV, and when R _MIT = 100 kΩ, the first output voltage offset is 50 mV. It can be confirmed that it is reduced. It is expected that the offset disappears from the numerical value in which the offset of the first output voltage decreases as _RMIT increases based on the slope of the graph.

FIGS. 12A and 12B are signal waveform diagrams showing the second output voltage _VOUT2 after passing through the capacitor in the circuit diagram of FIG. 8, except for _RMIT , experimental conditions such as input voltage and frequency. Applies the same as the measurement of the first output voltage according to Table 3.

Figure 12A shows a second output voltage _{V OUT2} at 120Ω ≦ _{R MIT} ≦ 200Ω region, it can be seen that the DC component is added to the second output voltage _{V OUT2} of the output waveform after passing the capacitor. For example, it can be confirmed that a DC voltage of about 0.5 V is applied (the base voltage increases). This is presumed to be caused by voltage application from the MIT element.

Figure 12B shows a second output voltage _{V OUT2} at the resistor region other than 120Ω ≦ _{R MIT} ≦ 200Ω region, the DC component is added again. The added DC voltage is measured to be 0.5V or more. Here, ch1 5V means that the scale interval of the input voltage portion is 5V, and ch2 1V means that the interval of the scale of the output voltage portion is 1V.

On the other hand, through comparison between the input voltage and the second output voltage in FIGS. 12A and 12B, it can be seen that the output signal after passing through the capacitor is reduced by 7 to 8 times the input signal. Further, if the DC voltage addition is not taken into account, the least offset occurs in the region of 120Ω ≦ R _MIT ≦ 200Ω.

The conclusions in the first output voltage and second output voltage measurement experiments through the circuit diagram of FIG. 8 are as follows.
a. As a result of changing the voltage and resistance applied to the MIT element in the RC high-frequency circuit, a first output voltage higher than that of the circuit composed only of RC is shown.
b. V _MIT = 4V indicates the maximum first output voltage (900 mV). Such a result indicates that the first output voltage is increased by about 4 times compared to when V _MIT is not applied.
c. As _RMIT increases, the first output voltage decreases, but the offset decreases.
d. When the resistance of the MIT element is in the condition of 120Ω ≦ R _MIT ≦ 200Ω, the offset is the smallest. Further, in this experiment, a high-frequency sine wave of 15 MHz was used as the input voltage, but the same result is expected to be obtained in the case of an RF signal.

  FIG. 13 is a circuit diagram of an electrical and electronic device including a variable gate FET according to another embodiment of the present invention.

  Referring to FIG. 13, the electrical / electronic device of the present embodiment may include a variable gate FET 1000 a and a driving element 300, similar to the electrical / electronic device of FIG. 4. However, the variable gate FET 1000a is different from the variable gate FET 1000 of FIG. That is, the variable gate FET 1000a of this embodiment can include the thermistor element 500 connected to the FET 100 and the gate G of the FET 100.

  The thermistor element 500 in this embodiment can perform the same function as the MIT element 200 in the electric and electronic apparatus of FIG. Thereby, the element connection structure of the variable gate FET 1000a in this embodiment is the same as that of the variable gate FET 1000 in FIG.

That is, the drive voltage source V _D is connected to the drain D of the FET 100, and the drive element 300 is connected to the source S. A gate voltage source V _G and a thermistor element 500 are connected to the gate G of the FET 100 through a contact A. One terminal of the thermistor element 500 is connected to the gate G of the FET 100, and the other terminal is connected to the control voltage source _VTh . Furthermore, a resistance element 400 is connected between the drain D of the FET 100 and the driving voltage source V _D, and other resistance elements can be added or omitted in each required part in the electrical and electronic device.

  The thermistor element 500 is a two-terminal or three-terminal element and has a characteristic that the resistance decreases as the temperature rises. The specific structure and features of the thermistor element 500 will be described in more detail in the description of FIGS. 15A and 15B.

  The operation principle of the variable gate FET 1000a in the electric / electronic device of this embodiment is similar to that of the variable gate FET 1000 in the electric / electronic device of FIG.

That is, the source and drain channel currents decrease while heat is generated by the high-speed switching of the FET 100. However, the heat generated at this time is transmitted to the thermistor element 500, and the resistance of the thermistor element 500 is reduced by heat, so that the voltage of the control voltage source V _Th is applied to the gate G of the FET 100 through the contact A, The gate voltage of the FET 100 is increased. However, in the case of the MIT element 200, since the transition is made to a metal, a voltage almost the same as the voltage of the control voltage source V _MIT is applied to the gate of the FET 100, but in the case of the thermistor element 500, the control voltage source V A voltage obtained by subtracting a voltage drop corresponding to the resistance value after resistance reduction from the _Th voltage is applied to the gate of the FET 100.

  As a result, as described above, the source and drain currents increase as the gate voltage of the FET 100 increases, and the temperature of the source and drain channel layers decreases as the source and drain currents increase.

  FIG. 14 is a circuit diagram of an electrical and electronic device including a variable gate FET according to another embodiment of the present invention.

  Referring to FIG. 14, the electrical / electronic device of the present embodiment has a similar structure to that of FIG. 13, but only the thermistor element 500 is different. That is, one terminal of the thermistor element 500 may be connected to the gate G of the FET 100 through the contact A, and the other terminal may be connected to the ground. By connecting the ground to the thermistor element 500 in this way, the source and drain currents of the FET 100 can be reduced. This is a circuit for the electric / electronic device of FIG. 5 and is the same as the reason or principle of applying a ground voltage to the MIT element 200. On the other hand, the variable gate FET using the thermistor thin film can be expanded to a circuit structure in which one thermistor element is connected to each FET in the FET array element together with the variable gate FET using the MIT element. Needless to say.

  Hereinafter, when describing the variable gate FET, for convenience of explanation, the MIT element 200 and the thermistor element 500 are commonly referred to as 'gate control elements'.

  15A and 15B are plan views of the thermistor element used in the variable gate FET in FIG. 13 or FIG. 14, FIG. 15A is a plan view of the two-terminal thermistor element, and FIG. It is a top view about a 3 terminal thermistor element.

  Referring to FIG. 15A, the two-terminal thermistor element 500 may include a substrate 510, a thermistor thin film 520, and an electrode thin film 530.

  The substrate 510 can be an insulating substrate or a semiconductor substrate such as silicon.

The thermistor thin film 520 is a thin film formed on the substrate 510 and having NTC (Negative temperature coefficient) characteristics. The NTC characteristics will be described with reference to the graph part of FIG. For example, the thermistor thin film 20 is a semiconductor including III + V group semiconductor, II + VI semiconductor, graphene and carbon nanotube as a carbon compound, a pn junction diode such as pn junction Si, V ₂ O ₅ , p-type GaAs, and p-type Ge. It can be formed of a thin film.

  The thermistor thin film 520 is formed between the first electrode thin film 531 and the second electrode thin film 533, and the first and second electrode thin films 531 in a rectangular band shape on the planar structure. 533 may be formed in a structure connected between the first and second electrode thin films 531 and 533 in a shape of at least two rectangular bands.

  The electrode thin film 530 is an electrode for applying a voltage to the thermistor thin film 520 and may include a first electrode thin film 531 and a second electrode thin film 533. The first electrode thin film 531 and the second electrode thin film 533 may be formed on the substrate 510 so as to face each other on both side surfaces of the thermistor thin film 520. Meanwhile, as illustrated, the first electrode thin film 531 and the second electrode thin film 533 may be formed so as to cover a part of the upper surface of the thermistor thin film 520.

  Referring to FIG. 15B, the three-terminal thermistor element 500a may include a substrate 510, a thermistor thin film 520, an electrode thin film 530, and a heat dissipation thin film 540. That is, unlike the two-terminal thermistor element 500 of FIG. 15A, the thermistor element 500a of this embodiment further includes a heat dissipation thin film 540 at the bottom of the substrate 510.

  The heat dissipation thin film 540 is a terminal for heat dissipation of the thermistor element 500a, and may be formed of a metal material that is often thermally transferred to the entire lower surface of the substrate 510. By releasing heat through such a heat dissipation thin film 540, it is possible to prevent malfunction of the thermistor element 500a due to its own temperature rise.

  On the other hand, although not shown, the thermistor elements 500 and 500a include a buffer layer (not shown) formed on the substrate 510 in order to relax lattice mismatch between the substrate 510 and the thermistor thin film 520. be able to. Further, the thermistor elements 500 and 500a may include a thermistor protective insulating film (not shown) formed on the electrode thin film 530 and the thermistor thin film 520 in order to protect the thermistor thin film 520.

  FIG. 16 is a graph showing resistance characteristics with respect to temperature of the thermistor element.

  Referring to FIG. 16, the graph of resistance A versus temperature of the thermistor element, more specifically, the thermistor film, decreases exponentially with increasing temperature as shown. A thermistor whose resistance decreases in inverse proportion to the temperature in this manner is called a negative temperature coefficient (NTC) thermistor.

  Such a thermistor thin film having NTC characteristics can be formed of a Be-doped GaAs thin film. However, the present invention is not limited to a Be-doped GaAs thin film, and it goes without saying that any kind of material thin film having NTC characteristics can be used for thermistor device fabrication. For example, a pn junction diode or a pn junction portion between the base and emitter of a transistor can be used as a thermistor element. The variable gate FET including the gate control element of the present embodiment described above is a high-speed, high-power, and low-heat generation switching element, which is an RF signal amplification element, a DC-DC switching element, a power supply switching element, a micro Switching element for high-speed signal processing by processor, switching element for power control of electronic equipment, switching element for lithium ion charging, switching element for LED control, switching element for display pixel control, switching element for memory cell control, It can be used for switching elements such as an audio signal amplification switching element, a photo relay, and an optical switch. Further, it can be effectively used for all electric and electronic devices such as mobile phones, notebook personal computers, computers, and memories including such switching elements.

  FIG. 17 is a plan view showing a state in which the variable gate FET according to one embodiment of the present invention is integrated into one package.

  Referring to FIG. 17, the variable gate FETs 1000, 1000a in the electrical and electronic devices of FIGS. 4, 5, 13, and 14, ie, the FET 100 and the gate control elements 200, 500 are as illustrated. One package 2000 can be made into one chip. In such a one-chip structure package 2000, the gate control elements 200 and 500 may be disposed in a portion where the heat of the FET 100 is likely to be generated.

  Pins 1 to 8 exposed to the outside of the one-chip structure package 2000 are connected to terminals of elements connected to the variable gate FETs 1000 and 1000a in the electric and electronic devices of FIGS. 4, 5, 13 and 14. Can be used for On the other hand, it goes without saying that the arrangement and number of pins of the one-chip structure package 2000 can be changed.

  18A and 18B are a cross-sectional view and a plan view showing another package structure of a variable gate FET according to an embodiment of the present invention.

  Referring to FIG. 18A, the package structure of the gate variable transistors 1000 and 1000a of the present embodiment is different from the one-chip structure package 2000 of FIG. 17, and the FET 100 and the gate control element constituting the variable gate FETs 1000 and 1000a. 200 and 500 may be packaged and combined.

  The second package 4000 in which the gate control elements 200 and 500 are packaged may be coupled to the first package 3000 in which the FET 100 is packaged through the heat transfer medium 3500. The heat transfer medium 3500 may be formed of a material that efficiently transfers heat generated from the FET 100 to the gate control elements 200 and 500, for example, a material having high thermal conductivity. In addition, the second package 4000 may be coupled to a portion of the first package 3000 where a lot of heat is generated to improve the operation performance of the gate control elements 200 and 500.

  Referring to FIG. 18B, the FET 100 may be disposed in the first package 3000, and the second package 4000 may be disposed on an elliptical dotted line portion B, which is a portion where much heat is generated. Although not shown because it is a plan view, it goes without saying that the heat transfer medium 3500 can exist between the first package 3000 and the second package 4000.

  The present invention has been described with reference to the embodiments illustrated in the drawings. However, the present invention is only exemplary, and various modifications and equivalent other embodiments may be made by those skilled in the art. You will understand that there is. Therefore, the true technical protection scope of the present invention must be determined by the technical idea of the claims.

  The present invention is suitably used in the technical field related to FETs.

100 FET
200, 200a MIT element 210 Substrate 220 Buffer 230, 230a MIT thin film 240, 240a Electrode thin film 241, 241a First electrode thin film 243, 243a Second electrode thin film 300 Drive element 400 Resistance element 500, 500a Thermistor element 510 Substrate 520 Thermistor thin film 530 Electrode thin film 531 First electrode thin film 533 Second electrode thin film 540 Heat radiation thin film 1000, 1000a Gate variable transistor 2000 One-chip structure package 3000 First package 3500 Heat transfer medium 4000 Second package

Claims (13)

FET,
A gate control element that is attached to the surface of the FET or a heat generating portion and is connected to the gate terminal of the FET in terms of circuit, and changes the voltage of the gate terminal;
A capacitor having a first terminal coupled to the gate terminal of the FET and the gate control element; and a second terminal coupled to a gate voltage source ;
The gate control element is
Including an MIT element in which a sudden metal-insulator transition (MIT) occurs at a critical temperature;
The MIT element is
An MIT thin film that causes an abrupt MIT at the critical temperature;
And at least two electrode thin films in contact with the abrupt MIT thin film,
The MIT element is a stacked type in which two electrode thin films are stacked one above the other through the MIT thin film, or a horizontal type in which two electrode thin films are arranged on both side surfaces of the MIT thin film. Yes,
A variable gate FET in which the gate control element changes the voltage of the gate terminal to control the channel current between the source and drain of the FET when the temperature of the FET is higher than a predetermined temperature. The MIT element is
An MIT thin film that causes an abrupt MIT at the critical temperature;
And a two electrode thin films that contact the abrupt MIT thin film,
The first electrode thin film which is one of the two electrode thin films is connected to the gate terminal of the FET and the first terminal of the capacitor, and the other second electrode thin film is The variable gate FET according to claim 1 , wherein the variable gate FET is connected to a control voltage source or a ground. When the temperature of the FET is rising above the critical temperature,
The variable gate FET according to claim 2 , wherein a control voltage or a ground voltage is applied to the gate terminal when the MIT thin film transitions from an insulator to a metal. A driving voltage source is connected to the drain electrode of the FET,
A driving element is connected to the source electrode of the FET,
3. The variable gate FET according to claim 2 , wherein the capacitor and the MIT element are commonly connected to a gate of the FET. The MIT element is
An MIT thin film that causes an abrupt MIT at the critical temperature;
And a two electrode thin films that contact the abrupt MIT thin film,
The variable gate FET according to claim 1 , wherein the MIT thin film is formed of VO ₂ . The FET is N-type or P-type,
2. The variable gate FET according to claim 1, wherein the FET includes any one of an IGBT (Insulated Gate Bipolar Transistor) and a MOS transistor. The gate control element and the FET is variable gate FET according to claim 1, characterized in that it is packaged into a single chip. The variable gate FET includes a heat transfer medium that transfers heat generated from the FET,
The gate control element and the FET is packaged respectively, the gate control element and the FET which is packaged is characterized in that it is coupled to be heat transfer through the heat transfer mediator The variable gate FET according to claim 1. A drive element;
The variable gate FET according to claim 1, wherein the variable gate FET is connected to the driving element and controls a current supplied to the driving element.
An electrical and electronic device comprising: The gate control element is
An MIT thin film that causes an abrupt MIT at the critical temperature;
And a two electrode thin films that contact the abrupt MIT thin film,
The first electrode thin film which is one of the two electrode thin films is connected to the gate terminal of the FET and the first terminal of the capacitor, and the other second electrode thin film is 10. The electric and electronic device according to claim 9 , wherein the electric and electronic device is connected to a control voltage source or a ground. A driving voltage source is connected to the drain electrode of the FET,
The drive element is connected to the source electrode of the FET,
The electrical and electronic device according to claim 10 , wherein the capacitor and the MIT element are commonly connected to a gate of the FET. The variable gate FET is plural,
The FETs of the plurality of variable gate FETs are arranged in an array structure to form FET array elements, and the gate control elements are connected to the FETs of the FET array elements. The electrical and electronic device according to claim 9 . The electrical and electronic device is
RF signal amplification element, DC-DC switching element, power supply switching element, microprocessor high-speed signal processing switching element, electronic device power control switching element, lithium ion charging switching A switching element for controlling an LED, a switching element for controlling a display pixel, a switching element for controlling a memory cell, an acoustic device including at least one of an acoustic and audio signal amplification switching element, a photo relay, and an optical switch. The electrical and electronic device according to claim 9 , wherein

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