JP5340713B2 - Semiconductor memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem, wherein it is difficult to change a mask ROM region to an EEPROM region, and vice versa because a mask ROM and an EEPROM are markedly different in structure from each other, and the memory capacity of each memory is fixed which results in a restricted flexibility of a system. <P>SOLUTION: A semiconductor memory device includes multiple memory elements which have memory insulating films of the same structure in channel regions on a semiconductor substrate. The multiple memory elements are first memory elements, each of which stores information through charge injection into a predetermined area of the memory insulating film, and second memory elements, each of which stores information by preventing a current from flowing between a source and a drain. This configuration facilitates changing of the first memory elements to the second memory elements, and vice versa. <P>COPYRIGHT: (C)2010,JPO&amp;INPIT

Description

The present invention relates to a semiconductor memory device, and more particularly to an electrically rewritable EEPROM (Electrically Erasable Programmable Read Only).
The present invention relates to a semiconductor memory device having a structure in which a memory) and a non-rewritable mask ROM are mixedly mounted on the same semiconductor substrate.

  Microcontrollers are used to control various devices such as various electronic devices, watches and other measuring devices, communication devices, and industrial devices. The microcontroller is a CPU (Central Processing Unit), a storage device, a timer circuit having a timekeeping function and a counter function, an input / output circuit, and the like as one integrated circuit (mostly a one-chip semiconductor device). The CPU is operated by a program or data written in the storage device.

  Some programs and data written to a storage device need to be frequently rewritten even after being written, and some programs and data need not be rewritten once written. For example, the former is data such as control values and measurement values, and the latter is a program that controls the operation.

  In general, the structure of the memory element constituting the storage device is to selectively use a volatile memory and a nonvolatile memory in accordance with the type of information stored such as programs and data. In the case of data, RAM (Random Access Memory), which is a volatile memory, or an electrically rewritable EEPROM is often used even if it is a nonvolatile memory. In the case of a program, a ROM, which is a non-volatile memory, is often used to prevent accidental erasure or rewriting.

In recent years, there are cases where a dedicated microcontroller is mounted for each electronic device to be controlled and a general-purpose microcontroller is used. When a general-purpose microcontroller is used, a basic program related to the overall control and individual operation of the microcontroller is stored in the ROM, and a control program corresponding to the electronic device to be controlled is stored in the EEPROM. Often done.
Further, the microcontroller may write data generated during its operation to the EEPROM, and may further include a RAM for temporary data writing.

Of course, ROMs used in microcontrollers are required to have high data retention characteristics, but mask ROMs are often used in anticipation of cost reduction.
The mask ROM is a ROM that stores information by creating information as a pattern in advance during the manufacturing process of the ROM. For this reason, there is a merit that the structure can be simpler than that of a normal ROM, so that the cost is low.

  As described above, a microcontroller equipped with a semiconductor memory device having a plurality of memory elements having different structures is generally widely known, and is equipped with a semiconductor memory device in which an EEPROM and a mask ROM, which are the same nonvolatile memory, are mounted together. Microcontrollers also see many proposals (see, for example, Patent Document 1).

In the prior art disclosed in Patent Document 1, data necessary for the operation of a microcontroller is stored in memory element regions having different structures depending on the application, and is selectively used depending on the use state (mode).

  The prior art disclosed in Patent Document 1 will be described with reference to the drawings. FIG. 11 is a block diagram showing the configuration of the semiconductor device of the prior art disclosed in Patent Document 1, which has been rewritten so as not to depart from the gist thereof for easy explanation.

  A microcontroller 91 shown in FIG. 11 holds a CPU 92, a boot ROM 93 constituted by a mask ROM, a program memory 94 in which a program for controlling the operation of the microcontroller 91 is stored, and during operation of the microcontroller 91. It comprises a first data memory 951 for storing necessary data, a second data memory 952 for storing temporary data, a peripheral circuit 96, and an input / output circuit 97. The program memory 94 and the first data memory 951 are both configured by an EEPROM, and the second data memory 952 is configured by a RAM.

The usage state of the microcontroller 91 shown in FIG. 11 will be briefly described.
In the microcontroller 91 shown in FIG. 11, there are three modes, and each memory element is selectively used in each mode.
The first mode is a mode in which a program for controlling the operation of the microcontroller 91 such as an address and data is written in the program memory 94 using an external device before the microcontroller 91 is incorporated in a predetermined application system such as an electronic device. It is.
In the first mode, the CPU 92 is not involved, and an external device writes a program for controlling the operation of the microcontroller 91 in the program memory 94.

The second mode is a mode in which the contents of the program memory 94 are rewritten after the microcontroller 91 is incorporated in a predetermined application system.
In this mode, the CPU 92 rewrites the contents of the program memory 94 by erasing and writing data in the program memory 94 based on the program written in the boot ROM 93.

Further, the third mode is a mode in which the microcontroller 91 incorporated in a predetermined application system operates based on the program written in the program memory 94.
The microcontroller 91 is normally used in this third mode.

Japanese Patent Laying-Open No. 2005-242621 (page 2-3, FIG. 6)

  The mask ROM has a structure different from that of the EEPROM of the same nonvolatile memory because information is previously created as a pattern in the ROM manufacturing process. In general, each of the mask ROM and the EEPROM is provided with a dedicated area and formed in the area.

As described above, there are microcontrollers specialized for each electronic device to be controlled and general microcontrollers.
In the case of a dedicated microcontroller, the amount of information (data or program) stored in the mask ROM or EEPROM is known in advance from the design stage of the microcontroller, or the microcontroller is in the process of operating the electronic device to be controlled. The amount of information to be handled (for example, measured numerical data) can be predicted.

However, in the case of a general-purpose microcontroller, the amount of information stored in the mask ROM or EEPROM varies depending on the electronic device to be mounted and the convenience of the user using the electronic device. In other words, at the design stage of a general-purpose microcontroller, it is impossible to predict the details of its use. Of course, even with a dedicated microcontroller, the amount of information stored in the mask ROM or EEPROM may change due to changes in the specifications of the electronic device to be controlled. It is difficult to predict changes in the amount of information in advance.

  For this reason, the mask ROM and the EEPROM mounted on the microcontroller are adapted to increase the memory capacity (storage capacity). However, since this means an increase in memory elements, there is a problem that the chip size of the microcontroller increases and the cost increases.

In some cases, it is desired to increase the memory capacity of either the mask ROM or the EEPROM. Even in such a case, the mask ROM and the EEPROM, which are the same non-volatile memories, are different in the structure of the memory elements, so that the EEPROM area cannot be changed to the mask ROM area.
If the prior art disclosed in Patent Document 1 is described, the areas of the boot ROM 93, which is a mask ROM, and the program memory 94, which is an EEPROM, and the first data memory 951 cannot be easily changed.
That is, there is a problem that even if there is a request for a change in memory capacity for a predetermined ROM, it cannot be handled.

  As described above, as in the prior art disclosed in Patent Document 1, in a microcontroller configured with mixed memory elements having different structures, the mask ROM data can be changed or the mask ROM area and the EEPROM area can be changed. Is not easy. For this reason, the memory capacity of each memory must be determined in consideration of the usage status and specifications of the electronic device on which the microcontroller is mounted at the design stage, and complicated simulations and calculations are essential. The load on the design was large, which also caused an increase in cost.

  The semiconductor memory device of the present invention is to solve such a problem. An object of the present invention is to provide a structure of a semiconductor memory device that can easily rewrite data in a mask ROM area and change between a mask ROM area and an EEPROM area.

  In order to achieve the above object, the semiconductor memory device of the present invention employs the structure described below.

A source region, a channel region, and a drain region are provided in a semiconductor substrate, a memory insulating film is provided on the semiconductor substrate above the channel region, a memory gate electrode is provided on the memory insulating film, and the memory gate electrode and the source region are provided. In a semiconductor memory device including a plurality of MOSFET-structured memory elements each having a gate wiring, a source wiring, and a drain wiring connected to the drain region through contact holes,
The memory element has a structure in which no current flows between the first memory element in which data is stored by injecting charges into a predetermined region of the memory insulating film and the source region and the drain region. A second memory element to be stored,
Memory insulating film between the first memory element and the second memory device, the structure is rather equal,
By changing the pattern layout of the photoresist, the second memory element has a structure in which the source region or the drain region is separated from the end of the memory gate electrode so that no current flows between the source region and the drain region. The boundary between the EEPROM area and the mask ROM area can be changed depending on whether the element is a first memory element or a second memory element .

  With such a configuration, it is possible to easily rewrite the mask ROM data and change the mask ROM area and the EEPROM area.

Further, with such a structure, the second memory element can have a so-called offset structure. As a result, even when a voltage that normally allows a current to flow between the source region and the drain region is applied to the memory gate electrode, no current flows between the source region and the drain region.

  The second memory element may have a structure in which no current flows between the source region and the drain region by not providing a contact hole that connects the source region or the drain region and the source electrode or the drain electrode. it can.

  With such a structure, the source region and the drain region of the second memory element are insulated from the source electrode and the drain electrode by providing no contact hole. As a result, no current flows between the source region and the drain region.

  The second memory element can have a structure in which current does not flow between the source region and the drain region by having a cut portion in the source wiring or the drain wiring connected to the source region or the drain region.

  With such a configuration, the source wiring and the drain wiring of the second memory element are insulated. As a result, no current flows between the source region and the drain region.

  The memory element can have an LDD structure in which a low-concentration impurity region having an impurity concentration lower than that of the source region and the drain region is provided in contact with the memory gate electrode side of the source region or the drain region.

  With such a configuration, the memory device can have a high breakdown voltage, and the rewriting of the mask ROM data and the change between the mask ROM area and the EEPROM area are low in the LDD (Lightly Doped Drain) structure. This can be done with or without the concentration impurity region.

  In the first memory element, the threshold voltage in the thermal equilibrium state may be a threshold voltage indicating the data erasure state.

  With such a configuration, it is not necessary to erase data for the first memory element. Furthermore, since the data state of the first memory element constituting the mask ROM area does not invert, the information stored in the mask ROM area can be correctly maintained.

  According to the present invention, it goes without saying that the mask ROM data is rewritten, and the change between the mask ROM area and the EEPROM area is used in a photolithography process for forming a resist pattern provided on the surface of the semiconductor substrate in an ion implantation process or an etching process. This can be done by changing only one photomask. For this reason, it is possible to easily change the memory capacity of each memory.

  Further, it is not necessary to fix the memory capacity of each memory at the design stage, and as a result, there is an advantage that the degree of freedom of the mounted system or electronic device is not limited. Since it is not necessary to create a semiconductor memory device from the beginning only for changing the memory capacity, the work load associated with the mask change including the manufacturing cost is greatly reduced.

In the semiconductor memory device of the present invention, a first memory element and a second memory element having different structures are mixedly mounted, and the first memory element stores data by injecting electric charge into the memory insulating film. The second memory element stores data by making a structure in which no current flows between the source region and the drain region.
In the embodiment of the semiconductor memory device of the present invention, an EEPROM region configured using only the first memory element as the memory element, and a mask configured using the first memory element and the second memory element as the memory element. ROM area.
The first memory element and the second memory element have the same memory insulating film structure above the semiconductor substrate. As a result, the memory element can be connected to the first memory only by changing the structure of the source region and the drain region below the semiconductor substrate of the memory element (inside the substrate) or changing the configuration of the wiring connected to the source region and the drain region. It can be an element or a second memory element.
That is, the boundary between the EEPROM area and the mask ROM area can be freely changed without recreating all the memory elements.

  DESCRIPTION OF THE PREFERRED EMBODIMENTS A structure of the best mode for carrying out a semiconductor memory device of the present invention will be described below with reference to the drawings. In the following embodiments, a case where a memory element is configured by a MONOS (Metal Oxide Nitride Oxide Semiconductor) memory having an N conductivity type will be described as an example. The MONOS memory is a memory element having a memory insulating film called an ONO film in which an oxide film, a nitride film, and an oxide film are stacked between a semiconductor substrate in a channel region and a memory gate electrode.

  Further, in the figure, for easy explanation, an example in which a plurality of MONOS memories are arranged side by side is shown. The structure shows only the part necessary for explanation, and the structure that does not affect the function of the present invention such as a protective film is omitted, and the wiring and the like are schematically shown.

[Overall Description of First Embodiment: FIG. 1]
The overall structure of the semiconductor memory device of the first embodiment will be described with reference to FIG. FIG. 1 is a cross-sectional view schematically showing a portion where an EEPROM region and a mask ROM region are adjacent to each other, and shows a case where two memory elements in each region are used.

  In FIG. 1, 1 is a semiconductor substrate, 2 is a field oxide film, 32 is an EEPROM region, and 33 is a mask ROM region. 321, 322, 331 and 332 are MONOS memories, 41, 42, 43 and 44 are channel regions, and 5 is a memory insulating film. 61, 62, 63 and 64 are memory gate electrodes, 71, 72, 73 and 74 are source regions, and 81, 82, 83 and 84 are drain regions.

The MONOS memories 321, 322, 331, and 332 have the same structure of the memory insulating film 5 provided above the semiconductor substrate 1.
Among these MONOS memories, the MONOS memories 321, 322, and 332 all have the same structure as a memory element. The MONOS memory 321 will be described as an example. A source region 71 and a drain region 81 are provided in a semiconductor substrate 1 and a channel region 41 is provided between them. A memory insulating film 5 is formed on the semiconductor substrate 1 above the channel region 41. The memory gate electrode 61 is provided on the memory insulating film 5. The memory insulating film 5 has a laminated film structure having an ONO film, details of which will be described later.
The MONOS memory 331 has a so-called offset structure in which a source region 73 and a drain region 83 provided in the semiconductor substrate 1 are arranged so as to be separated from the end of the memory gate electrode 63.

  In the semiconductor memory device of the present invention, a first memory element and a second memory element having different structures are mixedly mounted. Each memory element has a different data storage form. The first memory element stores data by injecting charges into a predetermined region of the memory insulating film, and the second memory element has a source region. Data is stored by adopting a structure in which no current flows between the drain region and the drain region. In the example shown in FIG. 1, the first memory elements are MONOS memories 321, 322, and 332. The second memory element is a MONOS memory 331.

The memory gate electrodes 61, 62, 63, and 64 of the MONOS memories 321, 322, 331, and 332 are arranged in parallel while facing the gate width direction. Note that the gate width direction is a length direction in which the source region and the drain region face each other. In FIG. 1, the direction is from the front to the back. Incidentally, the gate length direction indicates the direction from the source region to the drain region, and is the left-right direction in FIG. The gate length is often used in the same meaning as the channel width. For this reason, there are some documents that refer to the gate length direction and the channel width direction.
Each of the MONOS memories arranged in this way is isolated from each other by the field oxide film 2.

  The EEPROM area 32 is constituted by only a first memory element that stores data by injecting charges into a predetermined area of the memory insulating film as a memory element. Since each of the MONOS memories 321 and 322, which are the first memory elements shown in FIG. 1, can store binary data, the EEPROM area 32 in this example can store 2-bit information.

  The mask ROM area 33 includes a second memory element in which data is stored by having a structure in which no current flows between the source area and the drain area, and a first memory element as a memory element. doing. In the example shown in FIG. 1, binary data can be stored in each of the MONOS memory 332 as the first memory element and the MONOS memory 331 as the second memory element. 2-bit information can be stored.

  The MONOS memory 331 as the second memory element is designed in advance so as to have an offset structure, and has a structure in which no current flows between the source region and the drain region when the element is completed through a predetermined manufacturing process. Data) is stored.

  That is, the feature of the first embodiment is that, in the memory element that stores data among the MONOS memories constituting the mask ROM region 33, a state in which no current flows between the source region and the drain region, This is realized by an offset structure.

[Explanation of threshold value]
Here, the threshold value of the memory element will be described.
As is known, in order to determine whether data is stored or erased in a memory element, the presence or absence of current flowing between the source region and the drain region of the memory element It can be decided by.
A state where no current flows between the source region and the drain region is a state where data is stored, and conversely, a state where a current flows is a state where data is erased. These states may be defined in advance when the semiconductor memory device is used, and may be determined according to the specifications of the memory read circuit. In the embodiment of the present invention, a state in which no current flows between the source region and the drain region of the memory element is a state in which data is stored.

  Whether a current flows between the source region and the drain region of the memory element can be determined by a threshold value of the memory element. The threshold value of the memory element is a predetermined voltage value applied to the memory gate electrode when a current value flowing between the source region and the drain region shows a predetermined current value. Therefore, the memory element has a threshold value when data is stored in the memory element (when no current flows between the source region and the drain region) and when data is erased (source region and drain region). And a threshold value when a current flows between them.

Since the threshold value of these memory elements changes depending on whether electrons or holes are injected into a predetermined portion of the memory insulating film, whether or not data is written to or erased from the memory element can be determined by examining this threshold value. You can get to know.
The state in which electrons are injected into the memory insulating film is the state in which data is stored, the threshold voltage is Vtw, the state in which holes are injected into the memory insulating film is the state in which data is erased, the threshold voltage is Vte, the memory A state in which neither electrons nor holes are injected into the insulating film, that is, a threshold voltage in a thermal equilibrium state is set to V0 (details of the thermal equilibrium state will be described later).
When reading data stored in the memory element, the value of the read voltage Vcg applied to the memory gate electrode is set so that the relationship of Vte <V0 <Vcg <Vtw is established.
For example, when a read voltage Vcg is applied to the memory gate electrode of a memory element and a current flows between the source region and the drain region, the memory element knows that data has been erased.

  By the way, the predetermined part of the memory insulating film is, for example, a charge storage layer in the memory insulating film. When the memory insulating film is composed of a laminated film composed of a plurality of films, the charge accumulation layer can be composed of an independent film as one charge accumulation film.

[Explanation of thermal equilibrium state]
Next, the thermal equilibrium state of the memory element will be described.
In addition to a state where data is written and a state where data is erased, the memory element also has a state called a thermal equilibrium state.
In general, the thermal equilibrium state is a chemically stable state in which there is no temporal change and there is no flow of energy or substance. In the memory element, as described above, the charge in the memory insulating film is A state in which electrons and holes are not injected into the accumulation layer.

In the MONOS memories 321, 322, and 332, the threshold voltage in the thermal equilibrium state is a threshold voltage that indicates the data erasure state.
As described above, the state of the memory element can be determined by the threshold value (that is, the value of the threshold voltage). Therefore, in the MONOS memories 321, 322, and 332, the memory elements are designed so as to have a threshold voltage indicating the data erased state in the thermal equilibrium state.

  In this method, for example, the impurity concentration of the semiconductor substrate serving as the channel region and the film thickness of the memory insulating film are adjusted or designed. Such control of the threshold voltage is a known general technique and will not be described.

Next, a process for bringing the memory element into a thermal equilibrium state will be described. Generally, in the manufacturing process of a semiconductor device, a process such as a dry etching apparatus or a plasma CVD apparatus performs a process in an atmosphere in which a reactive gas is in a plasma state, or a manufacturing apparatus in which a component that contacts a semiconductor substrate during processing is charged with static electricity. There are several. Therefore, in the memory element, not a few electrons and holes are injected into the charge storage layer of the memory insulating film during the manufacturing process.
However, even if electrons and holes are injected into the charge storage layer, they can be removed.

  That is, the heat treatment process is performed after the process in which the reaction gas is processed in the plasma atmosphere or at the end of the manufacturing process. Electrons and holes injected during the manufacturing process by the heat treatment process are released from the charge storage layer of the memory insulating film by obtaining thermal energy. As a result, a thermal equilibrium state can be realized.

  Of course, in the course of the manufacturing process, the device state may be set and adjusted so that the injection amount is suppressed to such an extent that electrons and holes can be completely discharged from the charge storage layer of the memory insulating film by the heat treatment process. .

  The heat treatment process may be replaced with an existing manufacturing process. For example, a sintering process after the formation of the metal wiring (an activation process of the contact interface between the metal wiring and the semiconductor) is used instead.

  In the example shown in FIG. 1, the MONOS memories 321 and 322, which are the first memory elements constituting the EEPROM region 32, are in an erased state when completed through the manufacturing process. Similarly, the MONOS memory 332, which is the first memory element constituting the mask ROM area 33, is in an erased state. Since the MOS memory 331 as the second memory element constituting the mask ROM area 33 has an offset structure, data is stored.

  In the EEPROM region 32, for example, if the MONOS memory 321 is in a state where data is written by injecting electrons into the memory insulating film 5, when the read voltage Vcg is applied to the memory gate electrodes 61 and 62, the MONOS memory 321 By injecting electrons into the memory insulating film 5, no current flows between the source region 71 and the drain region 82 even when the read voltage Vcg is applied to the memory gate electrode 61, and the MONOS memory 321 It is determined that the data is stored. On the other hand, since a current flows between the source region 72 and the drain region 82 in the MONOS memory 322, the MONOS memory 322 determines that the data has been erased.

  Similarly, in the mask ROM region 33, when the read voltage Vcg is applied to the memory gate electrodes 63 and 64, a current flows between the source region 74 and the drain region 84 of the MONOS memory 332, so that the MONOS memory 332 stores data. It is determined that it has been erased. The MONOS memory 331 determines that data is stored because no current flows between the source region 73 and the drain region 83 regardless of the voltage applied to the memory gate electrode 63.

  The threshold value of such a thermal equilibrium state can be set to −0.2V, for example. Then, when a voltage of 0 V is applied to the memory gate electrode of each MONOS memory, the energization between the source region and the drain region can be examined.

  In the example shown in FIG. 1, if the data stored state is “1” and the erased state is “0”, the information stored in the EEPROM area 32 and the mask ROM area 33 is “ “0” and “0”, and “1” and “0” in the mask ROM area 33.

As described above, when the MONOS memory is used as the memory element, the threshold voltage in the thermal equilibrium state becomes the threshold voltage indicating the data erasure state. Therefore, all the MONOS memories have the data in the erasure state when the manufacturing process is completed. It has become.
Of the memory elements constituting the mask ROM region 33, if the second memory element is designed and manufactured as an offset structure, the memory element is in a state where data is stored, and the other memory elements are Data has been erased. That is, when the mask ROM area 33 has a state where data is stored and a state where data is erased, an operation of selecting a memory element and erasing the data becomes unnecessary.

  The same applies to the EEPROM area 32. In the EEPROM area 32, since all the data in the memory elements are erased when the manufacturing process is completed, there is no need for prior work such as once erasing all bits even when data is newly stored. . That is, it is only necessary to select a memory element in which data is to be stored and store the data.

  As described above, since the semiconductor memory device of the present invention uses the MONOS memory in which the thermal equilibrium state is the threshold voltage indicating the data erasure state, the data can be stored in the EEPROM area 32 or the mask ROM area 33. It is possible to shorten the turn required when storing. The example shown in FIG. 1 is a case where 4-bit data is handled, but when the number of bits is larger (the memory capacity is large), the effect is greater.

[Description of MONOS memory structure: FIG. 2]
Next, details of the structure of the MONOS memory will be described with reference to FIG.
FIG. 2 is a cross-sectional view showing the configuration in more detail while enlarging the boundary portion between the EEPROM region 32 and the mask ROM region 33 in the cross-sectional view shown in FIG. In addition, the same number is provided to the same structure already demonstrated.

  In FIG. 2, reference numeral 5 a denotes a first insulating film, 5 b denotes a second insulating film, and 5 c denotes a third insulating film, and the memory insulating film 5 is configured by sequentially stacking.

Similarly, in FIG. 2, 9 is an interlayer insulating film, and 10 is a contact hole. Reference numerals 11a, 12a, and 13a denote a gate electrode, a source electrode, and a drain electrode of the MONOS memory 332, respectively.
Reference numerals 11b, 12b, and 13b denote a gate electrode, a source electrode, and a drain electrode of the MONOS memory 331, respectively.

  In FIG. 2, 14 is a gate signal line, 15 is a source signal line, 16 is a drain signal line, and 17 is a bulk signal line. 18 is a power supply means, and 19 is a ground potential. These signal lines, power supply means 18 and ground potential 19 will be described in detail in the operation description of the MONOS memory.

  Similarly in FIG. 2, the distance L is the distance that the source region 73 and the drain region 83 of the MONOS memory 331 are separated from the end of the memory gate electrode 63.

  As the semiconductor substrate 1, for example, a silicon semiconductor substrate can be used. The first insulating film 5a is a tunnel insulating film and is composed of a silicon oxide film. The second insulating film 5b is a charge storage layer and is a silicon nitride film. The third insulating film 5c is a top insulating film and is composed of a silicon oxide film. These three insulating films are sequentially stacked on the surface of the semiconductor substrate 1 to form a memory insulating film 5 called an ONO film. Electrons and holes are accumulated in the second insulating film 5b which is the charge accumulation layer.

As shown in FIG. 2, the field oxide film 2 surrounds the area where the MONOS memory 322 and the MONOS memory 331 are provided on the surface of the semiconductor substrate 1 having a P-type conductivity. This field oxide film 2 is an element isolation film made of a silicon oxide film.
The MONOS memory 322 and the MONOS memory 331 each have a channel region 42.
43, memory gate electrodes 62 and 63 provided via the memory insulating film 5, and source regions 72 and 73 and drain regions 82 and 83 provided on both sides of these memory gate electrodes.

  The memory gate electrodes 62 and 63 are made of polycrystalline silicon whose conductivity type is N-type. Further, the source regions 72 and 73 and the drain regions 82 and 83 are regions into which a high-concentration impurity whose conductivity type is N-type is introduced.

On the MONOS memory 322 and the MONOS memory 331, an interlayer insulating film 9 made of a silicon oxide film is provided. In the interlayer insulating film 9, a contact hole 10 is provided above the memory gate electrodes 62 and 63, the source regions 72 and 73, and the drain regions 82 and 83.
Through the contact hole 10, the memory gate electrodes 62 and 63, the source regions 72 and 73, the drain regions 82 and 83, the gate electrodes 11a and 11b, the source electrodes 12a and 12b, and the drain electrodes 13a and 13b, Each is connected.
The gate electrodes 11a and 11b, the source electrodes 12a and 12b, and the drain electrodes 13a and 13b are made of, for example, aluminum or an aluminum alloy.

The source region 72 and the drain region 82 of the MONOS memory 322 are provided in contact with the end portion of the memory gate electrode 62. Further, although not shown, these regions may be provided so as to overlap the memory gate electrode 62 in a plane.
In the MONOS memory 331, the source region 73 and the drain region 83 are arranged at a distance L from the end of the memory gate electrode 63.
That is, the distance between the source region 73 and the drain region 83 of the MONOS memory 331 is separated from the distance between the source region 73 and the drain region 83 of the MONOS memory 331 by twice the distance L in the gate length direction. .

  In the MONOS memory 331, the source region 73 and the drain region 83 are arranged apart from the end of the memory gate electrode 63, so that a voltage is applied to the memory gate electrode 63 and a channel (not shown) is supplied to the channel region 43. Even if is formed, the source region 73 and the drain region 83 do not conduct through the channel.

That is, in the MONOS memory 331, no current flows between the source region 73 and the drain region 83 at a standard voltage necessary for normal operation of the MONOS memory. In other words, the threshold voltage has a very high voltage value.
As is known, the MONOS memory has an upper limit in the applied voltage and drive voltage, and is destroyed when an overvoltage is applied. In view of this, the MONOS memory 331 operates as a mask ROM that cannot electrically rewrite data in an environment where a standard voltage necessary for normal operation of the MONOS memory can be applied.

  By the way, in order to operate this MONOS memory normally, the standard voltage applied to the memory gate electrode is, for example, 7V to 9V for the write voltage and about 2 to 3V for the read voltage.

[Explanation of MONOS memory operation]
Next, a method for storing data in the MONOS memory will be described with reference to FIG. In this description, the MONOS memory 322 is used.
As described above, the memory gate electrode 62, the source region 72, and the drain region 82 are connected to the gate electrode 11a, the source electrode 12a, and the drain electrode 13a through the contact holes 10, respectively. These electrodes are connected to the gate signal line 14, the source signal line 15, and the drain signal line 16. The semiconductor substrate 1 is connected to the bulk signal line 17. Although not shown, the semiconductor substrate 1 and the bulk signal line 17 are provided with a diffusion region of the same conductivity type as that of the semiconductor substrate 1 and are electrically connected to the bulk signal line 17.

  The power supply means 18 has a known power supply circuit, is a power supply that generates a predetermined voltage, and generates a write voltage in the MONOS memory. For example, a booster circuit that receives a voltage value such as 1.5 V or 3.0 V, boosts the voltage value to 7.0 V or 9.0 V, and outputs the boosted voltage value may be provided. The ground potential 19 is a reference potential having a voltage value of 0V.

When data is stored in the MONOS memory 322, a predetermined voltage (hereinafter referred to as a write voltage) is applied to the memory gate electrode 62. Specifically, the write voltage generated by the power supply means 18 is applied to the memory gate electrode 62 so that the memory gate electrode 62 has a predetermined potential difference with respect to the potential of the channel region 42.
For example, in the state where the source signal line 15, the drain signal line 16, and the bulk signal line 17 are set to the ground potential 19, a write voltage of about +9.0 V is applied from the voltage supply unit 18 to the memory gate electrode 62 via the gate signal line 14. Apply. Then, the channel region 42 and the memory gate electrode 62 have a potential difference of +9.0 V, and electrons as charges are injected from the semiconductor substrate 1 into the second insulating film 5 b which is the charge storage layer of the memory insulating film 5. And the data is stored. This storage method is a so-called voltage writing method.

  Of course, there are other methods for storing data in the MONOS memory. However, the voltage writing method in which each electrode has the potential relationship as described above is simple because a predetermined voltage only needs to be applied to the memory gate electrode. It is.

  It is assumed that the MONOS memory 322 stores data in a state where charges are stored in the second insulating film 5b which is a charge storage layer. In the MONOS memory 322, since the source region 72 and the drain region 82 are N-type semiconductors, a channel is not formed in the channel region 42 in this state, and the source region 72 and the drain region 82 are not conductive. is there. In other words, due to the accumulation of electric charges in the second insulating film 5b, the threshold voltage becomes a higher voltage value than the voltage value before writing.

  In the example of FIG. 2, the MONOS memory 331 has been described with the configuration in which both the source region 73 and the drain region 83 are arranged apart from the end of the memory gate electrode 63. However, even if one of the source region 73 and the drain region 83 is arranged away from the end of the memory gate electrode 63, a structure in which no current flows between the source region 73 and the drain region 83. It can be.

  Further, the MONOS memory 322 and the MONOS memory 331 have been described by taking an example of a structure arranged adjacent to each other for ease of explanation, but each MONOS memory has a load for rewriting and reading information to and from the MONOS memory. A dedicated MIS transistor specialized for a predetermined application such as a load transistor or an address selection transistor for selecting an address may be provided adjacent to each other to constitute a memory cell.

[Description of Effects of Semiconductor Memory Device: FIGS. 1 and 3]
Next, the effect of the semiconductor memory device of the present invention will be described with reference to FIGS.
FIG. 3 is a plan view schematically showing a microcontroller equipped with the semiconductor memory device of the present invention. The following describes how the EEPROM area and the mask ROM area in the semiconductor memory device are changed when the specification of the microcontroller is changed. FIG. 3A shows a state before the change in the specifications of the microcontroller, and FIG. 3B shows a state after the change in the specifications of the microcontroller.

As described above, some programs and data written in the semiconductor memory device need to be frequently rewritten even after being stored, and some programs and data need not be rewritten once stored.
In the semiconductor memory device of the present invention, in the former case, the data may be stored in the MONOS memory in the EEPROM area 32. This is because it can be electrically rewritten. In the latter case, it may be stored in the MONO memory in the mask ROM area 33. The MONOS memory in the mask ROM area 33 has data written when the manufacturing process is completed, so that it is possible to avoid unexpected situations such as accidental rewriting of data and to have high data retention characteristics. This is because.

  In FIG. 3, reference numeral 30 denotes a microcontroller. Reference numeral 31 denotes a semiconductor memory device of the present invention. The semiconductor memory device 31 is composed of an EEPROM area 32 constituted only by the first memory element and a mask ROM area 33 constituted by the first memory element and the second memory element. The EEPROM area 32 and the mask ROM area 33 are arranged adjacent to each other, and the data reading method is the same. The other elements of the microcontroller 30 are not shown.

As described above, the microcontroller 30 is stored in the semiconductor memory device 31 depending on a change in the specification of the electronic device to be controlled, whether it is dedicated for each electronic device to be controlled or a general-purpose device. The amount of information to change may change. That is, the specification change of the microcontroller 30 in accordance with the specification change of the electronic device to be controlled.
For example, when a part of the program that controls the operation becomes unnecessary due to a change in the specifications of the electronic device, or numerical data that did not need to be stored so far for sending and receiving information to and from the electronic device, etc. This is a case where it is necessary to memorize a new one.

There is no problem as long as the amount of information stored in the semiconductor memory device 31 is reduced as the specification of the electronic device is changed. However, as described above, numerical data must be newly stored. In some cases, the amount of information stored in the semiconductor memory device 31 (in particular, the EEPROM area 32 in this case) determined in advance at the time of designing the microcontroller 30 must be changed.
In such a case, the semiconductor memory device of the present invention can cope with such a situation by changing the manufacturing process in the middle without remaking the microcontroller 30 from the first manufacturing process.

  That is, as shown in FIG. 1, the MONOS memories 321, 322, and 332 that are the first memory elements and the MONOS memory 331 that is the second memory elements have the same structure above the semiconductor substrate 1. The boundary between the EEPROM region 32 and the mask ROM region 33 can be changed simply by changing the configuration of the source regions 71, 72, 73, 74 below the substrate 1 and the drain regions 81, 82, 83, 84. it can.

As already described, FIGS. 3A and 3B show states before and after the specification change of the microcontroller 30 is made.
That is, the area of the EEPROM region 32 is larger in the semiconductor memory device 31 shown in FIG. 3B than in the semiconductor memory device 31 shown in FIG.
That is, this is the case, for example, when the information stored in the EEPROM area 32 is increased while the information stored in the mask ROM area 33 is decreased.

In the above-described prior art, in such a case, the EEPROM and the mask ROM having different structures had to be recreated. However, the microcontroller equipped with the semiconductor memory device of the present invention has a memory element. Since only the configuration of the source region and the drain region is changed, it can be realized in a much shorter manufacturing turn.

[Method of Manufacturing Structure in One Embodiment of the Present Invention: FIG. 2, FIG. 4 to FIG. 6, FIG. 7]
Next, a method for manufacturing the semiconductor memory device according to the first embodiment will be described with reference to cross-sectional views in FIGS.
4 to 6 are enlarged views of the boundary portion between the EEPROM region 32 and the mask ROM region 33 shown in FIG. 2, and are sectional views seen from the same direction as the direction shown in FIG. By this explanation, the effect of the first embodiment of the semiconductor memory device of the present invention will become clearer.

  4-6 is sectional drawing which shows the manufacturing method of 1st Embodiment in process order, and demonstrates it in order, using figures. The numerical values, film thicknesses, ion implantation amounts, materials, and the like exemplified in the manufacturing method described below are all examples.

  As shown in FIG. 4, a field oxide film 2 having a film thickness of 550 nm is formed on a semiconductor substrate 1 made of silicon and having a P conductivity type by a known selective oxidation method. The field oxide film 2 is formed so as to isolate the MONOS memory 322 and the MONOS memory 331 from each other.

Next, a first insulating film 5a made of a silicon oxide film having a thickness of 2 nm is formed on the entire upper surface of the semiconductor substrate 1 by a known oxidation method.
Further, a second insulating film 5b made of a silicon nitride film is formed to a thickness of 10 nm on the first insulating film 5a by using, for example, a CVD (Chemical Vapor Deposition) method.
Thereafter, the second insulating film 5b is oxidized by a known oxidation method to form a third insulating film 5c made of a silicon oxide film with a thickness of 5 nm, and the first insulating film 5a, the second insulating film 5b, and the third insulating film are formed. A memory insulating film 5 which is a laminated film of the film 5c is formed.

Next, an N-type polycrystalline silicon film 20 having a thickness of 350 nm is formed on the memory insulating film 5 by a CVD method using monosilane (SiH ₄ ) and phosphine (PH ₃ ) as a reaction gas.
For the polycrystalline silicon film 20 having the N conductivity type, after forming the non-doped polycrystalline silicon film, for example, phosphorus (P) is added under the condition of an ion implantation amount of about 1 × 10 ¹⁶ atoms / cm ² by ion implantation. It can also be formed.

  Further, a photoresist 21a is formed on the entire surface by a spin coating method, and exposure development processing is performed using a dedicated photomask, and the photoresist 21a remains in a region where the memory gate electrodes 62 and 63 of the MONOS memory 322 and the MONOS memory 331 are provided. Pattern it like this. Since the shape of the photoresist 21a is the shape of the memory gate electrodes 62 and 63, the MONOS memory 322 portion and the MONOS memory 331 portion are formed so that their gate width directions are opposed and arranged in parallel. .

  Next, as shown in FIG. 5, using the photoresist 21a formed in FIG. 4 as a mask, the polycrystalline silicon film 20 is etched using a known dry etching method to form memory gate electrodes 62 and 63. The gate length of the memory gate electrodes 62 and 63 is, for example, about 500 nm. Thereafter, although not shown, the photoresist 21a is removed.

Next, as shown in FIG. 6, a photoresist 21b is formed on the entire surface by spin coating, and exposure development processing is performed using a dedicated photomask, and the photoresist 21b is stored in the MONOS memory 33.
It is formed so as to remain around one memory gate electrode 63.
The photoresist 21b is formed to be longer than the end of the memory gate electrode 63 by a distance L ′ in the gate length direction. This distance L ′ is about 300 nm.

Next, using the photoresist 21b and the memory gate electrodes 62 and 63 as a mask, arsenic (As), which is an N-type impurity, is added under conditions of an ion implantation amount of about 3 × 10 ¹⁵ atoms / cm ^2. Concentration impurity regions 22 are formed.
The high concentration impurity region 22 is added to a region where the memory gate electrode 62 is self-aligned in the formation region of the MONOS memory 322, and is added to a region where the photoresist 21b is self-aligned in the formation region of the MONOS memory 331. That is, in the region where the MONOS memory 331 is formed, the high concentration impurity region 22 is formed at a distance L ′ from the end of the memory gate electrode 63.
This high-concentration impurity region 22 becomes source regions 72 and 73 or drain regions 82 and 83 in a later process. Thereafter, although not shown, the photoresist 21b is removed.

Next, although not shown, an annealing process is performed in a nitrogen atmosphere using an oxidation diffusion furnace in order to activate the high concentration impurity region 22.
By this annealing treatment, the impurities constituting the high concentration impurity region 22 are activated and diffused to become source regions 72 and 73 or drain regions 82 and 83 shown in FIG.

  Since the high concentration impurity region 22 is also diffused in the lateral direction by the annealing process, the distance L shown in FIG. 2 is shorter than the distance L ′ shown in FIG. 6 by the lateral diffusion. Although depending on the temperature and time of the annealing treatment, for example, when the distance L ′ is 300 nm, the distance L is about 150 nm.

Thereafter, an interlayer insulating film 9 made of a silicon oxide film is formed with a thickness of 1000 nm by a CVD method.
Then, a contact hole 10 is formed in the interlayer insulating film 9, and gate electrodes 11a and 11b, source electrodes 12a and 12b, which are connected to the memory gate electrodes 62 and 63, source regions 72 and 73, and drain electrodes 82 and 83, The drain electrodes 13a and 13b are formed of aluminum having a thickness of 1000 nm.

  Since the subsequent manufacturing steps are already known, the description thereof will be omitted, but the first embodiment of the semiconductor memory device of the present invention shown in FIG. 2 is completed by the manufacturing method described above.

As is apparent from the description of the manufacturing method described with reference to FIGS. 4 to 6, the MONOS memory 322 and the MONOS memory 331 have the same structure above the semiconductor substrate 1. It is common and can be formed in the same manufacturing process.
The structure of the source regions 72 and 73 and the drain regions 82 and 83 below the semiconductor substrate 1 is determined only by determining which MONOS memory is masked by using the photoresist 21b shown in FIG. It becomes a second memory element or a second memory element.

This will be described with reference to FIGS. 3 and 7. FIG.
7 (a) and 7 (b) show the same manufacturing process as that after the photoresist 21b shown in FIG. 6 is formed, but the number of MONOS memories is easy to explain. There are more than the example shown in FIG. Further, for ease of explanation, the mask ROM area 33 is described as being composed of only the second memory element unlike FIG. In the example shown in FIG. 7A, the EEPROM area 32 and the mask RO shown in FIG.
Each M region 33 is composed of three MONOS memories.

  When the memory capacity of the EEPROM area 32 or the mask ROM area 33 must be changed due to a change in the specification of the microcontroller on which the semiconductor memory device of the present invention is mounted, as shown in FIG. 7B, the pattern of the photoresist 21b By simply changing the layout, it is possible to change whether the MONOS memory is the first memory element or the second memory element. That is, the boundary between the EEPROM area 32 and the mask ROM area 33 can be changed.

  That is, the number of first memory elements constituting the EEPROM area 32 is increased from three to four, and the number of second memory elements constituting the mask ROM area 33 is reduced from three to two. Therefore, it is only necessary to change the pattern layout of the photoresist 21b for forming the source region and the drain region.

  By the way, in a manufacturing method of a semiconductor device or a semiconductor memory device, several wafers are often processed as one lot. In general, a predetermined number of wafers are not advanced to the next manufacturing process for each predetermined manufacturing process, and the process processing is generally waited. For example, even if the first manufacturing process is started with 24 wafers per lot, 16 wafers are kept waiting in a predetermined manufacturing process, and 8 wafers reach the final process. To do so.

  This is a measure for dealing with a sudden change in manufacturing process, change in manufacturing conditions, specification change of a completed semiconductor device or semiconductor memory device, and the like. In other words, except for the case where all manufacturing processes and manufacturing conditions are changed, the wafer is kept waiting during the manufacturing process, and the wafer is waiting in the manufacturing process before the manufacturing process and manufacturing conditions that have been changed. This is because the production can be completed in a shorter time than when the production is started from the first production process if the production is resumed by using.

  The above-described manufacturing method can be applied to the semiconductor memory device of the present invention. If a wafer waiting in the middle of the manufacturing process (for example, after the manufacturing process shown in FIG. 5) is used, the EEPROM region 32 or Even when it is necessary to change the memory capacity of the mask ROM area 33, it is possible to change the mask pattern of the photoresist 21b as shown in FIG. A semiconductor memory device having a memory capacity can be manufactured in a short time.

Next, a semiconductor memory device according to the second embodiment will be described.
In the second embodiment, the structures of the first memory element and the second memory element above the semiconductor substrate are the same as in the first embodiment already described.
The second memory element is one of the memory elements constituting the mask ROM region, and has a so-called non-contact structure in which a contact hole is not intentionally provided above the source region or the drain region. . And this 2nd memory element memorize | stores information by having this structure.

  That is, with such a structure, even when a standard voltage necessary for normal operation of the second memory element is applied to the memory gate electrode, an electric signal is not transmitted to the source region or the drain region, The source region or drain region is electrically isolated.

  That is, the feature of the second embodiment is that a state in which no current flows between the source region and the drain region is realized by a non-contact structure.

[Detailed Description of Second Embodiment: FIG. 8]
Next, a second embodiment will be described in detail using the cross-sectional view shown in FIG.
FIG. 8 is an enlarged cross-sectional view of the boundary between the EEPROM region 32 and the mask ROM region 33, as in FIG. 2 used for the description of the first embodiment. Also, the same number is assigned to the same configuration already described.

In the second embodiment shown in FIG. 8, the silicon oxide is formed on the MONOS memory 322 which is the first memory element and the MONOS memory 331 which is the second memory element, as in the first embodiment already described. An interlayer insulating film 9 made of a film is provided.
In the second embodiment, the interlayer insulating film 9 is provided with a contact hole 10 above the memory gate electrodes 62 and 63, the source regions 72 and 73, and the drain region 82. The gate electrodes 11a and 11b, the source electrodes 12a and 12b, and the drain electrode 13a are connected.

  However, the contact hole 10 is not provided in the upper part of the drain region 83 of the MONOS memory 331, and a so-called non-contact structure is formed, and the drain region 83 is not connected to the drain electrode 13b.

  In the MONOS memory 331 used as the mask ROM, since the drain region 83 and the drain electrode 13b are electrically insulated, a standard voltage necessary for normal operation of the MONOS memory is applied to the memory gate electrode 63. Even if a channel (not shown) is formed in the channel region 43 and the source region 73 and the drain region 83 are conducted through the channel, the source electrode 12b and the drain electrode 13b are not conducted. It is.

  That is, the MONOS memory 331 cannot electrically rewrite data in an environment where a standard voltage necessary for normal operation of the MONOS memory can be applied.

  In the structure of the second embodiment, in order for the MONOS memory 331 to have a structure in which the contact hole 10 is not provided between the drain region 83 and the drain electrode 13b, a known technique such as plasma etching using a reactive gas is used. When the contact hole 10 is formed in the interlayer insulating film 9, a photoresist having a pattern layout in which an opening is not provided only on the drain region 83 of the MONOS memory 331 is formed, and the contact hole 10 connected to the drain region 83 is formed between the interlayer regions. It is only necessary that the insulating film 9 is not formed.

  Similar to the first embodiment already described, even if the memory capacity of the EEPROM area 32 or the mask ROM area 33 as shown in FIG. Only by changing, it is possible to change whether the MONOS memory is the first memory element or the second memory element. That is, the boundary between the EEPROM area 32 and the mask ROM area 33 can be changed.

In the example described with reference to FIG. 8, the case where the contact hole 10 that connects the drain region 83 and the drain electrode 13 b is not provided in the MONOS memory 331 has been described. However, the present invention is not limited to this.
The contact hole 10 for connecting the source region 73 and the source electrode 12b may not be provided.
Of course, the contact hole 10 may not be provided so that the drain region 83 and the source region 73 are not connected to the drain electrode 13b and the source electrode 12b. In this way, the source region 73 and the drain region 8
Since 3 is insulated from any electrode, it can be said that the MONOS memory 331 is almost completely insulated.

Next, a semiconductor memory device according to a third embodiment will be described.
The third embodiment also has the same structure above the semiconductor substrate of the first memory element and the second memory element as in the first and second embodiments already described.
The second memory element is one of the memory elements constituting the mask ROM region, and has a so-called wiring disconnection structure in which a cut portion is formed in the wiring connected to the source region or the drain region. And this 2nd memory element memorize | stores information by having this structure.

  That is, with such a structure, even when a standard voltage necessary for normal operation of the second memory element is applied to the memory gate electrode, an electric signal is not transmitted to the source region or the drain region, The source region or drain region is electrically isolated.

  That is, the feature of the second embodiment is that a state in which no current flows between the source region and the drain region is realized by the disconnection structure of the wiring.

[Detailed Description of Third Embodiment: FIG. 9]
Next, a third embodiment will be described in detail using the plan view shown in FIG.
In FIG. 9, 23 is a cutting part. Reference numeral 24 denotes a drain wiring separated from the drain electrode 13 b by the cut portion 23. The distance X is a distance between the drain electrode 13 b and the drain wiring 24 divided by the cutting portion 23. Also, the same number is assigned to the same configuration already described. In FIG. 9, portions not related to the description such as the interlayer insulating film 9 are omitted for easy understanding of the drawing.

In the third embodiment shown in FIG. 9, as in the first and second embodiments already described, the MONOS memory 322 in which the structure above the semiconductor substrate of the MONOS memory is the first memory element. And the MONOS memory 331 which is the second memory element.
However, the drain electrode 13b connected to the drain region 83 of the MONOS memory 331 is separated from the drain wiring 24 by providing the cut portion 23, and has a so-called wiring disconnection structure. The drain wiring 24 is made of the same material as that of the drain electrode 13b. When the cutting portion 23 is not provided, the drain wiring 24 is integrated.

  In the MONOS memory 331 used as the mask ROM, since the drain region 83 and the drain electrode 13b are electrically insulated, a standard voltage necessary for normal operation of the MONOS memory is applied to the memory gate electrode 63. However, the source electrode 12b and the drain electrode 13b do not conduct.

  That is, the MONOS memory 331 cannot electrically rewrite data in an environment where a standard voltage necessary for normal operation of the MONOS memory can be applied.

  In the structure of the third embodiment, the cut portion 23 provided for the MONOS memory 331 to have a structure in which the drain electrode 13b and the drain wiring 24 are disconnected is the drain electrode 13b typified by aluminum. The conductive material of the (drain wiring 24) can be formed by processing by a known method such as plasma etching using a reactive gas using a photoresist pattern as an etching resistant mask.

The distance between the drain electrode 13b and the drain wiring 24 can be freely set in view of the wiring width of the drain electrode 13b. For example, when the wiring width of the drain electrode 13b is 0.8 μm, the distance X is 0.5 μm.

  Similar to the first and second embodiments already described, even if the memory capacity of the EEPROM area 32 or the mask ROM area 33 as shown in FIG. It is possible to change whether the MONOS memory is the first memory element or the second memory element only by providing the cut portion 23 in the electrode 13b (drain wiring 24). That is, the boundary between the EEPROM area 32 and the mask ROM area 33 can be changed.

In the example described with reference to FIG. 9, in the MONOS memory 331, the case where the cut portion 23 is provided in the drain electrode 13 b connected to the drain region 83 has been described, but the present invention is not limited to this.
You may make it the structure which provides the cutting part 23 in the electrode 12b for sources connected with the source region 73. FIG.
Of course, a configuration may be adopted in which the cut portions 23 are provided in both the drain electrode 13b and the source electrode 12b. In this way, since the source region 73 and the drain region 83 are insulated from any electrode, it can be said that the MONOS memory 331 is almost completely insulated.

Next, a semiconductor memory device according to a fourth embodiment will be described.
In the fourth embodiment, the structures of the first memory element and the second memory element above the semiconductor substrate are the same as in the first to third embodiments already described. Note that both the first memory element and the second memory element include a sidewall spacer on the sidewall of the memory gate electrode.
The first memory element has a so-called LDD structure in which a low-concentration impurity region having an impurity concentration lower than the impurity concentration of the source region and the drain region is provided in contact with the memory gate electrode side of the source region or drain region. It consists of memory.
The second memory element is one of the memory elements constituting the mask ROM region, and has a structure in which the source region and the drain region are arranged apart from the end of the memory gate electrode as in the first embodiment. It has a so-called offset structure. The second memory element stores information by having this structure.

  With such a structure, the first memory element can have a high breakdown voltage. Of course, in the second memory element, as in the first embodiment, even if a standard voltage necessary for normal operation of the second memory element is applied to the memory gate electrode, the source region Alternatively, an electric signal is not transmitted to the drain region, and the source region or the drain region is electrically insulated.

  In addition, both the first memory element and the second memory element can have an offset structure. However, only the first memory element can have an LDD structure by providing a low-concentration impurity region in a separated portion of the source region and the drain region separated from the channel region.

  That is, the fourth embodiment is characterized in that the first memory element can have a high breakdown voltage, and the second memory element can be configured with or without a low-concentration impurity region that constitutes the LDD structure. Is that you can.

[Detailed Description of Fourth Embodiment: FIG. 10]
Next, a fourth embodiment will be described in detail using the cross-sectional view shown in FIG.
FIG. 10 is an enlarged cross-sectional view of the boundary between the EEPROM region 32 and the mask ROM region 33, as in FIG. 2 used for the description of the first embodiment. In FIG. 10, reference numeral 25 denotes a side wall spacer provided on the side walls of the memory gate electrodes 62 and 63. Reference numeral 26 denotes a low concentration impurity region provided in contact with the source region 72 and the drain region 82. Also, the same number is assigned to the same configuration already described.

In the fourth embodiment shown in FIG. 10, as in the first embodiment already described, the second memory element has an offset structure so that the source region or the drain region is electrically insulated. Has been.
The MONOS memory 322 as the first memory element has a low concentration impurity region 26 on the channel region 42 side of the source region 72 and the drain region 82. The low-concentration impurity region 26 is a region having the same conductivity type as the source region 72 and the drain region 82 and a low impurity concentration. By providing the low-concentration impurity region 26, as is known, the electric field concentration near the drain is relaxed under the memory gate electrode 62, and the MONOS memory 322 can have a high breakdown voltage.
Both the MONOS memory 322 and the MONOS memory 331 as the second memory element have sidewall spacers 25 on the side walls of the memory gate electrodes 62 and 63.

The method for forming the sidewall spacer 25 and the method for forming the LDD structure are already known methods and will not be described in detail. However, both the MONOS memory 322 and the MONOS memory 331 may have the same offset structure. The presence or absence of the low concentration impurity region 26 can change whether the MONOS memory is the first memory element or the second memory element.
That is, as in the first embodiment already described, even when the memory capacity of the EEPROM region 32 or the mask ROM region 33 as shown in FIG. The boundary between the EEPROM area 32 and the mask ROM area 33 can be changed simply by changing the pattern layout of the photoresist to be provided.

In the example described with reference to FIG. 10, the case where the low concentration impurity region 26 is not provided in both the source region 73 and the drain region 83 in the MONOS memory 331 has been described. However, the present invention is not limited to this. .
A configuration in which the low concentration impurity region 26 is not provided only in one of the source region 73 and the drain region 83 may be employed.
Further, the side wall spacer 25 is often used together with the LDD structure, and is suitable for increasing the breakdown voltage of the memory element. The side wall spacer 25 depends on the required high breakdown voltage. It does not matter if the configuration is not provided.

  The semiconductor memory device of the present invention can easily rewrite mask ROM data and change the EEPROM area and the mask ROM area. For this reason, it is suitable as a semiconductor memory device mounted on a microcontroller that can deal with electronic devices whose specifications are frequently changed.

It is sectional drawing explaining the structure of the semiconductor memory device of this invention. It is sectional drawing explaining the detail about the structure of the semiconductor memory device in the 1st Embodiment of this invention. It is a typical top view explaining the effect of the semiconductor memory device of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor memory device in the 1st Embodiment of this invention, Comprising: It is a figure explaining the process of forming a memory insulating film and a polycrystalline silicon film on a semiconductor substrate. It is sectional drawing explaining the manufacturing method of the semiconductor memory device in the 1st Embodiment of this invention, Comprising: It is a figure explaining the process of forming a memory gate electrode. It is sectional drawing explaining the manufacturing method of the semiconductor memory device in the 1st Embodiment of this invention, Comprising: It is a figure explaining the process of forming a high concentration impurity region. FIG. 6 is a cross-sectional view illustrating the semiconductor memory device according to the first embodiment of the present invention, and is a diagram illustrating a process of increasing the number of MONOS memories in the state illustrated in FIG. 5. It is sectional drawing explaining the structure of the semiconductor memory device in the 2nd Embodiment of this invention. It is a top view explaining the structure of the semiconductor memory device in the 3rd Embodiment of this invention. It is sectional drawing explaining the structure of the semiconductor memory device in the 4th Embodiment of this invention. It is a circuit block diagram explaining the prior art shown in patent document 1.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Field oxide film 321, 322, 332 MONOS memory which is 1st memory element 331 MONOS memory which is 2nd memory element 41, 42, 43, 44 Channel area | region 5 Memory insulating film 5a 1st insulating film 5b Second insulating film 5c Third insulating film 61, 62, 63, 64 Memory gate electrode 71, 72, 73, 74 Source region 81, 82, 83, 84 Drain region 9 Interlayer insulating film 10 Contact hole 11a, 11b Gate electrode 12a, 12b Source electrode 13a, 13b Drain electrode 14 Gate signal line 15 Source signal line 16 Drain signal line 17 Bulk signal line 18 Power supply means 19 Ground potential 23 Cutting portion 24 Drain wiring 26 Low concentration impurity region 32 EEPROM region 33 Mask ROM area

Claims (2)

A semiconductor substrate is provided with a source region, a channel region, and a drain region, a memory insulating film is provided on the semiconductor substrate above the channel region, a memory gate electrode is provided on the memory insulating film,
In a semiconductor memory device comprising a plurality of MOSFET structured memory elements each having a gate wiring, a source wiring, and a drain wiring connected to the memory gate electrode, the source region, and the drain region through contact holes,
The memory element has a structure in which current does not flow between the first memory element in which data is stored by injecting electric charge into a predetermined region of the memory insulating film, and the source region and the drain region. And a second memory element in which data is stored,
The memory insulating film between said first memory element and the second memory device, the structure is rather equal,
By changing the pattern layout of the photoresist, the second memory element has the source region or the drain region separated from the end portion of the memory gate electrode, so that a current flows between the source region and the drain region. The structure does not flow, and the boundary between the EEPROM area and the mask ROM area can be changed depending on whether the memory element is the first memory element or the second memory element.
A semiconductor memory device. Said first memory device, the threshold voltage of the thermal equilibrium state, the semiconductor memory device according to claim 1, characterized in that the threshold voltage indicating the erased state of the data.

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