JP5755096B2 - Nonvolatile semiconductor memory device, manufacturing method thereof, and data rewriting method - Google Patents

Description

  The present invention relates to a nonvolatile semiconductor memory device.

  A nonvolatile semiconductor memory device stores data by accumulating electric charges in a charge accumulation film. Among these, a device that can electrically write and erase data is called an EEPROM (Electronically Erasable and Programmable Read Only Memory). There are two types of EEPROMs, which are roughly classified into different types of charge storage films.

  One is to form a gate insulating film by surrounding a conductor called a floating gate, which becomes a charge storage film, with an oxide film or the like so as to be electrically insulated. Floating Gate (floating gate) type.

  The other is to form a gate insulating film by laminating a plurality of insulating films. One of the plurality of insulating films is a charge storage film, and the amount of charge stored in a charge trap in the charge storage film. The MNOS (Metal-Nitride-Oxide-Silicon) type and the MONOS (Metal-Oxide-Nitride-Oxide-Silicon) type that store information by controlling.

  In the case of the FG type, since the charge storage film is a conductor, it is necessary to increase the thickness of the insulating film covering the charge storage film in order to make it difficult to escape the stored charge. Specifically, it is necessary to increase the thickness of a film (referred to as a tunnel insulating film) between the semiconductor substrate and the charge storage film. This inevitably increases the write voltage and the erase voltage.

  On the other hand, in the MNOS type or MONOS type EEPROM, since the charge storage film is an insulating film, the charge accumulated in the charge trap is difficult to escape, so the thickness of the tunnel insulating film or the like can be reduced. Therefore, there is a feature that data can be written and erased at a voltage lower than that of the FG type.

  In particular, in the case of the MONOS type, since a plurality of insulating films including the charge storage film can be made thinner than in the MNOS type, the voltage can be further reduced. For this reason, recently, it has attracted attention as a memory element that can contribute to lower power consumption.

  Threshold voltage in the state where electrons are stored in the charge storage film, that is, in the state where write data is stored, and Vth, and the threshold voltage in the state where holes are stored in the charge storage film, that is, where erase data is stored The value voltage is called Vte, and the threshold voltage in a state where neither electrons nor holes are accumulated in the charge storage film, that is, the thermal equilibrium state threshold voltage which is a stable state threshold voltage is called V0.

  Here, when the value of the voltage Vcg applied to the gate electrode of the memory element when reading the data stored in the memory element is set so that the relationship of Vte <Vcg <Vtw is established, the drain current of the memory element is Since it does not flow in a state where data is stored but flows in a state where erase data is stored, it is possible to discriminate between write data and erase data.

However, the values of Vtw and Vte are not always constant. The memory element gradually approaches a thermal equilibrium state that is a stable state of energy with the passage of time. That is, since the charge accumulated in the charge storage film is released over time, the values of Vtw and Vte approach V0, and finally Vtw = Vte = V0.

If the relationship of Vte <Vcg <Vtw does not hold in the process in which the values of Vtw and Vte approach V0, data cannot be read correctly.
That is, the EEPROM has a merit that data can be rewritten, and has a demerit that the retention time of stored data is finite.

  There is also a non-volatile semiconductor memory device different from an EEPROM that stores data by accumulating the above charges in a charge storage film, and a mask ROM is a typical one. The mask ROM is a ROM in which stored data is written during the LSI manufacturing process. There are roughly two types of mask ROMs with different writing methods.

  One is to adjust the impurity concentration in the channel region of the MOS transistor to produce two threshold voltages, similar to the above-mentioned EEPROM, and discriminate the stored data based on the presence or absence of the drain current.

  The other is based on the presence / absence of a contact hole (hereinafter referred to as a drain contact) provided in the drain region of the MOS transistor, which also determines stored data based on the presence / absence of a drain current.

Since the threshold voltage of the MOS transistor and the presence or absence of the drain contact hole do not change with the passage of time, the stored data does not disappear.
However, since the data to be stored is determined in the LSI manufacturing process, the data once stored cannot be rewritten.
That is, the mask ROM has a demerit that data cannot be rewritten together with a merit that stored data is not lost.

As described above, the EEPROM and the mask ROM each have advantages and disadvantages. However, the mask ROM has a limited practical range due to the disadvantage that data cannot be rewritten. Generally, the EEPROM has a little data holding time. However, it is put into practical use after taking measures to extend it.
As a method of extending the data retention time of such an EEPROM, several proposals are being seen (for example, see Patent Document 1).

  FIG. 14 is a circuit diagram described without changing the gist in order to explain the configuration of the read circuit of the nonvolatile semiconductor memory device described in the prior art disclosed in Patent Document 1.

In FIG. 14, 911 and 912 are sample cells, 920 is an average voltage output circuit, 930 is a select signal, 931 is a switch, 932 is a memory cell, and 933 is a read line.
Vw is a threshold voltage of the sample cell 911, Ve is a threshold voltage of the sample cell 912, Vo is an output voltage of the average voltage output circuit 920, and 940 is a gate electrode of the memory cell 932.

In FIG. 14, data is stored in the memory cell 932. The sample cell 911 and the sample cell 912 are storage elements having the same structure as the memory cell 932.
Positive data is stored in the sample cell 911, and Vw becomes a threshold voltage in a writing state. Negative data is stored in the sample cell 912, and Ve becomes the threshold voltage in the erased state.
The threshold voltage Vw and the threshold voltage Ve are input to the average voltage output circuit 920, and the average voltage output circuit 920 outputs an output voltage Vo that is an intermediate potential between the threshold voltage Vw and the threshold voltage Ve. .

The stored data is read by switching the switch 931 with the select signal 930 and applying the output voltage Vo to the gate electrode 940 of the memory cell 932.
At this time, if positive data is stored in the memory cell 932, the memory cell 932 is turned off. If negative data is stored in the memory cell 932, the memory cell 932 is turned on. By detecting the current flowing through the read line 933, the two states of the memory cell 932 are determined, and the stored data is read.

  The prior art disclosed in Patent Document 1 extends the data retention time by always keeping the read margin in the written state and the read margin in the erased state equal to the aging of the threshold voltage of the memory cell 932. It has the feature that it can.

JP-A-5-174487 (pages 3-4, FIG. 3)

  Although the prior art shown in Patent Document 1 is a technique that can certainly extend the data retention time, the point that the data retention time is finite is not different from the conventional one, and the stored data will eventually disappear. There is.

  The present invention has been made to solve such a problem, and an object thereof is to greatly extend the data retention time of the EEPROM. Specifically, since the data holding time can be infinite as in the mask ROM, a highly reliable EEPROM that can hold data for a long time can be provided.

  In order to solve the above problems, the present invention adopts the following configuration.

In a nonvolatile semiconductor memory device having a plurality of nonvolatile semiconductor memory elements that store data and can be rewritten,
The voltage value of the output terminal generated by the current inquiry between the nonvolatile semiconductor memory element that operates by being connected to the power supply VSS and the load transistor that is connected to the power supply VDD having a higher potential on the positive side than the power supply VSS. , the voltage level of the threshold when switching between the potential direction of the power supply VDD and the potential direction of the power supply VSS, and set the sense level of the non-volatile semiconductor memory device,
Among the plurality of nonvolatile semiconductor memory elements, the first nonvolatile semiconductor memory element in which the thermal equilibrium state threshold voltage is in the potential direction of the power supply VDD from the sense level, and the thermal equilibrium state threshold voltage is from the sense level. Also , the second nonvolatile semiconductor memory element in the potential direction of the power supply VSS is mixedly mounted.

  With such a configuration, the data retention time of the EEPROM can be made infinite.

Nonvolatile semiconductor memory elements
A memory insulating film having a structure in which a tunnel insulating film, a charge storage layer, and a top insulating film are stacked in this order,
You store data by injecting electrons or holes into the charge storage layer, or may be rewritten so that.

  With such a configuration, a MONOS type EEPROM can be obtained, so that data can be written and erased at a relatively low voltage, and power consumption can be reduced.

  In order to solve the above problems, the present invention employs the following manufacturing method.

In a method for manufacturing a nonvolatile semiconductor memory device having a plurality of nonvolatile semiconductor memory elements that store data and can be rewritten,
The voltage value of the output terminal generated by the current inquiry between the nonvolatile semiconductor memory element that operates by being connected to the power supply VSS and the load transistor that is connected to the power supply VDD having a higher potential on the positive side than the power supply VSS. , the voltage level of the threshold when switching between the potential direction of the power supply VDD and the potential direction of the power supply VSS, and set the sense level of the non-volatile semiconductor memory device,
Among the plurality of nonvolatile semiconductor memory elements, a step of forming a first nonvolatile semiconductor memory element in which the thermal equilibrium state threshold voltage is in the potential direction of the power supply VDD with respect to the sense level, and the thermal equilibrium state threshold voltage is Forming a second nonvolatile semiconductor memory element that is in the potential direction of the power source VSS with respect to the sense level ;
Writing positive data into the first nonvolatile semiconductor memory element based on the content of the data;
And writing negative data to the second nonvolatile semiconductor memory element based on the data content.

By using such a manufacturing method , data can be written to the EEPROM of the present invention having an infinite data retention time .

The step of writing into the first nonvolatile semiconductor memory element and the step of writing into the second nonvolatile semiconductor memory element are performed simultaneously by heat treatment .

By using such a manufacturing method , data can be written to the EEPROM of the present invention having an infinite data retention time in only one heat treatment step .

In a data rewriting method of a nonvolatile semiconductor memory device having a plurality of nonvolatile semiconductor memory elements that store data and can be rewritten,
The voltage value of the output terminal generated by the current inquiry between the nonvolatile semiconductor memory element that operates by being connected to the power supply VSS and the load transistor that is connected to the power supply VDD having a higher potential on the positive side than the power supply VSS. , the voltage level of the threshold when switching between the potential direction of the power supply VDD and the potential direction of the power supply VSS, and set the sense level of the non-volatile semiconductor memory device,
When the data to be written is positive data, among the plurality of nonvolatile semiconductor memory elements , the data is a first nonvolatile semiconductor whose thermal equilibrium state threshold voltage is in the potential direction of the power supply VDD from its sense level. Write to the memory element,
When the data to be written is negative data, among the plurality of nonvolatile semiconductor memory elements , the data is a second nonvolatile semiconductor whose thermal equilibrium state threshold voltage is in the potential direction of the power supply VSS from its sense level. Write to the memory element,
When rewriting positive data stored in the first nonvolatile semiconductor memory element,
Applying a write voltage such that the threshold value after data writing of the first nonvolatile semiconductor memory element is in the potential direction of the power supply VSS with respect to the sense level;
When rewriting negative data stored in the second nonvolatile semiconductor memory element,
A write voltage is applied such that a threshold value after data writing of the second nonvolatile semiconductor memory element is in the potential direction of the power supply VDD with respect to the sense level.

By adopting such a rewriting method, the data holding time of the positive data before rewriting becomes infinite, and the positive data can be rewritten to negative data. The data holding time of the negative data before rewriting becomes infinite, and the negative data can be rewritten to positive data.

The nonvolatile semiconductor memory device according to the present invention includes a first nonvolatile semiconductor memory element having a thermal equilibrium state threshold voltage in a positive direction with respect to a predetermined sense level and a second nonvolatile semiconductor memory element having a negative direction. As a result, the data retention time of the first stored data can be made infinite while having a data rewriting function that is a feature of the EEPROM.

It is explanatory drawing for demonstrating the threshold value and sense level of a non-volatile semiconductor memory element. It is explanatory drawing for demonstrating the concept of the non-volatile semiconductor memory device by this invention. It is explanatory drawing for demonstrating the concept of the non-volatile semiconductor memory device by this invention. It is a schematic diagram for demonstrating arrangement | positioning in the memory area of the non-volatile semiconductor memory device by this invention. FIG. 6 is a flowchart for explaining the flow of data writing and rewriting in the nonvolatile semiconductor memory device according to the present invention. It is sectional drawing for demonstrating the structure of the non-volatile semiconductor memory device by this invention. It is sectional drawing for demonstrating the manufacturing process of the channel region of the non-volatile semiconductor memory device by this invention. It is sectional drawing for demonstrating the manufacturing process of the channel region of the non-volatile semiconductor memory device by this invention. It is sectional drawing for demonstrating the manufacturing process of the laminated film of the non-volatile semiconductor memory device by this invention. It is sectional drawing for demonstrating shaping | molding of the laminated film of the non-volatile semiconductor memory device by this invention. It is sectional drawing for demonstrating shaping | molding of the gate of the non-volatile semiconductor memory device by this invention. It is explanatory drawing which shows the transistor characteristic at the time of the data writing of the non-volatile semiconductor memory device by this invention. It is explanatory drawing which shows the transistor characteristic at the time of the data rewriting of the non-volatile semiconductor memory device by this invention. 10 is a circuit diagram for explaining a circuit configuration of a conventional nonvolatile semiconductor memory device disclosed in Patent Document 1. FIG.

The nonvolatile semiconductor memory device according to the present invention includes a first nonvolatile semiconductor memory element having a thermal equilibrium state threshold voltage in a positive direction with respect to a predetermined sense level and a second nonvolatile semiconductor memory element having a negative direction. This is mixed and used.
First, the threshold value of such a nonvolatile semiconductor memory element will be described with reference to FIG. Next, the concept of the nonvolatile semiconductor memory device will be described with reference to FIGS. There are two methods for writing data to the nonvolatile semiconductor memory element: an electric writing method and a writing method by heat treatment applying heat. The former will be described with reference to FIG. 2, and the latter with reference to FIG. Then, the arrangement of the nonvolatile semiconductor memory element will be described with reference to FIG. Next, writing and rewriting procedures will be described with reference to FIG. Thereafter, an embodiment will be described with reference to FIGS.

[Explanation of Threshold and Sense Level of Nonvolatile Semiconductor Memory Element: FIG. 1]
First, the sense level of the nonvolatile semiconductor memory element will be described.
As described above, in the nonvolatile semiconductor memory element, data is written or erased by accumulating charges such as electrons and holes in the charge accumulating film, but the threshold depends on the accumulation state of the charges. The value voltage changes.

  A certain voltage level is defined for such a nonvolatile semiconductor memory element, and the presence or absence of data is known depending on whether the threshold voltage is on the positive side or the negative side. The voltage level is called the sense level.

An example of a read circuit of a nonvolatile semiconductor memory element that is generally well-known will be described with reference to FIG.
The read circuit shown in FIG. 1 has a load transistor FT that flows a predetermined constant current (operates at a constant current) and a nonvolatile semiconductor memory element MT, a power supply VDD having a high potential in the positive direction and a high potential in the negative direction. The power supply VSS to be supplied is connected in series between the two power supplies. That is, the drain electrodes are connected to each other. An output terminal OUT is provided from the connection point of the drain electrode, and a determination circuit (not shown) is connected thereto.

  Although there is originally an address transistor for selecting the nonvolatile semiconductor memory element MT between the load transistor FT and the nonvolatile semiconductor memory element MT, it is omitted because it is not related to the explanation of the sense level.

  Assuming that data is written (or erased) in the nonvolatile semiconductor memory element MT, the balance of the current flowing between the two power sources changes between the load transistor FT and the nonvolatile semiconductor memory element MT. Then, the voltage value output from the output terminal OUT also changes, and is recognized as positive data or negative data by a determination circuit (not shown).

  That is, if the amount of current that can be passed through the nonvolatile semiconductor memory element MT is small when data is written to the nonvolatile semiconductor memory element MT, the threshold value thereof changes, and a predetermined read state is obtained, the output terminal Since the read data output from OUT is in the potential direction of the power supply VDD connected to the source electrode of the load transistor FT, it is recognized as positive logic data by the determination circuit.

  If the amount of current that can be passed through the nonvolatile semiconductor memory element MT is large, the read data output from the output terminal OUT is in the potential direction of the power supply VSS connected to the source electrode of the nonvolatile semiconductor memory element MT. Therefore, it is recognized as negative logic data by the determination circuit.

  That is, the sense level is such that the voltage value of the output terminal OUT generated by the current attraction between the load transistor FT and the nonvolatile semiconductor memory element MT is from the potential direction of the power supply VDD to the potential direction of the power supply VSS or This is the threshold voltage level of the nonvolatile semiconductor memory element MT when switching to the potential direction of the power supply VDD.

Next, the threshold value will be described.
A nonvolatile semiconductor memory element that has not yet stored data after manufacture is in an indefinite state in which the threshold voltage is not stable. The threshold voltage at that time is VT0.
For a nonvolatile semiconductor memory element, a thermal equilibrium state in which no charge is present in the charge storage film is the most stable state. The threshold voltage at this time is the thermal equilibrium state threshold voltage.

  The threshold voltage of the non-volatile semiconductor memory element is obtained by obtaining the thermal energy at the normal temperature (for example, 25 ° C.) regardless of whether the data is written or the data is written. At the same time, electrons and holes escape from the charge storage film and eventually converge to the thermal equilibrium state threshold voltage.

Next, the creation of a predetermined thermal equilibrium state threshold voltage will be described.
The non-volatile semiconductor memory element of the present invention includes a first non-volatile semiconductor memory element in which the thermal equilibrium state threshold voltage is in the positive direction with respect to a predetermined sense level, and a second non-volatile semiconductor memory element in the negative direction. And are used. Such a non-volatile semiconductor memory element can be made separately at the manufacturing stage of the semiconductor device.

For example, this can be done by changing the impurity concentration of the channel region of the transistor element constituting the nonvolatile semiconductor memory element.
Further, the thickness of the gate insulating film may be changed. This is because the ease of conduction of the nonvolatile semiconductor memory element changes.
Further, the distance (channel length) between the source region and the drain region of the transistor element that constitutes the nonvolatile semiconductor memory element may be selected. When this distance is reduced, the threshold voltage of the nonvolatile semiconductor memory element becomes negative due to the short channel effect. This can be used to determine the threshold voltage.

[Description of Concept of Nonvolatile Semiconductor Memory Device of the Present Invention 1: FIG. 2]
FIG. 2 shows the change of the threshold voltage value of the nonvolatile semiconductor memory element over time, and is a diagram for explaining the relationship among the threshold voltage, the thermal equilibrium state threshold voltage, and the sense level. It is. The horizontal axis represents the passage of time on a logarithmic axis, and the vertical axis represents the threshold voltage value.

  In FIG. 2, VT1 and VT2 are threshold voltages of the nonvolatile semiconductor memory element, V01 and V02 are thermal equilibrium state threshold voltages, and SL is a sense level. T1, T2, T3, and T4 are times.

  The threshold voltage VT0 has a certain value before data is written to the nonvolatile semiconductor memory element, that is, after data has not been written once after completion of the manufacturing process. Omitted.

  2A is a diagram for explaining the first nonvolatile semiconductor memory element in which the thermal equilibrium state threshold voltage is in the positive direction with respect to a predetermined sense level, and FIG. FIG. 11 is a diagram for explaining a second nonvolatile semiconductor memory element in which a thermal equilibrium state threshold voltage is in a negative direction with respect to a predetermined sense level.

The first nonvolatile semiconductor memory element will be described with reference to FIG.
First, data is electrically written into the first nonvolatile semiconductor memory element completed through the manufacturing process. For example, a predetermined write voltage is applied by applying a probe needle to a bonding pad of a nonvolatile semiconductor memory device or the like. Such a technique is widely known. This time is T1.

Then, by performing such a data writing operation, the threshold voltage VT0 of the first nonvolatile semiconductor memory element changes to VT1. The degree to which the threshold voltage VT1 changes to the positive side with respect to VT0 depends on the strength of writing. For example, the threshold voltage VT1 changes to the positive side by increasing the write voltage or increasing the write time.
If threshold voltage VT1 is in the positive direction with respect to sense level SL, the stored data is recognized as positive data.

  The threshold voltage VT1 immediately after storing the positive data is in the positive direction with respect to the sense level SL, but changes in the negative direction with respect to the value immediately after the storage with the passage of time thereafter. This is because, as already described, charges gradually escape from the charge storage film of the nonvolatile semiconductor memory element.

If the threshold voltage VT1 continues to change and becomes negative with respect to the sense level SL, the stored positive data will disappear, but this is not the case.
This is because the threshold voltage VT1 stops changing when it reaches a thermal equilibrium state that is a stable state of energy. As shown in FIG. 2 (a), VT1 = V01 at time T2, and the negative direction with respect to the sense level SL does not become negative even if time elapses thereafter.

  In other words, since the first nonvolatile semiconductor memory element has a positive thermal equilibrium state threshold voltage with respect to a predetermined sense level, the data retention time of the stored positive data becomes infinite after time T2. It is.

The same applies to the second nonvolatile semiconductor memory element shown in FIG.
First, data is electrically written into the second nonvolatile semiconductor memory element. Then, the threshold voltage VT0 of the second nonvolatile semiconductor memory element changes to VT2 (this time is time T3).

Since the threshold voltage VT2 of the second nonvolatile semiconductor memory element is negative with respect to the sense level SL, the data stored at the time T3 is recognized as negative data. It changes in the positive direction with respect to the value immediately after storing.
The change is VT2 = V02 at time T4, and does not become positive with respect to the sense level SL even if time passes thereafter.

  That is, since the second nonvolatile semiconductor memory element has a negative thermal equilibrium state threshold voltage with respect to a predetermined sense level, the data holding time of the stored negative data becomes infinite after time T4. It is.

In the example shown in FIG. 2A, the threshold voltage at time T1 is higher in the positive direction in order to make it easier to see how the threshold voltage changes in the negative direction (slope) after data is written. It is shown as having a value. The example shown in FIG. 2B is the same, and in order to make the change in the threshold voltage easy to see, it is described as having a higher value in the negative direction.
In the present invention, it does not make sense to increase the threshold value after writing data in the positive or negative direction. The threshold voltage VT1 after the data is written may be higher in the positive direction than the sense level SL, and the threshold voltage VT2 may be higher in the negative direction than the sense level SL.

[Description of Concept of Nonvolatile Semiconductor Memory Device of the Present Invention 2: FIG. 3]
Next, writing data into the nonvolatile semiconductor memory element using a heat treatment method will be described with reference to FIG.
FIG. 3 shows the change of the threshold voltage value of the nonvolatile semiconductor memory element with the passage of time as in FIG. 2, and the vertical axis and the horizontal axis are the same. FIG. 3A corresponds to FIG. 2A and is a diagram for explaining the first nonvolatile semiconductor memory element. FIG. 3B also corresponds to FIG. It is a figure explaining a non-volatile semiconductor memory element.

  In FIG. 3, as in FIG. 2, the threshold voltage VT0 before data is written to the nonvolatile semiconductor memory element is a value that can be said to be an indefinite state, and is not shown. In order to facilitate understanding, it is assumed here that VT0 is in the vicinity of the sense level SL. The same elements as those in FIG. 2 are given the same symbols.

  First, the first nonvolatile semiconductor memory element completed through the manufacturing process is subjected to heat treatment by a heat treatment process.

  In the nonvolatile semiconductor memory element, the thermal equilibrium state is the most stable state (the threshold voltage at this time is the thermal equilibrium threshold voltage). As already explained, when data is written to the nonvolatile semiconductor memory element, even if it is at room temperature, the thermal energy is obtained and electrons and holes escape from the charge storage film over time. Since higher thermal energy can be applied, the thermal equilibrium state threshold voltage can be converged in a shorter time than normal temperature.

For example, after writing data, if it is left at room temperature for about 10 years, the charge is released and the threshold value changes to the thermal equilibrium state threshold voltage. The threshold voltage changes from the several hours to several tens of hours to the thermal equilibrium threshold voltage.
Although not particularly limited, heat treatment performed for data writing is performed at 300 ° C. for about 20 hours.

  By performing the data writing operation by such heat treatment, the threshold voltage VT0 before writing the data of the first nonvolatile semiconductor memory element is set to VT1, and the data before the data of the second nonvolatile semiconductor memory element is written. The threshold voltage VT0 changes to VT2.

  Assuming that the time for performing the heat treatment is time T5, at this time, as shown in FIG. 3A, the threshold voltage VT1 of the first nonvolatile semiconductor memory element is equal to the sense level SL and the thermal equilibrium state threshold value. It is between the voltage V01. Similarly, the threshold voltage VT2 of the second nonvolatile semiconductor memory element is between the sense level SL and the thermal equilibrium state threshold voltage V02.

  In the example shown in FIG. 3A, the threshold voltage VT1 immediately after storing the positive data is slightly positive with respect to the sense level SL. It further changes in the positive direction with respect to the value, and eventually becomes VT1 = V01 at time T6, and does not become negative with respect to the sense level SL even if time passes thereafter.

  Similarly, in the example shown in FIG. 3B, the threshold voltage VT2 immediately after storing the negative data is slightly negative with respect to the sense level SL. The value further changes in the negative direction with respect to the value immediately after, and eventually becomes VT2 = V02 at time T6, and does not become negative with respect to the sense level SL even if the time thereafter passes.

  As already described, with the passage of time, charges gradually escape from the charge storage film of the nonvolatile semiconductor memory element and change to a stable thermal equilibrium state threshold voltage. In the example shown in FIG. This is because the charge remaining in the charge storage film after data writing is also released with the passage of time thereafter, and the charge storage film is depleted of charge so that a stable state is achieved.

The threshold value varies depending on the strength of data writing. In this case, the strength is the temperature and time of heat treatment.
The first nonvolatile semiconductor memory element is manufactured such that its thermal equilibrium threshold voltage V01 is in the positive direction with respect to the sense level SL, and the second nonvolatile semiconductor memory element has its thermal equilibrium threshold. Since the value voltage V02 is manufactured so as to be in a negative direction with respect to the sense level SL, by selecting the strength of writing, the two nonvolatile semiconductor memory elements are simultaneously subjected to heat treatment, so that after data writing The threshold voltages VT1 and VT2 at (time T5) can be set to the same values as the respective thermal equilibrium state threshold voltages V01 and V02 which are in an energy stable state.

However, it does not make much sense to set the threshold voltage value after data writing to the same value as the thermal equilibrium state threshold voltage value. As described above, what is important is that the process is performed in the positive direction or the negative direction even slightly from the sense level SL.

Here, the characteristics of the nonvolatile semiconductor memory device of the present invention are summarized as follows.
The nonvolatile semiconductor memory device according to the present invention includes a first nonvolatile semiconductor memory element having a thermal equilibrium state threshold voltage in a positive direction with respect to a predetermined sense level and a second nonvolatile semiconductor memory element having a negative direction. This is mixed and used.
Based on the contents of the data to be stored, the threshold value changes over time by writing positive data to the first nonvolatile semiconductor memory element and writing negative data to the second nonvolatile semiconductor memory element. Even so, the threshold value eventually becomes the threshold value in the thermal equilibrium state, so that the written data will not disappear. Therefore, the data retention time can be infinite.

  When the nonvolatile semiconductor memory element is an N-type semiconductor transistor element, the state in which electrons are accumulated in the charge storage film of the nonvolatile semiconductor memory element is a state in which positive data is written, and the state in which holes are accumulated is negative data. Will be written.

  The speed at which electrons escape from the charge storage film over time and the speed at which holes escape, that is, the speed at which the threshold voltage changes when positive data is written and the threshold voltage when negative data is written It is different from the changing speed.

  Therefore, in the conventional technology, the value of the sense level must be strictly selected in order to maximize the data retention time. For this purpose, a nonvolatile semiconductor memory element is actually created and verified individually each time. Had to do. This is to cope with manufacturing variations of elements.

  On the other hand, in the nonvolatile semiconductor memory device of the present invention, the data retention time becomes infinite simply by making the thermal equilibrium state threshold voltage positive or negative with respect to a predetermined sense level. There is no need to set the sense level strictly in view of the speed at which the threshold voltage changes. Of course, there is no need to perform verification work for determining the sense level for each semiconductor transistor element that has been manufactured, and it is possible to shorten the manufacturing process of the nonvolatile semiconductor memory device, thereby reducing the manufacturing time and reducing the cost. Can be achieved.

[Description of Arrangement of Nonvolatile Semiconductor Memory Element of the Invention: FIG. 4]
Next, how the first nonvolatile semiconductor memory element and the second nonvolatile semiconductor memory element are arranged in the memory area for data to be written will be described with reference to FIG.

  FIG. 4 is a diagram schematically showing the arrangement in the memory area. In FIG. 4, 10 is a memory area, and 11 is a data string to be written.

  As shown in FIG. 4A, the memory area 10 is composed of, for example, eight nonvolatile semiconductor memory elements having addresses A1 to A8. Assume that one nonvolatile semiconductor memory element stores 1-bit data. Data reading is performed in the order of A1 to A8.

  FIG. 4B shows a data string 11 to be written. For example, if the case of positive data is “1” and the case of negative data is “0”, the content has a data structure of 8 bits “10111010”.

  FIG. 4C shows the arrangement of the first nonvolatile semiconductor memory element and the second nonvolatile semiconductor memory element in the memory region 10. M1 is a first nonvolatile semiconductor memory element, and M2 is a second nonvolatile semiconductor memory element.

  As already described, data is read in the order of A1 to A8. This eliminates the need for an address selection circuit that performs a complicated operation of selecting arbitrary addresses in order.

  Meanwhile, some known address selection circuits can select an arbitrary address and write data when writing data. In short, in the example of FIG. 4, addressing can be performed in any order within the addresses A1 to A8.

  In such an address selection circuit, as a matter of course, it is necessary to permanently hold address information indicating the order in which data is written in the nonvolatile semiconductor memory element in the memory area. If this is lost, correct addressing cannot be performed and data cannot be read out.

  However, the address information held in such an address selection circuit must also hold the information for the same period as the nonvolatile semiconductor memory element that stores data in the memory area. For this reason, as in the nonvolatile semiconductor memory device of the present invention, an address selection circuit for a nonvolatile semiconductor memory element having an infinite data retention time that can select an arbitrary address and write data is used. I can't.

  Therefore, in the nonvolatile semiconductor memory of the present invention, the nonvolatile semiconductor memory elements are arranged in accordance with the data string when data is written so that data is read in the order of A1 to A8.

  That is, according to the data string “10111010” shown in FIG. 4B, as shown in FIG. 4C, the addresses A1, A3, A4, A5, and A7 to which the data “1” is written are first non-volatile. A second non-volatile semiconductor memory element M2 is arranged in the memory area 10 at addresses A2, A6, and A8 where the data “0” is to be written in the semiconductor memory element M1.

  The first nonvolatile semiconductor memory element and the second nonvolatile semiconductor memory element have different structures because the thermal equilibrium state threshold voltage is changed. Therefore, in the nonvolatile semiconductor memory device of the present invention, the first nonvolatile semiconductor memory element and the second nonvolatile semiconductor memory element are arranged corresponding to the data string to be written in the manufacturing process, like the mask ROM. It is.

  Specifically, how the thermal equilibrium state threshold voltage is changed depends on the mask pattern for forming the channel region of the semiconductor transistor element constituting the nonvolatile semiconductor memory element. Make it separately. About this, since a manufacturing method is mentioned later, please refer to it.

[Description of data writing and rewriting flow: FIG. 5]
Next, the flow of data writing and rewriting to the nonvolatile semiconductor memory device will be described with reference to FIG.

  As shown in FIG. 5, in the nonvolatile semiconductor memory device, first, the nonvolatile semiconductor memory element to be selected differs depending on whether the data to be written to each address in the memory area is positive data or negative data (step (1)).

  If the data to be stored is positive data, the first nonvolatile semiconductor memory element is selected (step (2-a)). If the data to be stored is negative data, the second nonvolatile semiconductor memory element is selected. Is selected (step (2-b)).

Next, data is written (step (3-a), step (3-b)).
As described above, in addition to the conventional voltage writing method, the nonvolatile semiconductor memory device of the present invention can write positive data and negative data by heating to a high temperature. It is also possible to perform data writing in a batch.
The data holding time of the data written here is infinite like the mask ROM, and the data will not disappear.

  Next, when it is necessary to rewrite data (step (4-a), step (4-b)), it is possible to rewrite data in the same manner as a conventional EEPROM by applying a voltage (step (5-a). ), Step (5-b)).

  In the case where it is necessary to rewrite the data, this is a response to an unexpected situation where the data once written must be rewritten. This will be described later with reference to FIG.

  The above is the concept and characteristics of the nonvolatile semiconductor memory device of the present invention, and the writing and rewriting procedures. Hereinafter, the structure of the nonvolatile semiconductor memory device and the manufacturing method and rewriting method thereof will be described in detail. In the description, an N-type MONOS type EEPROM is used.

[Description of Structure of Embodiment of the Present Invention: FIG. 6]
The structure of the nonvolatile semiconductor memory device will be described in detail with reference to FIG.
FIG. 6 is a cross-sectional view schematically showing the configuration of the nonvolatile semiconductor memory device.

In FIG. 6, reference numeral 100 denotes a first nonvolatile semiconductor memory element, which is composed of a gate electrode 110, a memory gate insulating film 120, a channel region 130, a source region 160, a common region 170, and a semiconductor substrate 400. It is an element.
Reference numeral 101 denotes an address transistor for selecting the first nonvolatile semiconductor memory element 100, which is a MOS transistor element constituted by the gate electrode 140, the gate insulating film 150, the common region 170, the drain region 300, and the semiconductor substrate 400.

Reference numeral 200 denotes a second nonvolatile semiconductor memory element, which is a MONOS type semiconductor transistor element constituted by a gate electrode 210, a memory gate insulating film 220, a channel region 230, a source region 260, a common region 270, and a semiconductor substrate 400.
Reference numeral 201 denotes an address transistor for selecting the second nonvolatile semiconductor memory element 200, which is a MOS transistor element constituted by the gate electrode 240, the gate insulating film 250, the common region 270, the drain region 300, and the semiconductor substrate 400.

The first nonvolatile semiconductor memory element 100 and the address transistor 101 constitute a 1-bit memory, and the second nonvolatile semiconductor memory element 200 and the address transistor 201 constitute a 1-bit memory.
In the following description, it is assumed that the first and second nonvolatile semiconductor memory elements are memories that store binary information of “1” or “0”, respectively.

110, 140, 210 and 240 are gate electrodes, 120 and 220 are memory gate insulating films, 150 and 250 are gate insulating films, 130 and 230 are channel regions, 160 and 260 are source regions, and 170 and 270 are nonvolatile semiconductor memories. A common region serving as both the drain region of the elements 100 and 200 and the source region of the address transistors 101 and 201, 300 is a drain region, and 400 is a semiconductor substrate.

The memory gate insulating film 120 includes a top oxide film 121, a memory nitride film 122, and a tunnel oxide film 123. The memory gate insulating film 220 includes a top oxide film 221, a memory nitride film 222, and a tunnel oxide film 223.
These two memory gate insulating films have a so-called ONO film structure in which an oxide film, a nitride film, and an oxide film are sequentially stacked, and are one of the features of the MONOS type EEPROM.

  For example, the semiconductor substrate 400 can be a P-type silicon semiconductor substrate. The source regions 160 and 260, the common regions 170 and 270, and the drain region 300 are N-type diffusion regions. The channel regions 130 and 230 are P-type diffusion regions having an impurity concentration different from that of the semiconductor substrate 400.

  G11 is a terminal connected to the gate electrode 110, G21 is a terminal connected to the gate electrode 210, G14 is a terminal connected to the gate electrode 140, G24 is a terminal connected to the gate electrode 240, S16 is a terminal connected to the source region 160, S26 is a terminal connected to the source region 260, and D30 is a terminal connected to the drain region 300.

[Description of Data Reading Operation of Embodiment of the Present Invention: FIG. 6]
Next, the operation of reading data stored in the nonvolatile semiconductor memory device of this embodiment will be described with reference to FIG.

First, a read operation of the first nonvolatile semiconductor memory element 100 will be described.
By applying a voltage V14 higher than the threshold voltage of the address transistor 101 to the terminal G14, a channel is formed between the common region 170 and the drain region 300 (the address transistor 101 is turned on), and the first non-volatile property The semiconductor memory element 100 is selected. The voltage V14 is 1V, for example.

When the voltage V16 is applied to the terminal S16 and the voltage V11 is applied to the terminal G11, positive data is stored in the first nonvolatile semiconductor memory element 100, that is, the threshold voltage of the first nonvolatile semiconductor memory element 100. Is more positive than the voltage V11, no channel is formed in the channel region 130.
Therefore, it can be determined that no current flows between the terminal S16 and the terminal D30, and positive data is stored in the first nonvolatile semiconductor memory element 100.
The voltage V16 and the voltage V11 are, for example, 2V and 1V, respectively.

Here, the first nonvolatile semiconductor memory element 100 stores positive data by adjusting the impurity concentration of the channel region 130 and setting the thermal equilibrium state threshold voltage in the positive direction with respect to the voltage V11.
Alternatively, positive data may be stored by accumulating electrons in the memory nitride film 122 after setting the thermal equilibrium state threshold voltage in the positive direction with respect to the voltage V11.

  The threshold voltage of the memory element converges to the thermal equilibrium threshold voltage over time, but the thermal equilibrium threshold voltage of the first nonvolatile semiconductor memory element 100 is more positive than the voltage V11. Positive data never disappears.

Subsequently, a read operation of the second nonvolatile semiconductor memory element 200 will be described.
By applying a voltage V14 higher than the threshold voltage of the address transistor 201 to the terminal G24, a channel is formed between the common region 270 and the drain region 300 (the address transistor 201 is turned on), and the second nonvolatile property The semiconductor memory element 200 is selected. The voltage V14 at this time is the same as the voltage during the read operation of the first nonvolatile semiconductor memory element 100, and is 1 V, for example.

When the voltage V16 is applied to the terminal S26 and the voltage V11 is applied to the terminal G21, negative data is stored in the second nonvolatile semiconductor memory element 200, that is, the threshold voltage of the second nonvolatile semiconductor memory element 200. Is in the negative direction from the voltage V11, a channel is formed in the channel region 230.
Therefore, it can be determined that a current flows between the terminal S26 and the terminal D30 and negative data is stored in the second nonvolatile semiconductor memory element 200.
The voltage V16 and the voltage V11 at this time are, for example, 2V and 1V, respectively.

Here, the second nonvolatile semiconductor memory element 200 stores negative data by adjusting the impurity concentration of the channel region 230 and setting the thermal equilibrium state threshold voltage in a negative direction with respect to the voltage V11.
Alternatively, negative data may be stored by accumulating holes in the memory nitride film 222 after making the thermal equilibrium state threshold voltage in a negative direction with respect to the voltage V11.

  The threshold voltage of the memory element converges to the thermal equilibrium threshold voltage over time, but the thermal equilibrium threshold voltage of the second nonvolatile semiconductor memory element 200 is in a negative direction with respect to the voltage V11. Negative data never disappears.

  As described above, positive data is stored in the first nonvolatile semiconductor memory element 100 whose thermal equilibrium state threshold voltage is more positive than the voltage V11, and the second value whose thermal equilibrium state threshold voltage is more negative than the voltage V11 is stored. By storing negative data in the nonvolatile semiconductor memory element 200, the nonvolatile semiconductor memory device of this embodiment can make the stored data retention time infinite.

[Description of Manufacturing Method of Embodiment of the Present Invention: FIGS. 6 and 7 to 11]
Next, a method for manufacturing the nonvolatile semiconductor memory device of this embodiment will be described with reference to FIGS. 6 and 7 to 11. Since the same number is given to the same configuration as already described, the description is omitted.

  Here, the well formation by the known ion implantation method and thermal diffusion and the formation of the field oxide film and the active region by the LOCOS separation method are well-known techniques, so that the description thereof is omitted, and the formation is then performed in the active region. A method for manufacturing the first and second nonvolatile semiconductor memory elements and the address transistor will be described.

First, as shown in FIG. 7, a dummy oxide film 500 is formed on the surface of the semiconductor substrate 400 using a dummy oxide film forming process. Here, the dummy oxide film forming step is, for example, a thermal oxidation step in an atmosphere in which oxygen (O ₂ ) and nitrogen (N ₂ ) are mixed.

Next, a photoresist 601 is formed on the dummy oxide film 500 by using a known photolithography technique.
The photoresist 601 is formed in a shape excluding the region where the channel region 130 is formed.

Next, predetermined impurity ions are ion-implanted from above the semiconductor substrate 400 by a known ion implantation method. Since the photoresist 601 has an opening at a portion where the channel region 130 is formed, impurity ions are introduced into the semiconductor substrate 400 at this portion to form an impurity layer 130 ′.
This impurity layer 130 ′ is diffused into the semiconductor substrate 400 by heat application when forming a later-described top oxide film 121 and becomes a channel region 130.
Thereafter, the photoresist 601 is removed by a known wet etching technique.

  The thermal equilibrium state threshold voltage of the first nonvolatile semiconductor memory element 100 is determined by the implantation amount by the ion implantation method here. Therefore, the thermal equilibrium state threshold voltage of the first nonvolatile semiconductor memory element 100 is more positive than the voltage V11 applied to the terminal G11 shown in FIG. 6 in the read operation of the nonvolatile semiconductor memory device of this embodiment. Thus, the implantation amount of the ion implantation method is set.

The amount of ion implantation cannot be generally determined because it depends on the impurity concentration of the semiconductor substrate 400 and the size of the first nonvolatile semiconductor memory element 100. For example, phosphorus, which is an N-type impurity, is 1 × 10 ^12. Ions are implanted at a dose of (ions / cm ² ).

Next, as shown in FIG. 8, a photoresist 602 is formed on the dummy oxide film 500 by using a known photolithography technique.
The photoresist 602 is formed in a shape excluding the region where the channel region 230 is formed.

Next, an impurity layer 230 ′ to be a channel region 230 is formed through a subsequent process by a manufacturing method similar to the formation of the impurity layer 130 ′ of the first nonvolatile semiconductor memory element 100 described above with reference to FIG. 7. To do.
After the formation of the impurity layer 230 ', the photoresist 602 is removed by a known wet etching technique.

  The thermal equilibrium state threshold voltage of the second nonvolatile semiconductor memory element 200 is determined by the implantation amount by the ion implantation method here. Therefore, the thermal equilibrium state threshold voltage of the second nonvolatile semiconductor memory element 200 is more negative than the voltage V11 applied to the terminal G21 shown in FIG. 6 in the read operation of the nonvolatile semiconductor memory device of this embodiment. Thus, the implantation amount of the ion implantation method is set.

The amount of ion implantation at this time cannot be determined in the same way as when the impurity layer 130 ′ is formed. For example, phosphorus, which is an N-type impurity, is dosed by 5 × 10 ¹² (ions / cm ² ). Ion implantation.

  Next, as shown in FIG. 9, after the dummy oxide film 500 is removed by a known wet etching technique, an ONO film to be the memory gate insulating films 120 and 220 is formed. An example of the procedure is as follows.

First, a tunnel oxide film 723 is formed on the surface of the semiconductor substrate 400 using a tunnel oxide film formation step. The tunnel oxide film forming step uses a known oxidation method. For example, it is formed by thermal oxidation in an atmosphere in which oxygen (O ₂ ) and nitrogen (N ₂ ) are mixed.

Next, a memory nitride film 722 is formed in an upper layer portion of the tunnel oxide film 723 by a memory nitride film formation step. In this step, for example, it is formed by a CVD method using dichlorosilane (SiH ₂ Cl ₂ ) and ammonia (NH ₃ ) as a reaction gas.

Next, a top oxide film 721 is formed in an upper layer portion of the memory nitride film 722 by a top oxide film forming step. This step is formed, for example, by thermal oxidation in a steam atmosphere using an oxidation diffusion furnace.
Using this thermal oxidation, the impurity layers 130 ′ and 230 ′ shown in FIG. 8 are activated and diffused in the semiconductor substrate 400 to form channel regions 130 and 230.

  Note that when the top oxide film 721 is formed without thermal oxidation (for example, when an oxide film is formed by a CVD method), the channel regions 130 and 230 are formed using a separate heat treatment process.

Next, as shown in FIG. 10, a photoresist 603 is formed on the top oxide film 721 using a known photolithography technique.
Here, the region where the photoresist 603 is formed is a region where the channel region 130 and the channel region 230 are formed.
Next, using the photoresist 603 formed on the top oxide film 721 as a mask, the top oxide film 721, the memory nitride film 722, and the tunnel oxide film 723 are removed using a dry etching technique, and the channel regions 130 and 230 are formed. Leave the ONO film only on the top.

By this step, the ONO film has a predetermined shape as described above. Therefore, the top oxide film 721 remaining on the channel region 130 is the top oxide film 121, the memory nitride film 722 is the memory nitride film 122, and the tunnel oxide film 723. Is referred to as a tunnel oxide film 123.
The top oxide film 721 remaining on the channel region 230 is referred to as a top oxide film 221, the memory nitride film 722 is referred to as a memory nitride film 222, and the tunnel oxide film 723 is referred to as a tunnel oxide film 223.
Thereafter, the photoresist 603 is removed by a known wet etching technique.

Next, the process of forming a gate electrode is demonstrated using FIG.
First, although not shown, an oxide film for forming the gate insulating film 150 and the gate insulating film 250 is formed on the entire upper surface of the semiconductor substrate 400 using a gate insulating film forming step. The gate insulating film forming step is, for example, a thermal oxidation step in an atmosphere in which oxygen (O ₂ ) and nitrogen (N ₂ ) are mixed.
Subsequently, a polysilicon film for forming the gate electrode 110, the gate electrode 140, the gate electrode 210, and the gate electrode 240 is formed on the entire upper surface of the gate insulating film by using a CVD method. In this step, for example, monosilane (SiH ₄ ) is used as a reaction gas.

Thereafter, as shown in FIG. 11, a photoresist 604 is formed by using a known photolithography technique in a portion where the gate electrode 110, the gate electrode 140, the gate electrode 210, and the gate electrode 240 are to be formed, and this is used as a mask. The polysilicon film and the oxide film are removed using a dry etching technique.
By this step, the gate electrode 110 is formed on the top oxide film 121, the gate electrode 210 is formed on the top oxide film 221, the gate electrode 140 is formed on the gate insulating film 150, and the gate electrode 240 is formed on the gate insulating film 250. Are formed respectively.
Thereafter, the photoresist 604 is removed by a known wet etching technique.

Next, although not shown, the source region 160, the source region 260, the common region 170, the common region 270, and the drain region 300 are formed by a known ion implantation process and a thermal diffusion process of the impurity layer. A structure that forms the basis of the nonvolatile semiconductor memory device as shown in FIG.
Thereafter, using a known technique, an interlayer insulating film (not shown), various wirings and the like are formed to complete the structure of the semiconductor device having the nonvolatile semiconductor memory device.

[Description of Data Writing Process: FIGS. 2, 3, 6, and 12]
Next, how data is written in the nonvolatile semiconductor memory device having the completed structure will be described mainly with reference to FIGS. 6 and 12 and with reference to FIGS. In this example, a method of performing heat treatment and a method of writing data electrically will be described together.

  FIG. 12 is an explanatory diagram illustrating transistor characteristics of the nonvolatile semiconductor memory element. The horizontal axis represents the voltage (gate voltage) applied to the gate electrode of the nonvolatile semiconductor memory element, and the vertical axis represents the current (drain current) flowing between the source region and the drain region of the nonvolatile semiconductor memory element.

  In FIG. 12, VT0 is a threshold voltage before data writing, VT11 and VT22 are threshold voltages after data writing of the first and second nonvolatile semiconductor memory elements, and V01 and V02 are first and second voltages, respectively. The thermal equilibrium state threshold voltage SL of the nonvolatile semiconductor memory element 2 is a sense level.

  FIG. 12A is a diagram for explaining the first nonvolatile semiconductor memory element in which the thermal equilibrium state threshold voltage is in the positive direction with respect to a predetermined sense level, and FIG. It is a figure explaining the 2nd non-volatile semiconductor memory element whose thermal equilibrium state threshold voltage is a negative direction with respect to a level.

First, the first nonvolatile semiconductor memory element will be described.
As shown in FIG. 12A, it is assumed that the threshold voltage VT0 before data writing is in the vicinity of the sense level SL, although it is indeterminate whether it is positive data or negative data. Actually, it is not necessarily exactly near the sense level as shown in this figure, but is described in this way for the sake of easy understanding of the drawing.

Here, by performing a process of writing data to the first nonvolatile semiconductor memory element, the threshold value becomes the threshold voltage VT11 after data writing. This is indicated by a dotted arrow a in the figure.
As the step of writing data, for example, a heat treatment in which heating at 300 ° C. is performed for about 20 hours is used.

The threshold voltage VT0 before data writing converges to the thermal equilibrium state threshold voltage V01 as time elapses, but until it converges to the thermal equilibrium state threshold voltage V01 by heating to a high temperature as described above. Can be shortened.
By performing the above-described heat treatment, the threshold voltage VT11 after data writing of the first nonvolatile semiconductor memory element in which the thermal equilibrium state threshold voltage is in the positive direction with respect to the sense level SL is set to be higher than the sense level SL. Shifting in the positive direction, positive data is written.

  The state of FIG. 12A can be easily understood with reference to FIG. The threshold voltage VT1 after data writing shown in FIG. 3A eventually converges to the thermal equilibrium state threshold voltage V01 as time passes. Similarly, the threshold after data writing shown in FIG. The value voltage VT11 converges to the thermal equilibrium state threshold voltage V01 as time passes, as indicated by a dotted arrow b in the figure.

Alternatively, data may be written electrically by applying a voltage instead of performing heat treatment.
In FIG. 6, the threshold voltage of the first nonvolatile semiconductor memory element 100 is applied to the semiconductor substrate 400 and the terminal G11 so that the potential of the terminal G11 is in the positive direction with respect to the potential of the semiconductor substrate 400. As a result, electrons are accumulated in the memory nitride film 122 and become a positive value with respect to the sense level. Therefore, positive data is written.

  Here, the applied voltage is, for example, 0 V for the semiconductor substrate 400 and 8 V for the terminal G11. The time for applying this voltage is 1 ms.

  Considering the case of such electrical data writing in correspondence with FIG. 2A, although not shown, in FIG. 12A, the threshold voltage VT11 after data writing is in a thermal equilibrium state. It is on the right side in the figure with respect to the threshold voltage V01, shifts to the left in the figure as time passes, and eventually converges to the threshold voltage V01.

Next, the second nonvolatile semiconductor memory element will be described.
As shown in FIG. 12B, it is assumed that the threshold voltage VT0 before data writing is in the vicinity of the sense level SL as in the first nonvolatile semiconductor memory element.

Here, by performing the process of writing data to the second nonvolatile semiconductor memory element, the threshold value becomes the threshold voltage VT22 after data writing. This is indicated by a dotted arrow c in the figure.
As the step of writing data, for example, since the batch processing with the first nonvolatile semiconductor memory element is possible, heating at 300 ° C. is performed for about 20 hours.

  By performing the heat treatment described above, the threshold voltage VT22 after data writing in the second nonvolatile semiconductor memory element in which the thermal equilibrium state threshold voltage is in the negative direction with respect to the sense level SL is higher than the sense level SL. Shifts in the negative direction and negative data is written.

  The state of FIG. 12B can be easily understood with reference to FIG. The threshold voltage VT2 after the data writing shown in FIG. 3B eventually converges to the thermal equilibrium state threshold voltage V02 as time passes. Similarly, the threshold after the data writing shown in FIG. The value voltage VT22 converges to the thermal equilibrium state threshold voltage V02 as time passes, as indicated by a dotted arrow d in the figure.

Further, data may be written by applying a voltage instead of performing heat treatment in the same manner as the first nonvolatile semiconductor memory element.
In FIG. 6, the threshold voltage of the second nonvolatile semiconductor memory element 200 is applied to the semiconductor substrate 400 and the terminal G21 so that the potential of the terminal G21 is negative with respect to the potential of the semiconductor substrate 400. As a result, holes are accumulated in the memory nitride film 222 and become a negative value with respect to the sense level. Therefore, negative data is written.

  Here, the applied voltage is, for example, 0 V for the semiconductor substrate 400 and −8 V for the terminal G21. The time for applying this voltage is 200 ms.

  Considering such a case of writing electric data in correspondence with FIG. 2B, although not shown, in FIG. 12B, the threshold voltage VT22 after data writing is in a thermal equilibrium state. It is on the left side in the figure with respect to the threshold voltage V02, shifts to the right in the figure with time, and eventually converges to the threshold voltage V02.

Here, in the conventional technique, data written by applying a voltage disappears in the process in which the threshold voltage of the nonvolatile semiconductor memory element converges to the thermal equilibrium threshold voltage over time. .
Therefore, in order to extend the lifetime until the data disappears as much as possible, the potential difference between the semiconductor substrate and the gate electrode is increased, or the time for applying the voltage is increased to accumulate as much charge as possible. There is a need.

  However, in that case, in order to increase the potential difference between the semiconductor substrate and the gate electrode, it is necessary to increase the breakdown voltage of the nonvolatile semiconductor memory element itself and the peripheral circuit, which is a factor that hinders miniaturization of the nonvolatile semiconductor memory device. Become. Further, if the time for applying the voltage is lengthened, the manufacturing process of the nonvolatile semiconductor memory device is made redundant.

In contrast, in the nonvolatile semiconductor memory device of the present invention, the data written in the process in which the threshold voltage VT11 after the data writing in FIG. 12A converges to the thermal equilibrium threshold voltage V01 as time elapses. Will never disappear.
Similarly, in the process in which the threshold voltage VT22 after data writing in FIG. 12B converges to the thermal equilibrium state threshold voltage V02, the written data does not disappear.

  Therefore, it is only necessary that the threshold voltage VT11 after data writing is in the positive direction with respect to the sense level SL and the threshold voltage VT22 after data writing is in the negative direction with respect to the sense level SL. It is possible to reduce the voltage applied for writing and to shorten the application time.

[Description of Data Rewriting Method of Embodiment of the Present Invention: FIGS. 6 and 13]
Next, the case of rewriting data in the nonvolatile semiconductor memory device of this embodiment will be described with reference to FIGS.

In the nonvolatile semiconductor memory device of the present invention, the retention time of the written data becomes infinite as in the mask ROM. However, there is a case where data must be rewritten after data is written once.
For example, when the stored data is a system program for controlling the system, the system program needs to be changed. In addition, when the stored data is user-specific data, the user has changed or the information input by the user has been changed.

Changing the system program is an unforeseen event, but depending on the use of the nonvolatile semiconductor memory device of the present invention, it is more convenient to be able to respond to user-specific data changes. Will.
In the case of the mask ROM, since such data rewriting is not possible at all, there was only a countermeasure such as replacing the nonvolatile semiconductor memory device, but the nonvolatile semiconductor memory device of the present invention can cope with such a situation. Is possible. This will be described below.

  FIG. 13 is an explanatory diagram illustrating transistor characteristics of the nonvolatile semiconductor memory element. The horizontal axis represents the voltage (gate voltage) applied to the gate electrode of the nonvolatile semiconductor memory element, and the vertical axis represents the current (drain current) flowing between the source region and the drain region of the nonvolatile semiconductor memory element.

  In FIG. 13, VT11 and VT22 are threshold voltages after data writing in the first and second nonvolatile semiconductor memory elements, respectively, and VT12 and VT21 are after data rewriting in the first and second nonvolatile semiconductor memory elements, respectively. , V01 and V02 are thermal equilibrium threshold voltages of the first and second nonvolatile semiconductor memory elements, respectively, and SL is a sense level.

FIG. 13A is a diagram for explaining the first nonvolatile semiconductor memory element in which the thermal equilibrium state threshold voltage is in the positive direction with respect to a predetermined sense level, and FIG. 13B is a diagram illustrating the predetermined sense level. It is a figure explaining the 2nd non-volatile semiconductor memory element whose thermal equilibrium state threshold voltage is a negative direction with respect to a level.

First, the first nonvolatile semiconductor memory element will be described.
As shown in FIG. 13A, the threshold voltage VT11 after data writing is in the positive direction with respect to the sense level SL, and is in a state where positive data is written.

  Here, by rewriting data in the first nonvolatile semiconductor memory element, the threshold value becomes the threshold voltage VT12 after data rewriting. This is indicated by a dotted arrow e in the figure.

As a data rewriting method, for example, in FIG. 6, a voltage is applied to the semiconductor substrate 400 and the terminal G11 so that the potential of the terminal G11 is negative with respect to the potential of the semiconductor substrate 400, and the memory nitride film 122 is applied. Accumulate holes.
Accordingly, in FIG. 13A, the threshold voltage VT12 after data rewriting has a value in the negative direction with respect to the sense level SL. Therefore, negative data is written.

  Here, the applied voltage is, for example, 0 V for the semiconductor substrate 400 and −9 V for the terminal G11. The time for applying this voltage is 500 ms.

Next, the second nonvolatile semiconductor memory element will be described.
As shown in FIG. 13B, the threshold voltage VT22 after data writing is in the negative direction with respect to the sense level SL, and negative data is being written.

  Here, by rewriting data in the second nonvolatile semiconductor memory element, the threshold value becomes the threshold voltage VT21 after data rewriting. This is indicated by dotted arrows g in the figure.

As a data rewriting method, for example, in FIG. 6, a voltage is applied to the semiconductor substrate 400 and the terminal G11 so that the potential of the terminal G21 is positive with respect to the potential of the semiconductor substrate 400, and the memory nitride film 222 is applied. Accumulate electrons.
Accordingly, in FIG. 13B, the threshold voltage VT21 after data rewriting has a value in the positive direction with respect to the sense level SL. Therefore, positive data is written.

  Here, the applied voltage is, for example, 0 V for the semiconductor substrate 400 and 9 V for the terminal G21. The time for applying this voltage is 10 ms.

  That is, in the conventional technique, the data in the mask ROM that does not disappear cannot be rewritten, whereas the nonvolatile semiconductor memory device of the present invention can be electrically rewritten in the same manner as the EEPROM.

However, when the data rewriting described with reference to FIG. 13 is performed, the data retention does not become infinite.
As shown in FIG. 13A, in the first nonvolatile semiconductor memory element, the threshold voltage after data rewriting is VT12. However, the charge accumulated in the charge accumulation film is released over time. Then, as indicated by the dotted arrow f in the figure, it eventually converges to the thermal equilibrium state threshold voltage V01.
Similarly, in the second nonvolatile semiconductor memory element as shown in FIG. 13B, the threshold voltage VT21 after data rewrite is also in thermal equilibrium with the passage of time as shown by the dotted arrow h in the figure. It converges to the state threshold voltage V02.

  For example, assuming that the data retention period of the first and second nonvolatile semiconductor memory elements is 10 years equivalent to that of the conventionally known nonvolatile semiconductor memory elements, the data retention period is 10 years when data rewriting is performed. And become a finite value.

  However, if the data is not rewritten, the data retention period is infinite, which is equivalent to that of the mask ROM. In addition, the merit of being able to rewrite data that could not be supported at all by the mask ROM is very great. Therefore, it can be said that the feature that the data can be rewritten when this unexpected situation occurs is also an excellent point of the present invention.

The embodiment has been described above.
In the example described above, the case where one first nonvolatile semiconductor memory element and one second nonvolatile semiconductor memory element are mixedly mounted has been described. However, the present invention is not limited to this.
A multi-bit nonvolatile semiconductor memory device that uses a plurality of first nonvolatile semiconductor memory elements and a plurality of second nonvolatile semiconductor memory elements, respectively, may be configured.

The nonvolatile semiconductor memory device of the present invention has an infinite lifetime for data stored at the beginning, and also has a data rewriting function, and thus can be widely used for computer devices, electronic devices, and other various devices.
Further, it is possible to improve the reliability of the nonvolatile semiconductor memory device and shorten the development period.

VT1, VT2 Threshold voltage VT0 Threshold voltage before data writing VT11, VT22 Threshold voltage after data writing VT12, VT21 Threshold voltage after data rewriting V01, V02 Thermal equilibrium threshold voltage SL Sense level DESCRIPTION OF SYMBOLS 10 Memory area 11 Data string to write A1-A8 Address M1 1st non-volatile semiconductor memory element M2 2nd non-volatile semiconductor memory element FT Load transistor MT Non-volatile semiconductor memory element OUT Output terminal VDD High potential in the positive direction Power supply having VSS Power supply having a high potential in the negative direction 100 First nonvolatile semiconductor memory element 200 Second nonvolatile semiconductor memory element 101, 201 Address transistor 110, 140, 210, 240 Gate electrode 120, 220 Memory gate insulating film 15 , 250 Gate insulating film 121, 221, 721 Top oxide film 122, 222, 722 Memory nitride film 123, 223, 723 Tunnel oxide film 130, 230 Channel region 160, 260 Source region 170, 270 Common region 300 Drain region 400 Semiconductor substrate 500 Dummy oxide film 601, 602, 603, 604 Photoresist G11 Terminal connected to gate 110 G14 Terminal connected to gate 140 S16 Terminal connected to source 160 G21 Terminal connected to gate 210 G24 Terminal connected to gate 240 S26 Source 260 Terminal D30 Terminal 911, 912 Sample cell 920 Average voltage output circuit 930 Select signal 931 Switch 932 Memory cell 933 Read line 9 0 the output voltage of the threshold voltage Vo average voltage output circuit 920 of the threshold voltage Ve sample cell 912 of the gate electrode Vw sample cell 911 of the memory cell 932

Claims (5)

In a nonvolatile semiconductor memory device having a plurality of nonvolatile semiconductor memory elements that store data and can be rewritten,
The voltage value of the output terminal generated by an inquiry of current between the nonvolatile semiconductor memory element operating by being connected to the power supply VSS and the load transistor operating by being connected to the power supply VDD having a higher potential on the positive side than the power supply VSS but the voltage level of the threshold when switching between the potential direction of the power supply VDD potential direction as the power supply VSS, and set the sense level of the non-volatile semiconductor memory device,
Among the plurality of nonvolatile semiconductor memory elements, a first nonvolatile semiconductor memory element whose thermal equilibrium threshold voltage is in the potential direction of the power supply VDD with respect to the sense level, and a thermal equilibrium threshold voltage is the sense A non-volatile semiconductor memory device comprising a second non-volatile semiconductor memory element that is in a potential direction of the power supply VSS with respect to a level . The nonvolatile semiconductor memory element is
A memory insulating film having a structure in which a tunnel insulating film, a charge storage layer, and a top insulating film are stacked in this order,
The nonvolatile semiconductor memory device according to claim 1, wherein the data is stored or rewritten by injecting electrons or holes into the charge storage layer. In a method for manufacturing a nonvolatile semiconductor memory device having a plurality of nonvolatile semiconductor memory elements that store data and can be rewritten,
The voltage value of the output terminal generated by an inquiry of current between the nonvolatile semiconductor memory element operating by being connected to the power supply VSS and the load transistor operating by being connected to the power supply VDD having a higher potential on the positive side than the power supply VSS but the voltage level of the threshold when switching between the potential direction of the power supply VDD potential direction as the power supply VSS, and set the sense level of the non-volatile semiconductor memory device,
Among the plurality of the non-volatile semiconductor memory device, comprising the steps of thermal equilibrium threshold voltage to form a first non-volatile semiconductor memory device which is the potential direction of the sense level the power supply VDD than the thermal equilibrium threshold Forming a second nonvolatile semiconductor memory element whose voltage is in the potential direction of the power supply VSS with respect to the sense level ;
Writing positive data into the first nonvolatile semiconductor memory element based on the content of the data;
Writing negative data into the second nonvolatile semiconductor memory element based on the content of the data;
A method of manufacturing a nonvolatile semiconductor memory device, comprising: 4. The nonvolatile semiconductor memory device according to claim 3, wherein the step of writing into the first nonvolatile semiconductor memory element and the step of writing into the second nonvolatile semiconductor memory element are simultaneously performed by heat treatment. Production method. In a data rewriting method of a nonvolatile semiconductor memory device having a plurality of nonvolatile semiconductor memory elements that store data and can be rewritten,
The voltage value of the output terminal generated by an inquiry of current between the nonvolatile semiconductor memory element operating by being connected to the power supply VSS and the load transistor operating by being connected to the power supply VDD having a higher potential on the positive side than the power supply VSS but the voltage level of the threshold when switching between the potential direction of the power supply VDD potential direction as the power supply VSS, and set the sense level of the non-volatile semiconductor memory device,
When the data to be written is positive data, among the plurality of nonvolatile semiconductor memory elements , the data is a first nonvolatile memory whose thermal equilibrium state threshold voltage is in the potential direction of the power supply VDD with respect to the sense level. Writing into a conductive semiconductor memory element,
When the data to be written is negative data, among the plurality of nonvolatile semiconductor memory elements , the data is a second nonvolatile memory whose thermal equilibrium state threshold voltage is in the potential direction of the power supply VSS with respect to the sense level. Writing into a conductive semiconductor memory element,
When rewriting the positive data stored in the first nonvolatile semiconductor memory element,
Applying a write voltage such that a threshold value after data writing of the first nonvolatile semiconductor memory element is in a potential direction of the power supply VSS with respect to the sense level;
When rewriting the negative data stored in the second nonvolatile semiconductor memory element,
A write voltage is applied so that a threshold value after data writing of the second nonvolatile semiconductor memory element is in a potential direction of the power supply VDD with respect to the sense level. Data rewriting method.

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