KR20010036790A - Flash memory device and method for manufacturing the same - Google Patents

Abstract

PURPOSE: A flash memory device and a method for manufacturing the same are provided to stabilize an operational characteristic for erasing data by preventing a backward tunnel ring. CONSTITUTION: The first gate oxide layer(20) is formed on an active region of a silicon substrate(10). A word line gate(50) is formed on the first gate oxide layer(20). The second gate oxide layer(21) is formed on the silicon substrate(10) including the word line gate(50). A floating gate(60) is formed on the second gate oxide layer(21) in order to be overlapped one side of an upper portion of the word line gate(50). A source(11) and a bit line(13) are formed on the active region neighboring the word line gate(50) and the floating gate(60) by using the word line gate(50) and the floating gate(60) as a mask.

Description

Flash memory device and method for manufacturing the same

The present invention relates to a split gate type flash EEPROM, and more particularly, to stabilize the operation characteristics of data erasing by preventing reverse turnneling from the lower end of the word line gate to the floating gate. A flash memory device and a method of manufacturing the same.

In general, flash memory devices are based on the technology of semiconductor nonvolatile memory devices, EPROM and EEPROM, and are developed by combining the advantages of these two devices. It is a highly integrated nonvolatile memory device. The flash memory device is generally used as a solid memory device for the deviation of the BIOS, configuration data, and measurement equipment of the system, and is also used as a magnetic disk, a pen input personal computer, a PDA, It is used as a solid-state memory element of a portable device such as a smart card.

Flash memory devices are largely divided into noah and NAND types. Noah type, which requires less read access time due to the parallel structure and can be erased block by block, has a floating gate avalanche injection metal oxide semiconductor (FAMOS) structure. The hot electron injection currents are used and the Fowler-Nordheim (FN) turnneling currents are used for erasing. The sequential access in series takes a lot of lead time, but the NAND type flash memory device has a FLOTOX (floating gate tunneling oxide) structure that has a small cell area and is advantageous for high integration and large capacity because the selection gate can be minimized. All use FN tunneling currents.

In the case of a flash memory device, there is a problem in that a bit line leakage current due to over erasure increases due to one transistor and one cell. However, a separate selection transistor may be formed to solve this problem, but this adversely affects the degree of integration. .

Thus, super flash memory devices in the form of split gates are now widely used. At this time, source side channel hot electrons are used for programming, and F-N turnneling electrons through word lines are used for erasing.

However, in the conventional split gate flash memory device, the voltage Vs of the source 11 of the selected cell becomes 11V, the voltage Vbl of the bit line 13 becomes 0V, and the word line for data program. When the voltage Vwl of the gate 30 becomes 2V, as shown in FIG. 1A, hot electrons generated in the channel between the wordline gate and the floating gate are removed from the bitline 13 in the direction indicated by the arrow. It is charged to the floating gate 40 through the one-gate oxide film 20. Thus, a data program is made.

The voltage Vs of the source 11 of the selected cell is 0V, the voltage Vbl of the bit line 13 is 0V, and the voltage Vwl of the wordline gate 30 is 15V for data erasing. 1B, electrons are discharged to the word line gate 30 by turning the second gate oxide layer 21 from the sharp tip of the upper edge portion of the floating gate 40. . Thus, data erasing of the selected cell is performed.

However, conventionally, the voltage Vs of the source 11 of the non-selected cell becomes 11V, the voltage Vbl of the bit line 13 becomes 0V and the voltage of the word line gate 30 (in the data program of the selected cell). Since Vwl) becomes 0V, as shown in FIG. 2, electrons are reverse-turned from the wordline gate 30 to the floating gate 40 in the direction indicated by the arrow to charge the floating gate 40. As shown in FIG. . Thus, the data program is made to the unselected cells that have already been erased. This is because the lower edge portion A of the word line gate 30 adjacent to the side of the floating gate 40 sharply protrudes toward the floating gate 40 and thus takes a relatively strong electric field. This is due to the phenomenon that the thickness of the second gate oxide film 21 stacked on the upper end of 40 becomes thinner toward the lower end of the floating gate 40.

In order to suppress the reverse turnneling phenomenon, a spacer of an insulating material such as a nitride film is formed on the sidewall of the floating gate 40 so that the lower edge portion of the word line gate 30 adjacent to the side of the floating gate 40 ( It is desirable to form A) so as not to protrude sharply. However, although the high selectivity ratio of the nitride film and the oxide film constituting the spacer is required in the etch back process for forming the spacer, the edge of the floating gate is often used because the etch back process is often performed in a state in which the selectivity is low. The part is easily etched, which adds to the deterioration of the reverse turning voltage characteristics. In order to solve this problem, it is difficult to use the general dry etching equipment currently used, and special expensive precision dry etching equipment should be additionally used. Moreover, even when such dry etching equipment is used, the etching spread in the wafer is large, and the etching spread by wafer and lot occurs according to the state of the dry etching equipment, which tends to adversely affect the yield and characteristics of the flash memory cell.

Accordingly, an object of the present invention is to provide a flash memory device and a method of manufacturing the same, which prevents data erased unselected cells from being programmed together by reverse turning when the data of the selected cells are programmed. have.

1A is an exemplary diagram for explaining a data program of a flash memory device according to the prior art;

1B is an exemplary diagram for explaining data erasing of a flash memory device according to the prior art.

2 is an exemplary diagram for explaining reverse tunneling of a flash memory device according to the prior art;

3 is an exemplary view showing a data program of a flash memory device according to the present invention.

4 is an exemplary view showing data erasing of a flash memory device according to the present invention.

5 to 7 is a process chart showing a method of manufacturing a flash memory device according to the present invention.

Flash memory device according to the present invention for achieving the above object

A silicon substrate having an active region;

A source formed in a portion of the active region

A bit line spaced apart from the source and formed in another portion of the active region;

A first gate oxide film formed on the active region;

A word line gate formed on the first gate oxide layer and adjacent to the source and disposed in a partial region between the source and the bit line gate;

A second gate oxide film formed on the word line; And

And a floating gate formed on the second gate oxide layer and overlapping one side of an upper surface of the word line gate and extending to the bit line.

Preferably, the bottom edge of the word line gate side of the floating gate is formed in a pointed shape. In addition, the second gate oxide layer is formed thinner at a lower portion than the upper portion of the floating gate side of the word line gate. The floating gate may be formed of any one of a monolayer structure of polycrystalline silicon and a sandwich structure of a polycrystalline silicon layer and a tungsten silicide layer.

In addition, the flash memory device manufacturing method according to the present invention for achieving the above object is

Forming a first gate oxide film on the active region of the silicon substrate;

Forming a wordline gate on the first gate oxide film;

Forming a second gate oxide film on the silicon substrate including the wordline gate;

Forming a floating gate on the second gate oxide layer to overlap one side of an upper surface of the word line gate and extend by a partial length; And

And forming a source and a bit line in the active region adjacent to the word line gate and the floating using the word line gate and the floating gate as masks.

Preferably, the bottom edge of the word line gate side of the floating gate is formed in a pointed shape. The second gate oxide layer is formed thinner at the lower portion than the upper portion of the floating gate side of the word line gate. The floating gate may be formed of any one of a monolayer structure of polycrystalline silicon and a sandwich structure of a polycrystalline silicon layer and a tungsten silicide layer.

Therefore, the present invention is formed to overlap the floating gate in the word line gate to prevent the data program of the non-selected cells by reverse turning during the data program of the selected cell to ensure the data erase reliability of the non-selected cells.

Hereinafter, a flash memory device and a method of manufacturing the same according to the present invention will be described in detail with reference to the accompanying drawings. The same code | symbol is attached | subjected to the part of the same structure and the same action as the conventional part.

3 is a cross-sectional view showing a flash memory device according to the present invention.

As shown in FIG. 3, in the flash memory device of the present invention, a source 11 and a bit line 13 are spaced apart from each other in an active region of a silicon substrate 10, and a partial region of the source 11 and a source are disposed. The word line gate 50 is disposed on the first gate oxide layer 20 and overlaps a part of the active region between the bit line 13 and the bit line 13, and the word line gate 50 facing the bit line 13 is disposed. One side and side surfaces of the upper surface of the second gate oxide layer 21 overlapping the partial region, the active region between the word line gate 50 and the bit line 13, and the partial region of the bit line 50 together. Ting gate 60 is disposed.

In addition, the thickness of the oxide film between the word line gate 50 and the floating gate 60 is not thicker than the thickness of the second gate oxide film 21. The bottom edge of the wordline gate 50 side of the floating gate 60 protrudes sharply toward the wordline gate 50. The floating gate 60 has a single layer of a polysilicon layer or a sandwich structure of a polycrystalline silicon layer and a tungsten silicide layer. An oxide film between the word line gate 50 and the floating gate 60 is the same as the second gate oxide film 21.

Referring to the operation of the flash memory device configured as described above, first, the voltage Vwl of the word line gate 50 of the selected cell for the data program is low enough to turn on the channel under the word line gate 50. , For example, 0.5 to 5 V, preferably 2 V, and the voltage Vbl of the bit line 13 is a high voltage, for example, 11 V, and the voltage Vs of the source 11 and the silicon substrate 10. When the voltage Vb of the bulk becomes 0V, the strongest lateral and longitudinal electric field is applied between the wordline gate 50 and the floating gate 60. Accordingly, a channel hot electron flows along the channel under the word line gate 50 after electrons of the source 11 flow as shown in FIG. 3, and then the word line gate of the floating gate 60. 50 is injected into the floating gate 60 from the bottom edge. Therefore, the electrons in the floating gate 60 increases, which is the effect of applying a negative electric field to the channel under the floating gate 60 to turn off the channel under the floating gate 60.

For data erasing, the voltage Vwl of the word line gate 50 of the selected cell becomes a high voltage, for example, 14 to 16 V, the voltage Vs of the source 11, and the voltage Vbl of the bit line 13. And when the bulk voltage Vb becomes 0 V, a strong electric field from the floating gate 60 to the word line gate 50 is induced. Accordingly, the electrons present in the floating gate 60 are subjected to FN turnneling to the wordline gate 50 at the bottom edge of the wordline gate 50 side of the floating gate 60 as shown in FIG. 4. Cause Thus, the electrons in the floating gate 60 are reduced, which is the effect of applying a positive electric field to the channel under the floating gate 60 to inversion the channel under the floating gate 60.

Therefore, the present invention can increase the reliability of data erasing by preventing data programming of only selected cells and data programming of unselected cells during data programming.

A method of manufacturing the flash memory device of the present invention configured as described above will be described with reference to FIGS. For convenience of explanation, a description will be made based on one memory cell. The same reference numerals are given to the same parts as those in Figs. 3 and 4.

Referring to FIG. 5, first, a well (not shown) is formed in a first conductivity type, for example, P-type silicon substrate 10 using a conventional well process, and then a field region (not shown) is used to define an active region. ), A field oxide film is formed by an isolation process such as a conventional LOCOS (local oxidation of silicon) process. Thereafter, the first gate oxide film 20 is grown to a desired thickness on the active region of the silicon substrate 10 using a thermal oxidation process, and impurities for controlling the threshold voltage are ionized on the silicon substrate 10 of the active region. Inject.

Thereafter, a polysilicon layer for the word line gate 50 is stacked on the entire surface of the silicon substrate 10 including the first gate oxide film 20, and then the polysilicon layer is spaced apart from each other using a conventional photolithography process. It is formed in a pattern of four word line gates (50). Here, for convenience of description, although only two patterns of the word line gates 50 are shown in the figure, it is apparent to those skilled in the art that many more word line gates are formed. .

Referring to FIG. 6, a second gate oxide film 21 is stacked on the entire surface of the silicon substrate 10 including the word line gate 50 and the first gate oxide film 20. Of course, it is also possible to grow a second gate oxide film on the surface of the word line gate 50 using a thermal oxidation process.

At this time, when the second gate oxide film 21 is formed, the oxide film thickness of the lower end portion of the word line gate 50 on the floating gate 60 side is the oxide film of the upper end portion of the word line gate 50 on the floating gate 60 side. It is preferable to form thinner than thickness.

Thereafter, a polysilicon layer for the floating gate 60 is stacked on the entire surface of the silicon substrate 10 including the word line gate 50 and the second gate oxide layer 21, and the floating gate is formed by a photolithography process. It forms in the pattern of (60). Here, the floating gate 60 extends by a length toward the word line gate 50 facing the gate beyond the side of the word line gate 50 while overlapping a portion of the inner side of the upper surface of the word line gate 50. The floating gate 60 may be formed of a sandwich structure of the polysilicon layer and the tungsten silicide layer in addition to the monolayer structure of the polysilicon layer.

Referring to FIG. 7, N-type impurities are ion implanted into the active region using the word line gate 50 and the floating gate 60 as masks, so that the source 11 is formed in the active region outside the word line gate 50. ) And a bit line 13 in the active region between the floating gate 60.

Thereafter, an interlayer insulating film is stacked on the resultant structure, and respective contact holes for exposing portions of the source and bit lines are formed in the interlayer insulating film, and wirings are electrically connected to the sources and bit lines through the respective contact holes. . The description thereof is not related to the gist of the present invention, so a detailed description thereof will be omitted.

As described above, according to the present invention, the floating gate is formed to overlap a part of the upper surface of the word line gate. Channel hot electrons are injected into the bottom edge of the wordline side of the floating gate during data programming, and electrons are tunneled from the floating gate to the wordline gate by F-N turning when data is erased.

Therefore, the present invention prevents the data program of the unselected cell by reverse turning at the time of the data program of the selected cell, thereby ensuring data erasure reliability of the unselected cell.

On the other hand, the present invention is described based on the preferred example shown in the drawings, but not limited to this and various modifications and improvements are possible by those skilled in the art to which the present invention belongs without departing from the spirit of the invention. Of course.

Claims (8)

A silicon substrate having an active region; A source formed in a portion of the active region A bit line spaced apart from the source and formed in another portion of the active region; A first gate oxide film formed on the active region; A word line gate formed on the first gate oxide layer and adjacent to the source and disposed in a partial region between the source and the bit line gate; A second gate oxide film formed on the word line; And A floating gate formed on the second gate oxide layer and overlapping one side of an upper surface of the word line gate and extending to the bit line; Flash memory device. The flash memory device of claim 1, wherein a bottom edge of the floating gate is formed in a pointed shape. The flash memory device of claim 1, wherein the second gate oxide layer is formed thinner at a lower portion than an upper portion of a floating gate side of the word line gate. 2. The flash memory device of claim 1, wherein the floating gate comprises one of a monolayer structure of polycrystalline silicon and a sandwich structure of a polycrystalline silicon layer and a tungsten silicide layer. Forming a first gate oxide film on the active region of the silicon substrate; Forming a wordline gate on the first gate oxide film; Forming a second gate oxide film on the silicon substrate including the wordline gate; Forming a floating gate on the second gate oxide layer to overlap one side of an upper surface of the word line gate and extend by a partial length; And And forming a source and a bit line in the active region adjacent to the word line gate and the floating using the word line gate and the floating gate as masks. 6. The method of claim 5, wherein the bottom edge of the word line gate side of the floating gate is formed in a pointed shape. 6. The method of claim 5, wherein the second gate oxide film is formed thinner at a lower portion than an upper portion of a floating gate side of the word line gate. 6. The method of claim 5, wherein the floating gate is formed of any one of a monolayer structure of polycrystalline silicon and a sandwich structure of a polycrystalline silicon layer and a tungsten silicide layer.