JP5335552B2 - 情報処理装置、その制御方法、及びコンピュータプログラム - Google Patents
情報処理装置、その制御方法、及びコンピュータプログラム Download PDFInfo
- Publication number
- JP5335552B2 JP5335552B2 JP2009118042A JP2009118042A JP5335552B2 JP 5335552 B2 JP5335552 B2 JP 5335552B2 JP 2009118042 A JP2009118042 A JP 2009118042A JP 2009118042 A JP2009118042 A JP 2009118042A JP 5335552 B2 JP5335552 B2 JP 5335552B2
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Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0751—Error or fault detection not based on redundancy
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
- G06F11/0721—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment within a central processing unit [CPU]
- G06F11/0724—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment within a central processing unit [CPU] in a multiprocessor or a multi-core unit
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Debugging And Monitoring (AREA)
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2009118042A JP5335552B2 (ja) | 2009-05-14 | 2009-05-14 | 情報処理装置、その制御方法、及びコンピュータプログラム |
| US12/771,013 US8156386B2 (en) | 2009-05-14 | 2010-04-30 | Information processing apparatus, and method and computer program for controlling same, for detecting certain failures |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2009118042A JP5335552B2 (ja) | 2009-05-14 | 2009-05-14 | 情報処理装置、その制御方法、及びコンピュータプログラム |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2010267091A JP2010267091A (ja) | 2010-11-25 |
| JP2010267091A5 JP2010267091A5 (enExample) | 2012-06-28 |
| JP5335552B2 true JP5335552B2 (ja) | 2013-11-06 |
Family
ID=43069480
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2009118042A Expired - Fee Related JP5335552B2 (ja) | 2009-05-14 | 2009-05-14 | 情報処理装置、その制御方法、及びコンピュータプログラム |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US8156386B2 (enExample) |
| JP (1) | JP5335552B2 (enExample) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20120221884A1 (en) * | 2011-02-28 | 2012-08-30 | Carter Nicholas P | Error management across hardware and software layers |
| JP5737055B2 (ja) * | 2011-08-18 | 2015-06-17 | 三菱電機株式会社 | プログラム監視システム |
| JP5906807B2 (ja) * | 2012-02-28 | 2016-04-20 | 日本電気株式会社 | 演算処理装置及びストール監視方法 |
| EP3312726A1 (en) * | 2015-06-16 | 2018-04-25 | Olympus Corporation | Cpu monitoring device |
| JP6536374B2 (ja) * | 2015-11-17 | 2019-07-03 | 富士通株式会社 | 情報処理装置、情報処理方法及びプログラム |
Family Cites Families (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3996567A (en) * | 1972-05-23 | 1976-12-07 | Telefonaktiebolaget L M Ericsson | Apparatus for indicating abnormal program execution in a process controlling computer operating in real time on different priority levels |
| JPS594054B2 (ja) | 1979-04-17 | 1984-01-27 | 株式会社日立製作所 | マルチプロセツサ障害検出方式 |
| JPS63163932A (ja) * | 1986-12-26 | 1988-07-07 | Fuji Electric Co Ltd | 制御用計算機のシステム監視方式 |
| JPH05181760A (ja) | 1991-12-27 | 1993-07-23 | Sharp Corp | Cpuの暴走監視装置 |
| JPH05324409A (ja) * | 1992-05-27 | 1993-12-07 | Meidensha Corp | ソフトウェアの暴走監視方式 |
| US5737515A (en) * | 1996-06-27 | 1998-04-07 | Sun Microsystems, Inc. | Method and mechanism for guaranteeing timeliness of programs |
| JPH1063544A (ja) * | 1996-08-20 | 1998-03-06 | Toshiba Corp | タイムアウト監視方式 |
| JP3524700B2 (ja) * | 1996-11-01 | 2004-05-10 | シャープ株式会社 | タスク監視方法 |
| US6351824B1 (en) * | 1998-01-05 | 2002-02-26 | Sophisticated Circuits, Inc. | Methods and apparatuses for controlling the operation of a digital processing system |
| JP2000122900A (ja) * | 1998-10-20 | 2000-04-28 | Fujitsu Ltd | マイクロコントローラの暴走監視方法 |
| US6665758B1 (en) * | 1999-10-04 | 2003-12-16 | Ncr Corporation | Software sanity monitor |
| JP2001117796A (ja) * | 1999-10-22 | 2001-04-27 | Yamatake Building Systems Co Ltd | コンピュータ装置及びプログラム記録媒体 |
| US7194665B2 (en) * | 2001-11-01 | 2007-03-20 | Advanced Micro Devices, Inc. | ASF state determination using chipset-resident watchdog timer |
| US7219268B2 (en) * | 2003-05-09 | 2007-05-15 | Hewlett-Packard Development Company, L.P. | System and method for determining transaction time-out |
| US7383470B2 (en) * | 2004-09-30 | 2008-06-03 | Microsoft Corporation | Method, system, and apparatus for identifying unresponsive portions of a computer program |
| US20080126650A1 (en) * | 2006-09-21 | 2008-05-29 | Swanson Robert C | Methods and apparatus for parallel processing in system management mode |
| JP2009075769A (ja) * | 2007-09-19 | 2009-04-09 | Seiko Epson Corp | プログラムの暴走検出システムおよびプログラムの暴走検出方法 |
| US8099637B2 (en) * | 2007-10-30 | 2012-01-17 | Hewlett-Packard Development Company, L.P. | Software fault detection using progress tracker |
-
2009
- 2009-05-14 JP JP2009118042A patent/JP5335552B2/ja not_active Expired - Fee Related
-
2010
- 2010-04-30 US US12/771,013 patent/US8156386B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| US20100293414A1 (en) | 2010-11-18 |
| JP2010267091A (ja) | 2010-11-25 |
| US8156386B2 (en) | 2012-04-10 |
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