JP5334236B2 - Field effect transistor - Google Patents
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- JP5334236B2 JP5334236B2 JP2007193817A JP2007193817A JP5334236B2 JP 5334236 B2 JP5334236 B2 JP 5334236B2 JP 2007193817 A JP2007193817 A JP 2007193817A JP 2007193817 A JP2007193817 A JP 2007193817A JP 5334236 B2 JP5334236 B2 JP 5334236B2
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K77/00—Constructional details of devices covered by this subclass and not covered by groups H10K10/80, H10K30/80, H10K50/80 or H10K59/80
- H10K77/10—Substrates, e.g. flexible substrates
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
- H10K10/40—Organic transistors
- H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
- H10K10/462—Insulated gate field-effect transistors [IGFETs]
- H10K10/466—Lateral bottom-gate IGFETs comprising only a single gate
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
- H10K10/80—Constructional details
- H10K10/88—Passivation; Containers; Encapsulations
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/549—Organic PV cells
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Description
本発明は、電界効果型トランジスタおよび当該電界効果型トランジスタを有する有機エレクトロルミネッセンス素子に関するものである。 The present invention relates to a field effect transistor and an organic electroluminescence element having the field effect transistor.
現在、最も一般的な電界効果型トランジスタ(以下、「FET」という場合がある)は、SiやGa、Asなどの無機材料からなる基板上にソース電極とドレイン電極が形成され、これらの電極間にゲート絶縁層を有し、さらに当該ゲート絶縁層上にゲート電極が形成された構造を有する。そしてゲート電極に電圧を印加することによって、無機材料基板の一部(チャネル層)を通じてソース電極からドレイン電極へ電流が流れる。 Currently, the most common field effect transistor (hereinafter sometimes referred to as “FET”) has a source electrode and a drain electrode formed on a substrate made of an inorganic material such as Si, Ga, As, and the like. And a gate insulating layer, and a gate electrode is formed on the gate insulating layer. By applying a voltage to the gate electrode, a current flows from the source electrode to the drain electrode through part of the inorganic material substrate (channel layer).
近年、このチャネル層として有機半導体を用いた有機FETが注目されている。この有機半導体からなるチャネル層の利点としては、(1)従来の無機材料基板で用いられていた蒸着プロセス以外に低コストで大量生産し易い印刷などで形成できること、(2)低温で形成できるので熱に弱い有機材料基板を用いることができること、(3)有機半導体自体が柔軟であるので、フレキシブルで耐衝撃性が高く且つ軽量なFETを形成できるといったことが挙げられる。特に、軽量でフレキシブルという特長を有する有機FETは、RFタグ、電子ペーパー、有機ELや液晶ディスプレイ装置などの電子部品として極めて好ましい。 In recent years, an organic FET using an organic semiconductor as the channel layer has attracted attention. Advantages of this organic semiconductor channel layer are (1) that it can be formed by printing that is easy to mass-produce at low cost in addition to the vapor deposition process used in conventional inorganic material substrates, and (2) it can be formed at low temperature. It is possible to use a heat-sensitive organic material substrate, and (3) since the organic semiconductor itself is flexible, a flexible, high impact resistance and lightweight FET can be formed. In particular, an organic FET having the characteristics of being lightweight and flexible is extremely preferable as an electronic component such as an RF tag, electronic paper, an organic EL, and a liquid crystal display device.
その反面、有機半導体材料は酸素や水分の存在により劣化し易いので、FETの寿命が短くなるという欠点を有する。特に最近では軽量化などの観点から有機材料基板が用いられるようになってきているが、有機材料基板のガスバリア性は無機材料基板よりも低いためにトランジスタ中に水分やガスが浸入し易く、有機半導体の劣化が進むという問題がある。 On the other hand, since the organic semiconductor material easily deteriorates due to the presence of oxygen and moisture, it has a drawback that the lifetime of the FET is shortened. In recent years, organic material substrates have come to be used from the viewpoint of weight reduction. However, since the organic material substrate has a lower gas barrier property than that of an inorganic material substrate, moisture and gas can easily enter the transistor. There is a problem that semiconductor deterioration progresses.
そこで、ガスバリア層により水分やガスの浸入を防ぐ技術が検討されている。例えば特許文献1には、ポリイミドやポリエチレンテレフタレートからなる有機材料基板や有機半導体層の上にガスバリア層を設けることにより有機半導体を水やガスなどから保護する技術が開示されている。
上述した様に、基板やチャネル層が有機材料で形成されているものであって、基板上やチャネル層上にガスバリア層を形成することにより水やガスなどに弱い有機半導体を保護する技術は知られていた。しかしかかる従来技術では有機半導体の劣化を必ずしも抑制できなかった。 As described above, the substrate and the channel layer are formed of an organic material, and a technology for protecting an organic semiconductor that is sensitive to water or gas by forming a gas barrier layer on the substrate or the channel layer is known. It was done. However, such prior art cannot always suppress the deterioration of the organic semiconductor.
例えば上記特許文献1に記載の有機半導体装置では基板材料としてポリイミドまたはポリエチレンフタレートが用いられているが、これら材料はガスバリア性に乏しい。また、当該有機基板上の無機材料ガスバリア層はスパッタリングなどにより形成されるが、その際にピンホールなどの欠陥が生じがちであり、さらに、無機材料によるガスバリア層は屈曲により亀裂が発生する場合がある。よって、これら有機材料からなる基板上へ単にガスバリア層を設けるのみでは、水やガスの浸入を完全に防ぐことはできない。その結果、特にディスプレイなど常時駆動を強いられる電子機器に有機FETを適用した場合には、有機半導体の劣化が促進される。
For example, in the organic semiconductor device described in
その上、ポリエチレンテレフタレートなどからなるフィルムは耐熱性が低い。また、一般的な有機材料の熱膨張係数は金属や無機物よりも遥かに大きい。その結果、熱履歴を受けると寸法安定性に問題が生じたり、反りが発生する。 In addition, a film made of polyethylene terephthalate has low heat resistance. Moreover, the thermal expansion coefficient of a general organic material is much larger than that of a metal or an inorganic material. As a result, when receiving a thermal history, a problem arises in dimensional stability or warpage occurs.
そこで本発明が解決すべき課題は、フレキシブル性を有しながらも十分なガスバリア性を示す上に、高い寸法安定性を有する電界効果型トランジスタを提供することにある。また、本発明は、当該電界効果型トランジスタを含む有機エレクトロルミネッセンス素子を提供することも目的とする。 Therefore, the problem to be solved by the present invention is to provide a field effect transistor having high dimensional stability while exhibiting sufficient gas barrier properties while having flexibility. Another object of the present invention is to provide an organic electroluminescence element including the field effect transistor.
本発明者は、上記課題を解決すべく基板材料としてガスバリア性と寸法安定性の高い材料を探索した。その結果、液晶ポリマーは極めて高いガスバリア性と寸法安定性を示すことから電界効果型トランジスタの基板材料として優れることを見出して本発明を完成した。 In order to solve the above problems, the present inventor searched for a material having high gas barrier properties and high dimensional stability as a substrate material. As a result, the present invention was completed by finding that the liquid crystal polymer is excellent as a substrate material for a field effect transistor since it exhibits extremely high gas barrier properties and dimensional stability.
本発明の電界効果型トランジスタは、基板上に、少なくともソース電極、ドレイン電極、ゲート電極、ゲート絶縁層および有機半導体層を有し、当該基板が液晶ポリマーフィルムからなることを特徴とする。 The field effect transistor of the present invention is characterized by having at least a source electrode, a drain electrode, a gate electrode, a gate insulating layer, and an organic semiconductor layer on a substrate, and the substrate is made of a liquid crystal polymer film.
また、本発明の有機エレクトロルミネッセンス素子は、本発明の電界効果型トランジスタを含むことを特徴とする。 Moreover, the organic electroluminescent element of this invention is characterized by including the field effect transistor of this invention.
本発明の電界効果型トランジスタは、基板材料として液晶ポリマーを用いていることからフレキシブルでありながら十分なガスバリア性を有するので、有機半導体を水分やガスから保護することができ、長寿命である。また、高い寸法安定性を有するので熱履歴を受けても変形が少ない。よって、本発明の電界効果型トランジスタを、大画面の有機ELディスプレイ装置などに利用できる有機エレクトロルミネッセンス素子に適用することも可能である。従って本発明は、電子デバイス部品として産業上極めて有用である。 Since the field effect transistor of the present invention uses a liquid crystal polymer as a substrate material and has a sufficient gas barrier property while being flexible, the organic semiconductor can be protected from moisture and gas and has a long life. Moreover, since it has high dimensional stability, there is little deformation even if it receives a thermal history. Therefore, the field effect transistor of the present invention can be applied to an organic electroluminescence element that can be used for an organic EL display device having a large screen. Therefore, the present invention is extremely useful industrially as an electronic device component.
本発明の電界効果型トランジスタ(FET)は、基板上に、少なくともソース電極、ドレイン電極、ゲート電極、ゲート絶縁層および有機半導体層を有し、当該基板が液晶ポリマーフィルムからなることを特徴とする。 The field effect transistor (FET) of the present invention has at least a source electrode, a drain electrode, a gate electrode, a gate insulating layer, and an organic semiconductor layer on a substrate, and the substrate is made of a liquid crystal polymer film. .
本発明に係るFETの基板材料である液晶ポリマーは、耐熱性の熱可塑性樹脂であり、溶融状態で液晶性を示すサーモトロピック液晶ポリマーと溶液状態で液晶性を示すリオトロピック液晶ポリマーとがある。本発明で用いる液晶ポリマーとしてはサーモトロピック液晶ポリマーが好適であり、より具体的にはサーモトロピック液晶ポリエステルやサーモトロピック液晶ポリエステルアミドが好ましい。 The liquid crystal polymer that is the substrate material for the FET according to the present invention is a heat-resistant thermoplastic resin, and includes a thermotropic liquid crystal polymer that exhibits liquid crystal properties in a molten state and a lyotropic liquid crystal polymer that exhibits liquid crystal properties in a solution state. The liquid crystal polymer used in the present invention is preferably a thermotropic liquid crystal polymer, more specifically, a thermotropic liquid crystal polyester or a thermotropic liquid crystal polyester amide.
サーモトロピック液晶ポリエステル(以下、単に「液晶ポリエステル」という)とは、例えば、芳香族ジカルボン酸と芳香族ジオールや芳香族ヒドロキシカルボン酸などのモノマーを主体として合成される芳香族ポリエステルであって、溶融時に液晶性を示すものである。その代表的なものとしては、パラヒドロキシ安息香酸(PHB)とテレフタル酸と4,4’−ビフェノールから合成されるI型[下式(1)]、PHBと2,6−ヒドロキシナフトエ酸から合成されるII型[下式(2)]、PHBとテレフタル酸とエチレングリコールから合成されるIII型[下式(3)]が挙げられる。 Thermotropic liquid crystal polyester (hereinafter simply referred to as “liquid crystal polyester”) is, for example, an aromatic polyester synthesized mainly from aromatic dicarboxylic acid and monomers such as aromatic diol and aromatic hydroxycarboxylic acid. Sometimes it exhibits liquid crystallinity. Typical examples include type I [Formula (1)] synthesized from parahydroxybenzoic acid (PHB), terephthalic acid and 4,4′-biphenol, synthesized from PHB and 2,6-hydroxynaphthoic acid. Type II [Formula (2)] and type III [Formula (3)] synthesized from PHB, terephthalic acid and ethylene glycol.
本発明に係る液晶ポリマー樹脂としては、液晶性(特にサーモトロピック液晶性)を示すものであれば、例えば、上記(1)〜(3)式に示すユニットを主体(例えば、液晶ポリマーの全構成ユニット中50モル%以上)とし、他のユニットも有する共重合タイプのポリマーであってもよい。他のユニットとしては、例えばエーテル結合を有するユニット、イミド結合を有するユニット、アミド結合を有するユニットなどが挙げられる。本発明において特に好適な液晶ポリエステルからなるフィルムとしては、例えばジャパンゴアテックス社製の「BIAC(登録商標)」を挙げることができる。 As the liquid crystal polymer resin according to the present invention, as long as it exhibits liquid crystallinity (particularly thermotropic liquid crystallinity), for example, the unit represented by the above formulas (1) to (3) is mainly used (for example, the entire configuration of the liquid crystal polymer). It may be a copolymer type polymer having 50 mol% or more in the unit) and also having other units. Examples of the other unit include a unit having an ether bond, a unit having an imide bond, and a unit having an amide bond. Examples of the film made of liquid crystalline polyester that is particularly suitable in the present invention include “BIAC (registered trademark)” manufactured by Japan Gore-Tex.
液晶ポリエステルアミドとしては、他のユニットとしてアミド結合を有する上記液晶ポリエステルが該当し、例えば下式(4)の構造を有するものが挙げられる。例えば、式(4)中、sのユニット、tのユニットおよびuのユニットのモル比が、70/15/15のものが知られている。 Examples of the liquid crystal polyester amide include the above liquid crystal polyester having an amide bond as another unit, and examples thereof include those having a structure of the following formula (4). For example, in the formula (4), the molar ratio of the unit of s, the unit of t, and the unit of u is 70/15/15.
基板材料である液晶ポリマーとしては、上記液晶ポリマーを含むポリマーアロイを用いてもよい。この場合、液晶ポリマーと混合または化学結合させるアロイ用ポリマーとしては、融点が220℃以上、好ましくは280〜360℃のポリマーがある。例えば、ポリエーテルエーテルケトン、ポリエーテルサルホン、ポリイミド、ポリエーテルイミド、ポリアミド、ポリアミドイミド、ポリアリレートなどが挙げられるが、これらに限定される訳ではない。液晶ポリマーと上記アロイ用ポリマーの混合割合は特に制限されないが、例えば質量比で10:90〜90:10であることが好ましく、30:70〜70:30であることがより好ましい。液晶ポリマーを含むポリマーアロイも液晶ポリマーによる優れた特性を保有し得る。 As the liquid crystal polymer as the substrate material, a polymer alloy containing the above liquid crystal polymer may be used. In this case, the alloy polymer mixed or chemically bonded to the liquid crystal polymer includes a polymer having a melting point of 220 ° C. or higher, preferably 280 to 360 ° C. Examples include, but are not limited to, polyetheretherketone, polyethersulfone, polyimide, polyetherimide, polyamide, polyamideimide, and polyarylate. The mixing ratio of the liquid crystal polymer and the alloy polymer is not particularly limited. For example, the mass ratio is preferably 10:90 to 90:10, and more preferably 30:70 to 70:30. A polymer alloy containing a liquid crystal polymer can also have excellent characteristics due to the liquid crystal polymer.
本発明では以上で説明した液晶ポリマーを材料としてフィルムを形成し、基板とする。液晶ポリマーフィルムの厚さとしては10〜2000μm程度が好ましい。薄過ぎると強度やガスバリア性が不足する可能性がある一方で、厚過ぎるとフィルム化が困難となり得る。なお、平面形状や大きさは最終製品である液晶ディスプレイ装置などに合わせて決定すればよい。 In the present invention, a film is formed by using the liquid crystal polymer described above as a material to form a substrate. The thickness of the liquid crystal polymer film is preferably about 10 to 2000 μm. If it is too thin, strength and gas barrier properties may be insufficient. On the other hand, if it is too thick, film formation may be difficult. The planar shape and size may be determined in accordance with the liquid crystal display device that is the final product.
液晶ポリマーフィルムの表面粗度については、レーザー顕微鏡を用いて測定した場合の三次元中心面平均粗さ(SRa)が50nm以下であることが好ましく、より好ましくは25nm以下がよい。フィルム上に形成される電極などの厚みが10〜100nm程度と極めて薄いため、粗度が50nmより大きいと微細な領域で膜厚が不均一となり、電界効果移動度やオン/オフ比が低下するおそれがある。それに対して、当該粗度が高い場合であっても電極や半導体層などの厚さを厚くすれば歩留は維持できるが、それでは製造コストが上ってしまう。しかし当該粗度が50nm以下であれば、電極などの厚さを適度なものとした場合でも高品質のFETを効率良く製造することができる。 As for the surface roughness of the liquid crystal polymer film, the three-dimensional center plane average roughness (SRa) when measured using a laser microscope is preferably 50 nm or less, more preferably 25 nm or less. Since the thickness of the electrode formed on the film is as extremely thin as about 10 to 100 nm, if the roughness is larger than 50 nm, the film thickness becomes uneven in a fine region, and the field-effect mobility and on / off ratio are reduced. There is a fear. On the other hand, even if the roughness is high, the yield can be maintained by increasing the thickness of the electrode, the semiconductor layer, etc., but this increases the manufacturing cost. However, if the roughness is 50 nm or less, a high-quality FET can be efficiently manufactured even when the thickness of the electrode or the like is appropriate.
本発明における液晶ポリマーフィルムの表面粗度は、三次元中心面平均粗さ(SRa)をいうものとする。三次元中心面平均粗さは平面方向における凹凸をより正確に表すことができる。 The surface roughness of the liquid crystal polymer film in the present invention refers to the three-dimensional center plane average roughness (SRa). The three-dimensional center plane average roughness can more accurately represent the unevenness in the plane direction.
当該表面粗度は、以下の方法により測定することができる。例えばオリンパス製のOLS3000などのレーザー顕微鏡を使用し、レーザー種としてλ=408±5nmの半導体レーザーを用い、Z方向の移動分解能を0.01μmに設定して、192μm×256μmの範囲におけるZ方向の粗さを0.1μmピッチで50倍の共焦点モードで測定し、その平均値を求めるものとする。 The surface roughness can be measured by the following method. For example, using a laser microscope such as OLS3000 manufactured by Olympus, using a semiconductor laser of λ = 408 ± 5 nm as a laser type, setting the moving resolution in the Z direction to 0.01 μm, and moving in the Z direction in the range of 192 μm × 256 μm The roughness is measured in a confocal mode of 50 times at a pitch of 0.1 μm, and the average value is obtained.
液晶ポリマーフィルムの表面粗度を小さくするには、熱プレス装置を用いて表面平滑化処理をすることが好ましい。例えば、離型材として少なくとも片面を鏡面加工した金属板やポリイミドなど、平滑性、耐熱性および離型性を有する高分子フィルムや板状物で液晶ポリマーフィルムを挟み、加熱加圧処理すればよい。その際の温度は、液晶ポリマーが十分に軟化はするがその融点未満とする。また、圧力は液晶ポリマーの種類や加熱温度などにもよるが、通常は1〜10MPa程度とする。熱プレス装置の種類は特に制限されず、一般的な平板プレス機の他に、熱ロール間で連続的に加圧することもできる。上記の方法以外にも、研磨による平坦化や、別途液晶ポリマーや他のポリマー材料の溶液のコーティングによる平滑層の形成などの公知方法も用い得る。 In order to reduce the surface roughness of the liquid crystal polymer film, it is preferable to perform a surface smoothing treatment using a hot press apparatus. For example, a liquid crystal polymer film may be sandwiched between a polymer film or plate having smoothness, heat resistance, and release properties, such as a metal plate or polyimide having a mirror-finished at least one side as a release material, and then heated and pressurized. The temperature at that time is set below the melting point of the liquid crystal polymer, although it is sufficiently softened. The pressure is usually about 1 to 10 MPa, although it depends on the type of liquid crystal polymer and the heating temperature. The kind in particular of a hot press apparatus is not restrict | limited, In addition to a general flat plate press, it can also press continuously between hot rolls. In addition to the above method, known methods such as flattening by polishing and formation of a smooth layer by separately coating a solution of a liquid crystal polymer or other polymer material may be used.
上記液晶ポリマーフィルムではフィルム平面に平行な方向の線膨張係数が30ppm/℃以下に調整されていることが好ましい。より好ましくは25ppm/℃以下である。また、液晶ポリマーフィルムの上記線膨張係数の下限は5ppm/℃であることが望ましい。かかる範囲の線膨張係数を有する液晶ポリマーフィルムであれば、金属等からなる電極などとの線膨張係数の差が小さいため、熱履歴を受けた場合などに発生する反りが低減されるからである。例えば金属層が接する場合には液晶ポリマーフィルムの線膨張係数を5〜20ppm/℃程度とし、有機層と接する場合には20〜30ppm/℃とすることが好ましい。 In the liquid crystal polymer film, the linear expansion coefficient in the direction parallel to the film plane is preferably adjusted to 30 ppm / ° C. or less. More preferably, it is 25 ppm / ° C. or less. The lower limit of the linear expansion coefficient of the liquid crystal polymer film is desirably 5 ppm / ° C. If the liquid crystal polymer film has a linear expansion coefficient in such a range, the difference in the linear expansion coefficient from an electrode made of metal or the like is small, so that the warpage that occurs when receiving a thermal history is reduced. . For example, the linear expansion coefficient of the liquid crystal polymer film is preferably about 5 to 20 ppm / ° C. when the metal layer is in contact, and 20 to 30 ppm / ° C. when it is in contact with the organic layer.
液晶ポリマーフィルムの線膨張係数は、機器分析(TMA)法により測定することができる。より具体的には、例えば試験片幅:4.5mm、チャック間距離:15mm、荷重:1gとし、昇温速度:5℃/分で室温から200℃まで昇温後に降温速度:5℃/分で冷却する際に、160℃から25℃の間で測定される試験片の寸法変化から求める。液晶ポリマーフィルムのMD方向(フィルム製造時の走行方向)およびTD方向(MD方向に直交する方向)の線膨張係数のいずれもが上記範囲を満足することが好ましい。 The linear expansion coefficient of the liquid crystal polymer film can be measured by instrumental analysis (TMA) method. More specifically, for example, the width of the test piece is 4.5 mm, the distance between chucks is 15 mm, the load is 1 g, the temperature rising rate is 5 ° C./min. It is determined from the dimensional change of the test piece measured between 160 ° C. and 25 ° C. when it is cooled at. It is preferable that both the linear expansion coefficients of the liquid crystal polymer film in the MD direction (running direction during film production) and the TD direction (direction orthogonal to the MD direction) satisfy the above range.
なお、液晶ポリマーフィルムの線膨張係数は、分子配向を制御することにより調節することができる。また、フィラーの添加などにより調節してもよい。但しフィラーは液晶ポリマーフィルムの表面平滑性に悪影響を与える場合があるので、線膨張係数は好適には延伸条件により調整する。 The linear expansion coefficient of the liquid crystal polymer film can be adjusted by controlling the molecular orientation. Moreover, you may adjust by addition of a filler. However, since the filler may adversely affect the surface smoothness of the liquid crystal polymer film, the linear expansion coefficient is preferably adjusted according to the stretching conditions.
ディスプレイなど常時駆動を強いられる電子機器にFETを適用する場合には、有機半導体の劣化が進行し易いために基板にはより高度なガスバリア性が要求される。よって、本発明基板の少なくとも片面にはガスバリア性をより一層高めるためにガスバリア層を設けてもよい。かかるガスバリア層の材料としては、Al、Cr、Ni、Cu、Zn、Si、Fe、Ti、Ag、Au、Co;これら金属の酸化物;これら金属の窒化物;これら金属の酸化窒化物を挙げることができ、これらから1種を選択して用いるか、2種以上を選択し混合して用いることができる。 When an FET is applied to an electronic device that is forced to be constantly driven, such as a display, the substrate is required to have a higher gas barrier property because the organic semiconductor is easily deteriorated. Therefore, a gas barrier layer may be provided on at least one surface of the substrate of the present invention in order to further enhance the gas barrier property. Examples of the material of the gas barrier layer include Al, Cr, Ni, Cu, Zn, Si, Fe, Ti, Ag, Au, and Co; oxides of these metals; nitrides of these metals; oxynitrides of these metals. One of these can be selected and used, or two or more can be selected and mixed for use.
ガスバリア層の厚さは、通常5〜1000nm程度とする。5nm未満であるとガスバリア性が十分に発揮できないおそれがある一方で、1000nmを超えるとコスト高や素子が重くなるといった問題が生じ得る。 The thickness of the gas barrier layer is usually about 5 to 1000 nm. If the thickness is less than 5 nm, gas barrier properties may not be sufficiently exhibited. On the other hand, if the thickness exceeds 1000 nm, problems such as high cost and heavy elements may occur.
ガスバリア層の形成方法は特に制限されず、一般的な公知方法を用いることができる。例えば、ドライプロセスとしては真空蒸着、スパッタリング、イオンプレーティング等の各種PVD法と、プラズマCVD、熱CVD、レーザーCVD等の各種CVD法、ウエットプロセスとしてはゾル−ゲル法、めっき法、塗布法等を挙げることができる。 The formation method in particular of a gas barrier layer is not restrict | limited, A general well-known method can be used. For example, various PVD methods such as vacuum deposition, sputtering, and ion plating as dry processes, various CVD methods such as plasma CVD, thermal CVD, and laser CVD, and sol-gel methods, plating methods, coating methods, etc. as wet processes Can be mentioned.
ガスバリア層は基板の片面または両面に形成することができる。ガスバリア層を片面に設ける場合、通常は後述するゲート電極層と反対側にガスバリア層を形成する。但し、ガスバリア層を電極と同じ側に設けてもよい。例えば、基板上に形成した金属ガスバリア層をグラウンド電極として兼用してもよいし、また、当該ガスバリア層を部分的に金属酸化物とし、残留した金属部分を回路として利用してもよい。 The gas barrier layer can be formed on one side or both sides of the substrate. When the gas barrier layer is provided on one side, the gas barrier layer is usually formed on the side opposite to the gate electrode layer described later. However, the gas barrier layer may be provided on the same side as the electrode. For example, the metal gas barrier layer formed on the substrate may be used as a ground electrode, or the gas barrier layer may be partially made of metal oxide and the remaining metal portion may be used as a circuit.
本発明に係るFETの一態様を示す図1の通り、上記基板上にはソース電極、ドレイン電極、ゲート電極、ゲート絶縁層および有機半導体層を設ける。 As shown in FIG. 1 showing one embodiment of an FET according to the present invention, a source electrode, a drain electrode, a gate electrode, a gate insulating layer, and an organic semiconductor layer are provided on the substrate.
各電極は、AlやCuなどの金属、或いは金属やカーボンなどの導電物質を含むペーストにより形成することができる。 Each electrode can be formed of a paste containing a metal such as Al or Cu, or a conductive material such as metal or carbon.
電極の形成方法は特に制限されず、蒸着、スパッタリング、めっき、塗布、印刷など公知の形成方法を用いればよい。また、電極の厚さも特に制限されないが、一般的には50〜1000μm程度とすることができる。 The electrode formation method is not particularly limited, and a known formation method such as vapor deposition, sputtering, plating, coating, or printing may be used. The thickness of the electrode is not particularly limited, but can generally be about 50 to 1000 μm.
液晶ポリマー基板上にはゲート電極を形成し、当該ゲート電極をソース電極とドレイン電極と絶縁するためにゲート絶縁層で被覆する。 A gate electrode is formed on the liquid crystal polymer substrate, and the gate electrode is covered with a gate insulating layer in order to insulate the source electrode and the drain electrode.
ゲート絶縁層の材料は、従来FETのゲート絶縁層に用いられてきたものを使用できる。例えば、SiO2、Si3N4、Al2O3等の無機物や、フェノール系樹脂、アクリル系樹脂、エポキシ系樹脂、イミド系樹脂など絶縁性を有した樹脂を用いることができる。ゲート絶縁層の形成方法も従来公知のものを用いることができる。例えば、塗布、スパッタリング、ゾルゲル法、印刷などの方法で形成すればよい。 As the material of the gate insulating layer, those conventionally used for the gate insulating layer of FET can be used. For example, inorganic materials such as SiO 2 , Si 3 N 4 , and Al 2 O 3 , and resins having insulating properties such as phenol resins, acrylic resins, epoxy resins, and imide resins can be used. A conventionally known method for forming the gate insulating layer can also be used. For example, it may be formed by a method such as coating, sputtering, sol-gel method, or printing.
ゲート絶縁層の厚さは特に制限されないが、一般的には10nm以上、10μm以下程度とすることができる。この範囲であれば、電極間での短絡を確実に防止できる一方で、ゲート絶縁層が過剰に厚くならず余分なコストがかからない。 The thickness of the gate insulating layer is not particularly limited, but can generally be about 10 nm to 10 μm. Within this range, a short circuit between the electrodes can be surely prevented, while the gate insulating layer does not become excessively thick and no extra cost is incurred.
ゲート絶縁層上には、ソース電極とドレイン電極との間での電流路となる有機半導体層、即ちチャネル層を形成する。 On the gate insulating layer, an organic semiconductor layer serving as a current path between the source electrode and the drain electrode, that is, a channel layer is formed.
有機半導体層の材料は、従来FETの有機半導体層に用いられてきたものを使用できる。例えば、ペンタセン、テトラセン、アントラセン、フタロシアニンなどの低分子型有機半導体材料や、ポリチオフェン、ポリアセン、ポリアセチレン、ポリアニリンなどの高分子型半導体材料を用いることができる。有機半導体層の形成方法も従来公知のものを用いることができる。例えば、蒸着、塗布、スパッタリング、ゾルゲル法、印刷などの方法で形成すればよい。 As the material of the organic semiconductor layer, those conventionally used for the organic semiconductor layer of the FET can be used. For example, a low molecular organic semiconductor material such as pentacene, tetracene, anthracene, or phthalocyanine, or a high molecular semiconductor material such as polythiophene, polyacene, polyacetylene, or polyaniline can be used. Conventionally known methods can be used for forming the organic semiconductor layer. For example, it may be formed by a method such as vapor deposition, coating, sputtering, sol-gel method, or printing.
有機半導体層の厚さは特に制限されないが、一般的には10nm以上、500μm以下程度とすることができる。この範囲であれば、電極間での短絡を確実に防止できる一方で、有機半導体層が過剰に厚くならず余分なコストがかからない。 The thickness of the organic semiconductor layer is not particularly limited, but can generally be about 10 nm or more and 500 μm or less. If it is this range, while being able to prevent a short circuit between electrodes reliably, an organic-semiconductor layer does not become excessively thick and extra cost does not start.
有機半導体層上にはソース電極とドレイン電極を形成する。これら電極は、ゲート電極と同様に形成することができる。或いは、あらかじめゲート絶縁膜直上にソース電極とドレイン電極を形成し、その後、有機半導体層を形成してもよい。 A source electrode and a drain electrode are formed on the organic semiconductor layer. These electrodes can be formed in the same manner as the gate electrode. Alternatively, the source electrode and the drain electrode may be formed directly on the gate insulating film in advance, and then the organic semiconductor layer may be formed.
本発明のFETは、基板もチャネル層も有機材料で形成されていることから軽量で且つ薄膜化も可能であり、フレキシブルである。その上、基板としてガスバリア性に優れる液晶ポリマーフィルムが用いられていることから内部への水分やガスの浸入が抑制されており、また、熱履歴を受けても寸法安定性に優れる。よって本発明のFETは、水分などによる有機半導体の劣化が抑制されているので長寿命であり、且つ大画面の有機ELディスプレイ装置などの電子部品として適するものである。 Since the FET and the channel layer of the present invention are made of an organic material, they are lightweight and can be made thin, and are flexible. In addition, since a liquid crystal polymer film having excellent gas barrier properties is used as the substrate, the intrusion of moisture and gas into the inside is suppressed, and the dimensional stability is excellent even when subjected to a thermal history. Therefore, the FET of the present invention has a long life because deterioration of the organic semiconductor due to moisture or the like is suppressed, and is suitable as an electronic component such as a large screen organic EL display device.
以下、実施例を挙げて本発明をより具体的に説明するが、本発明はもとより下記実施例により制限を受けるものではなく、前・後記の趣旨に適合し得る範囲で適当に変更を加えて実施することも可能であり、それらはいずれも本発明の技術的範囲に含まれる。 EXAMPLES Hereinafter, the present invention will be described more specifically with reference to examples. However, the present invention is not limited by the following examples, but may be appropriately modified within a range that can meet the purpose described above and below. It is also possible to implement, and they are all included in the technical scope of the present invention.
実施例1 本発明に係るFETの製造
縦100mm×横100mm×厚さ125μmの液晶ポリマーフィルム(ジャパンゴアテックス製、BIAC BC125)の上下を、離型フィルムとして十分に大きな20μm厚ポリイミドフィルム(宇部興産製、ユーピレックス20S)で挟み、真空熱プレス装置を用いて290℃、3MPaの条件で5分間加熱加圧することによって、表面平滑化処理を行った。得られた表面平滑化液晶ポリマーフィルムの粗度(Ra)をレーザー顕微鏡(オリンパス製、OLS3000)により測定した。具体的には、レーザー種としてλ=408±5nmの半導体レーザーを用い、Z方向の移動分解能を0.01μmに設定して、192μm×256μmの範囲におけるZ方向の粗さを0.1μmピッチで50倍の共焦点モードで測定した。その結果、粗度(SRa)は20nmであった。
Example 1 Manufacture of FET according to the present invention A 20 μm thick polyimide film (Ube Industries, Ltd.) large enough as a release film on the top and bottom of a liquid crystal polymer film (Japan Gore-Tex, BIAC BC125) of 100 mm long × 100 mm wide × 125 μm thick And smoothing treatment was performed by heating and pressurizing at 290 ° C. and 3 MPa for 5 minutes using a vacuum hot press apparatus. The roughness (Ra) of the obtained surface smoothed liquid crystal polymer film was measured with a laser microscope (OLS3000, manufactured by Olympus). Specifically, a semiconductor laser of λ = 408 ± 5 nm is used as the laser type, the moving resolution in the Z direction is set to 0.01 μm, and the roughness in the Z direction in the range of 192 μm × 256 μm is set at a pitch of 0.1 μm. Measurements were made in a 50 × confocal mode. As a result, the roughness (SRa) was 20 nm.
また、上記液晶ポリマーフィルムの線膨張係数を以下の通り測定した。即ち、液晶ポリマーフィルムを幅4.5mmに切り取り、チャック間距離:15mmで装置(TAインストロメンツ製、TMA2940)に固定し、荷重:1g、昇温速度:5℃/分で室温から200℃まで昇温後に降温速度:5℃/分で冷却する際に、160℃から25℃の間で測定される試験片の寸法変化を測定した。その結果、TD方向の線膨張係数は16ppm/℃、MD方向の線膨張係数は16ppm/℃であった。 Moreover, the linear expansion coefficient of the liquid crystal polymer film was measured as follows. That is, a liquid crystal polymer film was cut into a width of 4.5 mm, fixed to an apparatus (TA Instruments, TMA2940) with a distance between chucks: 15 mm, a load: 1 g, a heating rate: 5 ° C./min. When the temperature was lowered to a temperature lowering rate of 5 ° C./min, the dimensional change of the test piece measured between 160 ° C. and 25 ° C. was measured. As a result, the linear expansion coefficient in the TD direction was 16 ppm / ° C., and the linear expansion coefficient in the MD direction was 16 ppm / ° C.
上記表面平滑化液晶ポリマーフィルムを32mm×25mmに切断した。その片面に、メタルマスクを用いた真空蒸着法で縦幅30μm×横長さ25mm×厚さ0.2μmのアルミニウム薄膜層を形成し、これをゲート電極とした。当該ゲート電極上へ、スパッタリングにより厚さ100nmのSiO2薄膜を形成してゲート絶縁層とした。さらに当該ゲート絶縁層上に、真空蒸着法によりペンタセンからなる厚さ100nmの有機半導体層を形成した。当該有機半導体層上に、スパッタリング装置を用い、チャネル幅10mm、チャネル長さ30μmの金からなるソース電極とドレイン電極を形成した。ソース電極とドレイン電極を形成した有機半導体層上に、スパッタリング装置を用い、SiO2からなる厚さ100nmの封止層を形成した。 The surface smoothed liquid crystal polymer film was cut into 32 mm × 25 mm. On one side, an aluminum thin film layer having a vertical width of 30 μm × horizontal length of 25 mm × thickness of 0.2 μm was formed by vacuum deposition using a metal mask, and this was used as a gate electrode. A SiO 2 thin film having a thickness of 100 nm was formed on the gate electrode by sputtering to form a gate insulating layer. Further, an organic semiconductor layer made of pentacene and having a thickness of 100 nm was formed on the gate insulating layer by a vacuum deposition method. A source electrode and a drain electrode made of gold having a channel width of 10 mm and a channel length of 30 μm were formed on the organic semiconductor layer using a sputtering apparatus. A sealing layer made of SiO 2 and having a thickness of 100 nm was formed on the organic semiconductor layer on which the source electrode and the drain electrode were formed, using a sputtering apparatus.
比較例1
有機材料基板として液晶ポリマーフィルムの代わりに厚さ125μmのポリイミドフィルム(宇部興産製、ユーピレックス125S)を用いた以外は上記実施例1と同様にしてFETを製造した。
Comparative Example 1
An FET was manufactured in the same manner as in Example 1 except that a 125 μm-thick polyimide film (Ube Industries, Upilex 125S) was used instead of the liquid crystal polymer film as the organic material substrate.
試験例1 透湿度の測定
JIS K7129Bで定められた等圧法(MOCON法)に従い、ガスとしてO2ガスを用いて各有機EL素子の透湿度を求めた。結果を表1に示す。なお、表1中の「LCP」は液晶ポリマーを示し、「PI」はポリイミドを示す。
Test Example 1 Measurement of moisture permeability The moisture permeability of each organic EL element was determined using O 2 gas as a gas according to the isobaric method (MOCON method) defined in JIS K7129B. The results are shown in Table 1. In Table 1, “LCP” indicates a liquid crystal polymer, and “PI” indicates polyimide.
試験例2 電界効果移動度の測定
実施例1および比較例1で製造したFETを常温常圧下で放置し、作成から2時間後と720時間経過後に所定のゲート電圧を印加し、下記式により各FETの電界効果移動度(μ)を求めた。結果を表1に示す。
μ=2LIds/WCi(Vg−Vth)2
[式中、Lはチャネル長、Idsは飽和領域におけるドレイン電流値、Wはチャネル幅、Ciはゲート絶縁膜の単位面積あたりの容量、Vgはゲート電圧、Vthは閾値電流を示す]
Test Example 2 Measurement of Field Effect Mobility The FETs manufactured in Example 1 and Comparative Example 1 were allowed to stand at room temperature and normal pressure, a predetermined gate voltage was applied after 2 hours and 720 hours from the preparation, The field effect mobility (μ) of the FET was determined. The results are shown in Table 1.
μ = 2LI ds / WC i (V g −V th ) 2
[In the formula, L is the channel length, I ds is the drain current value in the saturation region, W is the channel width, C i is the capacitance per unit area of the gate insulating film, V g is the gate voltage, and V th is the threshold current. ]
表1の通り、ポリイミドからなる基板のガスバリア性は低く、当該基板を用いたFETの電界移動度は時間の経過に伴って低下した。一方、液晶ポリマーフィルムのガスバリア性は高いことから液晶ポリマーフィルムを基板とするFETは耐久性に優れ、空気中で製造から720時間放置した後の性能もほとんど低下していなかった。よって、本発明に係るFETの優れた特性が実証された。 As shown in Table 1, the gas barrier property of the substrate made of polyimide was low, and the electric field mobility of the FET using the substrate decreased with the passage of time. On the other hand, since the gas barrier property of the liquid crystal polymer film is high, the FET having the liquid crystal polymer film as a substrate is excellent in durability, and the performance after being left in the air for 720 hours after production was hardly deteriorated. Therefore, the excellent characteristics of the FET according to the present invention were demonstrated.
1:液晶ポリマー基板、 2:ゲート電極、 3:ゲート絶縁層、 4:有機半導体層、 5:ソース電極、 6:ドレイン電極 1: liquid crystal polymer substrate, 2: gate electrode, 3: gate insulating layer, 4: organic semiconductor layer, 5: source electrode, 6: drain electrode
Claims (3)
当該基板が、下記式(1)で表されるI型サーモトロピック液晶ポリエステルまたは下記式(2)で表されるII型サーモトロピック液晶ポリエステルの液晶ポリマーフィルムからなり、
The substrate comprises a liquid crystal polymer film of type I thermotropic liquid crystal polyester represented by the following formula (1) or type II thermotropic liquid crystal polyester represented by the following formula (2) :
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