JP5326830B2 - Level shift circuit - Google Patents

Description

  The present invention relates to a level shift circuit for transmitting a logic value signal from a primary-side potential system to a secondary-side potential system having a higher potential than the primary-side potential system.

A first configuration example of a conventional level shift circuit is shown in FIG. FIG. 4 shows a level shift circuit disclosed in Japanese Patent Application Laid-Open No. 2007-174627 (Patent Document 1) filed prior to the present application by the present applicant.
The level shift circuit shown in FIG. 4 includes an input circuit 10 and a latch circuit 20.
The input circuit 10 includes a pulse generation circuit 11 that operates between a primary high potential V1H and a primary low potential V1L, and N-channel MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) M11 and M12. The
The pulse generation circuit 11 receives the input signal IN and outputs an output signal O1 and an output signal O2. The output signal O1 of the pulse generation circuit 11 is connected to the gate of the N-channel MOSFET M11, and the output signal O2 of the pulse generation circuit 11 is connected to the gate of the N-channel MOSFET M12. The sources of the N-channel MOSFETs M11 and M12 are connected to the primary low potential V1L, and the drains are connected to the inputs N1 and N2 of the latch circuit 20, respectively.

The latch circuit 20 includes inverters U21 and U22 that operate between a secondary high potential V2H and a secondary low potential V2L, and resistors R21 and R22.
The input N1 of the latch circuit 20 is connected to the input of the inverter U21 and is connected to the output of the inverter U22 via the resistor R22. The input N2 of the latch circuit 20 is connected to the input of the inverter U22, and is connected to the output of the inverter U21 via the resistor R21. The output of the inverter U22 becomes the output OUT of the latch circuit 20.
Here, FIG. 5 and FIG. 6 will be described. FIG. 5 shows a specific configuration of the pulse generation circuit 11 in FIG. 4, and FIG. 6 shows input / output operation waveforms of the pulse generation circuit 11.
As shown in FIG. 5, the pulse generation circuit 11 includes a delay circuit D1 configured by connecting four stages of inverters U1 to U4 in series, inverters U5 and U6, and two-input NOR circuits U7 and U8. The output signals O1 and O2 are generated from the input signal IN and output.

The output signal O1 is input from a two-input NOR circuit U7 having the input signal IN as a first input and an inverted signal obtained by delaying the input signal IN through the delay circuit D1 and the inverter U5 for a predetermined time as a second input. Is output. The output signal O2 is obtained from a two-input NOR circuit U8 having a first input of an inverted signal of the input signal IN by the inverter U6 and a second input of a signal obtained by delaying the input signal IN by the delay circuit D1 for a predetermined time. Is output.
The pulse generation circuit 11 having such a configuration generates and outputs a signal having a minute pulse width synchronized with the rising and falling of the input signal IN, as in the input / output operation waveform shown in FIG. That is, a minute pulse signal synchronized with the falling edge of the input signal IN is output as the output signal O1, and a minute pulse signal synchronized with the rising edge of the input signal IN is output as the output signal O2. The minute pulse width is determined by the delay time set by the delay circuit D1.

Based on the operation of the pulse generation circuit 11 described above, the operation of the level shift circuit shown in FIG. 4 will be described.
When the input signal IN to the input circuit 10 rises from the L level (V1L) to the H level (V1H), a minute pulse is input from the output signal O2 of the pulse generation circuit 11 to the gate of the N-channel MOSFET M12, and M12 is turned on for a minute time. To do. Then, the potential of the input N2 of the latch circuit 20 decreases (V1L), the output of the inverter U22 becomes H level (V2H), and the output of the inverter U21 becomes L level (V2L). That is, the output OUT of the latch circuit 20 becomes H level.
On the other hand, when the input signal IN to the input circuit 10 falls from the H level (V1H) to the L level (V1L), a minute pulse from the output signal O1 of the pulse generation circuit 11 is input to the gate of the N-channel MOSFET M11, and M11 is Turns on for a short time. Then, the potential of the input N1 of the latch circuit 20 decreases (V1L), the output of the inverter U21 becomes H level (V2H), and the output of the inverter U22 becomes L level (V2L). That is, the output OUT of the latch circuit 20 becomes L level.

As described above, the level shift circuit shown in FIG. 4 operates only for a very short time of rising and falling of the input signal IN, and in a steady state where there is no potential change, the N-channel MOSFETs M11 and M12 are in an off state and have low power consumption. It is the composition which realizes.
However, if the primary power supply (V1H, V1L) is delayed from the secondary power supply (V2H, V2L), the input signal IN is not determined and the inputs N1 and N2 of the latch circuit 20 are also undefined. The output OUT of the latch circuit 20 becomes indefinite.
Next, FIG. 7 will be described. FIG. 7 shows a second configuration example of a conventional level shift circuit, which is disclosed in Patent Document 2. In FIG.
The circuit shown in FIG. 7 includes an input circuit 10a, a latch circuit 20a, and initial value setting circuits 131 and 132. Unlike the first configuration example shown in FIG. 4, the primary low potential V1L The low potential V2L on the secondary side is set to the same potential and connected to the reference potential GND.

The input circuit 10a includes inverters U11 and U12 that operate between a primary high potential V1H and a reference potential GND, and N-channel MOSFETs M11 and M12.
The inverter U11 receives the input signal IN and outputs its logical inversion signal. The output of the inverter U11 is connected to the gate of the N-channel MOSFET M11 and the input of the inverter U12. The inverter U12 outputs a signal in phase with the input signal IN and inputs it to the gate of the N-channel MOSFET M12. N-channel MOSFETs M11 and M12 have sources connected to reference potential GND and drains connected to inputs N1a and N2a of latch circuit 20a, respectively. The input circuit 10a has a configuration in which the pulse generation circuit 11 is omitted from the input circuit 10 of FIG. 4 and the outputs of the inverters U11 and U12 are directly input to the gates of the N-channel MOSFETs M11 and M12.

The latch circuit 20a includes inverters U21 and U22 that operate between the secondary high potential V2H and the reference potential GND.
The inverter U21 is composed of a P-channel MOSFET M21 and an N-channel MOSFET M22 connected in series between the secondary high potential V2H and the reference potential GND, and the gates of both are commonly connected to the input N1a of the latch circuit 20a. It has become. The input N1a is connected to the drain of the N-channel MOSFET M11 and the output of the inverter U22, and to the initial value setting circuit 131. The inverter U22 includes a P-channel MOSFET M23 and an N-channel MOSFET M24 connected in series between the secondary high potential V2H and the reference potential GND, and the gates of both are commonly connected to the input N2a of the latch circuit 20a. It has become. The input N2a is connected to the drain of the N-channel MOSFET M12 and the output of the inverter U21, and to the initial value setting circuit 132. The output of the inverter U22 becomes the output OUT of the latch circuit 20a.

The initial value setting circuit 131 includes a P-channel MOSFET M3H whose gate and source are connected to the secondary high potential V2H and whose drain is connected to the input N1a of the latch circuit 20a. The initial value setting circuit 132 includes an N-channel MOSFET M3L whose gate and source are connected to the reference potential GND and whose drain is connected to the input N2a of the latch circuit 20a.
The operation of the level shift circuit shown in FIG. 7 configured as described above will be described.
First, the steady state operation in which the primary power supply V1H and the secondary power supply V2H are supplied will be described.
The P-channel MOSFET M3H of the initial setting circuit 131 is turned off because the gate and source are connected to the secondary side high potential V2H. Similarly, the N-channel MOSFET M3L of the initial value setting circuit 132 is also turned off because the gate and source are connected to the reference potential GND.

Therefore, the latch circuit 20a outputs a signal corresponding to the input signal IN from the output OUT. That is, when the input signal IN is at the H level (V1H), the N-channel MOSFET M11 is turned off and M12 is turned on. Then, the potential of the input N2a of the latch circuit 20a is lowered (GND), the output of the inverter U22 is H level (V2H), and the output of the inverter U21 is L level (GND). That is, the output OUT of the latch circuit 20a becomes H level.
On the other hand, when the input signal IN is L level (GND), the N-channel MOSFET M11 is turned on and M12 is turned off. Then, the potential of the input N1a of the latch circuit 20a decreases (GND), the output of the inverter U21 becomes H level (V2H), and the output of the inverter U22 becomes L level (GND). That is, the output OUT of the latch circuit 20a becomes L level.

Next, the operation when the primary side power-on (V1H, GND) is later than the secondary side power-on (V2H, GND) and the input signal IN is not fixed will be described.
The power supply voltage (V2H-GND potential) on the secondary side is higher than the voltage (threshold voltage: for example, 0.5 to 1.0 V) at which the MOSFETs M21, M22, M23, and M24 constituting the latch circuit 20a start operating. At a low voltage, leakage currents (off-leakage currents) flow through the initial setting MOSFETs M3H and M3L which are in the off state. The off-leakage current determines the potentials of the inputs N1a and N2a of the latch circuit 20a. That is, the input N1a to which the P-channel MOSFET M3H is connected becomes H level (V2H), and the input N2a to which the N-channel MOSFET M3L is connected becomes L level (GND). In this state, when the secondary-side high potential power supply V2H further rises, the inputs N1a and N2a also rise while holding this potential. Thereby, the output of the inverter U21 becomes L level (GND), and the output of the inverter U22 becomes H level (V2H). That is, the output OUT of the latch circuit 20a is set to the H level (V2H), and the initial state is determined.

  In addition, when the primary side power supply potential (V1H, GND) is turned on in this initial state, the operation is the same as that in the above-described steady state, and thus the description thereof is omitted.

JP 2007-174627 A JP 2008-17456 A

The conventional level shift circuit described above has the following desirable improvements.
First, in the first configuration example shown in FIG. 4, low power consumption is realized in the steady state, but the primary side power-on (V1H, V1L) is delayed from the secondary side power-on (V2H, V2L). In this case, since the input signal IN is not fixed and the inputs N1 and N2 of the latch circuit 20 are also undefined, the output OUT of the latch circuit 20 is undefined.
In the second configuration example shown in FIG. 7, even if the primary side power-on (V1H, V1L) is delayed from the secondary side power-on (V2H, V2L), an initial value setting circuit is provided. Although the state of the output OUT of the latch circuit 20a is set, there is a problem that the accuracy of the initial setting operation is low because the circuit configuration uses the threshold value of the MOSFET and the off-leakage current.

That is, the threshold voltage and off-leakage current of the MOSFET vary greatly depending on variations in the manufacturing process, power supply voltage to be used, rise time, and temperature conditions. Therefore, the relative relationship between the MOSFET constituting the inverter and the MOSFET constituting the initial value setting circuit is relatively small. The logical operation is determined by the characteristic comparison, and it is difficult to guarantee the desired initial setting operation.
Furthermore, in the second configuration example shown in FIG. 7, the N-channel MOSFETs M11 and M12 that transmit signals from the primary-side potential system to the secondary-side potential system perform complementary on / off operations according to the input signal IN. Therefore, there is no problem when the primary low potential V1L and the secondary low potential V2L are the same potential, but there is a problem when operating at different potentials as in the configuration shown in FIG. That is, in the N-channel MOSFET that constitutes the N-channel MOSFET M11 or M12 and the inverter U21 or U22, between the primary low potential V1L and the secondary low potential V2L via the MOSFET that is turned on, from the high potential side. There is a problem that a continuous path through which current flows to the lower potential side is formed. For example, when V2L> V1L and the input signal IN is at the H level, the MOSFETs M12 and M22 are turned on, and a continuous current path of V2L → M22 → M12 → V1L is formed. That is, the second configuration example shown in FIG. 7 cannot be used when the primary-side low potential V1L and the secondary-side low potential V2L are different.

  The present invention has been made in view of the above-described problems, and the problem to be solved can be used even when the low potential V1L on the primary side and the low potential V2L on the secondary side are different, and It is an object of the present invention to provide a level shift circuit that ensures the determination of an output state even when power is turned on.

In order to solve the above-described problem, according to the level shift circuit of claim 1, a logic value signal is transmitted from the primary-side potential system to the secondary-side potential system having a higher potential than the primary-side potential system. A level shift circuit, wherein the first and second inverters operating in the secondary-side potential system are connected in a circular manner by connecting resistors between their inputs and outputs; First and second MOSFETs connected between inputs of the first and second inverters and a low-potential-side reference potential of the primary-side potential system; and the first and second inverters An initial value setting circuit connected to at least one of the inputs, and as the initial value setting circuit, one of the inputs of the first and second inverters and the high potential side of the potential system on the secondary side Connected between the first and the second Between the first parallel circuit in which the resistor and the first capacitor are connected in parallel, and the other input of the first and second inverters and the low potential side potential of the secondary potential system At least one of a connected second resistor and a second parallel circuit in which a second capacitor is connected in parallel is provided.

Further, according to the level shift circuit according to claim 2, wherein said level shift circuit, the work on the primary side of the potential system, first generates a first pulse signal with the rising of the logic value signal A pulse that inputs a pulse signal to the gate of the first MOSFET, generates a second pulse signal at the falling edge of the logical value signal, and inputs the second pulse signal to the gate of the second MOSFET A generation circuit is provided.

According to the level shift circuit of claim 3 , the pulse generation circuit includes a delay circuit that outputs a signal obtained by delaying the logic value signal for a predetermined time, and outputs the logic value signal and the output of the delay circuit. The first pulse signal is generated by a logical product with an inverted signal, and the second pulse signal is generated by a logical product of an inverted signal of the logical value signal and an output signal of the delay circuit. .

  In the level shift circuit according to the present invention, an input circuit that operates in a primary-side potential system is composed of a pulse generation circuit and two N-channel MOSFETs, and a latch circuit that operates in a secondary-side potential system is connected between two inverters. The input / output of the inverter is connected in a ring through a resistor, and has an initial value setting circuit that sets the secondary side to a high or low potential, and the input of at least one inverter is connected to the initial value setting circuit Thus, low power consumption in a steady state is realized, and the output state is guaranteed to be confirmed even when the power is turned on.

It is a figure which shows the 1st reference example of the level shift circuit which concerns on this invention. It is a figure which shows the 2nd reference example of the level shift circuit which concerns on this invention. It is a figure which shows the Example of the level shift circuit which concerns on this invention. It is a figure which shows the 1st structural example of the conventional level shift circuit. 2 is a diagram illustrating a specific configuration of a pulse generation circuit 11. FIG. 3 is a diagram showing input / output operation waveforms of a pulse generation circuit 11. FIG. It is a figure which shows the 2nd structural example of the conventional level shift circuit.

Reference example 1

Hereinafter, a level shift circuit according to an embodiment of the present invention will be described with reference to the drawings.
FIG. 1 is a block diagram showing a first reference example of the level shift circuit according to the present invention. The same parts as those in the conventional circuit example shown in FIGS. 4 and 7 are denoted by the same reference numerals, and detailed description thereof is omitted.
The level shift circuit shown in FIG. 1 includes an input circuit 10, a latch circuit 20, and initial value setting circuits 31, 32, and initial value setting circuits 31, 32 are added to the conventional level shift circuit shown in FIG. It becomes the composition.
The initial value setting circuit 31 includes a resistor RH having one end connected to the secondary high potential V2H and the other end connected to the input N1 of the latch circuit 20. The initial value setting circuit 32 includes a resistor RL having one end connected to the secondary low potential V2L and the other end connected to the input N2 of the latch circuit 20.

Here, when inverters U21 and U22 are each constituted by a CMOS inverter, the resistance values of resistors RH and RL (respective resistance values are also indicated as RH and RL), N-channel MOSFETs M11 and M12, and inverters U21 and U22 are configured. The on-resistance (Ron) of the MOSFET is set so as to satisfy the following expressions (1) to (4).
RH >> Ron (U22; NMOS) + R22 (1)
RL >> Ron (U21; PMOS) + R21 (2)
Ron (M11) << Ron (U22; PMOS) + R22 (3)
Ron (M12) << Ron (U21; PMOS) + R21 (4) Here, Ron (M11) and Ron (M12) mean the on-resistances of the N-channel MOSFETs M11 and M12, respectively, and Ron (U22; NMOS) ) Means the on-resistance of the N-channel MOSFET constituting the inverter U22, and Ron (U21; PMOS) and Ron (U22; PMOS) mean the on-resistance of the P-channel MOSFET constituting the inverters U21 and U22, respectively. The resistance values of the resistors R21 and R22 are also indicated as R21 and R22.

The specific configuration and input / output operation waveforms of the pulse generation circuit 11 are the same as those shown in FIGS. 5 and 6 showing the configuration and input / output waveforms of the pulse generation circuit 11 in the conventional level shift circuit shown in FIG. Is omitted.
The operation of the level shift circuit shown in FIG. 1 configured as described above will be described.
First, the operation in a steady state in which the primary power supply potentials V1H and V1L and the secondary power supply potentials V2H and V2L are supplied will be described.
When the above expressions (1) to (4) are satisfied, the resistance RH of the initial value setting circuit 31 and the resistance RL of the initial value setting circuit 32 can be ignored in a steady state. Therefore, the operation is the same as that of the conventional level shift circuit shown in FIG.
That is, when the input signal IN to the input circuit 10 rises from the L level (V1L) to the H level (V1H), a minute pulse is input from the output signal O2 of the pulse generation circuit 11 to the gate of the N-channel MOSFET M12, and M12 is minute. Turn on time. Then, the potential of the input N2 of the latch circuit 20 decreases (V1L), the output of the inverter U22 becomes H level (V2H), and the output of the inverter U21 becomes L level (V2L). That is, the output OUT of the latch circuit 20 becomes H level.

On the other hand, when the input signal IN to the input circuit 10 falls from the H level (V1H) to the L level (V1L), a minute pulse from the output signal O1 of the pulse generation circuit 11 is input to the gate of the N-channel MOSFET M11, and M11 is Turns on for a short time. Then, the potential of the input N1 of the latch circuit 20 decreases (VL1), the output of the inverter U21 becomes H level (V2H), and the output of the inverter U22 becomes L level (V2L). That is, the output OUT of the latch circuit 20 becomes L level.
Next, an operation when the primary side power-on (V1H, V1L) is later than the secondary side power-on (V2H, V1L) and the input signal IN is not fixed will be described.
When the power supply potential (V2H, V2L) on the secondary side is turned on, the input N1 of the latch circuit 20 rises to H level (V2H) by the resistance RH of the initial value setting circuit 31, and the resistance of the initial value setting circuit 32 Due to the RL, the input N2 of the latch circuit 20 is lowered to the L level (V2L).

In this state, when the secondary side power supply voltage (the potential between V2H and V2L) rises above the voltage (threshold voltage: 0.5 to 1.0 V) at which the inverters U21 and U22 operate, the input N1 also This potential rises while holding it, and this value (the logic value H of the input N1) is latched by the latch circuit 20. That is, the output of the inverter U21 is L level (V2L), and the output of the inverter U22 is H level (V2H). As a result, the output OUT of the latch circuit 20 is set to the H level (V2H), and the initial state is determined.
It should be noted that if the primary power supply potential (V1H, V1L) is turned on in this initial state, the operation is the same as in the steady state described above, and the description thereof is omitted.
As described above, in the level shift circuit shown in FIG. 1, the N-channel MOSFETs M11 and M12 are OFF in the steady state where the input signal IN has no potential change, and the output OUT is at the L level. Excluding the minute current that flows from V2H to V2L through resistors RH and R22 and the N-channel MOSFET of inverter U21 that is on, and the minute current that flows from the output (H level) of inverter U21 to V2L via resistors R21 and RL Low power consumption can be achieved with a circuit configuration that does not consume current constantly. If the input signal IN is not determined later than the primary power supply (V1H, V1L) than the secondary power supply (V2H, V1L), set the resistance values of the resistors RH and RL of the initial value setting circuit appropriately. By setting, the output state of the latch circuit can be set reliably, and a low power consumption level shift circuit can be realized with a simple circuit configuration without being affected by manufacturing variations and operating conditions.

In particular, the level shift circuit shown in FIG. 1 has an initial setting operation when the rising speed of the secondary power supply voltage (the potential between V2H and V2L) is slow because the initial value setting circuits 31 and 32 are configured by resistors. It becomes suitable for.
Although FIG. 1 shows the level shift circuit including the initial value setting circuits 31 and 32, the level shift circuit including either one may be embodied. Further, the connection between the initial value setting circuits 31 and 32 and the inputs N1 and N2 may be changed.

Reference example 2

FIG. 2 is a block diagram showing a second reference example of the level shift circuit of the present invention. The same parts as those in the first reference example shown in FIG. 1 and the conventional circuit examples shown in FIGS. 4 and 7 are denoted by the same reference numerals, and detailed description thereof is omitted.
The circuit shown in FIG. 2 includes an input circuit 10, a latch circuit 20, and initial value setting circuits 31a and 32a. The configurations and operations of the input circuit 10 and the latch circuit 20 are the same as those in FIG.
The initial value setting circuit 31a includes a capacitor CH having one end connected to the secondary high potential V2H and the other end connected to the input N1 of the latch circuit 20. The initial value setting circuit 32a includes a capacitor CL having one end connected to the secondary low potential V2L and the other end connected to the input N2 of the latch circuit 20.

In addition, in order to apply a capacity | capacitance to an initial value setting circuit, it is necessary to consider parasitic capacitances, such as the gate capacity | capacitance of MOSFET and wiring capacity. Therefore, the parasitic capacitance 21 including the gate capacitance of the inverter U21 connected to the input N1 is changed between the parasitic capacitance CP1 between the input N1 and the secondary side high potential V2H and between the input N1 and the secondary side low potential V2L. This is shown in FIG. 2 divided into parasitic capacitance CN1. Similarly, the parasitic capacitance 22 connected to the input N2 including the gate capacitance of the inverter U22 is connected between the parasitic capacitance CP2 between the input N2 and the secondary side high potential V2H and between the input N2 and the secondary side low potential V2L. This is shown in FIG.
Here, the capacitance values CH and CL of the initial value setting circuit (also referred to as CH and CL) are the capacitance values of the parasitic capacitances (CP1, CN1, CP2, and CN2) (also CP1, CN1, and CP2). , CN2), and the capacitance value ratio (hereinafter simply referred to as the capacitance ratio) is set so as to satisfy the following equation.

(CH + CP1) / CN1> CP2 / (CL + CN2) (5)
The operation of the level shift circuit shown in FIG. 2 configured as described above will be described.
First, the operation in a steady state in which the primary power supply potentials V1H and V1L and the secondary power supply potentials V2H and V2L are supplied will be described.
In the steady state, the capacitance CH of the initial value setting circuit 31a, the capacitance CL of the initial value setting circuit 32a, and the parasitic capacitances 21 (CP1, CN1) and 22 (CP2, CN2) can be ignored, and are the same as those in FIG. It becomes the operation. Therefore, further explanation is omitted.
Next, an operation when the primary side power-on (V1H, V1L) is later than the secondary side power-on (V2H, V1L) and the input signal IN is not fixed will be described.
When the secondary side power supply voltage (the potential between V2H and V2L) is turned on, the input N1 of the latch circuit 20 divides the power supply voltage by the capacity ratio between the capacitance CH of the initial value setting circuit 31a and the parasitic capacitances CP1 and CN1. The input N2 is a potential obtained by dividing the power supply voltage by the capacitance ratio between the capacitance CL of the initial value setting circuit 32a and the parasitic capacitances CP2 and CN2. Here, since the capacitance ratio is set as shown in equation (5), the potentials of the inputs N1 and N2 of the latch circuit 20 have a relationship of (potential of input N1)> (potential of input N2). (Note: Since it is a partial pressure, it does not reach the value of V2H or V2L, and becomes an intermediate potential)
In this state, when the secondary-side power supply voltage (the potential between V2H and V2L) rises above the voltage (threshold voltage: for example, 0.5 to 1.0 V) at which inverters U21 and U22 operate, input N1 and N2 also rises while maintaining the above relationship, and based on this, the state of the latch circuit 20 is determined. That is, the output of the inverter U21 is L level (V2L), and the output of the inverter U22 is H level (V2H). As a result, the output OUT of the latch circuit 20 is set to the H level (V2H), and the initial state is determined.

It should be noted that if the primary power supply potential (V1H, V1L) is turned on in this initial state, the operation is the same as in the steady state described above, and the description thereof is omitted.
As described above, the level shift circuit shown in FIG. 2 is in the initial state even when the input signal IN is not fixed after the primary side power-on (V1H, V1L) is slower than the secondary side power-on (V2H, V1L). By appropriately setting the capacitance ratio between the capacitance (CH, CL) of the value setting circuit and the parasitic capacitance (CP1, CN1, CP2, CN2), it becomes possible to reliably set the output state of the latch circuit, resulting in manufacturing variations. A level shift circuit with low power consumption can be realized with a simple circuit configuration without being affected by the operating conditions.
In particular, in the level shift circuit shown in FIG. 2, since the initial value setting circuits 31a and 32a are configured only by capacitors, delay elements due to combinations of resistors and capacitors can be eliminated, and the secondary side power supply voltage ( This is suitable for the initial setting operation when the rise of the potential between V2H and V2L is steep.

Although FIG. 2 shows the level shift circuit including the initial value setting circuits 31a and 32a, the level shift circuit including either one may be embodied. Further, the connection between the initial value setting circuits 31a and 32a and the inputs N1 and N2 may be changed.
The level shift circuit shown in FIG. 2 only needs to satisfy the equation (5) for the capacitance ratio. Therefore, the capacitors CH and CL of the initial value setting circuit are not provided individually, and only the parasitic capacitances CP1 and CN2 are (5 ) The gate capacities of the inverters U21 and U22 may be set so as to satisfy the equation.

FIG. 3 is a block diagram showing an embodiment of the level shift circuit of the present invention. The same parts as those in the reference example shown in FIGS. 1 and 2 are denoted by the same reference numerals, and detailed description thereof is omitted.
The level shift circuit shown in FIG. 3 is configured by combining FIG. 1 and FIG. That is, the input circuit 10 and the latch circuit 20 are the same as those in FIG. 1 and FIG. 2, and the initial value setting circuits 31b and 32b are the resistors (RH and RL) shown in FIG. In addition, the resistor RH and the capacitor CH, and the resistor RL and the capacitor CL are connected in parallel using both of the capacitors (CH and CL). The resistance and capacitance are set so as to satisfy the above-described equations (1) to (5).
The level shift circuit shown in FIG. 3 configured as described above selectively uses the operation described in FIGS. 1 and 2 depending on the rising speed of the power supply voltage (V2H-V2L potential) on the secondary side.

When the primary side power-on (V1H, V1L) is slower than the secondary side power-on (V2H, V1L), the operation effect of the initial value setting circuits 31b and 32b is different due to the difference in the rising speed of the secondary-side power supply voltage. Different. That is, when the rising speed is slow, the current flowing through the capacitor is ignored, the current flowing through the resistor is dominant, and the potentials of the inputs N1 and N2 are set. On the other hand, when the rising speed is fast, the current flowing through the capacitor becomes dominant, and the potentials of the inputs N1 and N2 are set by the divided voltage of the capacitance ratio.
As described above, the level shift circuit shown in FIG. 3 is not affected by the rise time of the secondary side power supply when the power supply on the secondary side is slower than the power supply on the primary side, and the output state of the latch circuit is not affected. A level shift circuit with low power consumption can be realized with a simple circuit configuration without being affected by manufacturing variations, operating conditions, and rise time of the secondary power supply.

Although FIG. 3 shows the level shift circuit including the initial value setting circuits 31b and 32b, the level shift circuit including either one may be embodied. Further, the connection between the initial value setting circuits 31b and 32b and the inputs N1 and N2 may be changed. Further, the capacitance of the initial value setting circuit may be set with only a parasitic capacitance.
Although the embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments, and various improvements and modifications can be made without departing from the scope of the present invention.

10, 10a Input circuit 11 Pulse generation circuit 20, 20a Latch circuit 21, 22 Equivalent circuit showing parasitic capacitance 31, 32, 31a, 32a, 31b, 32b, 131, 132 Initial value setting circuit CH, CL capacitance or capacitance value thereof CP1, CP2, CN1, CN2 Parasitic capacitance or its parasitic capacitance value D1 Delay circuit GND Reference power supply terminal or its potential IN Input signal M11, M12 N-channel MOSFET
M21, M23, M3H P-channel MOSFET
M22, M24, M3L N-channel MOSFET
N1, N2, N1a, N2a Input of latch circuit O1, O2 Output signal of pulse generation circuit OUT Output of latch circuit R21, R22 Resistor or its resistance value RH, RL Resistance or its resistance value Ron On resistance value of MOSFET U1, U2 , U3, U4, U5, U6 Inverter U7, U8 NOR circuit U11, U12, U21, U22 Inverter V1H Primary side high potential power supply terminal or its potential V1L Primary side low potential power supply terminal or its potential V2H Secondary side high Potential power terminal or its potential V2L Secondary side low potential power terminal or its potential

Claims (3)

A level shift circuit for transmitting a logical value signal from a primary potential system to a secondary potential system having a higher potential than the primary potential system;
A latch circuit formed by connecting the first and second inverters operating in the secondary side potential system in a circular manner by connecting a resistor between each input and output;
First and second MOSFETs connected between inputs of the first and second inverters and a low-potential-side reference potential of the primary-side potential system;
An initial value setting circuit connected to at least one of the inputs of the first and second inverters;
Equipped with a,
As the initial value setting circuit,
A first resistor and a first capacitor connected in parallel between the input of one of the first and second inverters and the high potential side potential of the secondary side potential system are connected in parallel. 1 parallel circuit;
A second resistor and a second capacitor connected in parallel between the input of either one of the first and second inverters and the low potential side potential of the secondary side potential system are connected in parallel. Two parallel circuits;
A level shift circuit comprising at least one of the above . The level shift circuit operates in the potential system on the primary side, generates a first pulse signal at the rising edge of the logical value signal, and inputs the first pulse signal to the gate of the first MOSFET. 2. A pulse generation circuit for generating a second pulse signal at the falling edge of the logic value signal and inputting the second pulse signal to the gate of the second MOSFET. The level shift circuit described .   The pulse generation circuit includes:
  A delay circuit that outputs a signal obtained by delaying the logical value signal by a predetermined time;
  The first pulse signal is generated by a logical product of the logical value signal and an inverted signal of the delay circuit output,
  3. The level shift circuit according to claim 2, wherein the second pulse signal is generated by a logical product of an inverted signal of the logical value signal and an output signal of the delay circuit.

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