JP5321530B2 - Three-phase voltage type PWM inverter control device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve a problem of a conventional three-phase voltage-type PWM inverter controller that phase current information for two phases may not be detected from a direct-current bus current during a one PWM period if the controller performs control under a condition that a modulation rate of an output voltage vector Vs is higher than 1 since the controller is supposed to perform control under a condition that the modulation rate of the output voltage vector Vs is 1 or lower. <P>SOLUTION: There is provided an inverter control unit including: output voltage vector calculation means for calculating an output voltage vector Vs based on a direct-current bus current, a direct-current bus voltage and an angle speed instruction value supplied from outside; and output time management means for generating an output voltage vector Vs' and an output voltage vector Vs'' based on the output voltage vector Vs and managing an output time per half of a PWM period of each of two basic vectors that are adjacent to the output voltage vector Vs' and are not zero such that each output time becomes a prescribed time TMIN or longer. <P>COPYRIGHT: (C)2012,JPO&amp;INPIT

Description

  The present invention generates a PWM (Pulse Width Modulation) drive signal based on a DC current flowing in a DC bus of the inverter main circuit, and drives the plurality of semiconductor switching elements in the inverter main circuit with the drive signal, thereby The present invention relates to a three-phase voltage type PWM inverter control device that converts DC power supplied from a bus to three-phase AC power.

  The conventional three-phase voltage type PWM inverter control device generates an output voltage vector Vs based on a direct current flowing in the direct current bus of the inverter main circuit, and at least one of the two vector components of the vector Vs is less than a predetermined time TMIN. At some point, a vector Vs ′ and a vector Vs ″ are generated from the vector Vs, two vector components of the vector Vs ′ are at least equal to the predetermined time TMIN, and a vector average of the vectors Vs ′ and Vs ″ is the output voltage. The semiconductor switching element of the inverter main circuit is driven and controlled by applying Vs ′ to the first half cycle of the PWM cycle and Vs ″ to the second half cycle of the PWM cycle so as to be equal to the vector Vs. 1).

  In addition, as another conventional three-phase voltage type PWM inverter control device, a phase current calculation unit that calculates a three-phase current based on a DC current flowing in a DC bus of the inverter main circuit, and a 3 based on a current command value and a phase current. A current control unit that outputs a first voltage command value of the phase; and a PWM pulse generation unit that outputs a PWM pulse based on the first voltage command value. When the difference between the phases arranged in order of magnitude is smaller than the predetermined interval value, at least one of the first voltage command values of the two phases having a small difference between the phases is set to the same value as the average value for each PWM cycle. In some cases, correction processing is performed to correct the second voltage command value that is different between the first half and the second half of the cycle (see, for example, Patent Document 2).

Japanese Patent Laid-Open No. 11-4594 Japanese Patent No. 3664040

  In the three-phase voltage type PWM inverter control device described in Patent Document 1 and Patent Document 2, even when the modulation rate of the output voltage vector Vs is small or when the output voltage vector Vs is close to the phase of a single basic voltage vector, Since phase current information for two phases can be detected from the DC current flowing in the DC bus during one PWM period, inverter driving based on inexpensive current detection means for detecting the DC bus current is enabled.

  However, since the conventional three-phase voltage type PWM control device is premised on the control with the modulation factor of the output voltage vector Vs being 1 or less, when applied in a state where the modulation factor is larger than 1, the DC bus current is detected during one PWM cycle. There was a problem that a situation in which phase current information for two phases could not be detected occurred. For this reason, there has been a problem that the inverter control operation becomes unstable, causing the worst step out and the motor stopping.

  The present invention has been made to solve the above-described problems, and a first object of the present invention is to provide two phases from a DC bus current during one PWM period even when the modulation factor of the output voltage vector Vs is larger than one. It is to be able to detect minute phase current information. Thus, a three-phase voltage type inverter control device capable of stable inverter driving even when the modulation factor of the output voltage vector Vs is larger than 1 can be obtained by an inexpensive current detecting means for detecting the DC bus current.

  Further, the second object is to enable detection of phase current information for two phases from the DC bus current during one PWM period even when the modulation factor of the output voltage vector Vs is larger than 1, so that the DC bus current can be detected. It is to obtain a three-phase voltage type PWM inverter control device capable of driving an inverter with a high-efficiency permanent magnet type synchronous motor having a high induced voltage constant as a load by an inexpensive current detecting means for detecting the current.

  The third object is to make it possible to detect phase current information for two phases from the DC bus current during one PWM period even when the modulation factor of the output voltage vector Vs is greater than 1, and To obtain a three-phase voltage type PWM inverter control device capable of suppressing current pulsation in a phase current caused by interference between an inverter frequency and a carrier frequency for generating a PWM drive signal.

  The three-phase voltage type PWM inverter control device of the present invention includes an inverter main circuit that converts DC power supplied from a DC bus into three-phase AC power using a plurality of switching elements, and a DC bus current flowing through the DC bus. DC current detecting means for detecting, a DC voltage detecting circuit for detecting a DC bus voltage between the positive side and the negative side of the DC bus, and an inverter control unit for outputting a PWM drive signal for controlling a switching element of the inverter main circuit The inverter control unit comprises: an output voltage vector calculation means for calculating an output voltage vector Vs based on the DC bus current, the DC bus voltage, and an angular velocity command value given from the outside; and an output voltage vector Vs ′ And Vs ″ are equal to the output voltage vector Vs, and the output voltage vector Vs ′ A first calculation for calculating the output voltage vectors Vs ′ and Vs ″ so that each of the output times per 1/2 PWM period of two adjacent non-zero basic voltage vectors has a predetermined time TMIN or more. If the sum of the output times per 1/2 PWM period of the two basic voltage vectors with non-zero magnitude adjacent to the process and Vs '' is greater than 1/2 PWM period, the shorter of the two output times Output time management means for managing the output time by a second calculation process in which Vs ″ is recalculated so that the output time is further reduced and the sum of the output times becomes a ½ PWM cycle, PWM drive signal generating means for generating a PWM drive signal based on the recalculated output voltage vectors Vs ′ and Vs ″, and the recalculated output voltage vectors Vs ′ and Vs ′ Average vector of 'is characterized in that not necessarily equal to the output voltage vector Vs.

  The three-phase voltage type PWM inverter control device of the present invention has an effect that stable inverter driving can be realized even when the modulation factor is larger than 1, using an inexpensive current detecting means for detecting a DC bus current.

  Further, the three-phase voltage type PWM inverter control device of the present invention uses an inexpensive current detecting means for detecting a DC bus current, and uses an inverter driven with a high-efficiency permanent magnet type synchronous motor having a high induced voltage constant as a load. Has the effect of being able to.

  Further, the three-phase voltage type PWM inverter control device of the present invention can drive the inverter while suppressing current pulsation in the phase current caused by interference between the inverter frequency of the inverter control device and the carrier frequency for generating the PWM drive signal. It has the effect.

FIG. 3 is a configuration diagram of a three-phase voltage type PWM inverter control device in the first embodiment. Vector diagram of output voltage vector Vs (when Vs: SCT_Vs = 0, TMIN / 2 ≦ ti <TMIN, tk ≧ TMIN). The figure which showed the correspondence of a basic voltage vector and the switching state of a semiconductor switching element. Timing chart of PWM inverter control (when Vs: SCT_Vs = 0, TMIN / 2 ≦ ti <TMIN, tk ≧ TMIN, Vs is applied to the first half and the second half of the PWM cycle). The figure which showed the relationship between the phase voltage obtained from an output voltage vector state, a PWM drive signal, and a DC bus current. The figure which showed the relational relationship between the sector holding information (SCT_Vst) of the output voltage vector Vs, and the phase current information obtained from the DC bus current information (Idc1_r, Idc2_r) detected at two detection timings. Vector diagram of output voltage vectors Vs, Vs ′, Vs ″ (when Vs: SCT_Vs = 0, TMIN / 2 ≦ ti <TMIN, tk ≧ TMIN). Timing chart of PWM inverter control (when Vs: SCT_Vs = 0, TMIN / 2 ≦ ti <TMIN, tk ≧ TMIN, Vs ′ is applied to the first half of the PWM cycle, and Vs ″ is applied to the second half of the PWM cycle). Vector diagram of output voltage vectors Vs, Vs ′, Vs ″ (when Vs: SCT_Vs = 0, ti <TMIN / 2, tk ≧ TMIN). Timing chart of PWM inverter control (when Vs: SCT_Vs = 0, ti <TMIN / 2, tk ≧ TMIN, Vs ′ is applied to the first half of the PWM cycle, and Vs ″ is applied to the second half of the PWM cycle). The operation | movement flowchart of the output voltage vector Vs calculating means 15. FIG. FIG. 6 is an operation flowchart of the output voltage vectors Vs ′ and Vs ″ calculating means 16. The figure which showed the sector (SCT_Vs, SCT_Vs ', SCT_Vs ") of output voltage vector Vs, Vs', Vs" corresponding to each case. The output time (ti, tk, ti ′, tk ′, ti ″, tk ″) per ½ PWM period of the basic voltage vector component of the output voltage vectors Vs, Vs ′, Vs ″ is shown corresponding to each case. Figure. Operation flow diagram (case = 1, ti ≧ TMIN, TMIN) of the output time (ti ′, tk ′, ti ″, tk ″) calculation portion (corresponding to STEP 30) of the output voltage vectors Vs ′, Vs ″ calculation means 16 / 2 ≦ tk <TMIN). The operation | movement flowchart of each phase timer value calculating means 17 is shown. The figure which showed the relationship between the sector (SCT_Vs ') of output voltage vector Vs', and each phase first half timer value (Tu_f, Tv_f, Tw_f). The figure which showed the relationship between the sector (SCT_Vs '') of output voltage vector Vs ", and each phase latter half timer value (Tu_r, Tv_r, Tw_r). Waveform corresponding to one electrical angle cycle of the sum of the U-phase first half timer value and the U-phase second half timer value (Tu_f + Tu_r) (when the modulation factor Vk of the output voltage vector Vs is 1.5). Waveform of one cycle of electrical angle of terminal voltage Vun (when modulation factor Vk of output voltage vector Vs = 1.5). Waveform (output voltage vector Vs) of the electrical angle of one cycle of the difference between the sum of the U-phase first half timer value and the U-phase second half timer value (Tu_f + Tu_r) and the sum of the V-phase first half timer value and the V-phase second half timer value (Tv_f + Tv_r) When the modulation rate Vk = 1.5). Waveform of one cycle of the electrical angle of the line voltage Vuv (when the modulation factor Vk of the output voltage vector Vs = 1.5). The block diagram of the three-phase voltage type PWM inverter control apparatus in Embodiment 2. FIG. The waveform of the U-phase current when the current pulsates in the second embodiment. The waveform of the U-phase current when current pulsation in the second embodiment is suppressed.

Embodiment 1.
The configuration and operation of the three-phase voltage type PWM inverter control device in the first embodiment will be described with reference to the drawings. FIG. 1 shows an overall configuration of a three-phase voltage type PWM inverter control device (hereinafter also simply referred to as an inverter control device). The inverter control device shown in FIG. 1 converts an AC power source 1, a converter circuit 2 that converts AC power output from the AC power source 1 into DC power, and converts DC power output from the converter circuit 2 into three-phase AC power. The inverter main circuit 3, the three-phase motor 4 driven by the three-phase AC power output from the inverter main circuit 3, and the DC bus current flowing on the DC bus negative side N between the converter circuit 2 and the inverter main circuit 3 are detected. DC current detection means 5, DC voltage detection circuit 6 for detecting a DC bus voltage between DC bus positive side P and negative side N which is the output side of converter 2, output of DC current detection means 5 and DC voltage detection circuit 6 and an inverter control unit 7 that outputs a PWM drive signal for controlling the inverter main circuit 3 based on an angular velocity command value ω1 * given from the outside.

  The converter circuit 2 includes a full-wave rectifier circuit or a voltage doubler rectifier circuit, which are known techniques. The converter circuit 2 may be provided with a booster circuit capable of boosting a DC voltage (for example, described in Japanese Patent No. 2763479) and a circuit configuration capable of stepping up and down the DC voltage.

  The inverter main circuit 3 includes power switching elements SW1 to SW6 having insulated gate inputs, diodes D1 to D6 connected in reverse parallel to the switching elements, and drive circuits 3a to 3f for driving the switching elements. The inverter main circuit 3 may be realized by an IPM (Intelligent Power Module).

  The three-phase motor 4 includes a three-phase Y-shaped stator 4a composed of a U phase, a V phase, and a W phase, and a permanent magnet rotor 4b.

  The DC current detecting means 5 is composed of a shunt resistor 5a provided on the DC bus negative side N and an amplifier 5b for amplifying a voltage drop generated between the shunt resistors 5a due to the DC bus current, and the amplified signal is an inverter control unit 7 Is output to the A / D conversion circuit 8. The amplifier 5b can be configured using, for example, an operational amplifier. Here, the configuration is such that the DC current flowing through the DC bus is detected by amplifying the voltage drop across the shunt resistor 5a, but the configuration using a DC current converter (DCCT) capable of detecting the DC bus current is also realized. can do.

  The DC voltage detection circuit 6 divides the DC voltage between the DC buses PN on the output side of the converter 2 and outputs the divided voltage to the A / D conversion circuit 9 in the inverter control unit 7.

  The inverter control unit 7 turns on the semiconductor switching elements SW1 to SW6 of the inverter main circuit 3 based on the output of the DC current detection means 5, the output of the DC voltage detection circuit 6, and the angular velocity command value ω1 * given separately from the outside. PWM drive signals (UP, UN, VP, VN, WP, WN) for off control are output. Here, UP, VP, and WP are PWM drive signals on the upper arm side of the inverter main circuit 3, and are drive signals for SW1, SW2, and SW3, respectively. UN, VN, and WN are PWM drive signals on the lower arm side of the inverter main circuit 3, and are drive signals for SW4, SW5, and SW6, respectively. The inverter control unit 7 can be realized by a microprocessor, for example.

  Next, the internal configuration and operation of the inverter control unit 7 will be described. The A / D conversion circuit 8 converts the value input from the amplifier 5b into a digital value at a trigger timing (Trg1, Trg2) generated by a detection timing generation means 19 described later. The multiplier 10 multiplies the converted digital value output from the A / D conversion circuit 8 by a DC current restoration gain (Idc_GAIN), thereby calculating values (Idc1_r, Idc2_r) obtained by restoring the DC bus current Idc. On the other hand, the A / D conversion circuit 9 converts a value input from the DC voltage detection circuit 6 into a digital value at a triangular wave carrier peak timing described later. The multiplier 11 calculates a value (Vdc_r) obtained by restoring the DC voltage Vdc by multiplying the converted digital value output from the A / D conversion circuit 9 by a DC voltage restoration gain (Vdc_GAIN).

  The direct current / phase current conversion means 12 is based on the output of the multiplier 10 (Idc1_r, Idc2_r) and the sector information (SCT_Vst) of the output voltage vector Vs held by the Vs sector holding means 20 described later. The DC current information of the DC bus is converted into phase current information for two phases. Further, the phase current information for the remaining one phase is calculated using the phase current information for the two phases after conversion, and each phase current information (Iu_r, Iv_r, Iw_r) is obtained. Here, Iu_r is a restored value of the U-phase current Iu, Iv_r is a restored value of the V-phase current Iv, and Iw_r is a restored value of the W-phase current Iw.

  The current coordinate conversion unit 13 is configured to output each phase current output from the DC current / phase current conversion unit 12 based on a phase θ which is an output of a later-described γ-δ axis voltage command value (Vγ, Vδ, θ) calculation unit 14. The information (Iu_r, Iv_r, Iw_r) is coordinate-transformed to the γ-δ axis, which is the rotational coordinate system assumed on the rotor 4b, to obtain the γ-axis current Iγ and the δ-axis current Iδ.

  The γ-δ-axis voltage command value (Vγ, Vδ, θ) calculation means 14 converts the output of the current coordinate conversion means 13 to the γ-axis current Iγ, the δ-axis current Iδ, and the angular velocity command value ω1 * given separately from the outside. Based on this, a γ-axis voltage command Vγ, a δ-axis voltage command Vδ, and a phase θ are calculated. Here, the phase θ is an angle from the U phase (corresponding to a basic voltage vector V1 described later) to the γ axis of the stator 4a. Also, the angular velocity and phase related data used here are all converted to electrical angles. Note that a specific calculation method in the γ-δ axis voltage command value (Vγ, Vδ, θ) calculation means 14 may be configured using a known technique (for example, a method described in Japanese Patent No. 3860031). it can.

  The output voltage vector Vs calculation means 15 is the output of the γ-δ axis voltage command value (Vγ, Vδ, θ) calculation means 14, the γ-axis voltage command Vγ, the δ-axis voltage command Vδ, the phase θ, and the multiplier 11. Based on the output DC voltage information Vdc_r, the modulation rate Vk and phase θs of the output voltage vector Vs are calculated, and the sector (SCT_Vs) of the output voltage vector Vs and the output voltage vector Vs are calculated from the modulation rate Vk and phase θs. The output times ti, tk per ½ PWM period of two basic voltage vectors having non-zero magnitudes adjacent to are calculated.

  Here, the modulation factor Vk is calculated using the equation (1). Further, the magnitude | Vs | and the phase θs of the output voltage vector Vs are defined by equations (2) and (3), respectively. Here, the phase θs is an angle from the U phase of the stator 4a (corresponding to a basic voltage vector V1 described later) to the output voltage vector Vs.

However,

  A specific method for calculating the output times ti and tk per ½ PWM period of two non-zero magnitude basic vectors adjacent to the output voltage vector Vs will be described later.

  The γ-δ axis voltage command value (Vγ, Vδ, θ) calculating means 14 and the output voltage vector Vs calculating means 15 constitute an output voltage vector calculating means, and a DC bus current, a DC bus voltage, and an angular velocity command given from the outside. An output voltage vector Vs based on the value is calculated.

  The output time management (output voltage vector Vs ′, Vs ″ calculation) means 16 outputs the output voltage vector Vs based on the output time ti, tk and the sector of the Vs (SCT_Vs) which is the output of the output voltage vector Vs calculation means 15. 'And Vs'' are generated. Here, the output voltage vectors Vs ′ and Vs ′ are set so that the output times per 1/2 PWM period of two basic voltage vectors of non-zero magnitude adjacent to the output voltage vector Vs ′ are equal to or longer than the predetermined time TMIN. 'Is generated.

Next, the output time management (output voltage vector Vs ′, Vs ″ calculation) means 16 outputs the basic voltage vector components (ti ′, tk ′, ti ″, tk ′) of the output voltage vectors Vs ′ and Vs ″. ') And the output voltage vectors Vs ′ and Vs ″, respectively, sectors (SCT_Vs ′, SCT_Vs ″) are calculated and output. Here, the basic voltage vector components ti ', tk', ti ", tk" of the output voltage vectors Vs' and Vs "represent the output time of the basic voltage vector per 1/2 PWM period. A specific calculation method of the sectors of the output voltage vectors Vs ′ and Vs ″ and the basic voltage vector components ti ′, tk ′, ti ″, tk ″ of the output voltage vectors Vs ′ and Vs ″ will be described later. .

  Each phase timer value calculation means 17 outputs the output times ti ′, tk ′, ti ″, tk ″ and the output voltage vector Vs, which are outputs of the output time management (output voltage vectors Vs ′, Vs ″ calculation) means 16. The phase timer values (Tu_f, Tu_r, Tv_f, Tv_r, Tw_f, Tw_r) are calculated and output based on the sectors (SCT_Vs ′, SCT_Vs ″) of “, Vs”. Here, Tu_f is the U phase first half timer value in the first half of the PWM cycle, Tu_r is the U phase second half timer value in the second half of the PWM cycle, Tv_f is the V phase first half timer value in the first half of the PWM cycle, and Tv_r is the V phase second half timer value in the second half of the PWM cycle. , Tw_f represents the W-phase first half timer value in the first half of the PWM cycle, and Tw_r represents the W-phase second half timer value in the second half of the PWM cycle. The output voltage vector Vs ′ is applied to the first half of the PWM cycle, and the output voltage vector Vs ″ is applied to the second half of the PWM cycle.

  In this embodiment, each phase timer value is used to generate a PWM drive signal. A method for generating a PWM drive signal based on each phase timer value can be realized by diverting a known technique (for example, refer to Japanese Patent No. 3610897). In actual control, it is necessary to convert each phase timer value into a value corresponding to the counter clock. However, for the sake of simplification of explanation as in the case of the above-mentioned publicity, the time to be output is directly used as each phase timer value. I will use it.

  The PWM drive signal generation means 18 is based on each phase timer value (Tu_f, Tu_r, Tv_f, Tv_r, Tw_f, Tw_r) that is an output of each phase timer value calculation means 17, and the semiconductor switching elements SW1 to SW1 of the inverter main circuit 3. PWM drive signals (UP, UN, VP, VN, WP, WN) for ON / OFF control of SW6 are output.

  The detection timing generation means 19 outputs each phase first half timer value (Tu_f, Tv_f, Tw_f) that is an output of each phase timer value calculation means 17 and a sector (SCT_Vs) of Vs that is an output of the output voltage vector Vs calculation means 15. Based on this, two trigger timings (Trg1, Trg2) in A / D conversion in the A / D conversion circuit 8 are generated in one PWM cycle. The A / D conversion circuit 8 converts the value input from the amplifier 5b into a digital value based on the two trigger timings, and obtains two DC current information (Idc1_r, Idc2_r) related to the DC bus during one PWM period. A specific method for generating the trigger timing (Trg1, Trg2) will be described later.

  The Vs sector holding unit 20 holds the sector (SCT_Vs) of Vs that is the output of the output voltage vector Vs calculation unit 15. The stored sector information (SCT_Vst) is used when the DC current / phase current conversion means 12 converts the DC bus current information (Idc1_r, idc2_r) into phase current information (Iu_r, Iv_r, Iw_r).

Next, the detailed operation inside the inverter control unit 7 will be described.
First, the relationship between the output voltage vector Vs and the control of the switching elements of the inverter main circuit 3 will be described. FIG. 2 is a vector diagram of the output voltage vector Vs. In FIG. 2, V0 to V7 are basic voltage vectors and correspond to the switching states of the switching elements SW1 to SW6 of the inverter main circuit 3. Specifically, as shown in FIG. 3, the basic voltage vectors V0 to V7 and the eight combinations of the on / off states of the switching elements SW1 to SW6 correspond to each other on a one-to-one basis.

  For example, the basic voltage vector V1 corresponds to the state of the switching element in which SW1, SW5, and SW6 are in the ON state and SW2, SW3, and SW4 are in the OFF state. The basic voltage vector can be expressed as (SW1, SW2, SW3) when the switch on the upper arm side is expressed as “1” and when it is in the OFF state as “0”. Using this notation, the basic voltage vector V1 can be expressed as (1, 0, 0), and the basic voltage vector V2 can be expressed as (1, 1, 0). Of the basic voltage vectors, V0 (0, 0, 0) and V7 (1, 1, 1) are zero vectors of zero magnitude. On the other hand, V1 to V6 are non-zero basic voltage vectors.

  The output voltage vector Vs is assumed to rotate in the direction of V1-> V2-> V3-> V4-> V5-> V6-> V1-. Further, the angle θs from the basic voltage vector V1 to the output voltage vector Vs is a sector 0 in a section where 0 ° ≦ θs <60 °, a sector 1 in a section where 60 ° ≦ θs <120 °, and 120 ° ≦ θs <180 °. , The sector of 180 ° ≦ θs <240 ° is the sector 3, the sector of 240 ° ≦ θs <300 ° is the sector 4, and the sector of 300 ° ≦ θs <360 ° is the sector 5. The aforementioned sector of Ss (SCT_Vs) indicates a section where the output voltage vector Vs exists. For example, since the output voltage vector Vs illustrated in FIG. 2 exists in the sector 0 section, SCT_Vs = 0.

  In FIG. 2, ti is 1 of the basic voltage vector (V1 in FIG. 2) of the rotation direction among the non-zero basic voltage vectors (V1, V2 in the case of FIG. 2) adjacent to the output voltage vector Vs. / 2 is an output time per PWM cycle, and tk is an output time per 1/2 PWM cycle of the basic voltage vector (V2 in FIG. 2) ahead in the rotation direction.

  TMIN is the minimum predetermined time necessary to detect the DC bus current. The predetermined time TMIN is a dead time set so that the inverter main circuit 3 is not short-circuited vertically, a delay time of the switching elements SW1 to SW6, a delay time of the amplifier 5b, and an A / D conversion time of the A / D conversion circuit 8. The value is set separately in consideration of the ringing time of the DC bus current Idc.

  FIG. 2 shows the output times ti and tk and the predetermined time TMIN, where the vector length of the non-zero basic voltage vectors V1 to V6 is time Tp / 2 (Tp is 1 PWM cycle). The basic voltage vector components ti and tk of the voltage vector Vs are shown as TMIN / 2 ≦ ti <TMIN and tk ≧ TMIN.

  4 shows that when the output voltage vector Vs is in the state of FIG. 2 (SCT_Vs = 0, TMIN / 2 ≦ ti <TMIN, tk ≧ TMIN), the output voltage vector Vs is applied to the PWM drive in both the first half and the second half of the PWM cycle. FIG. 4, (a) shows each phase timer value (Tu_f, Tu_r, Tv_f, Tv_r, Tw_f, Tw_r) and a waveform of a triangular wave carrier for modulating each phase timer value, and (b) shows each phase timer value. Waveforms of PWM drive signals (UP, VP, WP, UN, VN, WN) generated by comparing triangular wave carriers, (c) is a DC bus current Idc detected by the DC current detection means 5, (d) Is the state of the output voltage vector, and (e) is phase current information obtained from the DC bus current Idc. Further, to is the output time of the zero vector V0 per 1/2 PWM period in the output voltage vector Vs, and th is the output time per 1/2 PWM period of the zero vector V7 in the output voltage vector Vs. FIG. 4 shows a case where the ratio of to to th is to: th = 1: 1.

  In FIG. 4, the PWM drive signals (UP, VP, WP, UN, VN, WN) compare each phase timer value (Tu_f, Tu_r, Tv_f, Tv_r, Tw_f, Tw_r) with a triangular wave carrier of amplitude Tmax. It is obtained by. However, Tmax is the MAX value of the timer value and corresponds to a 1/2 PWM cycle (Tp / 2).

  In the first half of the PWM cycle, UP, VP, and WP are “H” when the timer values Tu_f, Tv_f, and Tw_f are less than or equal to the triangular wave carrier, and are “L” when they are larger than the triangular wave carrier. In the latter half of the PWM cycle, UP, VP, and WP are “H” when the timer values Tu_r, Tv_r, and Tw_r are equal to or lower than the triangular wave carrier, and are “L” when they are larger than the triangular wave carrier. UN, VN, and WN are signals obtained by inverting UP, VP, and WP, respectively. Here, when the PWM drive signal is “H”, the corresponding switching element is driven to the “ON” state, and when the PWM drive signal is “L”, the corresponding switching element is driven to the “OFF” state. For example, when UP is “H”, the corresponding switching element SW1 is in the “ON” state, and when UP is “L”, SW1 is in the “OFF” state. Actually, it is necessary to provide a dead time of several μs in order to prevent the switching element of the inverter main circuit 3 from being vertically short-circuited, but is omitted here for the sake of simplicity.

  In the case shown in FIG. 4, the voltage vector state has four types of states of V0, V1, V2, and V7. When the voltage vector state is V1, the U-phase upper arm side switching element SW1 and the V-phase and W-phase lower arm side switching elements SW5 and SW6 are turned on. Therefore, DC current flows from the DC bus positive side P through SW1 through the U-phase winding of the three-phase motor 4, passes through the V-phase and W-phase windings, and is shunted through the lower arm side switching elements SW5 and SW6. It flows through the resistor 5a and returns to the DC bus negative side N. Accordingly, when the direction of current flowing into the three-phase motor 4 is positive, the DC bus current Idc detected when the voltage vector state is V1 is + Iu (+ U phase current). Here, the above description is made when a current flows through a switching element that is turned on. However, other current flows (for example, current flows in diodes D1 to D6 connected in antiparallel to the switching element). In such a case, the DC bus current Idc detected when the voltage vector state is V1 is + Iu (+ U phase current).

  Next, the operation when the voltage vector state is V2 will be described. When the voltage vector state is V2, the upper arm side switching elements SW1 and SW2 of the U phase and the V phase and the lower arm side switching element SW6 of the W phase are turned on. The DC current at this time flows from the DC bus positive side P through SW1 and SW2 through the U-phase and V-phase windings of the three-phase motor 4, passes through the W-phase winding, and passes through the lower arm side switching element SW6. It flows through the shunt resistor 5a and returns to the negative side N of the DC bus. Therefore, when the direction of current flowing into the three-phase motor 4 is positive, the DC bus current Idc detected when the voltage vector state is V2 is −Iw (−W phase current). Here, the above description is made when the current flows through the switching element that is turned on, but the DC bus current Idc that is detected when the voltage vector state is V2 even when other current flows is −Iw (−W phase current).

  When the voltage vector state is V0, only the lower arm side switching elements SW4, SW5, SW6 are turned on. When the voltage vector state is V7, only the upper arm side switching elements SW1, SW2 and SW3 are turned on. Therefore, when the voltage vector state is zero vectors V0 and V7, the phase current information obtained from the detected DC bus current Idc is indefinite. FIG. 5 summarizes the relationship between the voltage vector state and the phase current information obtained from the DC bus current Idc. In FIG. 5, the voltage vector states are also included when the state is other than V0, V1, V2, and V7.

  As described above, when the output voltage vector Vs is in sector 0 (SCT_Vs = 0), when the voltage vector state is V1 or V2, from the DC bus current Idc, + Iu (+ U phase current) or −Iw (− W-phase current) can be detected. That is, phase current information for two phases can be obtained from the DC bus current Idc in the output state of two basic voltage vectors of non-zero magnitude adjacent to the output voltage vector Vs.

  The phase current detection for two phases is performed by the A / D conversion circuit 8 using the two A / D conversion trigger timings (Trg1, Trg2) generated by the detection timing generation means 19. It is performed by sampling and A / D conversion processing.

  The detection timing generation unit 19 sets the timing advanced by the A / D conversion time (Tad) of the A / D conversion circuit 8 based on the timer value having an intermediate size among the first half timer values of the respective phases. Set as / D conversion trigger timing (Trg1). Further, a timing delayed by a predetermined time TMIN from the timing of Trg1 is set as the second A / D conversion trigger timing (Trg2).

  Here, a timer value having an intermediate magnitude among the first half timer values of each phase can be obtained from the sector of Vs (SCT_Vs). For example, when SCT_Vs = 0 as shown in FIG. 4, the timer value having an intermediate size among the first half timer values of each phase is Tv_f. The DC bus current information detected at the timing of Trg1 is Idc1_r, and the DC bus current information detected at the timing of Trg2 is Idc2_r.

  The DC current / phase current conversion means 12 obtains the phase current information for two phases from the sector information (SCT_Vst) at the DC current detection timing held in the Vs sector holding means 20 and the DC bus current information (Idc1_r, Idc2_r). obtain. FIG. 6 shows the phase current information obtained from the DC bus current information (Idc1_r, Idc2_r) based on the sector information (SCT_Vst) at the DC current detection timing held by the Vs sector holding means 20. For example, when SCT_Vst = 0, Idc1_r = + Iu_r and Idc2_r = −Iw_r. Further, the phase current for the remaining one phase can be obtained from the relationship of “Iu + Iv + Iw = 0”. The direct current / phase current conversion means 12 outputs the U, V, and W phase currents Iu_r, Iv_r, and Iw_r thus obtained.

  Next, the operation of the output voltage vector Vs calculation means 15 will be described with reference to the operation flowchart of FIG. First, the modulation factor Vk and the phase θs of the output voltage vector Vs are calculated from the above-described equations (1), (2), and (3) (STEP 1). From the phase θs, the sector of Vs (SCT_Vs) is calculated by equation (4) (STEP 2).

Next, based on the modulation factor Vk of the output voltage vector Vs, the phase θs and the sector (SCT_Vs) of Vs, the output times ti and tk of two basic voltage vectors adjacent to the output voltage vector Vs and having a non-zero magnitude are expressed as follows. Calculation is performed according to (5) to (7) (STEP 3).

However,

  Next, it is determined whether or not the sum of the output times ti and tk is greater than ½ PWM cycle (Tp / 2) (STEP 4). If it is determined that the sum of the output times ti and tk is greater, STEP 5 The output times ti and tk are recalculated by the processes of .about.7.

  On the other hand, if it is determined in STEP 4 that the sum of the output times ti and tk is equal to or less than ½ PWM period (Tp / 2), the output times ti and tk are determined as they are and the process ends.

  In the recalculation of the output times ti and tk, a time tz that is a difference between the sum of the output times ti and tk and the 1/2 PWM period (Tp / 2) is calculated, and ½ of this tz is calculated from ti and tk, respectively. By subtracting, ti and tk are updated (STEP 5).

  Next, when the output time ti after the update of STEP5 is not 0 ≦ ti ≦ Tp / 2, the limiter is multiplied by ti. Specifically, ti = 0 is set when ti <0, and ti = Tp / 2 is set when ti> Tp / 2 (STEP 6). Similarly, the limiter process is performed for the output time tk after the update of STEP 5 (STEP 7).

  By performing the processing of STEP 5 to 7, even when the modulation factor Vk is larger than 1, the sum of the output times ti and tk can be reduced to 1/2 PWM cycle (Tp / 2) or less, and further supplied to the motor 4. The phase of the fundamental frequency component of the line voltage can be made the same before and after recalculation.

  Next, the detailed operation of the output time management (output voltage vector Vs ′, Vs ″ calculation) means 16 will be described. First, the necessity of the output voltage vector Vs ′, Vs ″ calculation in the output time management means 16 and the basic calculation principle will be described.

  When the output time of two basic voltage vector components having a non-zero magnitude adjacent to the output voltage vector Vs is less than the predetermined time TMIN, the time required for detecting the DC bus current cannot be secured. DC bus current at can not be detected accurately. In the case described with reference to FIGS. 2 and 4, since TMIN / 2 ≦ ti <TMIN and tk ≧ TMIN, the DC bus current at the output time tk can be detected, but the DC bus current at the output time ti cannot be detected accurately. Therefore, in this case, phase current information for two phases cannot be obtained from the DC bus current Idc during one PWM period.

  In such a case, by separating the output voltage vector Vs into output voltage vectors Vs ′ and Vs ″ as shown in FIG. 7, phase current information for two phases is obtained from the DC bus current Idc during one PWM period. Can be made. In FIG. 7, an output voltage vector Vs ′ in which the output time per 1/2 PWM cycle of V1 is TMIN, the output time per 1/2 PWM cycle of V2 is tk, and the output time per 1/2 PWM cycle of V1 is 2 Xti-TMIN, V2 is divided into output voltage vector Vs '' where the output time per 1/2 PWM period is tk. FIG. 8 is a timing chart when Vs ′ is applied to the first half of the PWM cycle and Vs ″ is applied to the second half of the PWM cycle when the output voltage vector Vs is in the state of FIG. 7 (FIG. 2).

  In FIG. 8, ti ′ is a basic voltage vector (V1 in FIG. 7) of the rotation direction among two non-zero basic voltage vectors (V1 and V2 in FIG. 7) adjacent to the output voltage vector Vs ′. Output time per 1/2 PWM period, tk ′ is the output time per 1/2 PWM period of the basic voltage vector ahead in the rotation direction (V2 in FIG. 7), and to ′ is per 1/2 PWM period in the output voltage vector Vs ′. The zero vector V0 output time, th ′ is the output time per 1/2 PWM period of the zero vector V7 in the output voltage vector Vs ′.

  Also, ti '' is the basic voltage vector (V1 in FIG. 7) that is the original rotation direction among the two non-zero magnitude basic voltage vectors (V1 and V2 in FIG. 7) adjacent to the output voltage vector Vs ''. Output time per 1/2 PWM period, tk ″ is the output time per 1/2 PWM period of the basic voltage vector ahead of the rotation direction (V2 in FIG. 7), and to ″ is 1 / of the output voltage vector Vs ″. The output time of zero vector V0 per 2 PWM periods, th ″ is the output time per 1/2 PWM period of zero vector V7 in output voltage vector Vs ″. Therefore, ti ′ = TMIN, tk ′ = tk, ti ″ = 2 × ti−TMIN, tk ″ = tk. FIG. 8 shows a case where the ratio of the zero vector length is to ′: th ′ = 1: 1 and to ″: th ″ = 1: 1.

  As described above, if Vs ′ and Vs ″ are used instead of the output voltage vector Vs, ti ′ = TMIN and tk ′ = tk ≧ TMIN, so that the DC bus current is output during the output times ti ′ and tk ′. It becomes possible to detect Idc. Thus, phase current information for two phases can be obtained from the DC bus current Idc during one PWM period.

  In FIG. 7, the sector to which the output voltage vectors Vs ′ and Vs ″ belong is the same as the sector to which the output voltage vector Vs belongs. Next, a case where the sector to which the output voltage vector Vs ′ or Vs ″ belongs is different from the sector to which the output voltage vector Vs belongs will be described.

  FIG. 9 is a vector diagram when the output voltage vector Vs of FIG. 7 is further rotated and is in a state of ti <TMIN / 2 and tk ≧ TMIN. Also in this case, if the output voltage vector Vs is output in both the first half and the second half of the PWM cycle, phase current information for two phases cannot be obtained from the DC bus current Idc during one PWM cycle. Therefore, by separating the output voltage vector Vs into output voltage vectors Vs ′ and Vs ″ as in FIG. 7, phase current information for two phases can be obtained from the DC bus current Idc during one PWM period. Can do.

  Specifically, as shown in FIG. 9, an output voltage vector Vs ′ having an output time per 1/2 PWM period of V1 as TMIN, an output time per 1/2 PWM period of V2 as tk, and a 1/2 PWM of V2 The output time per period is divided into tk− (TMIN−2 × ti), and the output time per 1/2 PWM period of V3 is divided into output voltage vector Vs ″.

  FIG. 10 is a timing diagram when Vs ′ is applied in the first half of the PWM cycle and Vs ″ is applied in the second half of the PWM cycle in the state where the output voltage vector Vs is in the state of FIG. 9. In FIG. 9, the output voltage vector Vs ′ is in the sector 0 section (SCT_Vs ′ = 0) as in FIG. 7, but the output voltage vector Vs ″ is in the sector 1 section (SCT_Vs ″ = 1). ti ″ is an output time per 1/2 PWM cycle of V2 in the output voltage vector Vs ″, and tk ″ is an output time per 1/2 PWM cycle of V3 in the output voltage vector Vs ″. Accordingly, ti ′ = TMIN, tk ′ = tk, ti ″ = tk− (TMIN−2 × ti), and tk ″ = TMIN−2 × ti.

  As described above, in FIG. 10, Vs ′ and Vs ″ are used instead of the output voltage vector Vs as in the case of FIG. 8, so that ti ′ = TMIN and tk ′ = tk ≧ TMIN. As a result, the DC bus current Idc can be detected during the output times ti ′ and tk ′, and phase current information for two phases can be obtained from the DC bus current Idc during one PWM period.

  Next, the operation of the output time management (output voltage vector Vs ′, Vs ″ calculation) means 16 will be described with reference to the operation flow chart of FIG. The output time management (output voltage vector Vs ′, Vs ″ calculation) means 16 has 11 cases (steps 8 to 28) based on the output time ti, tk calculated by the output voltage vector Vs calculation means 15 and the predetermined time TMIN. ) And execute arithmetic processing.

  When the output time ti is equal to or longer than the predetermined time TMIN and the output time tk is equal to or longer than the predetermined time TMIN, case = 0 is set (STEP 10). The output time ti is equal to or longer than the predetermined time TMIN and the output time tk is equal to or lower than the predetermined time TMIN / 2. If the output time ti is equal to or greater than the predetermined time TMIN and the output time tk is less than the predetermined time TMIN / 2, then case = 2 (STEP 13).

When the output time ti is less than the predetermined time TMIN TMIN / 2 or more and the output time tk is the predetermined time TMIN or more, case = 3 (STEP 16), and the output time ti is less than the predetermined time TMIN / 2 and more than the output time TMIN / 2. When tk is less than TMIN and greater than or equal to TMIN / 2, case = 4 (STEP 19), the output time ti is less than the predetermined time TMIN less than TMIN / 2, the sum of the output times ti and tk is greater than or equal to TMIN, and the output time tk is the predetermined time. When it is less than TMIN / 2, case = 5 (STEP 20), and when the output time ti is less than TMIN / 2 for a predetermined time and the sum of the output times ti and tk is less than TMIN, case = 6 (STEP 21). To do.

When the output time ti is less than the predetermined time TMIN / 2 and the output time tk is greater than or equal to the predetermined time TMIN, case = 7 (STEP 23) is set, and the output time ti is less than the predetermined time TMIN / 2 and the output time tk is the predetermined time. If the sum of the output times ti and tk is less than TMIN and the sum of the output times ti and tk is TMIN or more, case = 8 (STEP 25), the output time ti is less than the predetermined time TMIN / 2 and the sum of the output times ti and tk is less than TMIN and the output time tk. Is equal to or less than TMIN / 2 for a predetermined time TMIN / 2 (STEP 27), and when output time ti is less than the predetermined time TMIN / 2 and output time tk is less than the predetermined time TMIN / 2, case = 10 ( STEP 28).

  Next, in STEP 29, the sectors (SCT_Vs ′, SCT_Vs ″) of the output voltage vectors Vs ′ and Vs ″ in the case calculated in STEPs 8 to 28 are calculated. The sectors (SCT_Vs ′, SCT_Vs ″) of the output voltage vectors Vs ′ and Vs ″ in each case can be obtained from the correspondence relationship of FIG. 13 from the sectors (SCT_Vs) of the output voltage vector Vs. For example, when SCT_Vs = 0 and case = 5, SCT_Vs ′ = 0 and SCT_Vs ″ = 5. For SCT_Vs ′, SCT_Vs ′ = SCT_Vs holds in all cases.

As an example, when the processes of STEPs 8 to 28 described above are applied to the output voltage vector Vs in the state of FIG. 7, it is determined that case = 3, and when applied to the output voltage vector Vs of FIG. 9, case = 7 is determined.

  Next, in STEP 30, the magnitude adjacent to the output times ti ′, tk ′ and Vs ″ per ½ PWM period of two basic voltage vectors whose magnitude is adjacent to the output voltage vector Vs ′ is nonzero. The output times ti ″ and tk ″ per 1/2 PWM period of the two basic voltage vectors are calculated. First, the flow of calculation processing will be described.

  First, based on the output times ti, tk and the case numbers calculated in STEPs 8 to 28, the output times ti ', tk', ti ", tk" are obtained from the relationship shown in FIG. For example, when case = 5, ti ′ = TMIN, tk ′ = TMIN, ti ″ = TMIN−2 × tk, tk ″ = 2 × (ti + tk−TMIN).

  Here, when case = 1, 2, 3, and 7, one or both of the sum of the output times ti ′ and tk ′ and the sum of the output times ti ″ and tk ″ is 1/2 PWM period (Tp / 2). A larger condition may occur. Therefore, in such a case, recalculation of ti ′, tk ′, ti ″, tk ′ ′ is performed as follows.

  First, when the sum of output times ti ′ and tk ′ is greater than ½ PWM period (Tp / 2), the difference between the sum of output times ti ′ and tk ′ and ½ PWM period (Tp / 2) is calculated. The difference is subtracted from the larger output time of the output times ti ′ and tk ′. Next, the difference is added to the larger output time of the output times ti ″ and tk ″. Subsequently, when the sum of output times ti ″ and tk ″ is greater than ½ PWM period (Tp / 2), the sum of output times ti ″ and tk ″ and ½ PWM period (Tp / 2) Is subtracted from the smaller one of the output times ti ″ and tk ″.

  If ti ′, tk ′, ti ″, and tk ″ are set according to FIG. 14, ti ′> tk ′ and ti ″> tk ″ when case = 1, and ti ′> tk ′ when case = 2. , Ti '' <tk '', and in case = 3, ti '<tk', ti '' <tk '', and in case = 7, ti '<tk', ti ''> tk '' These magnitude relationships are relationships that hold even after recalculation of ti ′, tk ′, ti ″, and tk ″.

  Next, a specific calculation procedure of the output times ti ′, tk ′, ti ″, tk ″ will be described based on the operation flow diagram of FIG. 15 in the case of case = 1.

  First, in STEP 31, ti ′, tk ′, ti ″, tk ″ when case = 1 is set according to FIG. 14. Then, tov1 is calculated by subtracting ½ PWM period (Tp / 2) from the sum of output times ti ′ and tk ′.

  In STEP 32, it is determined whether or not tov1 is greater than 0. If tov1 is greater than 0, the processing of STEPs 33 to 38 is performed to recalculate the output times ti ′, tk ′, ti ″, tk ″. . On the other hand, when tov1 is 0 or less, the output times ti ′, tk ′, ti ″, and tk ″ are not recalculated, and the process ends as it is.

  Next, the recalculation procedure of the output times ti ′, tk ′, ti ″, tk ″ will be described. First, in STEP 33, the time tov1 is subtracted from the output time ti 'to update the output time ti', and the time tov1 is added to the output time ti '' to update the output time ti ''.

  In STEP 34, the limiter is applied so that ti ″ obtained in STEP 33 is in the range of 0 ≦ ti ″ ≦ Tp / 2.

  In STEP 35, tov2 is calculated by subtracting a 1/2 PWM period (Tp / 2) from the sum of the output times ti "and tk".

  In STEP 36, it is determined whether or not the time tov2 is greater than 0. If it is determined that the time tov2 is greater than 0, the output time tk ″ is updated by subtracting the time tov2 from the output time tk ″ (STEP 37). The calculation of STEP 37 further shortens the output time of tk ″, which is the shorter of the two output times ti ″ and tk ″, so that the sum of the two output times becomes a 1/2 PWM cycle. Vs ″ is recalculated.

  Next, a limiter is applied so that tk ″ calculated in STEP 37 is in a range of 0 ≦ tk ″ ≦ Tp / 2 (STEP 38).

  On the other hand, if it is determined in STEP 36 that the time tov2 is 0 or less, the output time tk ″ is not recalculated, and the processing is terminated as it is.

  In the re-calculation processing of ti ′, tk ′, ti ″, tk ″ described above, tk ′ is not changed and tk ′ = TMIN. Also, ti ′ is ti ′ = Tp / 2−TMIN. Therefore, if TMIN ≦ Tp / 4, ti ′ ≧ TMIN. Here, in the PWM control of the inverter, the condition TMIN ≦ Tp / 4 is a practically achievable constraint condition. Therefore, by performing the recalculation processing of ti ′, tk ′, ti ″, tk ″, a PWM drive signal that can detect phase current information for two phases from the DC bus current Idc during one PWM period is output. It becomes possible to do.

  In addition, due to the recalculation process of ti ′, tk ′, ti ″, tk ″, the average vector of the output voltage vectors Vs ′ and Vs ″ after the recalculation may not be equal to the output voltage vector Vs. . This means that priority is given to outputting a PWM drive signal capable of detecting phase current information for two phases from the DC bus current Idc during one PWM period.

  The case where case = 1 has been described above, but the output times ti ′, tk ′, ti ″, and tk ″ are recalculated in the same manner when cases = 2, 3, and 7. With these recalculation processes, even in the case of cases = 2, 3, and 7, it is possible to output a PWM drive signal that can detect phase current information for two phases from the DC bus current Idc during one PWM period.

Next, the operation of each phase timer value calculation means 17 will be described with reference to the operation flowchart of FIG. First, in STEP 39, zeros in the output voltage vector Vs ′ using the output times ti ′, tk ′, ti ″, tk ″ calculated by the output time management (output voltage vector Vs ′, Vs ″ calculation) means 16. The output time to ′ per 1/2 PWM cycle of the vector V0 and the output time to ″ per 1/2 PWM cycle of the zero vector V0 in the output voltage vector Vs ″ are calculated by the equations (8) and (9).

  However, Kv0 ′ is the ratio of the output time to ′ of the zero vector V0 to the total output time (to ′ + th ′) of the zero vector per 1/2 PWM period in the output voltage vector Vs ′, and Kv0 ″ is the output voltage vector. This is the ratio of the output time to ″ of the zero vector V0 to the total output time (to ″ + th ″) of the zero vector per ½ PWM period in Vs ″. For example, output is performed at to ′: th ′ = 1: 1. In this case, Kv0 ′ = 0.5 is set.

  Next, in STEP 40, based on the sector (SCT_Vs') of the output voltage vector Vs' and the output times ti ', tk', to ', the first half timer values (Tu_f, Tv_f, Tw_f) are calculated from FIG. Similarly, based on the sector (SCT_Vs ″) of the output voltage vector Vs ″ and the output times ti ″, tk ″, and to ″, the latter half phase timer values (Tu_r, Tv_r, Tw_r) are obtained from FIG. Calculate.

  For example, when SCT_Vs = 0 and case = 3, since SCT_Vs ′ = 0 and SCT_Vs ″ = 0 (see FIG. 13), Tu_f = to ′, Tv_f = Tu_f + ti ′, Tw_f = Tv_f + tk ′, Tu_r = to ″ , Tv_r = Tu_r + ti ″, Tw_r = Tv_r + tk ″.

  The PWM drive signal generation means 18 compares each phase timer value (Tu_f, Tu_r, Tv_f, Tv_r, Tw_f, Tw_r) generated by each phase timer value calculation means 17 with the carrier for performing the triangular wave modulation. As shown in FIG. 8, PWM drive signals (UP, UN, VP, VN, WP, WN) are generated.

  19 to 22 show each phase timer value when the modulation rate Vk is 1.5, and the voltage between terminals of the three-phase motor 4 with respect to the phase of the output voltage vector Vs.

  FIG. 19 shows the waveform of the sum of the U-phase timer values Tu_f and Tu_r, FIG. 20 shows the waveform of the terminal-to-terminal voltage Vun between the U-phase and the bus negative side N of the three-phase motor 4, and FIG. 21 shows the U-phase timer values Tu_f and Tu_r. The waveform of the difference between the sum and the sum of the V-phase timer values Tv_f and Tv_r, FIG. 22 is the waveform of the line voltage Vuv between the U-phase and the V-phase of the three-phase motor 4.

  19 to 22, the horizontal axis represents the phase θs of the output voltage vector Vs, and each figure shows a waveform for one electrical angle cycle. Further, (a) in each figure is a waveform when the output voltage vector Vs remains (case 0), and (b) in each figure is a waveform when the present embodiment is applied. However, in actuality, the waveform is such that carriers are superimposed on the inter-terminal voltage Vun and the line voltage Vuv. Here, the case where the ratio of zero vectors per 1/2 PWM cycle is V0: V7 = 1: 1 is shown. However, the waveforms in FIGS. 21 and 22 are the same regardless of the zero vector ratio.

  The waveform of FIG. 19 is also a waveform of the output time of “H” per 1 PMW period of the U-phase lower arm drive signal UN. The waveform of the output time of “H” per 1 PMW cycle of the U-phase upper arm drive signal UP is a waveform obtained by inverting the waveform of FIG. 19 around “Tp / 2”. The waveform of FIG. 21 is also a waveform of a difference in output time of “H” per 1 PMW period between the U-phase lower arm drive signal UN and the V-phase lower arm drive signal VN. The waveform of the difference in output time of “H” per 1 PMW period between the U-phase upper arm drive signal UP and the V-phase upper arm drive signal VP is a waveform obtained by inverting the waveform of FIG. 21 around “0”.

  As can be seen by comparing the waveforms of (a) and (b) in FIGS. 19 to 22, even when the modulation rate is greater than 1, various waveforms can be deformed by controlling the output time management means according to the present embodiment. Can be generated as much as possible to generate PWM drive signals (UP, UN, VP, VN, WP, WN).

  Also, as shown in FIGS. 22A and 22B, when the modulation rate becomes larger than 1, a sine wave state cannot be secured as the waveform of the line voltage, but it is larger than when the modulation rate is limited to 1. Output voltage can be output.

  In the present embodiment, the case where the ratio of zero vectors per 1/2 PWM cycle is set to V0: V7 = 1: 1 has been described, but this ratio may be set to an arbitrary value. Further, although the case where the output voltage vector Vs ′ is applied to the first half period of the PWM cycle and the output voltage vector Vs ″ is applied to the second half period of the PWM cycle has been described, the output voltage vector Vs ′ is applied to the second half period of the PWM cycle. The output voltage vector Vs ″ may be applied to the first half period of the PWM cycle. Needless to say, the constituent elements can be modified and embodied without departing from the gist of the present invention, and the constituent elements can be replaced by alternative means having equivalent functions.

  As described above, in the first embodiment, the sum of the output times per 1/2 PWM period of two non-zero magnitude adjacent to the output voltage vector Vs by the control process described in FIG. Since the value obtained by subtracting ½ of the time, which is the difference from the ½ PWM cycle, from each of the output times is recalculated as the respective output times. The sum of the output times is within ½ PWM period, and the phase of the fundamental frequency component of the line voltage supplied to the motor can be made the same before and after recalculation. In other words, since the modulation factor is larger than 1, a sine wave state cannot be secured as the waveform of the line voltage, but the phase of the fundamental frequency component of the line voltage can be prevented from being affected. The influence on controllability can be minimized.

  Further, as described with reference to FIG. 12, when calculating the output voltage vectors Vs ′ and Vs ″, two basic voltage vectors of non-zero magnitude adjacent to the output voltage vector Vs per ½ PWM period. Since the calculation is divided into 11 cases based on the output time and the predetermined time TMIN, finer calculation is possible, and a PWM drive signal close to the characteristics when controlled by the output voltage vector Vs can be output. it can. That is, it is possible to suppress distortion of the phase current waveform caused by outputting a basic voltage vector component that does not occur in the output voltage vector Vs. In addition, noise and the like generated along with it can be suppressed.

  Further, as described with reference to FIGS. 12 to 15, each of the output times per 1/2 PWM period of two basic voltage vectors of non-zero magnitude adjacent to the output voltage vector Vs ′ is equal to or longer than the predetermined time TMIN. Is provided with output time management means for managing the output time of the output voltage vectors Vs ′ and Vs ″, so that a PWM drive signal capable of detecting phase current information for two phases from the DC bus current is output during one PWM period. be able to. As a result, by using an inexpensive current detecting means for detecting the DC bus current, stable inverter drive control is possible even in a state where the modulation factor is greater than 1.

  Further, even when the modulation factor of the output voltage vector Vs is larger than 1, the phase current information for two phases can be detected from the DC bus current during one PWM period, thereby reducing the DC bus current. It is possible to use a high-efficiency permanent magnet type synchronous motor with a high induced voltage constant as a load of the inverter control device by using a simple current detection means.

  Further, as described in STEPs 36 to 38 in FIG. 15, the sum of output times per 1/2 PWM period of two basic voltage vectors of non-zero magnitude adjacent to the output voltage vector Vs '' is 1/2 PWM period. If larger, the output time of the shorter one of the two output times is further shortened, and Vs '' is recalculated so that the sum of the two output times becomes 1/2 PWM period. Therefore, even when the modulation rate is larger than 1, the generation of basic voltage vector components other than the two basic voltage vector components having a non-zero magnitude adjacent to the output voltage vector Vs is suppressed.

  Further, since the ratio of the two zero vectors in the output voltage vector Vs ′ and the ratio of the two zero vectors in the output voltage vector Vs ″ can be arbitrarily set, for example, the ratio of the zero vectors can be varied at random. Thus, noise can be reduced even when the carrier frequency for generating the PWM drive signal is kept constant.

  In the region other than case = 6, 9, and 10 described in FIG. 12, a PWM drive signal generated by a combination of three basic voltage vectors other than the zero vector close to the output voltage vector Vs and the zero vector is 1 PWM cycle. Since it is possible to detect the phase current information for two phases from the DC bus current, the section of Kv0 ′ = Kv0 ″ = 1, 90 ° ≦ θs <150 ° in the section of 30 ° ≦ θs <90 °. Then, two-phase modulation control can be performed by varying the zero vector ratio every 60 °, such as Kv0 ′ = Kv0 ″ = 0, and the switching loss of the inverter main circuit can be reduced. Become.

  Further, by setting the predetermined time TMIN as the minimum time necessary for detecting the DC bus current, a PWM drive signal closer to the characteristics when controlled by the output voltage vector Vs can be output. That is, it is possible to suppress distortion of the phase current waveform caused by outputting a basic voltage vector component that does not occur in the output voltage vector Vs. In addition, noise and the like generated along with it can be suppressed.

  Further, the output voltage vector Vs ′ is applied to the first half period or the second half period of the PWM cycle, and the output voltage vector Vs ″ is applied to a PWM half cycle different from the output voltage vector Vs ′. Phase current information for two phases can be detected from the DC bus current during the ½ PWM period that is the output period of the voltage vector Vs ′. For this reason, the remaining phase current information of one phase can be obtained with high accuracy, and the controllability of the inverter drive can be improved.

  Further, since the interval for obtaining the phase current information for two phases from the DC bus current is set to the predetermined time TMIN, the phase current information for the remaining one phase can be obtained more accurately, and the inverter drive Controllability can be further improved.

  Further, by using a wide gap semiconductor element as a semiconductor element constituting the inverter main circuit, it is possible to shorten the time such as dead time time and switching time of the inverter main circuit. As a result, the minimum time required to detect the DC bus current can be reduced, and a PWM drive signal closer to the characteristics when controlled by the output voltage vector Vs can be output. That is, it is possible to suppress distortion of the phase current waveform caused by outputting a basic voltage vector component that does not occur in the output voltage vector Vs. In addition, noise and the like generated along with it can be suppressed. Examples of the wide gap semiconductor element include silicon carbide (SiC), gallium nitride (GaN) -based material, and diamond.

  Further, by connecting the inverter control device of the present embodiment to a compressor equipped with a permanent magnet electric motor, a compressor drive device that is inexpensive and generates less noise can be obtained. Moreover, the same effect is acquired also about the air conditioner carrying the inverter control apparatus of this Embodiment.

Embodiment 2.
In the first embodiment, even when the modulation factor of the output voltage vector Vs is larger than 1, phase current information for two phases can be detected from the DC bus current Idc during one PWM cycle. In the second embodiment, a three-phase voltage type PWM inverter control device that can further suppress current pulsation generated in a phase current due to interference between the inverter frequency of the inverter control device and the carrier frequency for generating the PWM drive signal will be described. To do.

  FIG. 23 shows the configuration of the inverter control apparatus according to the second embodiment. In the second embodiment, a pulsation suppression compensator 21 and an adder 22 are provided, and a γ-δ axis voltage command value (Vγ, Vδ, θ) calculation means 14 ′ is an adder instead of an angular velocity command value ω1 * given from the outside. The calculation is based on the output from 22. Since other configurations are the same as those of the first embodiment, the same components as those of the first embodiment are denoted by the same reference numerals and description thereof is omitted.

The operation of the inverter control device in the present embodiment will be described with reference to FIG.
The pulsation suppression compensator 21 extracts a current pulsation component generated in the δ-axis current Iδ output from the current coordinate conversion means 13, and outputs a value proportional to the current pulsation component as an angular velocity compensation amount ωd. The adder 22 adds the angular velocity command value ω1 * and the angular velocity compensation amount ωd given from the outside, and outputs the result to the γ-δ axis voltage command value (Vγ, Vδ, θ) computing means 14 ′. Here, the pulsation suppression compensator 21 can be realized by a configuration using a bandpass filter which is a known technique (for example, described in the public relations of JP 2009-44873 A). In the above-mentioned public relations, the current value in the dq coordinate axis that is the rotating coordinate system is used as the input of the pulsation suppression compensator. However, the current value in the γδ coordinate axis that is the rotating coordinate system is used as in the present embodiment. The current pulsation component can be detected.

  As an example, the U-phase current waveform when the number of poles of the three-phase motor 4 is 6, the inverter frequency is 342 Hz, and the angular velocity compensation amount ωd = 0 (corresponding to the case without the pulsation suppression compensator 21). Is shown in FIG. In FIG. 24, the U-phase current pulsates at a period of about 18.5 ms, that is, 54 Hz. This is because the phase current pulsates at a difference of 54 Hz, that is, a period of about 18.5 ms, due to interference between 4446 Hz which is the 13th harmonic of the inverter frequency and the carrier frequency of 4500 Hz of the inverter.

Therefore, as in this embodiment, a bandpass filter is configured so that the current pulsation component can be extracted by the pulsation suppression compensator 21, and a value proportional to the current pulsation component is set as an angular velocity compensation amount ωd to perform pulsation suppression compensation. FIG. 25 shows the U-phase current waveform when it is performed. As can be seen from FIG. 25, by performing this pulsation suppression compensation, it is possible to reduce the phase current pulsation that occurred at a period of about 18.5 ms.

  In order to accurately extract the current pulsation component from the pulsation suppression compensator 21, it is premised that phase current information for two phases is detected from the DC bus current Idc during one PWM period. For this reason, the calculation control described in the first embodiment enables detection of phase current information for two phases from the DC bus current Idc during one PWM period even when the modulation factor Vk of the output voltage vector Vs is larger than 1. It is necessary to.

  As described above, in the second embodiment, the current pulsation component generated in the δ-axis current Iδ output from the current coordinate conversion means 13 is extracted, and a value proportional to the current pulsation component is output as the angular velocity compensation amount ωd. The pulsation suppression compensator 21 that performs the above operation and the adder 22 that adds the angular velocity command value ω1 * and the angular velocity compensation amount ωd given from the outside can be used to control the inverter controller even when the modulation factor of the output voltage vector Vs is greater than 1. Current pulsation generated in the phase current due to interference between the inverter frequency and the carrier frequency for generating the PWM drive signal can be suppressed. Since the phase current peak value can be suppressed by suppressing the phase current pulsation, it is possible to prevent the operation from being stopped by an overcurrent protection circuit (not shown).

  In the present embodiment, the case where current pulsation generated in the phase current due to the interference between the inverter frequency and the carrier frequency for generating the PWM drive signal is suppressed has been described. Concerning the current pulsation caused by the interference, the current pulsation can be suppressed by configuring the bandpass filter in the pulsation suppression compensator 21 so that the current pulsation component can be extracted. Needless to say, it is also possible to simultaneously suppress the current pulsation caused by the interference between the inverter frequency and the carrier frequency and the current pulsation caused by the interference between the inverter frequency and the AC power supply frequency.

  By applying the control means in the present embodiment to an electric device such as an air conditioner, the operating range of the device can be expanded and the maximum performance can be improved. In addition, since it is possible to prevent the generation of noise due to phase current pulsation, there is also an effect of reducing the noise of the equipment.

DESCRIPTION OF SYMBOLS 1 AC power source, 2 Converter circuit, 3 Inverter main circuit, 4 3-phase motor, 5 DC current detection means, 6 DC current detection means, 7 Inverter control part, 8 A / D conversion circuit, 9 A / D conversion circuit, 10 Multiplier, 11 Multiplier, 12 DC current / phase current conversion means, 13 Current coordinate conversion means, 14 γ-δ axis voltage command value (Vγ, Vδ, θ) calculation means, 15 Output voltage vector Vs calculation means, 16 outputs Time management (output voltage vector Vs ′, Vs ″ calculation) means, 17 each phase timer value calculation means, 18 PWM drive signal generation means, 19 detection timing generation means, 20 Vs sector holding means, 21 pulsation suppression compensator, 22 Adder

Claims (18)

An inverter main circuit for converting DC power supplied from the DC bus into three-phase AC power using a plurality of switching elements;
DC current detecting means for detecting a DC bus current flowing in the DC bus;
A DC voltage detection circuit for detecting a DC bus voltage between the positive side and the negative side of the DC bus;
An inverter control unit that outputs a PWM drive signal for controlling the switching element of the inverter main circuit,
The inverter control unit
Output voltage vector computing means for computing an output voltage vector Vs based on the DC bus current, the DC bus voltage, and an angular velocity command value given from the outside;
Output per ½ PWM period of two basic voltage vectors whose average vectors of the output voltage vectors Vs ′ and Vs ″ are equal to the output voltage vector Vs and whose magnitude is adjacent to the output voltage vector Vs ′. A first calculation process for calculating the output voltage vectors Vs ′ and Vs ″ such that each of the times is equal to or greater than a predetermined time TMIN; and two basic voltage vectors having non-zero magnitude adjacent to the Vs ″ If the sum of output times per 1/2 PWM period is greater than 1/2 PWM period, the shorter output time of the two output times is further reduced, and the sum of the output times is 1/2 PWM period. An output time management means for managing the output time by the second calculation process for recalculating Vs ″ so that
PWM drive signal generation means for generating a PWM drive signal based on the recalculated output voltage vectors Vs ′ and Vs ″,
The three-phase voltage type PWM inverter control device, wherein an average vector of the output voltage vectors Vs ′ and Vs ″ after the recalculation is not necessarily equal to the output voltage vector Vs. The output voltage vector calculation means includes
Γ-δ-axis voltage command value calculating means for calculating a γ-axis voltage command Vγ, a δ-axis voltage command Vδ, and a phase θ based on the DC bus current, the DC bus voltage, and an angular velocity command value given from the outside;
Output voltage vector Vs calculating means for calculating an output voltage vector Vs based on the γ-axis voltage command Vγ, δ-axis voltage command Vδ, phase θ, and the DC bus voltage;
The output voltage vector Vs calculation means is configured to output the output time when a sum of output times per 1/2 PWM period of two basic voltage vectors having a non-zero magnitude adjacent to the output voltage vector Vs is greater than 1/2 PWM period. The output time is recalculated by subtracting ½ of the difference time from each of the output times, and the output voltage vector Vs is updated. The three-phase voltage type PWM inverter control device according to claim 1.   The output time management means is divided into a plurality of cases based on the output time per 1/2 PWM period of two basic voltage vectors of non-zero magnitude adjacent to the output voltage vector Vs and the predetermined time TMIN. The three-phase voltage type PWM inverter control device according to claim 1 or 2, wherein the output time is managed. The PWM drive signal generation means includes
Applying the output voltage vector Vs ′ to the first half period or the second half period of the PWM cycle,
The three-phase voltage type PWM inverter control device according to any one of claims 1 to 3, wherein the output voltage vector Vs''is applied to a PWM half cycle different from the output voltage vector Vs'.   5. The ratio of two zero vectors in the output voltage vector Vs ′ and the ratio of two zero vectors in the output voltage vector Vs ″ can be arbitrarily set, respectively. 6. Three-phase voltage type PWM inverter control device.   6. The three-phase voltage type PWM inverter control device according to claim 1, wherein the predetermined time TMIN is a minimum time required for detecting the direct current.   The three-phase voltage type PWM inverter control device according to any one of claims 1 to 6, wherein an interval for obtaining phase current information for two phases from the DC current is a predetermined time TMIN. The inverter control unit includes a pulsation suppression compensation unit that calculates an angular velocity compensation amount based on a current pulsation component generated in a phase current due to an interference between an inverter frequency of the inverter control device and a carrier frequency for generating the PWM drive signal. Adding means for adding the angular velocity compensation amount to the angular velocity command value,
The three-phase voltage type PWM inverter control device according to claim 1, wherein a current pulsation component generated in the phase current is suppressed. A converter circuit that converts AC power output from an AC power source into the DC power,
The inverter control unit includes a current pulsation component generated in a phase current due to interference between an inverter frequency of the inverter control device and a carrier frequency for generating the PWM drive signal, and interference between the inverter frequency and the frequency of the AC power supply. Pulsation suppression compensation means for calculating an angular velocity compensation amount based on at least one current pulsation component of the current pulsation component generated in the phase current, and addition means for adding the angular velocity compensation amount to the angular velocity command value,
The three-phase voltage type PWM inverter control device according to claim 1, wherein a current pulsation component generated in the phase current is suppressed. The inverter control unit includes DC current / phase current conversion means for converting the DC bus current detected by the DC current detection means into each phase current output from the inverter main circuit, and the current in the rotating coordinate system. Current coordinate conversion means for converting to a value,
10. The pulsation suppression compensation means extracts a current pulsation component from a current value in the rotating coordinate system, and outputs a value proportional to the current pulsation component as the angular velocity compensation amount. The three-phase voltage type PWM inverter control device described in 1.   11. The three-phase voltage type PWM inverter control device according to claim 1, wherein the switching element is formed of a wide gap semiconductor element.   12. The three-phase voltage type PWM inverter control device according to claim 11, wherein the wide band gap semiconductor is silicon carbide (SiC), gallium nitride (GaN) based material, or diamond.   A compressor equipped with a permanent magnet motor driven by three-phase AC power output from the inverter main circuit, and the three-phase voltage type PWM inverter control device according to claim 1. A compressor driving device characterized by the above.   A refrigerant is circulated by the compressor driving device according to claim 13. An inverter main circuit for converting DC power supplied from the DC bus into three-phase AC power using a plurality of switching elements;
DC current detecting means for detecting a DC bus current flowing in the DC bus;
A DC voltage detection circuit for detecting a DC bus voltage between the positive side and the negative side of the DC bus;
A control method of a three-phase voltage type PWM inverter device comprising an inverter control unit for outputting a PWM drive signal for controlling a switching element of the inverter main circuit,
An output voltage vector calculation step of calculating an output voltage vector Vs based on the DC bus current, the DC bus voltage, and an angular velocity command value given from the outside;
Output per ½ PWM period of two basic voltage vectors whose average vectors of the output voltage vectors Vs ′ and Vs ″ are equal to the output voltage vector Vs and whose magnitude is adjacent to the output voltage vector Vs ′. A first calculation process for calculating the output voltage vectors Vs ′ and Vs ″ such that each of the times is equal to or greater than a predetermined time TMIN; and two basic voltage vectors having non-zero magnitude adjacent to the Vs ″ If the sum of output times per 1/2 PWM period is greater than 1/2 PWM period, the shorter output time of the two output times is further reduced, and the sum of the output times is 1/2 PWM period. An output time management step for managing the output time by the second calculation process for recalculating Vs ″ so that
A PWM drive signal generating step for generating a PWM drive signal based on the output voltage vectors Vs ′ and Vs ″ after the recalculation,
The control method of the three-phase voltage type PWM inverter control device, wherein an average vector of the output voltage vectors Vs ′ and Vs ″ after the recalculation is not necessarily equal to the output voltage vector Vs. A pulsation suppression compensation step for calculating an angular velocity compensation amount based on a current pulsation component generated in a phase current due to interference between the inverter frequency of the inverter control device and the carrier frequency for generating the PWM drive signal; and the angular velocity command value An addition step of adding the angular velocity compensation amount,
16. The method of controlling a three-phase voltage type PWM inverter control device according to claim 15, wherein a current pulsation component generated in the phase current is suppressed. A converter circuit for converting AC power output from an AC power source into the DC power;
An inverter main circuit for converting DC power supplied from the DC bus into three-phase AC power using a plurality of switching elements;
DC current detecting means for detecting a DC bus current flowing in the DC bus;
A DC voltage detection circuit for detecting a DC bus voltage between the positive side and the negative side of the DC bus;
A control method of a three-phase voltage type PWM inverter device comprising an inverter control unit for outputting a PWM drive signal for controlling a switching element of the inverter main circuit,
Current pulsation component generated in the phase current due to interference between the inverter frequency of the inverter control device and the carrier frequency for generating the PWM drive signal, and current pulsation generated in the phase current due to interference between the inverter frequency and the frequency of the AC power supply A pulsation suppression compensation step of calculating an angular velocity compensation amount based on at least one current pulsation component of the component, and an addition step of adding the angular velocity compensation amount to the angular velocity command value,
16. The method of controlling a three-phase voltage type PWM inverter control device according to claim 15, wherein a current pulsation component generated in the phase current is suppressed. DC current / phase current conversion step for converting the DC bus current detected by the DC current detection step into each phase current output by the inverter main circuit, and current coordinates for converting each phase current into a current value in a rotating coordinate system A conversion step,
18. The pulsation suppression compensation step extracts a current pulsation component from a current value in the rotating coordinate system, and outputs a value proportional to the current pulsation component as the angular velocity compensation amount. A control method of the three-phase voltage type PWM inverter control device described in 1.

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