JP5321333B2 - Phase comparator and clock recovery circuit using the phase comparator - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a phase detector which can highly accurately detect a phase of a zero cross point between reception data sampled by a clock. <P>SOLUTION: The phase comparator includes: a timing discriminator which generates a discrimination signal comprising a logic corresponding to a first data value of first reception data and a second data value of the second reception data; a first zero cross extractor for extracting first phase information, which is obtained by interpolation calculation from a sampling time and the first data value of the first reception data and a sampling time and the second data value of the second reception data, relating to a phase relation between a first zero cross time and a clock; a second zero cross extractor for extracting second phase information, which is determined using increment of the data value per unit time based on the first data value and the sampling time of the first reception data, relating to a phase relation between a second zero cross time and the clock; and a selector for selecting either the first phase information or the second phase information in accordance with the logic of the discrimination signal. <P>COPYRIGHT: (C)2011,JPO&amp;INPIT

Description

  The present invention relates to a phase comparator for detecting phase information with respect to a sampling clock at a time point when received data crosses a zero point (zero cross point), and a clock recovery circuit using the phase comparator.

The clock and data recovery circuit used in the receiver is a circuit that samples the received data signal with the internal clock generated inside the receiver and outputs the received data with the recovered clock synchronized with the edge of the received data signal. is there.
The clock / data recovery circuit includes an ADC (Analog Digital Converter) circuit, a demultiplexer, a phase comparator, a data decision unit, a filter, a phase interpolator, and a FIFO (First In First Out).
Therefore, in the clock / data recovery circuit, in order to accurately synchronize the recovered clock with the edge of the received data signal, the phase comparator accurately compares the phase of the edge of the received data signal with the phase of the internal clock (sampling clock). Need to do well. This is because the recovered clock is generated by adjusting the phase from the internal clock.

Therefore, a circuit that executes a phase error calculation method using a so-called zero-cross point has been proposed (see Patent Document 1: WO 2005/027122).
The phase error calculation method includes the following steps. The first step is a step of detecting two consecutive received data having different signs from among a plurality of received data sampled by the internal clock. Next, the second step is a step of detecting a time point when the received data changes from a negative value to a positive value or a time point (zero cross point) when the received data changes from a positive value to a negative value between the two received data. The third step is a step of calculating a phase error based on the zero cross point.

  In the above, a zero cross point is obtained by interpolation from two sampled received data.

However, when one of the received data is close to the zero level, both of the received data for obtaining the zero cross point are not necessarily in the rising state or the falling state of the same data value. For example, if the interval of sampling performed in synchronization with the clock is about half of the period of the received data signal, even if the previous sampling is performed in the rising period, the subsequent sampling is the data value after the half period. This is because it is performed in the falling state.
As a result, the zero cross point obtained by interpolation using the two sampled received data is away from the actual zero cross point. This is because the zero-cross point obtained by interpolation is located on the reception data side obtained by the subsequent sampling due to the influence of the reception data obtained by the later sampling.

International Publication WO2005 / 027122 Pamphlet

  The subject of this invention is providing the phase detector which can extract the phase information of the zero crossing point between the received data sampled with the internal clock with high precision.

A timing discriminator for generating a discrimination signal having logic corresponding to the first data value of the first received data and the second data value of the second received data;
The first zero crossing time when the data value becomes zero level and the sampling clock obtained from the sampling time and first data value of the first received data and the sampling time and second data value of the second received data by interpolation calculation A first zero cross extractor for extracting first phase information relating to the phase of the rise;
The phase between the second zero crossing time when the data value becomes zero level and the rising edge of the sampling clock, which is obtained by using the increment of the data value per unit time based on the sampling time of the first data value and the first received data. A second zero cross extractor for extracting second phase information for
And a selector that selects one of the first phase information and the second phase information in accordance with the logic of the determination signal.

  It is possible to provide a phase detector that can extract phase information of a zero cross point between received data sampled by an internal clock with high accuracy.

FIG. 1 is a diagram illustrating a clock / data recovery circuit 10 according to the first embodiment. FIG. 2 shows the phase comparator 40 of the first embodiment. FIG. 3 is a flowchart for explaining the operation of the phase comparator 40 according to the first embodiment. 4A and 4B are diagrams for explaining parameters for determining the logic of the timing discriminator 41 and the discrimination signal. FIG. 5 is a diagram showing the zero cross extractor 42. FIG. 6 is a diagram illustrating the principle of the zero cross phase information selector 424. 7A and 7B are diagrams showing a zero-cross extractor 44 using inclination. FIG. 8 is a diagram illustrating the principle of the zero-cross phase information selector 44 using tilt. FIG. 9 shows the phase comparator 60 of the second embodiment. 10A and 10B are diagrams for explaining the timing discriminator 61 and parameters for determining the logic of the discrimination signal. FIG. 11 shows the zero cross extractor 62 of the second embodiment. FIG. 12 is a diagram illustrating a phase comparator 80 according to the third embodiment. FIG. 13 is a diagram for explaining the details of the zero-cross extractor 81. FIG. 14 is a diagram for explaining the operation principle of the zero-cross extraction circuit 81. FIG. 15 is a diagram illustrating the zero-cross extractor 101 according to the fourth embodiment. FIG. 16 is a diagram illustrating the logic determination circuit 105 according to the fourth embodiment.

  The present invention includes the embodiments described below that have been modified by the design that can be conceived by those skilled in the art, and those in which the components shown in the embodiments have been recombined. Further, the present invention includes those in which the constituent elements are replaced with other constituent elements having the same operational effects, and are not limited to the following embodiments.

FIG. 1 is a diagram illustrating a clock / data recovery circuit 10 according to the first embodiment. The clock / data recovery circuit 10 includes ADCs (Analog Digital Converters) 1 and 2, a DMX (Demux) circuit 3, a phase comparator 40, a data determination unit 5, a filter 6, a FIFO (First in first out) 7, and a phase interpolation circuit 8. Is provided.
The ADCs 1 and 2 are circuits that sample received data composed of analog signals according to an internal clock and convert them into digital signals. Note that ADC1 and ADC2 operate alternately in response to rising or falling of the internal clock (sampling clock).
The DMX circuit 3 is a circuit that multiplexes reception data composed of digital signals output from the ADCs 1 and 2 with a wide bit width and converts the data into reception data composed of a digital signal having a long basic period.
The phase comparator 40 includes zero-cross phase information 46 of a zero-cross point at which received data obtained by primary interpolation from a plurality of consecutively sampled digitized received data output from the DMX circuit 3 crosses the zero level. And a circuit for generating a zero-cross vector phi for the zero-cross point. Here, the zero cross vector Phi is obtained by taking the time coordinate difference of the sampled first received data from the time coordinate of the intersection.
The zero-cross phase information 46 is a first range in which the phase from the rising edge to the falling edge of the sample clock logic is 0 to 1/8, a second range from 1/8 to 1/4, and from 1/4. This is a binary number indicating to which phase phase the time coordinate of the zero cross point belongs when divided into a third range up to 3/8 and a fourth range from 3/8 to 1/2. The detailed operation of the phase comparator 40 will be described with reference to FIGS. 2, 3, 4 A, 4 B, 5, 6, and 7.

The filter circuit 6 receives the zero-cross phase information 46 and the zero-cross vector phi, stores N pieces of past zero-cross phase information and zero-cross vectors phi, adds N pieces of zero-cross phase information and zero-cross vectors Phi, and then divides by N. Thus, the averaged zero-cross phase information and the average vector ph0 are obtained.
The data determination unit 5 uses the zero cross phase information 46 and the zero cross vector phi output from the phase comparator 40, the average vector ph0 of the past zero cross vector Phi output from the filter 6, and the averaged zero cross phase information. This is a circuit that selects received data having a fixed phase relationship with respect to the zero cross point from a plurality of continuous digitized received data, and outputs the selected data to the FIFO 7.
Therefore, the selection of the received data is performed as follows. First, as a result of obtaining the zero-cross phase information 46 on the sampled received data, the phase range to which the zero-cross point belongs is specified. Next, when the phase range of the zero cross point is in the range of 0 to 1/8, or in the range of 1/8 to 1/4, 1/2 phase is added to the zero cross phase information 46, the zero cross vector Phi, or the average vector Ph0. Assume that there is a data center at the position. On the other hand, when the phase range of the zero cross point is in the range of 1/4 to 3/4 or 3/4 to 1/2, the zero cross phase information 46, the zero cross vector Phi or the average vector Ph0 is 1/2 phase. Assume that the center of the received data is at the subtracted position. Next, the data determiner 5 selects the sampled received data having a time coordinate close to the center of the received data. Next, the data determination unit 5 outputs the selected received data to the FIFO 7.
The phase interpolation circuit 8 is a circuit that receives an internal clock (sampling clock), adjusts the phase of the internal clock according to the average vector ph0 output from the filter 6, and generates a restored clock.
The FIFO 7 is a circuit that receives the reception data output from the data determination unit 5 according to the internal clock, and outputs the reception data as the recovered reception data using the recovery clock. That is, the FIFO 7 is a circuit for retiming the received data so as to synchronize with the restored clock from the internal clock.

FIG. 2 shows the phase comparator 40 of the first embodiment. The phase comparator 40 includes a timing discriminator 41, a zero-cross extractor 42, a gradient-use zero-cross extractor 44, and a selector 47.
The sampled received data is represented by a sampling time T of the received data and a data value S.

The timing discriminator 41 is a circuit that outputs a discrimination signal having a logic corresponding to the relationship between the data values S ₁ and S _{2 of} two consecutive sampled received data and a given threshold value Vth. Details of the operation of the timing discriminator 41 will be described in detail with reference to FIGS. 4A and 4B.

The zero-cross extractor 42 obtains first zero-cross phase information 431 from the data values S ₁ and S _{2 of the two} received data with respect to the first zero-cross data obtained by linear interpolation from two consecutive sampled received data. Is a circuit that generates This will be described in detail later with reference to FIGS.

The zero-cross extractor 44 using the gradient is a straight line starting from received data having a small data value in two consecutive sampled received data, and obtained from the past consecutive sampled received data. The second zero-cross data obtained using a straight line having a ratio of the time increment and the time increment is calculated from the average of the data values S _{1 and} the average of the plurality of data values S ₂ of the plurality of past received data. This is a circuit for generating zero-cross phase information 452. This will be described in detail later with reference to FIGS.

  The selector 47 selects the first zero-cross phase information 431 from the zero-cross extractor 42 as the zero-cross phase information when the logic of the discrimination signal 45 from the timing discriminator 41 is logic “H”, and the timing discriminator 41. 2 is selected as the zero-cross phase information 46, the second zero-cross phase information 452 from the gradient-use zero-cross extractor 44 is selected.

FIG. 3 is a flowchart for explaining the operation of the phase comparator 40 according to the first embodiment.
op10: The phase comparator 40 receives three received data from the DMX circuit 3. Then, arbitrary two received data are selected from the three received data.
op20: The timing discriminator 41 is the product of the data values S ₁ and S ₂ of any two selected received data, that is, whether S ₁ × S ₂ is less than 0 (S ₁ × S ₂ <0) Judging. When S ₁ × S ₂ <0, it is determined that there is a transition of received data, and the process proceeds to op40. However, if S ₁ × S ₂ <0 is not satisfied, it is determined that there is no transition of received data, and the process proceeds to op30.

op30: The phase comparator 40 selects the other two received data different from the received data handled in op20, and proceeds to op20.
op40: The timing discriminator 41 compares the given threshold value Vth with the absolute values of the data values S ₁ and S ₂ of the received data. As a result, if the absolute values of the data values S ₁ and S ₂ are both greater than the threshold value Vth, it is determined that both of the two received data are present on the data transition, and then the operation proceeds to op50.
On the other hand, when _one of the absolute values of the data values S ₁ and S ₂ is smaller than the threshold value Vth, it is determined that only one received data exists on the data transition. It is assumed that the reception data existing on the data transition is reception data having a small data value. Then, it progresses to op60.

op50: The timing discriminator 41 outputs a discrimination signal 45 of logic “H” to the selector 47, and proceeds to op70.
op60: The timing discriminator 41 outputs a discrimination signal 45 of logic “L” to the selector 47, and proceeds to op70.

op70: The zero cross extractor 42 generates first zero cross phase information. Then, it progresses to op80.
op80: The selector 47 outputs the first zero-cross phase information as the zero-cross phase information when the logic of the discrimination signal 45 output from the timing discriminator 41 is “H”, and the logic of the discrimination signal 45 is “L”. In this case, the second zero cross phase information is output as zero cross phase information.

4A and 4B are diagrams illustrating parameters that determine the logic of the timing discriminator 41 and the discrimination signal 45. FIG.
FIG. 4A is a diagram for explaining the timing discriminator 41. The timing discriminator 41 is a circuit that outputs a discriminating signal 54 having the following logic in accordance with the relationship between the data values S ₁ and S _{2 of} two consecutive received data 50 and a predetermined threshold value Vth. is there.
When the product of S ₁ and S ₂ (S ₁ × S ₂ ) is less than 0 and both the absolute value of S _{1 and} the absolute value of S ₂ are equal to or greater than a predetermined threshold value Vth, The logic is logic “H”.
When the product of S ₁ and S ₂ (S ₁ × S ₂ ) is less than 0, and either the absolute value of S ₁ or the absolute value of S ₂ is less than or equal to a predetermined threshold value Vth The logic of the determination signal is logic “L”.

FIG. 4B is a diagram illustrating parameters that determine the logic of the determination signal 45. That is, FIG. 4B is a diagram showing an axis representing data values on the vertical axis and a time axis represented by dotted lines on the horizontal axis. The parameters that determine the logic of the discrimination signal 45 are sampled received data 51 represented by (t ₁ , S ₁ ), sampled received data 52 represented by (t ₂ , S ₂ ), threshold Vth, The threshold value is −Vth.
The sampled received data 51 represented by (t ₁ , S ₁ ) indicates that the data value is S ₁ when the received signal data is sampled at time t1.
The sampled received data 52 represented by (t ₂ , S ₂ ) indicates that the data value is S ₂ when the received signal data is sampled at time t ₂ .
The threshold value Vth is a positive constant value set in advance with respect to the data value. The threshold value −Vth is a negative constant value set in advance with respect to the data value.
In addition, FIG. 4B also shows the received signal data represented by the sampled received data 53 represented by (t ₃ , S ₃ ), the zero cross point represented by (tx, 0), a solid line, and a curve. In addition, an inversion signal datax of the received signal represented by a dotted line and a curve, a zero-cross vector Phi representing the difference in time coordinates between the received data 51 and the zero-cross point, and a dotted line running on the 0 value of the data value are shown.
The sampled received data 52 represented by (t ₃ , S ₃ ) indicates that the data value is S3 when the received signal data is sampled at time t3.
The zero cross point represented by (tx, 0) is the intersection of the solid line connecting the received data 51 and the received data 52 and the time axis represented by the dotted line on the zero level of the data value. This is a point approximated to be an intersection of a line representing received data and a time axis represented by a dotted line on the zero level of the data value.
The zero cross vector phi is a vector defined on the time axis from the time t ₁ when the reception data 51 is sampled to the time tx of the zero cross point. However, when the output from the phase comparator 40 is output as difference data for tx and t _1.

FIG. 5 is a diagram showing the zero cross extractor 42. The zero-cross extractor 42 includes arithmetic units 421 and 423, an adder 422, and a zero-cross phase information selector 424.
The computing unit 421 is a circuit that multiplies the absolute value of the data value S ₁ of the received data received at the input terminal 425 by 4.
The adder 422 is a circuit that adds the absolute value of the data value S _{1 and} the absolute value of the data value S ₂ of the received data received from the input terminal 425 and the input terminal 426.
The arithmetic unit 423 is a circuit that multiplies the absolute value of the data value S ₂ of the received data received at the input terminal 426 by 4.
When _one of the following relational expressions is established for the data value S ₁ and the data value S ₂ , the zero-cross phase information selector 424 converts the phase represented by the binary number corresponding to the relational expression to the zero crossing. It is a circuit that outputs as phase information 431.
When the relational expression 1 | S ₂ | <| S ₁ | and 4 × | S ₂ | <| S ₁ | + | S ₂ | holds, the phase 427 represented by the binary number (11) is expressed as zero-crossing phase information. 431 is output.
When the relational expression 2 | S ₂ | <| S ₁ | and 4 × | S ₂ |> | S ₁ | + | S ₂ | holds, the phase 428 represented by the binary number (10) is expressed as zero-cross phase information. 431 is output.
When the relational expression 3 | S ₁ | <| S ₂ | and 4 × | S ₁ |> | S ₁ | + | S ₂ | holds, the phase 429 represented by the binary number (01) is expressed as zero-crossing phase information. 431 is output.
When the relational expression 4 | S ₁ | <| S ₂ | and 4 × | S ₁ | <| S ₁ | + | S ₂ | holds, the phase 430 represented by the binary number (00) is expressed as zero-cross phase information. 431 is output.
The input terminal 425 is connected to the zero cross phase information selector 424, the multiplier 421, and the adder 422. The input terminal 426 is connected to the zero cross phase information selector 424, the multiplier 423, and the adder 422.

  FIG. 6 is a diagram illustrating the principle of the zero cross phase information selector 424. In FIG. 6, the horizontal axis represents the phase in the clock for sampling the received data. On the other hand, the vertical axis represents the data value of the sampled received data. Assuming that one period of the clock is phase 1, sampling of the received signal by the clock is performed at the rising edge and falling edge of the clock, so the time interval between two consecutive received data is 1 / clock of the clock. It corresponds to two phases.

Satisfy the above relation 1, when S ₁ is a negative number, the line connecting the received data 52 and the received data 51 is included in the upper right of the rhombic region of (1) in FIG. Therefore, the phase of the zero cross point represented by (tx, 0) is in the range from phase 3/8 to phase 1/2. Here, when the phase of the zero cross point is within the range from the phase 3/8 to the phase 1/2, the phase is expressed by the binary number (11). Therefore, the zero cross phase information selector 424 has the zero cross phase. The phase 427 is output as information 431.
Satisfy the above relation 2, when S ₁ is a negative number, the line connecting the received data 51 received data 52 is included in the rhombic region of (2) in FIG. Therefore, the phase of the zero cross point represented by (tx, 0) is in the range from phase 1/4 to phase 3/8. Then, similarly to the above, the zero cross phase information selector 424 outputs the zero cross phase information 431 represented by the binary number (10).
Satisfy the above relation 3, when S ₁ is a negative number, the line connecting the received data 51 received data 52 is included in the rhombic region of (3) in FIG. Therefore, the phase of the zero cross point represented by (tx, 0) is in the range from phase 1/8 to phase 1/4. Then, similarly to the above, the zero cross phase information selector 424 outputs zero cross phase information 431 represented by a binary number (01).
Satisfy the above relation 4, when S ₁ is a negative number, the line connecting the received data 51 received data 52 is included in the rhombic region of (4) in FIG. Therefore, the phase of the zero cross point represented by (tx, 0) is in the range from phase 0 to phase 1/8. Then, similarly to the above, the zero cross phase information selector 424 outputs the zero cross phase information 431 represented by a binary number (00).
In the above description, the case where S ₁ is a negative numerical value is described. However, when S ₁ is a positive numerical value, the lines connecting the reception data 51 and the reception data 52 are (1) and (2) in FIG. ), (3), and (4) are included in the rhombus region and the rhombus region that is a line object with respect to the zero level. As a result, even if S ₁ is a positive numerical value, the zero-cross phase information 431 is expressed by (11), (10), (01), (00) corresponding to the relational expressions 1, 2, 3, and 4. The zero cross phase information 431 is output.
That is, the zero cross phase information selector 424 outputs the zero cross phase information 431 related to the phase of the zero cross point in accordance with the data values of the two consecutive received data.

7A and 7B are diagrams showing a zero-cross extractor 44 using inclination. The slope-utilized zero-cross extractor 44 shown in FIG. 7A includes arithmetic units 441 and 443, an average value generator 442, and a zero-cross phase information selector 444.
The arithmetic unit 441 is a circuit that multiplies the absolute value of the data value S ₁ of the received data received at the input terminal 445 by 4.
The calculator 443 is a circuit that multiplies the absolute value of the data value S ₂ of the received data received at the input terminal 447 by 4.
The average value generator 442 includes a plurality of reception data sampled before the reception data 51 and the reception data 52 are sampled, corresponding to a terminal that receives the reception data 51 and a terminal that receives the reception data 52. keeping. The average values M1 and M2 of the received data acquired in the past are held for each terminal. Then, receiving the discrimination signal 54, performs an operation when the logic is "L" of the discrimination signal 54, the average value M1, M2, absolute values of the data values _{S 1,} the absolute value of the data values _{S 2,} in Figure 7B (| S ₁ | + | S ₂ |) _AVG is calculated by the following formula. An example of the logic circuit of the average value generator 442 is shown in FIG. 7B.
When _one of the following relational expressions is established for the data value S ₁ and the data value S ₂ , the zero-cross phase information selector 444 converts the phase represented by the binary number corresponding to the relational expression to the zero crossing. This is a circuit that outputs the phase information 452.
Relational expression 5 | S ₂ | <| S ₁ | and 4 × | S ₂ | <(| S ₁ | + | S ₂ |) When _AVG is established, a phase 448 represented by a binary number (11) is expressed. Output as zero-cross phase information 452.
Relational expression 6 | S ₂ | <| S ₁ | and 4 × | S ₂ |> (| S ₁ | + | S ₂ |) When _AVG is established, a phase 449 represented by a binary number (10) is expressed. Output as zero-cross phase information 452.
Relational Expression 7 | S ₁ | <| S ₂ | and 4 × | S ₁ |> (| S ₁ | + | S ₂ |) When _AVG is established, a phase 450 expressed by a binary number (01) is expressed. Output as zero-cross phase information 452.
Relational Expression 8 | S ₁ | <| S ₂ | and 4 × | S ₁ | <(| S ₁ | + | S ₂ |) When _AVG is established, a phase 451 represented by a binary number (00) is expressed. Output as zero-cross phase information 452.

FIG. 7B shows a logic diagram of the average value generator 442. The average value calculation unit 442 includes an adder 455, a signal gate 457, a storage circuit 456, a calculator 457, and a switch 458.
The average value generator 442 receives the data value S ₁ and the data value S ₂ , performs an addition operation on the absolute value of the data value S _{1 and} the absolute value of the data value S ₂ , and adds the added value (| S ₁ | + | S ₂ |) (hereinafter referred to as S ₁ S ₂ addition), data value S ₁ and data value received before data value S ₂ and data received from terminal 445 average value M1 corresponding to the historical data values S _1, the average value M2 corresponding to the historical data of the data values S ₂ received from the terminal 445, a memory circuit 456 for storing the respective operations along the equation 9 below And a switch 458 for selecting which one of the results of the adder 455 and the calculator 457 is to be output according to the logic of the determination signal 54. That is, the average value generator 442 outputs the following calculated value.
In the case of the logic “H” of the determination signal, (| S ₁ | + | S ₂ |) _AVG = (| S ₁ | + | S ₂ |)
In the case of the logic “L” of the discrimination signal, (| S ₁ | + | S ₂ |) _AVG
= K1 × K2 × M / (s ² + K1 × s + K1 × K2)
―――――― Relational formula 9
Here, K1 and K2 are predetermined constants. S is the frequency of the sampling clock. M is an added value of the average value M1 and the average value M2.

FIG. 8 is a diagram illustrating the principle of the zero-cross extractor 44 using inclination. In FIG. 8, the horizontal axis represents a phase in a clock for sampling received data. On the other hand, the vertical axis represents the data value of the sampled received data. Assuming that one period of the clock is phase 1, sampling of the received signal by the clock is performed at the rising edge and falling edge of the clock, so the time interval between two consecutive received data is 1 / clock of the clock. It corresponds to two phases. In FIG. 8, the solid line is the actual received data. A one-dot chain line is a one-dot chain line connecting the reception data 51 and the reception data 52. Furthermore, the dotted line is a straight line starting from the reception data 51 and having a slope obtained from the increment of the data value per unit time obtained from the reception data sampled in the past. In addition, it is calculated | required by the increment (| M1 | + | M2 |) / (T2-T1) of the data value per unit time calculated | required from the received data sampled in the past. Here, M1 and M2 are average values of the data values accumulated in the average value generator 442, and T1 and T2 are average values of the sampling times of the received data fetched from the terminals 445 and 447, respectively.
In addition, when the time coordinate of the intersection of the straight line (dashed line) connecting the reception data 51 and the reception data 52 and the line indicating that the data value is zero level is compared with the time coordinate of the zero cross point, It can be seen from FIG. 8 that the time coordinate at the zero cross point is closer to the time coordinate at the intersection of the actual received data (solid line) and the line indicating that the data value is zero level. When the zero cross point is obtained using a straight line having a slope obtained from the increment of data per unit time, obtained from the reception data 51 closer to the zero level and obtained from the reception data sampled in the past, the reception data This is because the data value of 52 is not affected.

Satisfy the relationship 5 above, when S ₁ is a negative number, a straight line with one starting point the received data 51, obtained from the received data sampled in succession past per unit of time A straight line having a slope obtained from the increment of the data value falls within the rhombus region of (1) in FIG.
Therefore, the phase of the zero cross point represented by (tx, 0) is in the range from phase 0 to phase 1/8. Here, when the phase of the zero cross point is in the range from phase 0 to phase 1/8, the phase is represented by binary number (11). Therefore, the zero cross phase information selector 444 has zero cross phase information 452. As a result, the phase 448 is output.
Satisfy the above relation 6, when S ₁ is a negative number, a straight line with one starting point the received data 51, obtained from the received data sampled in the past, the data value per unit time A straight line having a slope obtained from the increment enters the rhombus region of (2) in FIG.
Therefore, the phase of the zero cross point represented by (tx, 0) is in the range from phase 1/8 to phase 1/4. Then, similarly to the above, the zero-cross phase information selector 444 outputs zero-cross phase information 452 expressed by a binary number (10).
Satisfy the above relation 7, when S ₁ is a negative number, a straight line with one starting point the received data 51, obtained from the received data sampled in succession past per unit of time A straight line having a slope obtained from the increment of the data value falls within the rhombus region of (3) in FIG.
Therefore, the phase of the zero cross point represented by (tx, 0) is in the range from phase 1/4 to phase 3/8. Then, similarly to the above, the zero-cross phase information selector 444 outputs zero-cross phase information 452 expressed by a binary number (01).
Satisfy the above relation 8, when S ₁ is a negative number, a straight line with one starting point the received data 51, obtained from the received data sampled in succession past per unit of time A straight line having a slope obtained from the increment of the data value falls in the rhombic area of (4) in FIG. Therefore, the phase of the zero cross point represented by (tx, 0) is in the range from phase 3/8 to phase 1/2. Then, similarly to the above, the zero-cross phase information selector 444 outputs zero-cross phase information 452 expressed by a binary number (00).
In the above description, the case where S ₁ is a negative numerical value is described. However, when S ₁ is a positive numerical value, lines starting from the reception data 51 are represented by (1), (2), and FIG. It is included in the rhombus regions shown in (3) and (4) and the rhombus region that is a line object with respect to the zero level. As a result, even if S ₁ is a positive numerical value, the zero-cross phase information 452 is expressed by (11), (10), (01), (00) corresponding to the relational expressions 1, 2, 3, and 4. The zero cross phase information 431 is output.
That is, the zero-cross phase information selector 444 outputs phase information corresponding to the phase range of the zero-cross point, that is, zero-cross phase information 452 from two consecutive received data.

From the above, the phase comparator 40 according to the first embodiment that detects the phase of the zero cross point between the first reception data and the second reception data sampled in synchronization with the clock is as follows.
A timing discriminator (timing discriminator 41) for generating a discriminating signal having a logic corresponding to the first data value of the first received data and the second data value of the second received data;
A first zero cross time at which the data value becomes zero, which is obtained by interpolation calculation from the sampling time and the first data value of the first received data and the sampling time and the second data value of the second received data; A first zero-cross extractor (zero-cross extractor 42) for extracting first phase information relating to the phase of the rising edge of the sampling clock;
Based on the sampling time of the first data value and the first received data, the second zero crossing time at which the data value becomes zero, the rising edge of the sampling clock, which is obtained by using the increment of the data value per unit time, A second zero cross extractor (zero cross extractor 44) for extracting second phase information relating to the phase with the second zero cross time;
The phase comparator includes a selector (selector 47) that selects one of the first phase information and the second phase information corresponding to the logic of the determination signal.
The logic corresponding to the first data value and the second data value is derived from the comparison result between the first data value and the first threshold value and the comparison result between the second data value and the second threshold value. Features.
Then, when one of the absolute value of the data value of the first received data or the absolute value of the second received data value is less than or less than the first threshold value or the second threshold value, the selector 47 selects the second zero cross extractor 44. Select results from. On the other hand, if both of the absolute value of the first received data value or the absolute value of the second received data value are equal to or greater than the first threshold value, the second threshold value, or exceeded the threshold value, the selector 47 selects the first value. The result from the zero cross extractor 42 is selected. Therefore, the phase comparator can extract the phase information based on the zero cross point closer to the actual zero cross point.

Furthermore, in the phase comparator 40 of the first embodiment,
The first zero cross extractor obtains a result value obtained by doubling the smaller one of the absolute value of the first data value or the absolute value of the second data value, and the absolute value of the first data value. Extracting the first phase information according to a comparison result between a value and an average value of absolute values of the second data values;
The second zero cross extractor is configured to sample a result value obtained by doubling an absolute value of the first data value or a smaller one of the absolute values of the second data value and the first received data. The second phase information is extracted according to a comparison result with time or an average value of third data values of a plurality of third reception data sampled before the sampling time of the second reception data.

From the above, the clock recovery circuit 10 according to the first embodiment is
An analog-digital conversion circuit that samples a plurality of received data in synchronization with a clock and converts the data value of the received data from an analog value to a digital value;
A demax circuit that continuously arranges the plurality of received data in order of sampling time;
A phase comparator 40 for receiving the plurality of received data from a demax circuit, extracting a zero cross point between two of the received data, and outputting phase information between the zero cross point and the clock;
A filter that receives the phase information, accumulates a predetermined number of the phase information, obtains an average value from the accumulated phase information, and sets the average phase information;
A data determination unit that receives the phase information, the average phase information, and the plurality of reception data, and selects one of the plurality of reception data based on the phase information and the average phase information;
A phase interpolation circuit that receives the clock and adjusts the phase of the clock according to the phase information or average phase information to form a recovered clock; and
A FIFO that stores received data selected by the data determiner from the plurality of received data in synchronization with the clock, and outputs the received data selected by the data determiner based on the restored clock; A clock recovery circuit comprising:
Then, since the clock recovery circuit includes the phase comparator that extracts the phase information of the zero cross point between the reception data sampled by the internal clock with high accuracy, the phase of the zero cross point can be grasped with high accuracy. Therefore, the clock recovery circuit can grasp the boundary of the received data with higher accuracy when the zero cross point is the boundary of the received data. Therefore, the clock recovery circuit can extract the position of the center of the received data based on the zero cross point estimated by the phase comparator that is closer to the actual zero cross point. The sampled received data can be output in synchronization with the restoration clock.

The phase comparator 40 according to the first embodiment sequentially selects any two consecutive received data from the three received data received, and whether there is a zero cross point between the two selected received data. The phase comparator 40 outputs xerox phase information 46 from two received data having the specified zero-cross point in between.
Then, the timing discriminator 41 of the phase comparator 40 according to the first embodiment causes the timing discriminator 41 to determine the state of the received data based on a predetermined threshold, and the phase comparator 40 The zero-cross phase information 46 is output by operating the data extractor 44 or the zero-cross extractor 42 using the slope according to the state.
However, the phase comparator according to the second embodiment is a phase comparator that determines the state of received data based on four consecutive received data without using a predetermined threshold value.
In the phase comparator 60 of the second embodiment, a part of the normal zero cross extractor and a part of the zero cross extractor using the gradient are made common to reduce the number of circuit components.
FIG. 9 shows the phase comparator 60 of the second embodiment. The phase comparator 50 includes a timing discriminator 61 and a zero cross extractor 62.
Timing discriminator 61, four reception data (0th received data (t0, S0), first reception data _{(t 1, S} 1), second reception data _{(t 2, S} 2), third received data (T ₂ , S ₃ )) is received, and when the data value of each received data is in the state shown by the relational expression in FIG. 10A, a determination signal having a logic corresponding to that state is output. The relational expression in FIG. 10A and the logic of the discrimination signal corresponding thereto will be described later with reference to FIG. 10A.
The zero-cross extractor 62 operates as the gradient-based zero-cross extractor 44 described in the first embodiment when the logic of the determination signal is logic “L”, but when the logic of the determination signal is logic “H”, This is a circuit that operates as the zero-cross extractor 42 described in the first embodiment. The detailed circuit configuration will be described with reference to FIG.

10A and 10B are diagrams for explaining the timing discriminator 61 and parameters for determining the logic of the discrimination signal. The timing determiner 61 shown in FIG. 10A is represented by received data 64 represented by (t ₀ , S ₀ ), received data 65 represented by (t ₁ , S ₁ ), and (t ₂ , S ₂ ). In response to the received data 67 represented by (t3, S3), a determination signal 63 having the following logic is generated according to the relationship defined for each data value of the received data 64-67. It is a circuit to output.
Condition 1 (S ₀ × S ₁ is less than 0 and S ₁ × S ₂ is less than 0 and the absolute value of S ₂ is greater than the absolute value of S ₀ ) or Condition 2 If S ₁ × S ₂ is less than 0 and S ₂ × S ₃ is less than 0 and the absolute value of S ₁ is larger than the absolute value of S ₃ , The logic is logic “L”.
When the condition 1 is not satisfied and the condition 2 is not satisfied, the logic of the determination signal 63 is logic “H”.
In the first embodiment, the condition is that the data value of the second received data is larger than the data value of the zeroth received data and the data value of the third received data is larger than the data value of the first received data. A condition similar to the condition that “the received data value of the first received data and the data value of the second received data are both larger than the absolute value of the predetermined threshold value” is secured for the first received data and the second received data. ing.
The reason for doing so is that both the data value of the first received data and the data value of the second received data are sufficiently larger than the data value 0. This is because the condition is to use a xerox extractor that is not a zero-cross extractor.

FIG. 10B is a diagram illustrating parameters that determine the logic of the determination signal 63. In FIG. 4B, the vertical axis represents the data value, and the horizontal axis represents the time axis indicated by the dotted line. Received data 64 parameter represented by (t0, S0) to determine the logic of the determination signal _{63, (t 1, S 1} ) received data 65 represented by _the received expressed by _{(t 2, S} 2) Received data 67 represented by data 66, (t ₃ , S ₃ ), and obtained by sampling the received signal data represented by a solid line at time t ₀ , t ₁ , t ₂ , t ₃ with an internal clock. Received data. Note that the dotted curve is a signal having inverted logic with respect to the received signal data. The zero cross point represented by (tx, 0) is the intersection of the solid line connecting the received data 65 and the received data 66 and the time axis represented by the dotted line on the data value 0, and the actual received data is This is a point that is estimated to be the intersection of the line represented and the time axis represented by the dotted line on the data value 0.
The zero cross vector phi is a vector defined on the time axis from the time t1 when the reception data 51 is sampled to the time tx of the zero cross point. However, when it is output from the phase comparator 60, it is output as difference data between tx and t1.

FIG. 11 shows the zero cross extractor 62 of the second embodiment. The zero-cross extractor 62 includes computing units 621 and 625, an adder 622, a selector 623, an average value generator 624, and a zero-cross phase information selector 633.
The calculator 621 is a circuit that multiplies the absolute value of the data value S ₁ of the received data received at the input terminal 626 by 4.
The adder 622 is a circuit that adds the absolute value of the data value S _{1 and} the absolute value of the data value S ₂ of the received data received from the input terminal 628 and the input terminal 628.
The arithmetic unit 625 is a circuit that multiplies the absolute value of the data value S ₂ of the received data received at the input terminal 628 by 4.
The average value generator 624 receives the discrimination signal 63 and operates when the logic of the discrimination signal 63 is “L”. From the absolute value of the data value S _{1 and} the absolute value of the data value S ₂ , the average value generator 624 is shown in FIG. 7B. (| S ₁ | + | S ₂ |) _AVG represented by the equation is calculated. Note that the average value generator 624 is a circuit having a function of performing the calculation of the relational expression 9 similarly to the average value generator 442.
The selector 623 selects the operation result of the adder 622 and outputs it as a signal representing the numerical value A when the logic of the determination signal 63 is “H”. On the other hand, when the logic of the discrimination signal 63 is “L”, the selector 623 selects the calculation result of the average value generator 624 and outputs it as a signal representing the numerical value A.
When _one of the following relational expressions is established for the data value S ₁ and the data value S ₂ , the zero-cross phase information selector 633 converts the phase expressed by the binary number corresponding to the relational expression to the zero crossing. This is a circuit that outputs the phase information 64.
When the relational expression 10 | S ₂ | <| S ₁ | and 4 × | S ₂ | <A holds, the phase 629 represented by the binary number (11) is output as the zero-cross phase information 64.
When the relational expression 11 | S ₂ | <| S ₁ | and 4 × | S ₂ |> A holds, the phase 630 represented by the binary number (10) is output as the zero-cross phase information 64.
When the relational expression 12 | S ₁ | <| S ₂ | and 4 × | S ₁ |> A holds, the phase 631 represented by the binary number (01) is output as the zero-cross phase information 64.
When the relational expression 13 | S ₁ | <| S ₂ | and 4 × | S ₁ | <A holds, the phase 632 represented by the binary number (00) is output as the zero-cross phase information 64.
The input terminal 626 is connected to the average value generator 624, the multiplier 621, the adder 622, and the zero cross phase information selector 633. The input terminal 428 is connected to the average value generator 624, the multiplier 625, the adder 622, and the zero cross phase information selector 424. The input terminal 627 receives the discrimination signal 63 and is connected to the average generator 624 and the selector 623.

From the above, the phase comparator 60 of the second embodiment is
A timing discriminator (timing discriminator 61) for generating a discrimination signal having logic corresponding to the first data value of the first reception data and the second data value of the second reception data;
A first average value generator that obtains an average of the first data value and the second data value as a first average value;
A second average value generator that obtains an average of the third data values of a plurality of third received data sampled before the sampling time of the first received data or the sampling time of the second received data and sets it as a second average value; ,
A select circuit for selecting the first average value or the second average value according to the logic of the determination signal;
When the first average value is output from the select circuit, an interpolation calculation is performed from the sampling time and the first data value of the first reception data, and the sampling time and the second data value of the second reception data. First phase information relating to the phase between the first zero cross time when the data value becomes zero and the rising edge of the sampling clock is obtained, the first average value, the absolute value of the first data value, or the second data value. According to the comparison result with the result value obtained by doubling the smaller one of the absolute values of
When the second average value is output from the select circuit, the data value obtained using the increment of the data value per unit time based on the sampling time of the first data value and the first received data The second phase information regarding the phase of the second zero cross time when the zero becomes zero, the rising edge of the sampling clock and the second zero cross time, the second average value, the absolute value of the first data value, or the second data value And a logic discriminating circuit that extracts in accordance with a comparison result with a result value obtained by doubling the smaller one of the absolute values of the phase comparator.
However, in the phase comparator 60 of the second embodiment, the timing discriminator (timing discriminator 61) continuously samples the 0th data value of the 0th received data (sampled before the first received data). Received data) and the first data value of the first received data, the comparison result of the first data value of the first received data and the second data value of the second received data, the second data of the second received data A comparison result between the value and the third data value of the third received data (received data sampled after the second received data), and the third data value of the third received data and the first value of the zeroth received data A determination signal having logic corresponding to the states of the zeroth data value, the first data value, the second data value, and the third data value, which is derived from the comparison result with the zero data value; To occur The features.
The zero-cross extractor 62 according to the second embodiment is a circuit including calculators 621 and 625, an adder 622, a selector 623, an average value generator 624, and a zero-cross phase information selector 633. Here, the zero-cross phase information selector 633 is a circuit that operates as both the zero-cross extractor 42 of the first embodiment and the zero-cross extractor 44 using the gradient of the first embodiment according to the numerical value A output from the selector 623. is there. Then, the circuit has the same function as the zero-cross extractor 62 of the second embodiment and the zero-cross extractor 42 of the first embodiment.
In the phase comparator 60 of the second embodiment, the timing discriminator 61 does not use a predetermined threshold value, and whether or not the first reception data or the second reception data is close to the zero level. Can be detected by using the 0th received data and the 3rd received data before and after.

The phase comparator 40 according to the first embodiment sequentially selects any two consecutive received data from the three received data received, and whether there is a zero cross point between the two selected received data. The phase comparator 40 outputs xerox phase information 46 from two received data having the specified zero-cross point in between.
On the other hand, the phase comparator according to the third embodiment is a phase comparator that specifies a zero cross point from all three received data and outputs zero cross information.
FIG. 12 is a diagram illustrating a phase comparator 80 according to the third embodiment. The phase comparator 80 receives three sampled received data (received data a represented by (ta, Sa), received data b represented by (tb, sb), and received by (tc, Sc). This is a circuit that receives data c, has a zero-cross point between any received data, and outputs zero-cross phase information 96 for the zero-cross point, and a phase comparator 80 includes zero-cross extractors 81 and 82, adders 84, 85, It consists of binary code data storage circuits 83 and 86, arithmetic circuits 89 and 91, 1 addition circuits 90 and 92, most significant bit setting circuits 87 and 88, a selector 94, a mode circuit 93, and a 4-bit latch circuit 95. .

The zero-cross extractor 81 receives the two received data a and the received data b, and determines whether the zero-cross point is between the two received data a and b and the range of the phase range of the zero-cross point. This circuit is detected and represented by a binary code, and details thereof will be described with reference to FIGS. Note that the zero-cross extractors 81 and 82 respectively include phase-range binary codes u-ab and u-bc indicating the zero-cross point phase range and transition binary codes tran-ab and tran- indicating that the zero-cross point exists. bc is output. The zero-cross extractor 82 receives the two pieces of received data b and c, and performs the same operation as the zero-cross extractor 81.
The adder 84 adds the binary code u-ab output from the zero cross extractor 81 and the binary code u-bc output from the zero cross extractor 82, and outputs the binary code u-abc after the addition. Circuit.
The adder 85 is a circuit that adds the binary code u-abc output from the adder 84 and the binary code 97 represented by (1101) output from the binary code data storage circuit 86.
The arithmetic circuit 89, the most significant bit setting circuit 87, and the 1 addition circuit 90 perform an operation of doubling the binary code u-ab output from the zero cross extractor 81, and set the most significant bit to 0. The circuit adds 1 to the binary code obtained as a result.
The arithmetic circuit 91, the most significant bit setting circuit 88, and the 1 addition circuit 92 perform an operation of doubling the binary code u-bc output from the zero cross extractor 82, and set the most significant bit to 0. The circuit adds 1 to the binary code obtained as a result.
The mode circuit 93 is a circuit that performs a mode 16 operation, that is, an operation of cutting out the lower 4 bits, on the binary code 99 output from the adder 85.
The selector 94 selects one of the four input signals by combining the logical value of the binary code tran-ab from the zero-cross extractor 81 and the logical value of the binary code tran-bc from the zero-cross extractor 82, This circuit outputs a selected signal. Specifically, the selector 94 outputs a signal from the binary code storage circuit 83 when the binary code tran-ab and the binary code tran-bc are (00). The selector 94 outputs a signal from the 1 addition circuit 90 when the binary code tran-ab and the binary code tran-bc are (10). The selector 94 outputs a signal from the 1 addition circuit 92 when the binary code tran-ab and the binary code tran-bc are (01). The selector 94 outputs a signal from the mode circuit 93 when the binary code tran-ab and the binary code tran-bc are (11).

FIG. 13 is a diagram for explaining the details of the zero-cross extractor 81. The zero-cross extractor 81 includes operation circuits 811 and 813, subtraction circuits 812 and 814, addition circuits 815 and 816, and a logic determination circuit 817. The zero cross extractor 82 is a circuit having the same configuration as the zero cross extractor 82.
The arithmetic circuit 811 is a circuit that quadruples the data value Sa of the input received data a. The subtraction circuit 812 is a circuit that subtracts the data value Sb of the reception data b input from the − terminal from the data value Sa of the reception data a input from the + terminal. The subtraction circuit 814 subtracts the data value (Sa−Sb) from the subtraction circuit 812 input from the −terminal from the data value 4 × Sa input from the arithmetic circuit 811 input from the + terminal, and the result , A circuit for outputting a data value (3Sa + Sb).
The adder circuit 815 is a circuit that adds the data value Sa and the data value Sb and outputs a data value (Sa + Sb).
The arithmetic circuit 813 is a circuit that quadruples the data value Sb of the input received data b. The adder circuit 816 is a circuit that subtracts the data value (Sa−Sb) from the subtraction circuit 812 from the data value 4 × Sb from the arithmetic circuit 813 and outputs the data value (Sa + 3 × Sb) as a result. is there.
The logic determination circuit 817 receives the data value Sa, the data value (3Sa + Sb) from the subtraction circuit 814, the data value (Sa + Sb) from the addition circuit 815, and the data value (Sa + 3 × Sb) from the addition circuit 816. This is a circuit for determining whether or not the relational expressions 14, 15, 16, 17, 18 are satisfied. When the relational expressions 14, 15, 16, and 17 are satisfied, the logic determination circuit 817 outputs the phase range binary code u-ab indicating the zero-cross point phase range corresponding to each relational expression. If the relational expression 18 is satisfied, the binary code tran-ab corresponding to the relational expression is output. Specifically, the relational expressions 14, 15, 16, 17 and the binary code u-ab corresponding to the relational expression are as follows. Further, the relational expression 18 and the binary code tran-ab corresponding to the relational expression are output.

When the relational expression 14 IF ((Sa> = 0) & (3Sa + Sb <0)) OR ((Sa <= 0) & (3Sa + Sb> 0)) = 1 is satisfied, the binary code u-ab is used as the binary code. 00 is output.
When the relational expression 15 IF ((3Sa + Sb> = 0) & (Sa + Sb <0)) OR ((3Sa + Sb <= 0) & (Sa + Sb> 0)) = 1 is satisfied, a binary code u-ab is used as a binary code 01 is output.
When the relational expression 16 IF ((Sa + Sb> = 0) & (Sa + 3 × Sb <0)) OR ((Sa + Sb <= 0) & (Sa + 3Sb> 0)) = 1 is satisfied, the binary code u−ab is 2 The decimal code 10 is output.
When the relational expression 17 IF ((Sa + 3Sb> = 0) & (Sb <0)) OR ((Sa + 3Sb <= 0) &(Sb> 0)) = 1 is satisfied, the binary code u-ab is used as the binary code. 11 is output.
When the relational expression 18 IF ((Sa> = 0) XOR ((Sb> = 0) is satisfied, the binary code 1 is output as the binary code tran-ab.

FIG. 14 is a diagram for explaining the operation principle of the zero-cross extraction circuit 81. In FIG. 14, the vertical axis represents the data value, and the horizontal axis represents the phase.
In FIG. 14, the data value of the reception data a sampled at time 0 is the data value Sa, and the data value of the reception data b sampled after a half cycle of the clock is the data value Sb. Here, assuming that the rising edge of the clock is phase 0, the half cycle of the clock corresponds to phase 1/2. The range from phase 0 to phase 1/8 is indicated by a binary number represented by (00), and the range from phase 1/8 to phase 1/4 is indicated by a binary number represented by (01). The range from phase 1/4 to phase 3/8 is represented by a binary number represented by (10), and the range from phase 3/8 to phase 1/2 is represented by a binary number represented by (11).
In FIG. 14, the data value Sa of the reception data a is a positive value, and the data value Sb of the reception data b is a negative value. Further, the data value Sa of the received data a is a positive value, but (3Sa + Sb) / 4 is a negative value.
Therefore, the operation principle will be described below. First, the zero-cross extraction circuit 81 determines that the zero-cross point is between the received data a and the received data b when the relation 18 is satisfied in the combination of the positive and negative data values Sa and the positive and negative data values Sb. “1” is output as the hexadecimal code tran-ab. For example, in FIG. 14, the condition of the relational expression 18 is satisfied (that is, the data value Sa of the received data a is positive and the data value Sb of the received data b is a negative number), and the received data A zero cross point exists between a and the received data b, and the zero cross extraction circuit 81 outputs “1” as the binary code tran-ab.
Next, the zero-cross extraction circuit 81 calculates a calculation result (that is, a value Sa, a value (3Sa + Sb) / 4, a value (Sa + Sb) / 2, a value (Sa + 3Sb) / 4) and a value 0 obtained from the value Sa and the value Sb. By comparison, the phase range in which the zero cross point exists can be determined. The reason is that the value Sa, the value (3 × Sa + Sb) / 4, the value (Sa + Sb) / 2, and the value (Sa + 3Sb) / 4 are straight lines connecting the coordinates (0, Sa) and the coordinates (1/2, Sb). This corresponds to the data value coordinates of the points intersecting with phase 0, phase 1/8, phase 1/4, phase 3/8, and phase 1/2, respectively. For example, in FIG. 14, the condition that satisfies the relational expression 15 is satisfied (that is, the data value Sa is a positive value and (3Sa + Sb) is a negative value, or the data value Sa is a negative value and (3Sa + Sb) is a positive value. The zero-cross extraction circuit 81 outputs “00” as the binary code u-ab.

From the above, the phase comparator 80 of the third embodiment is
When the first data value of the first received data (received data a) is positive and the second data value of the second received data (received data b) is negative, or the first data value of the first received data is negative When the second data value of the second received data is positive, it is determined that the first zero cross point is between the first received data and the second received data, and a first zero cross presence signal is output,
A first zero cross extractor for determining a first phase range of the first zero cross point by comparing zero with a result obtained by calculation from the first data value and the second data value;
When the second data value of the second received data (received data b) is positive and the third data value of the third received data (received data c) is negative, or the second data value of the second received data is When negative and the third data value of the third received data is positive, it is determined that the second zero cross point is between the second received data and the third received data, and the second zero cross presence signal is output. ,
A second zero cross extractor that determines a second phase range of the second zero cross point by comparing zero with a result obtained by calculation from the second data value and the third data value;
And a selector that selects one of the first phase range and the second phase range according to the logic of the first zero-cross presence signal and the logic of the second zero-cross presence signal.
The phase comparator 80 according to the third embodiment performs extraction of a zero cross point between the first reception data and the second reception data, and extraction of a zero cross point between the second reception data and the third reception data. This circuit outputs the phase range of the extracted zero cross point.
The first phase information of the first zero-cross extractor and the second phase information of the second zero-cross extractor according to the third embodiment are the first phase range from phase 0 to phase 1/8, and from phase 1/8 to phase 1 Information indicating one of the second phase range up to / 4, the third phase range from phase 1/4 to phase 3/8, and the fourth phase range from phase 3/8 to phase 1/2 It is characterized by that.

In the phase comparator 80 of the third embodiment, the phase range of the zero crossing point between the received data and the received data is obtained by interpolation from the data values of the received data, phase 0, phase 1/8, phase 1/4, phase It is obtained by comparing a data value corresponding to 3/8 and phase 1/2 with “0”. However, the phase range of the zero cross point can be set in more detail.
In the phase comparator of the fourth embodiment, the phase range of the zero cross point is from phase 0 to phase 1/16, phase 1/16 to phase 1/8, phase 1/8 to phase 3/16, and phase 3/16 to phase. Zero cross extractor that can specify the range of 1/4, phase 1/4 to phase 5/16, phase 3/16 to phase 7/16, phase 7/16 to phase 1/2 Reference numerals 101 and 110 denote phase comparators arranged in place of the zero-cross extractors 81 and 82 in the phase comparator of the third embodiment. However, since the zero cross extractor 101 outputs a 3-bit binary code, the arithmetic circuits 89 and 91 and the 1 adder circuits 90 and 92 are not necessary.

FIG. 15 is a diagram illustrating the zero-cross extractor 101 according to the fourth embodiment. The zero cross extractor 101 is a modification of the zero cross extractor 81 of the third embodiment. The zero-cross extractor 101 includes a subtraction circuit 102, an addition circuit 103, a shifter & adder 104, and a logic determination circuit 105.
The subtraction circuit 102 is a circuit that subtracts the data value Sb of the reception data b from the data value Sa of the reception data a.
The adder circuit 103 is a circuit that adds the data value Sa and the data value Sb.
The shifter & adder 104 uses the calculation result (Sa + Sb) of the addition circuit 103, the calculation result (Sa−Sb) of the subtraction circuit 102, the data value Sa and the data value Sb from the data terminal, and A = (7 × Sa + b), B = (3 × Sa + Sb), C = (5 × Sa + 3 × Sb), D = (3 × Sa + 5 × Sb), E = (Sa + 3 × Sb), F = (Sa + 7 × Sb) It is. However, using calculation results (Sa + Sb) and (Sa-Sb), addition is performed using adder, and multiplication is performed using shifter to calculate A to F according to the following modified formula.
A = 7 × Sa + b = 8 × Sa− (Sa−Sb), B = 3 × Sa + Sb = 4 × Sa− (Sa−Sb), C = 5 × Sa + 3 × Sb = 4 × (Sa + Sb) + (Sa−Sb) ), D = 3 × Sa + 5 × Sb = 4 × (Sa + Sb) − (Sa−Sb), E = Sa + 3 × Sb = 4 × Sb + (Sa−Sb), F = Sa + 7 × Sb = 8 × Sb + (Sa−Sb) )
The logic determination circuit 105 determines whether a 3-bit binary code (u-ab (2), binary code u-ab) depends on whether relational expressions 19, 20, 21, and 22 shown in FIG. (1) A binary code u-ab (0)) and a 1-bit binary code tran are output.

FIG. 16 is a diagram illustrating the logic determination circuit 105 according to the fourth embodiment. The logic determination circuit 105 receives the inputs A to F and determines whether the relational expressions 19 to 22 are satisfied. Depending on which relational expression is satisfied, a 3-bit binary code (u-ab106 ( 2) A binary code u-ab 106 (1), a binary code u-ab 106 (0)) and a 1-bit binary code tran 107 are output.
Relational Expression 19 u-ab (2) = (Sa + Sb> = 0) AND (Sb <0) + (Sa + Sb <= 0) AND (Sb> 0)
Relational expression 20 u−ab (1) = [(3 × Sa + Sb> = 0) AND (Sa + Sb <0) + (3 × Sa + Sb <= 0) AND (Sa + Sb> 0)] OR [(Sa + 3 × Sb> = 0 ) AND (Sb <0) + (Sa + 3 × Sb <= 0) AND (Sb> 0)]
Relational expression 21 u−ab (0) = [(7 × Sa + Sb> = 0) AND (3 × Sa + Sb <0) + (7 × Sa + Sb <= 0) AND (3 × Sa + Sb> 0)] OR [(5 × Sa + 3 × Sb> = 0) AND (Sa + Sb <0) + (5 × Sa + 3 × Sb <= 0) AND (Sa + Sb> 0)] OR [(3 × Sa + 5 × Sb> = 0) AND (Sa + 3 × Sb <0) ) + (3 × Sa + 5 × Sb <= 0) AND (Sa + 3 × Sb> = 0)] OR [(Sa + 7 × Sb> = 0) AND (Sb <0) + (Sa + 7 × Sb <= 0) AND (Sb> 0)]
Relational expression 22 tran = (Sa> = 0) XOR (Sb> = 0)
The zero-cross extraction circuit 105 has a value Sa, a value (7 × Sa + Sb) / 8, a value (3 × Sa + Sb) / 4, a value (5 × Sa + 3 × Sb) / 8, a value (Sa + Sb) / 2, and a value (3 × Sa + 5 × By comparing Sb) / 8, value (Sa + 3 × Sb) / 4, value (Sa + 7 × Sb) / 8, value Sb and value 0, the phase range in which the zero cross point exists can be determined. The reasons are: value Sa, value (7 × Sa + Sb) / 8, value (3 × Sa + Sb) / 4, value (5 × Sa + 3 × Sb) / 8, value (Sa + Sb) / 2, value (3 × Sa + 5 × Sb ) / 8, value (Sa + 3 × Sb) / 4, value (Sa + 7 × Sb) / 8, and value Sb are respectively the straight lines connecting coordinates (0, Sa) and coordinates (1/2, Sb). 0, phase 1/16, phase 1/8, phase 3/16, phase 1/4, phase 5/16, phase 3/8, phase 7/16, and the data value coordinate at the point where phase 1/2 is crossed It is because it corresponds.

From the above, the phase comparator of Example 4 is
When the first data value of the first received data (received data a) is positive and the second data value of the second received data (received data b) is negative, or the first data value of the first received data is negative When the second data value of the second received data is positive, it is determined that the first zero cross point is between the first received data and the second received data, and a first zero cross presence signal is output,
A first zero cross extractor (zero cross extractor 101) that determines a first phase range of the first zero cross point by comparing zero with a result obtained by calculation from the first data value and the second data value. )When,
When the second data value of the second received data (received data b) is positive and the third data value of the third received data (received data c) is negative, or the second data value of the second received data is When negative and the third data value of the third received data is positive, it is determined that the second zero cross point is between the second received data and the third received data, and the second zero cross presence signal is output. ,
A second zero-cross extractor (zero-cross extractor 110) that determines a second phase range of the second zero-cross point by comparing zero with a result obtained by calculation from the second data value and the third data value. )When,
And a selector that selects one of the first phase range and the second phase range according to the logic of the first zero-cross presence signal and the logic of the second zero-cross presence signal.
The phase information of the zero-cross extractor of the fourth embodiment includes the first phase range from phase 0 to phase 1/16, the second phase range from phase 1/16 to phase 1/8, and the phase 1/8 to phase 3/16. 3rd phase range up to, 4th phase range from phase 3/16 to phase 1/4, 5th phase range from phase 1/4 to phase 5/16, 5th phase range from phase 5/16 to 3/8 Including information indicating one of a sixth phase range, a seventh phase range from phase 3/8 to phase 7/16, and an eighth phase range from phase 7/16 to phase 1/2. To do.

The features of the present invention are described below.
(Appendix 1)
A timing discriminator for generating a discrimination signal having logic corresponding to the first data value of the first received data and the second data value of the second received data;
A first zero cross time at which the data value is zero level, obtained by interpolation calculation from the sampling time and the first data value of the first received data, and the sampling time and the second data value of the second received data. A first zero-cross extractor that extracts first phase information related to a phase relationship between the sampling clock and the rising edge of the sampling clock;
Based on the sampling time of the first data value and the first received data, the second zero crossing time at which the data value becomes zero level and the rising edge of the sampling clock, which are obtained by using the increment of the data value per unit time, A second zero cross extractor for extracting second phase information relating to the phase relationship of
And a selector that selects one of the first phase information and the second phase information corresponding to the logic of the determination signal.

(Appendix 2)
The logic corresponding to the first data value of the first received data and the second data value of the second received data is a comparison result between the first data value and a first threshold value and the second data value. The phase comparator according to appendix 1, wherein the phase comparator is derived from a comparison result of the second threshold value.

(Appendix 3)
The first zero cross extractor obtains a result value obtained by doubling the smaller one of the absolute value of the first data value or the absolute value of the second data value, and the absolute value of the first data value. Extracting the first phase information according to a comparison result between a value and an average value of absolute values of the second data values;
The second zero cross extractor is configured to sample a result value obtained by doubling an absolute value of the first data value or a smaller one of the absolute values of the second data value and the first received data. The second phase information is extracted according to a comparison result with a time or an average value of the third data values of a plurality of third reception data sampled before the sampling time of the second reception data. The phase comparator according to 1.

(Appendix 4)
A timing discriminator for generating a discrimination signal having logic corresponding to the first data value of the first received data and the second data value of the second received data;
A first average value generator that obtains an average of the first data value and the second data value as a first average value;
A second average value generator that obtains an average of the third data values of a plurality of third received data sampled before the sampling time of the first received data or the sampling time of the second received data and sets it as a second average value; ,
A select circuit for selecting the first average value or the second average value according to the logic of the determination signal;
When the first average value is output from the select circuit, an interpolation calculation is performed from the sampling time and the first data value of the first reception data, and the sampling time and the second data value of the second reception data. First phase information relating to the phase relationship between the first zero crossing time when the data value becomes zero and the rising edge of the sampling clock is obtained, the first average value, the absolute value of the first data value, or the second data. Extracted according to the comparison result with the result value obtained by doubling the smaller value of the absolute values,
When the second average value is output from the select circuit, the data value obtained using the increment of the data value per unit time based on the sampling time of the first data value and the first received data Second phase information relating to the phase relationship between the second zero crossing time when the zero becomes zero and the rising edge of the sampling clock, the second average value and the absolute value of the first data value or the absolute value of the second data value A phase comparator comprising: a logic discriminating circuit that extracts in accordance with a comparison result with a result value obtained by doubling the smaller value.

(Appendix 5)
The logic corresponding to the first data value of the first received data and the second data value of the second received data is calculated based on the first data value and the received data sampled before the first received data. The comparison result with the 0th data value, the comparison result between the first data value and the second data value, the third data value of the received data sampled after the second data value and the second received data The phase comparator according to claim 4, wherein the phase comparator is derived from a comparison result between the third data value and the zeroth received data.

(Appendix 6)
When the first data value of the first received data is positive and the second data value of the second received data is negative, or when the first data value is negative and the second data value is positive , Determining that the first zero cross point is between the first received data and the second received data, and outputting a first zero cross presence signal,
A first zero cross extractor for determining a first phase range of the first zero cross point by comparing zero with a result obtained by calculation from the first data value and the second data value;
When the second data value is positive and the third data value of the third received data is negative, or when the second data value is negative and the third data value is positive, the second zero crossing Determining that a point is between the second received data and the third received data, and outputting a second zero cross presence signal;
A second zero cross extractor that determines a second phase range of the second zero cross point by comparing zero with a result obtained by calculation from the second data value and the third data value;
A phase comparator comprising: a selector that selects one of the first phase range or the second phase range according to the logic of the first zero-cross presence signal and the logic of the second zero-cross presence signal.

(Appendix 7)
An analog-digital conversion circuit that samples a plurality of received data in synchronization with a clock and converts the data value of the received data from an analog value to a digital value;
A demax circuit that continuously arranges the plurality of received data in order of sampling time;
A phase comparator that receives the plurality of received data from a demax circuit, extracts a zero cross point between two of the received data, and outputs phase information between the zero cross point and the clock;
A filter that receives the phase information, accumulates a predetermined number of the phase information, obtains an average value from the accumulated phase information, and sets the average phase information;
A data determination unit that receives the phase information, the average phase information, and the plurality of reception data, and selects one of the plurality of reception data based on the phase information and the average phase information;
A phase interpolation circuit that receives the clock and adjusts the phase of the clock according to the phase information or average phase information to form a recovered clock; and
A FIFO that stores received data selected by the data determiner from the plurality of received data in synchronization with the clock, and outputs the received data selected by the data determiner based on the restored clock; A clock recovery circuit comprising:

  It is possible to provide a phase detector capable of detecting phase information of a zero cross point between received data sampled by an internal clock with high accuracy.

1, 2 ADC
3 DMX circuit 5 Data decision unit 6 Filter 7 FIFO
8 Phase Interpolation Circuit 10 Clock / Data Recovery Circuit 40, 60, 80 Phase Comparator 41 Timing Discriminator 42, 81, 101 Zero Cross Extractor 44 Inclined Zero Cross Extractor 45 Discrimination Signal 46 Zero Cross Phase Information 47 Selector

Claims (5)

A timing discriminator for generating a discrimination signal having logic corresponding to a first data value of the first received data and a second data value of the second received data;
A first zero cross time at which the data value is zero level, obtained by interpolation calculation from the sampling time and the first data value of the first received data, and the sampling time and the second data value of the second received data. A first zero-cross extractor that extracts first phase information related to a phase relationship between the sampling clock and the rising edge of the sampling clock;
Based on the sampling time of the first data value and the first received data, the second zero crossing time at which the data value becomes zero level and the rising edge of the sampling clock, which are obtained by using the increment of the data value per unit time, A second zero cross extractor for extracting second phase information relating to the phase relationship of
And a selector that selects one of the first phase information and the second phase information corresponding to the logic of the determination signal.   The logic corresponding to the first data value of the first received data and the second data value of the second received data is a comparison result between the first data value and a first threshold value and the second data value. The phase comparator according to claim 1, wherein the phase comparator is derived from a comparison result of the second threshold value. The first zero cross extractor obtains a result value obtained by doubling the smaller one of the absolute value of the first data value or the absolute value of the second data value, and the absolute value of the first data value. Extracting the first phase information according to a comparison result between a value and an average value of absolute values of the second data values;
The second zero cross extractor is configured to sample a result value obtained by doubling an absolute value of the first data value or a smaller one of the absolute values of the second data value and the first received data. The second phase information is extracted according to a comparison result with time or an average value of third data values of a plurality of third reception data sampled before a sampling time of the second reception data. Item 2. The phase comparator according to Item 1. A timing discriminator for generating a discrimination signal having logic corresponding to the first data value of the first received data and the second data value of the second received data;
A first average value generator that obtains an average of the first data value and the second data value as a first average value;
A second average value generator that obtains an average of the third data values of a plurality of third received data sampled before the sampling time of the first received data or the sampling time of the second received data and sets it as a second average value; ,
A select circuit for selecting the first average value or the second average value according to the logic of the determination signal;
When the first average value is output from the select circuit, an interpolation calculation is performed from the sampling time and the first data value of the first reception data, and the sampling time and the second data value of the second reception data. First phase information relating to the phase relationship between the first zero crossing time when the data value becomes zero and the rising edge of the sampling clock is obtained, the first average value, the absolute value of the first data value, or the second data. Extracted according to the comparison result with the result value obtained by doubling the smaller value of the absolute values,
When the second average value is output from the select circuit, the data value obtained using the increment of the data value per unit time based on the sampling time of the first data value and the first received data Second phase information relating to the phase relationship between the second zero crossing time when the zero becomes zero and the rising edge of the sampling clock, the second average value and the absolute value of the first data value or the absolute value of the second data value A phase comparator comprising: a logic discriminating circuit that extracts in accordance with a comparison result with a result value obtained by doubling the smaller value. An analog-digital conversion circuit that samples a plurality of received data in synchronization with a clock and converts the data value of the received data from an analog value to a digital value;
A demax circuit that continuously arranges the plurality of received data in order of sampling time;
A phase comparator that receives the plurality of received data from a demax circuit, extracts a zero cross point between two of the received data, and outputs phase information between the zero cross point and the clock;
A filter that receives the phase information, accumulates a predetermined number of the phase information, obtains an average value from the accumulated phase information, and sets the average phase information;
A data determination unit that receives the phase information, the average phase information, and the plurality of reception data, and selects one of the plurality of reception data based on the phase information and the average phase information;
A phase interpolation circuit that receives the clock and adjusts the phase of the clock according to the phase information or average phase information to form a recovered clock; and
A FIFO that stores received data selected by the data determiner from the plurality of received data in synchronization with the clock, and outputs the received data selected by the data determiner based on the restored clock; A clock recovery circuit comprising: