JP5309672B2 - Thin film element and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method for making a peripheral part of the bottom of a bottomed cylindrical pixel electrode (thin film) provided in a through-hole of an insulating film hard to be damaged in a thin film transistor panel formed by being transferred from a temporary substrate with high heat resistance to a film substrate with low heat resistance. <P>SOLUTION: A separation layer 52, a base insulating film 1, and a gate insulating film 4 are formed on the temporary substrate 51. A recessed part 12a is formed on the upper surface side of the separation layer 52 by forming through-holes 12 to the base insulating film 1 and the gate insulating film 4. The bottomed cylindrical pixel electrode 13 is formed in the through-hole 12 and a part of the recessed part 12a. A reinforcement film 41 consisting of silicon nitride, etc. is formed on the pixel electrode 13 and the gate insulating film 4, after a film substrate 42 is stuck on the reinforcement film 41 via an adhesive layer 43, the temporary substrate 51 and the separation layer 52 are removed. At this state, the bottom of the pixel electrode 13 is projected on the lower side of the base insulating film 1, however, the peripheral part of the bottom of the pixel electrode 13 hard to be damaged by the reinforcement film 41. <P>COPYRIGHT: (C)2010,JPO&amp;INPIT

Description

  The present invention relates to a thin film element and a method for manufacturing the same.

  Some conventional thin film elements use a substrate formed of a material that cannot withstand the temperature during the manufacturing process (see, for example, Patent Document 1). As a manufacturing method in this case, first, a separation layer is formed on a temporary substrate made of a material that can withstand the temperature during the manufacturing process. Next, a thin film element structure is formed on the separation layer. Next, a substrate made of a material that cannot withstand the temperature during the manufacturing process is bonded onto the thin film element structure via an adhesive layer. Next, the temporary substrate and the separation layer are removed.

JP 2004-140382 A

  By the way, Patent Document 1 describes what is applied to a thin film transistor panel of a liquid crystal display device (see FIGS. 23 to 27 of Patent Document 1). The pixel electrode portion in the completed state of the thin film transistor panel has a structure as shown in FIG. That is, an interlayer insulating film 101 made of silicon oxide is provided on the upper surface of the base insulating film 100 made of silicon oxide. A protective film 102 made of silicon oxide is provided on the upper surface of the interlayer insulating film 101.

  A through hole 103 is provided at a predetermined position of the protective film 102, the interlayer insulating film 101, and the base insulating film 100. A bottomed cylindrical pixel electrode (thin film) 104 is provided on the inner wall surface of the through hole 103, the lower portion of the through hole 103, and the upper surface of the protective film 102 around the through hole 103. A substrate 105 made of a material that cannot withstand the temperature during the manufacturing process is bonded to the upper surfaces of the pixel electrode 104 and the protective film 102 via an adhesive layer 106.

  Next, a manufacturing method of the pixel electrode 104 portion of the thin film transistor panel will be described. First, as shown in FIG. 22, a separation layer 108 made of amorphous silicon, a base insulating film 100 made of silicon oxide, and an interlayer made of silicon oxide are formed on the upper surface of a temporary substrate 107 made of a material that can withstand the temperature during the manufacturing process. An insulating film 101 and a protective film 102 made of silicon oxide are formed.

  Next, as shown in FIG. 23, through holes 103 are formed at predetermined locations in the protective film 102, the interlayer insulating film 101, and the base insulating film 100 by photolithography. Next, as shown in FIG. 24, a bottomed cylindrical pixel electrode 104 is patterned on the inner wall surface of the through hole 103, the lower portion of the through hole 103, and the upper surface of the protective film 102 around the through hole 103.

  Next, as illustrated in FIG. 25, the substrate 105 is bonded to the upper surfaces of the pixel electrode 104 and the protective film 102 through an adhesive layer 106. Next, as shown in FIG. 26, the temporary substrate 107 can be peeled from the separation layer 108 by irradiating an excimer laser beam from the lower side of the temporary substrate 107. Next, the temporary substrate 107 is peeled off from the separation layer 108. Next, the separation layer 108 is etched away. Thus, the one shown in FIG. 21 is obtained.

  By the way, as shown in FIG. 23, when the through hole 103 is formed in a predetermined portion of the protective film 102, the interlayer insulating film 101, and the base insulating film 100 by a photolithography method, an oxidation that is a material of the protective film 102 or the like. Since the etching selectivity is not so high between silicon and amorphous silicon, which is the material of the separation layer 108, actually, as shown in FIG. A recess 109 having a certain depth is formed on the upper surface side.

  As a result, as shown in FIG. 27B, in the completed state, the pixel electrode 104 formed in the lower portion of the through hole 103 slightly protrudes below the base insulating film 100. In this state, an adhesive layer 106 is filled in the bottomed cylindrical pixel electrode 104 formed in the through hole 103. However, the adhesive layer 106 may not be reliably filled up to the periphery of the inner bottom portion of the bottomed cylindrical pixel electrode 104. In such a case, the thickness of the pixel electrode 104 is extremely thin, for example, about 0.05 μm, and the area of the bottom of the pixel electrode 104 is relatively large, so that the bottom peripheral portion 104a of the pixel electrode 104 is mechanically There is a problem that it becomes weak and may be damaged.

  Accordingly, an object of the present invention is to provide a thin film element and a method for manufacturing the same which can prevent the bottom peripheral portion of the bottomed cylindrical thin film provided in the through hole from being easily damaged.

In order to achieve the above object, one aspect of the thin film element of the present invention includes an insulating film having a first through-hole and a bottomed cylindrical region provided so as to adhere to the inner wall surface of the first through-hole. A reinforcing film provided on the thin film and on the insulating film, and a substrate provided on the reinforcing film via an adhesive layer , the insulating film comprising a base insulating film and A gate insulating film provided on the base insulating film; and a gate electrode and a gate wiring connected to the gate electrode are provided on the base insulating film, and the gate insulating film is provided on the gate insulating film. A gate wiring relay wiring connected to one end of the gate wiring via a contact hole provided in the gate wiring, and a gate wiring external connection terminal connected to the gate wiring relay wiring. The connection terminal is the gate An inner wall surface of a third through hole provided in the edge film and the base insulating film, a lower portion of the third through hole, and an upper surface of the gate insulating film around the third through hole; The reinforcing film is provided on the wiring external connection terminal and the gate insulating film, and the gate wiring external connection terminal provided below the third through hole protrudes below the base insulating film. It is characterized by being .
In order to achieve the object, an aspect of the method for manufacturing a thin film element of the present invention includes a step of forming a separation layer on a temporary substrate, a step of forming an insulation film on the separation layer, Forming a first through hole and forming a first recess on the upper surface side of the separation layer in a portion corresponding to the first through hole; and attaching to the inner wall surface of the first through hole Forming a thin film so that the region corresponding to the through hole has a bottomed cylindrical shape, forming a reinforcing film on the thin film and the insulating film, and an adhesive layer on the reinforcing film A step of adhering a substrate through a step, and a step of removing the temporary substrate and the separation layer, wherein the step of forming the insulating film includes forming a base insulating film on the separation layer, A gate electrode and a gate wiring connected to the gate electrode are formed on the insulating film, and Including a step of forming a gate insulating film on the gate electrode, the gate wiring, and the base insulating film, and a step of forming a semiconductor thin film on the gate insulating film on the gate electrode, Forming a source electrode and a drain electrode, and forming the first through hole and the first recess includes forming a third through hole in the gate insulating film and the base insulating film. A third recess is formed on the upper surface side of the isolation layer in a portion corresponding to the third through hole, and a contact hole is formed in the gate insulating film in a portion corresponding to one end of the gate wiring. The step of forming the source electrode and the drain electrode is connected to one end of the gate wiring through the contact hole on the gate insulating film. Relay wiring for gate wiring, and the relay wiring for gate wiring on the upper surface of the gate insulating film around the inner wall surface of the third through hole, the third recess, and the third through hole Forming the reinforcing connection film on the source electrode, the drain electrode, the external connection terminal for the gate wiring, and the gate insulating film. The method further includes the step of forming the reinforcing film .

According to the present invention, it is possible to the bottom periphery of the bottomed cylindrical thin film provided in the through hole is so difficult to break.

(First embodiment)
FIG. 1 shows a cross-sectional view of a main part of a thin film transistor panel as a first embodiment of the present invention. In this case, from the left side to the right side of FIG. 1, a cross-sectional view of the drain wiring external connection terminal 21, a cross-sectional view of the thin film transistor 11 including the pixel electrode 13, and a cross-section of the gate wiring external connection terminal 31. The figure is shown.

  First, a portion of the thin film transistor 11 including the pixel electrode 13 will be described. A gate electrode 2 made of chromium or the like and a gate wiring 3 connected to the gate electrode 2 are provided at predetermined locations on the upper surface of the base insulating film 1 made of an inorganic material such as silicon nitride. A gate insulating film 4 made of an inorganic material such as silicon nitride is provided on the upper surface of the base insulating film 1 including the gate electrode 2 and the gate wiring 3.

  A semiconductor thin film 5 made of intrinsic amorphous silicon is provided at a predetermined position on the upper surface of the gate insulating film 4 on the gate electrode 2. A channel protective film 6 made of an inorganic material such as silicon nitride is provided at substantially the center of the upper surface of the semiconductor thin film 5. Ohmic contact layers 7 and 8 made of n-type amorphous silicon are provided on both sides of the upper surface of the channel protective film 6 and on the upper surface of the semiconductor thin film 5 on both sides thereof.

  A source electrode 9 made of chromium or the like is provided on the upper surface of one ohmic contact layer 7 and the upper surface of the gate insulating film 4 in the vicinity thereof. A drain electrode 10 made of chromium or the like is provided on the upper surface of the other ohmic contact layer 8. Here, the gate electrode 2, the gate insulating film 4, the semiconductor thin film 5, the channel protective film 6, the ohmic contact layers 7 and 8, the source electrode 9 and the drain electrode 10 constitute a thin film transistor 11.

  A first through hole 12 is provided at a predetermined location of the gate insulating film 4 and the base insulating film 1 in the vicinity of the thin film transistor 11. A bottomed cylindrical pixel electrode (thin film) 13 made of ITO is formed on the inner wall surface of the first through-hole 12, the lower portion of the first through-hole 12, and the upper surface of the gate insulating film 4 around the first through-hole 12. Is connected to the source electrode 9. In this case, the pixel electrode 13 provided below the first through-hole 12 slightly protrudes below the base insulating film 1, and the lower surface of the protruding portion is flat. A drain wiring 14 made of chromium or the like is connected to the drain electrode 10 at a predetermined location on the upper surface of the gate insulating film 4.

  Next, the drain wiring external connection terminal 21 will be described. The drain wiring external connection terminal 21 includes an inner wall surface of the second through hole 22 provided at a predetermined position of the gate insulating film 4 and the base insulating film 1, a lower portion of the second through hole 22, and a second through hole. 22 is provided on the upper surface of the gate insulating film 4 around the periphery. In this case, the drain wiring external connection terminal 21 provided in the lower portion of the second through hole 22 is slightly protruded to the lower side of the base insulating film 1, and the lower surface of the protruding portion is flat. The drain wiring external connection terminal 21 is connected to one end of the drain wiring 14.

  Next, the part of the external connection terminal 31 for gate wiring will be described. The external connection terminal 31 for gate wiring is a base on the inner wall surface of the third through hole 32 provided at a predetermined position of the base insulating film 1, the lower part of the third through hole 32, and the periphery of the third through hole 32. It is provided on the upper surface of the insulating film 1. In this case, the gate wiring external connection terminal 31 provided in the lower portion of the third through hole 32 slightly protrudes to the lower side of the base insulating film 1, and the lower surface of the protruding portion is flat. The gate wiring external connection terminal 31 is connected to one end of the gate wiring 3. A gate insulating film 4 is provided on the upper surface of the gate wiring external connection terminal 31 including the gate wiring 3.

  Next, the whole shown in FIG. 1 will be described. On the upper surfaces of the thin film transistor 11, the pixel electrode 13, the drain wiring 14, the drain wiring external connection terminal 21, and the gate insulating film 4, a reinforcing film 41 made of an inorganic material such as silicon nitride is provided. The lower surface of the film substrate 42 made of an organic resin such as a polyimide resin, which is a material that cannot withstand the temperature during the manufacturing process, is bonded to the upper surface of the reinforcing film 41 via an adhesive layer 43 made of an epoxy resin or the like. ing.

  Next, an example of a method for manufacturing this thin film transistor panel will be described. First, as shown in FIG. 2, a separation layer 52 made of amorphous silicon, silicon nitride, etc. are formed on the upper surface of a temporary substrate 51 made of a glass substrate, which is a material that can withstand the temperature during the manufacturing process, by plasma CVD. A base insulating film 1 made of an inorganic material is continuously formed.

  Next, as shown in FIG. 3, a third through hole 32 is formed at a predetermined location of the base insulating film 1 by photolithography. In this case, since the etching selectivity is not so high between, for example, silicon nitride, which is the material of the base insulating film 1, and amorphous silicon, which is the material of the separation layer 52, the separation layer in the portion corresponding to the third through hole 32 is obtained. A third recess 32 a having a certain depth is formed on the upper surface side of 52.

  Next, as shown in FIG. 4, a metal made of chromium or the like formed by sputtering at a predetermined location on the upper surface of the base insulating film 1 including the inside of the third through hole 32 and the inside of the third recess 32a. By patterning the film by photolithography, the gate electrode 2, the gate wiring 3 connected to the gate electrode 2, and the gate wiring external connection terminal 31 connected to one end of the gate wiring 3 are formed.

  Next, as shown in FIG. 5, gate insulation made of an inorganic material such as silicon nitride is formed on the upper surface of the base insulating film 1 including the gate electrode 2, the gate wiring 3, and the gate wiring external connection terminal 31 by plasma CVD. The film 4, the intrinsic amorphous silicon film 53, and the channel protective film forming film 54 made of an inorganic material such as silicon nitride are successively formed. Next, the channel protective film 6 is formed by patterning the channel protective film forming film 54 by photolithography.

  Next, as shown in FIG. 6, an n-type amorphous silicon film 55 is formed on the upper surface of the intrinsic amorphous silicon film 53 including the channel protective film 6 by plasma CVD. Next, when the n-type amorphous silicon film 55 and the intrinsic amorphous silicon film 53 are successively patterned by photolithography, ohmic contact layers 7 and 8 and the semiconductor thin film 5 are formed as shown in FIG.

  Next, as shown in FIG. 8, first and second through holes 12 and 22 are formed at predetermined locations in the gate insulating film 4 and the base insulating film 1 by photolithography. Also in this case, since the etching selectivity is not so great between the material of the gate insulating film 4 and the base insulating film 1, for example, silicon nitride and the amorphous silicon as the material of the separation layer 52, the first and second penetrations First and second recesses 12 a and 22 a having a certain depth are formed on the upper surface side of the separation layer 52 in portions corresponding to the holes 12 and 22.

  Next, as shown in FIG. 9, a film is formed by sputtering at predetermined locations on the upper surfaces of the ohmic contact layers 7 and 8 and the gate insulating film 4 including the inside of the second through hole 22 and the inside of the second recess 22a. The patterned metal film made of chromium or the like is patterned by photolithography, so that the source electrode 9, the drain electrode 10, the drain wiring 14 connected to the drain electrode 10, and the drain connected to one end of the drain wiring 14 Wiring external connection terminals 21 are formed.

  Next, as shown in FIG. 10, a film is formed by sputtering at predetermined locations on the upper surfaces of the ohmic contact layers 7 and 8 and the gate insulating film 4 including the inside of the second through hole 22 and the inside of the second recess 22a. The formed ITO film is patterned by photolithography to form the pixel electrode 13 connected to the source electrode 9.

  Next, as shown in FIG. 11, the upper surfaces of the thin film transistor 11, the pixel electrode 13, the drain wiring 14, the drain wiring external connection terminal 21 and the gate insulating film 4 are made of an inorganic material such as silicon nitride by plasma CVD. A reinforcing film 41 is formed. Next, as shown in FIG. 12, an adhesive layer 43 having a flat upper surface is formed on the upper surface of the reinforcing film 41 by using a transparent epoxy resin by spin coating or screen printing. Next, a film substrate 42 made of an organic resin such as a polyimide resin, which is a material that cannot withstand the temperature during the manufacturing process, is bonded. In this case, a transparent acrylic resin is formed on the reinforcing film 41 by using a spin coat method or a screen printing method, and an insulating layer having a flat upper surface is formed. An adhesive layer is formed on the insulating layer, and an adhesive layer is formed on the adhesive layer. The film substrate 42 may be adhered to the substrate.

  Next, as shown in FIG. 13, the temporary substrate 51 can be peeled from the separation layer 52 by irradiating an excimer laser beam from the lower side of the temporary substrate 51. In the case where the separation layer 52 is formed of amorphous silicon containing hydrogen, irradiation with an excimer laser beam releases hydrogen as a gas and promotes peeling. Next, the temporary substrate 51 is peeled off from the separation layer 52. Next, the separation layer 52 is removed by etching. Thus, the thin film transistor panel shown in FIG. 1 is obtained.

  By the way, as shown in FIG. 11, in order to form the reinforcing film 41 made of an inorganic material such as silicon nitride by the plasma CVD method, the bottomed bottom formed in the first through hole 12 and the first recess 12a is formed. The reinforcing film 41 can be reliably formed up to the periphery of the inner bottom part of the cylindrical pixel electrode 13. As a result, in the thin film transistor panel shown in FIG. 1, even if the thickness of the pixel electrode 13 is very thin, for example, about 0.05 μm, and the bottom area of the pixel electrode 13 is relatively large, It is possible to prevent the bottom peripheral portion 13a of the pixel electrode 13 protruding from being easily damaged.

  In the thin film transistor panel manufacturing method, as shown in FIG. 3, the step of forming the third through hole 32 and the first and second through holes 12, 22 are formed as shown in FIG. Since the steps are separate, the number of steps by the photolithography method increases. Then, next, an embodiment in which the number of steps by the photolithography method can be reduced will be described.

(Second Embodiment)
FIG. 14 shows a cross-sectional view of a main part of a thin film transistor panel as a second embodiment of the present invention. The thin film transistor panel is different from the thin film transistor panel shown in FIG. 1 in that the gate wiring external connection terminal 31 has a different structure. In other words, a gate wiring connection pad portion 3 a composed of one end of the gate wiring 3 is provided at a predetermined location on the upper surface of the base insulating film 1. A gate wiring relay line 33 is provided at a predetermined position on the upper surface of the gate insulating film 4 so as to be connected to the gate wiring connection pad portion 3 a via a contact hole 34 provided in the gate insulating film 4.

  The gate wiring external connection terminal 31 includes an inner wall surface of the third through hole 32 provided at a predetermined position of the gate insulating film 4 and the base insulating film 1, a lower portion of the third through hole 32, and a third through hole. 32 is provided on the upper surface of the gate insulating film 4 around the periphery. Also in this case, the gate wiring external connection terminal 31 provided below the third through-hole 32 slightly protrudes to the lower side of the base insulating film 1, and the lower surface of the protruding portion is flat. The external connection terminal 31 for gate wiring is connected to one end of the relay wiring 33 for gate wiring.

  Next, an example of a method for manufacturing this thin film transistor panel will be described. First, as shown in FIG. 15, a separation layer 52 made of amorphous silicon, silicon nitride, etc. are formed on the upper surface of a temporary substrate 51 made of a glass substrate, which is a material that can withstand the temperature during the manufacturing process, by plasma CVD. A base insulating film 1 made of an inorganic material is continuously formed.

  Next, a metal film made of chromium or the like formed by sputtering at a predetermined location on the upper surface of the base insulating film 1 is patterned by photolithography to be connected to the gate electrode 2 and the gate electrode 2 Gate wiring 3 is formed. In this case, one end of the gate wiring 3 is a gate wiring connection pad 3a.

  Next, as shown in FIG. 16, an inorganic material such as silicon nitride is formed on the upper surface of the base insulating film 1 including the gate electrode 2 and the gate wiring 3 (including the gate wiring connection pad portion 3a) by plasma CVD. A gate insulating film 4, an intrinsic amorphous silicon film 53 and a channel protective film forming film 54 made of an inorganic material such as silicon nitride are successively formed. Next, the channel protective film 6 is formed by patterning the channel protective film forming film 54 by photolithography.

  Next, as shown in FIG. 17, an n-type amorphous silicon film 55 is formed on the upper surface of the intrinsic amorphous silicon film 53 including the channel protective film 6 by plasma CVD. Next, when the n-type amorphous silicon film 55 and the intrinsic amorphous silicon film 53 are successively patterned by photolithography, ohmic contact layers 7 and 8 and the semiconductor thin film 5 are formed as shown in FIG.

  Next, as shown in FIG. 19, first, second, and third through holes 12, 22, and 32 are formed at predetermined locations of the gate insulating film 4 and the base insulating film 1 by photolithography, and Then, a contact hole 34 is formed in the gate insulating film 4 in a portion corresponding to the gate wiring connection pad portion 3a. Also in this case, since the etching selectivity is not so high between, for example, silicon nitride, which is the material of the gate insulating film 4 and the base insulating film 1, and amorphous silicon, which is the material of the separation layer 52, the first, second, second First, second, and third concave portions 12a, 22a, and 32a having a certain depth are formed on the upper surface side of the separation layer 52 in portions corresponding to the three through holes 12, 22, and 32.

  Next, as shown in FIG. 20, a metal film made of chromium or the like formed by sputtering is patterned by photolithography, so that the ohmic structure including the inside of the second through hole 22 and the inside of the second recess 22a is obtained. A source electrode 9, a drain electrode 10, a drain wiring 14 connected to the drain electrode 10, and a drain connected to one end of the drain wiring 14 at predetermined locations on the upper surfaces of the contact layers 7 and 8 and the gate insulating film 4. Forming the wiring external connection terminal 21 and forming the gate wiring external connection terminal 31 at a predetermined position on the upper surface of the gate insulating film 4 including the inside of the third through hole 32 and the inside of the third recess 322a; Further, the gate wiring intermediate layer is formed at a predetermined position on the upper surface of the gate insulating film 4 including the gate wiring connection pad portion 3 a exposed through the contact hole 34. The wiring 33 is connected to the external connection terminal 31 for the gate wiring is formed.

  Thereafter, through the same steps as in the first embodiment, the thin film transistor panel shown in FIG. 14 is obtained. As described above, in this thin film transistor panel manufacturing method, as shown in FIG. 19, the first, second and third through holes 12, 22, 32 and the contact hole 34 are formed in the same process. Compared with the case of the first embodiment, the number of steps by the photolithography method can be reduced only once.

(Other embodiments)
In each of the above embodiments, the case where the separation layer 52 is formed of amorphous silicon has been described. However, the present invention is not limited to this. For example, the separation layer 52 may be formed of zinc oxide. In this case, for example, when immersed in an etching solution (for example, 0.5 w% acetic acid aqueous solution) after the step shown in FIG. 12, the separation layer 52 made of zinc oxide is dissolved and removed, and the temporary substrate 51 is naturally peeled off. Removed.

Sectional drawing of the principal part of the thin-film transistor panel as 1st Embodiment of this invention. Sectional drawing of an original process in the case of manufacture of the thin-film transistor panel shown in FIG. Sectional drawing of the process following FIG. Sectional drawing of the process following FIG. Sectional drawing of the process following FIG. Sectional drawing of the process following FIG. Sectional drawing of the process following FIG. Sectional drawing of the process following FIG. FIG. 9 is a cross-sectional view of the process following FIG. 8. Sectional drawing of the process following FIG. Sectional drawing of the process following FIG. Sectional drawing of the process following FIG. Sectional drawing of the process following FIG. Sectional drawing of the principal part of the thin-film transistor panel as 2nd Embodiment of this invention. FIG. 15 is a cross-sectional view of an initial process in manufacturing the thin film transistor panel shown in FIG. 14. FIG. 16 is a cross-sectional view of the process following FIG. 15. FIG. 17 is a cross-sectional view of the process following FIG. 16. FIG. 18 is a cross-sectional view of the process following FIG. 17. FIG. 19 is a cross-sectional view of the process following FIG. 18. FIG. 20 is a cross-sectional view of the process following FIG. 19. Sectional drawing of the part of the pixel electrode of the conventional thin-film transistor panel. FIG. 22 is a cross-sectional view of an initial process in manufacturing the thin film transistor panel shown in FIG. 21. FIG. 23 is a sectional view of a step following FIG. 22; FIG. 24 is a sectional view of a step following FIG. 23. FIG. 25 is a sectional view of a step following FIG. 24. FIG. 26 is a sectional view of a step following FIG. 25. (A), (B) is sectional drawing shown in order to demonstrate the problem of the pixel electrode part of the conventional thin-film transistor panel.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Base insulating film 2 Gate electrode 3 Gate wiring 3a Color change layer 4 Gate insulating film 5 Semiconductor thin film 6 Channel protective film 7, 8 Ohmic contact layer 9 Source electrode 10 Drain electrode 11 Thin-film transistor 12 1st through-hole 12a 1st recessed part 13 Pixel electrode 14 Drain wiring 21 Drain wiring external connection terminal 22 Second through hole 22a First recess 31 Gate wiring external connection terminal 32 Third through hole 32a First recess 41 Reinforcing film 42 Film substrate 43 Adhesive layer 51 Temporary substrate 52 Separation layer 53 Intrinsic amorphous silicon film 54 Channel protective film formation film 55 N-type amorphous silicon film

Claims (16)

An insulating film having a first through hole;
A thin film having a bottomed cylindrical region provided to adhere to the inner wall surface of the first through hole;
A reinforcing film provided on the thin film and the insulating film;
A substrate provided on the reinforcing film via an adhesive layer ;
Equipped with a,
The insulating film has a base insulating film and a gate insulating film provided on the base insulating film,
A gate electrode and a gate wiring connected to the gate electrode are provided on the base insulating film,
A gate wiring relay line connected to one end of the gate wiring through a contact hole provided in the gate insulating film on the gate insulating film, and a gate wiring external connected to the gate wiring relay wiring A connection terminal is provided,
The external connection terminal for gate wiring includes the inner wall surface of a third through hole provided in the gate insulating film and the base insulating film, the lower portion of the third through hole, and the periphery of the third through hole. Provided on the upper surface of the gate insulating film,
The reinforcing film is provided on the gate wiring external connection terminal and the gate insulating film,
The external connection terminal for gate wiring provided in the lower part of the third through hole protrudes below the base insulating film.
A thin film element characterized by the above. A semiconductor thin film is provided on the gate insulating film on the gate electrode;
A source electrode and a drain electrode are provided on the semiconductor thin film,
The first through hole is provided in the gate insulating film and the base insulating film;
A pixel electrode as the thin film is provided on the inner wall surface of the first through hole, the lower portion of the first through hole, and the upper surface of the gate insulating film around the first through hole, connected to the source electrode. And
The reinforcing film is provided on the pixel electrode, the source electrode, the drain electrode, and the gate insulating film,
The thin film element according to claim 1. A drain wiring connected to the drain electrode and a drain wiring external connection terminal connected at one end of the drain wiring are provided on the gate insulating film,
The drain wiring external connection terminal includes the gate in the inner wall surface of the second through hole provided in the gate insulating film and the base insulating film, the lower part of the second through hole, and the periphery of the second through hole. Provided on the top surface of the insulating film,
The reinforcing film is provided on the drain wiring external connection terminal and the gate insulating film,
The drain wiring external connection terminal provided in the lower portion of the second through hole protrudes below the base insulating film.
The thin film element according to claim 2. The pixel electrode provided under the first through hole protrudes below the base insulating film;
The thin film element according to claim 2. The lower surface of the protruding portion of the pixel electrode provided in the lower portion of the first through hole is flat.
The thin film element according to claim 4. The reinforcing membrane comprises an inorganic material;
The thin film device according to claim 1, wherein the thin film device is a thin film device. The substrate is a film substrate;
The thin film device according to claim 1, wherein the thin film device is a thin film device. Forming a separation layer on the temporary substrate;
Forming an insulating film on the separation layer;
Forming a first through hole in the insulating film and forming a first recess on the upper surface side of the separation layer in a portion corresponding to the first through hole ;
Forming a thin film such that a region corresponding to the through hole is attached to the inner wall surface of the first through hole to have a bottomed cylindrical shape;
A step that form a reinforcing film on the thin film and on said insulating film,
Adhering a substrate on the reinforcing film via an adhesive layer;
Removing the temporary substrate 及 beauty the separation layer,
I have a,
The step of forming the insulating film includes forming a base insulating film on the isolation layer, forming a gate electrode and a gate wiring connected to the gate electrode on the base insulating film, and forming the gate electrode on the gate electrode. Including a step of forming a gate insulating film on the wiring and the base insulating film,
Forming a semiconductor thin film on the gate insulating film on the gate electrode;
Forming a source electrode and a drain electrode on the semiconductor thin film;
The step of forming the first through hole and the first recess includes forming a third through hole in the gate insulating film and the base insulating film, and in a portion corresponding to the third through hole. Forming a third recess on the upper surface side of the isolation layer, and further forming a contact hole in the gate insulating film in a portion corresponding to one end of the gate wiring;
The step of forming the source electrode and the drain electrode includes forming a gate wiring relay wiring connected to one end of the gate wiring through the contact hole on the gate insulating film, and the third wiring Forming a gate wiring external connection terminal connected to the gate wiring relay wiring on the upper surface of the gate insulating film around the inner wall surface of the through hole, the third recess, and the third through hole; ,
The step of forming the reinforcing film includes the step of forming the reinforcing film on the source electrode, the drain electrode, the external connection terminal for gate wiring, and the gate insulating film.
A method for manufacturing a thin film element. The step of forming the first through hole and the first recess includes forming the first through hole in the gate insulating film and the base insulating film and corresponding to the first through hole. Forming the first recess on the upper surface side of the separation layer in
The step of forming the thin film includes the step of forming the pixel electrode as the thin film on the upper surface of the gate insulating film in the inner wall surface of the first through hole, in the first recess, and around the first through hole. It is a process of forming by connecting to an electrode,
The step of forming the reinforcing film includes the step of forming the reinforcing film on the pixel electrode and the gate insulating film.
The method for producing a thin film element according to claim 8. The step of forming the first through hole and the first recess includes forming a second through hole in the gate insulating film and the base insulating film, and in a portion corresponding to the second through hole. Forming a second recess on the upper surface side of the separation layer,
In the step of forming the source electrode and the drain electrode, a drain wiring connected to the drain electrode is formed on the gate insulating film, and an inner wall surface of the second through hole, in the second recess And forming a drain wiring external connection terminal connected to one end of the drain wiring on the upper surface of the gate insulating film around the second through hole,
The step of forming the reinforcing film includes the step of forming the reinforcing film on the drain wiring external connection terminal and the gate insulating film.
The method for producing a thin film element according to claim 9. The reinforcing film is formed of an inorganic material.
The method for manufacturing a thin film element according to any one of claims 8 to 10. The reinforcing film is formed by a plasma CVD method.
The method for manufacturing a thin film element according to any one of claims 8 to 11. The separation layer is formed of amorphous silicon;
The step of removing the temporary substrate and the separation layer includes:
Irradiating a laser beam from the lower side of the temporary substrate to make the temporary substrate peelable from the separation layer;
Peeling and removing the temporary substrate from the separation layer;
Etching away the separation layer;
including,
The method for manufacturing a thin film element according to any one of claims 8 to 12. The separation layer is formed of zinc oxide;
The step of removing the temporary substrate and the separation layer is a step of removing the temporary substrate naturally by etching and removing the separation layer.
The method for manufacturing a thin film element according to any one of claims 8 to 12. The temporary substrate is a glass substrate;
The method for producing a thin film element according to claim 8, wherein the thin film element is produced. The substrate is a film substrate;
The method for manufacturing a thin film element according to any one of claims 8 to 15.

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