JP5280739B2 - Image display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To allow uniform display even when a relation between the gate voltage and the drain current of a thin film transistor shows hysteresis characteristics. <P>SOLUTION: In the first half of a set period, reset switch element of all pixels are turned on to cause control electrodes of driving transistor of all pixels to converge to a prescribed voltage, and a step signal in a first voltage level is supplied from a step signal generation circuit to each signal line. In the latter half of the set period, reset switch elements of all pixels are turned off, and a step signal in a second voltage level different from the first signal level is supplied from the step signal generation circuit to each signal line, and a voltage exceeding a second supply voltage or a voltage exceeding a voltage range supplied from a signal driving part is input to control electrodes of driving transistors of all pixels as a voltage for characteristic value setting. <P>COPYRIGHT: (C)2010,JPO&amp;INPIT

Description

  The present invention relates to an image display device using an organic EL element and the like, and more particularly to an image display device capable of high-quality display at a low voltage and high definition.

In recent years, demand for flat display devices has increased in place of CRTs that have been the mainstream of conventional display devices. In particular, display devices using organic EL (Electro Luminescence) elements (OLEDs) are excellent in terms of power consumption, lightness, thinness, video characteristics, viewing angle, etc., and are developed and put into practical use. Is also progressing.
In an image display device using an organic EL element, there are a voltage program method and a current program method for writing image signals to pixels. A technique using a voltage program method with a high writing speed is described in, for example, Patent Document 1 and Non-Patent Document 1 below.
In the image display devices described in Patent Document 1 and Non-Patent Document 1, the technology described in Patent Document 2 below is available as a technology that can reduce the number of elements and the number of wirings and achieve high definition. Are known.
In Patent Document 2, the switch between the signal line and the recording capacity is eliminated, and one frame period is divided into a writing period and a light emission period. When writing a signal to each pixel, the gate voltage and the drain electrode of a thin film transistor (hereinafter referred to as a driving TFT) that sends current to the organic EL element are short-circuited so that the gate voltage is uniformly converged. The difference voltage between the signal voltages applied to the lines is held in the storage capacity. In the light emission period, all pixels are caused to emit light simultaneously by inputting a triangular wave voltage to all signal lines.

In Patent Document 2, when the power supply voltage is lowered by reducing the power, the current flowing through the drive TFT in the reset operation becomes small, so the convergence time becomes long and the gate voltages of the drive TFTs of all the pixels are not uniform. There is a problem. Because of this problem, since the gate voltage of the driving TFT at the time of signal writing is not determined, the gate voltage-drain current characteristic of the driving TFT is not determined, and an afterimage occurs.
As a technique for solving the problem of insufficient writing, a technique described in Non-Patent Document 2 below is known.
The difference between Non-Patent Document 2 and Patent Document 2 is that a system for precharging the initial voltage from the outside of the pixel to the gate electrode of the driving TFT at the time of signal writing is provided. By precharging the initial voltage at the time of signal writing, the gate voltages of the driving TFTs can be made constant and all the driving TFTs can be used with the same characteristics. As a result, the afterimage is eliminated.

As prior art documents related to the invention of the present application, there are the following.
JP 2003-5709 A JP 2003-122301 A Digest of Technical Papers, SID98 pp11-14 Digest of Technical Papers, SID07 pp1382-1385

In the image display devices described in Patent Documents 1 and 2 or Non-Patent Documents 1 and 2, smear may occur due to low power and high definition. This problem will be described with reference to FIGS.
In a thin film transistor (hereinafter referred to as TFT), the gate voltage-drain current relationship may exhibit hysteresis characteristics.
This hysteresis characteristic will be described with reference to FIG.
The relationship between the gate voltage (Vg) and the drain current (Id) of the TFT varies depending on the number of carriers (CAP) trapped in the gate insulating film (GI).
In the state A where the number of carriers (CAP) trapped in the gate insulating film (GI) is large as shown in FIG. 13A, the relationship between the TFT gate voltage (Vg) -drain current (Id) is as shown in FIG. According to characteristic A of c).
On the other hand, in the state B where the number of carriers (CAP) trapped in the gate insulating film (GI) is small as shown in FIG. 13B, the relationship between the gate voltage (Vg) -drain current (Id) of the TFT is shown in FIG. According to characteristic B of 13 (c).
Further, when the number of trapped carriers (CAP) decreases due to the emission of trapped carriers (CAP), the relationship between the gate voltage (Vg) and the drain current (Id) transitions from the characteristic A to the characteristic B. . Therefore, when the number of trapped carriers (CAP) decreases, the operation may be performed according to the region C between the characteristics A and B.
Note that FIG. 13 shows the characteristics of the p-type TFT, and the gate voltage (Vg) on the horizontal axis is negative with respect to the source voltage. G is a gate electrode.

A signal input to the gate electrode of the p-type TFT having a hysteresis characteristic in the relationship of gate voltage (Vg) -drain current (Id) changes from a voltage of Vg1 to a voltage of Vg0 as shown in FIG. The number of carriers (CAP) trapped in the gate insulating film (GI) increases as the time (ton) for applying the voltage Vg1 is longer and the potential difference (ΔVg) between the voltage Vg1 and Vg0 is larger. The relationship between the gate voltage (Vg) and the drain current (Id) maintains a characteristic close to the characteristic A as shown in FIG.
On the other hand, as the signal input to the gate electrode changes from the voltage Vg2 to the voltage Vg0 as shown in FIG. 14C, the shorter the time (ton) for applying the voltage Vg2, the shorter Vg2 is. The smaller the potential difference (ΔVg) between the voltage Vg0 and the voltage Vg0, the faster the relationship between the gate voltage (Vg) and the drain current (Id) approaches the characteristic B as shown in FIG. In FIG. 14, Id0 is a drain current when the gate voltage is Vg0.
In the above-mentioned Patent Document 2, since the convergence voltage of the gate electrode of the driving TFT at the reset operation is sufficiently lower than the power supply voltage with respect to the power supply voltage (that is, the gate-source voltage (Vgs) is sufficiently large). Therefore, all the driving TFTs operate with characteristics close to the characteristic A, such as the characteristic C1 shown in FIG.
Further, in the above-mentioned Non-Patent Document 2, by reducing the initial voltage precharged to the gate electrode of the driving TFT at the time of writing, the power supply voltage is maintained while maintaining the characteristics of the driving TFT at the characteristic C1 shown in FIG. Or the precharge time can be shortened.

However, in the above-mentioned Non-Patent Document 2, when the power supply voltage is further lowered, or when the precharge time is shortened due to high definition, the characteristics of the driving TFT approach the characteristics B shown in FIG. In some cases, the driving TFT operates in a transition region between the characteristic A and the characteristic B such as the characteristic C2.
At this time, for example, when black is displayed only in the central portion of the screen and white is displayed in other portions, the driving TFT for writing image signals to the pixels a to f in FIG. The relationship between the gate voltage (Vg) and the drain current (Id) varies depending on the pixel as shown in FIGS.
In the pixel b on the signal line 12A and the pixel e on the signal line 12B, due to the difference in the time during which the driving TFT is turned on in the light emission period (the light emission time of the pixel b is longer than the light emission time of the pixel e). The number of carriers trapped in the gate insulating film (GI) is different, and the driving TFT exhibits different characteristics.
Further, in the pixel f on the signal line 12B, the signal line voltage decreases when writing the black region, and accordingly, the gate voltage (Vg) of the driving TFT of the pixel f also decreases. Therefore, in the pixel f, the number of carriers trapped in the gate insulating film (GI) is different from that of the pixel c on the signal line 12A in spite of the same time during which the driving TFT is turned on during the light emission period. The driving TFTs have different characteristics. Therefore, smear occurs due to the difference in characteristics of the driving TFT.
The present invention has been made to solve the problems of the prior art, and an object of the present invention is to enable uniform display even when the gate voltage-drain current relationship of the thin film transistor exhibits hysteresis characteristics. An image display apparatus is provided.
The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

Of the inventions disclosed in this application, the outline of typical ones will be briefly described as follows.
In the present invention, before applying a signal voltage to the pixels, a sufficient forward bias voltage is applied to the gate voltage of the driving TFT, so that the driving TFTs of all the pixels have the characteristic C1 shown in FIG. And driven with characteristics close to the characteristics A.
The specific configuration is as follows.
(1) A plurality of pixels each having a self-luminous element, a plurality of signal lines for inputting an image signal to each pixel, a drive circuit for supplying the image signal to each signal line, and a step for each signal line Each of the pixels includes a driving transistor that drives the self-luminous element based on the image signal, a corresponding signal line of the plurality of signal lines, and a driving transistor. A capacitive element connected between the control electrode and a reset switch element connected between the control electrode and the second electrode of the drive transistor, wherein the first electrode of the drive transistor is a first power source; The other end of the self-luminous element is connected to a second power supply voltage. The image display device is connected to a second power supply voltage. A write period for writing image signals, and during the first half of the set period, the reset switch elements of all the pixels are turned on, and the control electrodes of the drive transistors of all the pixels are converged to a predetermined voltage. And supplying a step signal of a first voltage level from the step signal generation circuit to each signal line, turning off the reset switch elements of all the pixels in the latter half of the setting period, and the step A step signal having a second voltage level different from the first signal level is supplied from the signal generation circuit to each of the signal lines, and a characteristic value setting voltage is supplied to the control electrodes of the driving transistors of all the pixels as the second voltage level. A voltage exceeding the power supply voltage or a voltage exceeding the voltage range supplied from the signal driver is input.

(2) A plurality of pixels each having a self-luminous element, a plurality of signal lines for inputting an image signal to each pixel, a plurality of reference lines for inputting a reference voltage to each pixel, and the signal lines A drive circuit that supplies an image signal; and a step signal generation circuit that supplies a step signal to each of the signal lines. Each of the pixels includes a drive transistor that drives the self-luminous element based on the image signal; A capacitive element connected between a corresponding signal line of the plurality of signal lines and the control electrode of the driving transistor, a corresponding reference voltage line of the plurality of reference voltage lines, and a control electrode of the driving transistor, A first switch electrode connected to a first power supply voltage, and the other end of the self-luminous element. An image display device connected to the second power supply voltage, and having a set period and a write period for writing the image signal to each pixel in succession to the set period within one frame period, In the first half of the set period, the reference switch elements of all the pixels are turned on, a predetermined voltage is input to the control electrodes of the drive transistors of all the pixels, and each signal line from the step signal generation circuit Is supplied with a step signal of a first voltage level, and the reference switch elements of all the pixels are turned off during the latter half of the set period, and the first signal is supplied from the step signal generation circuit to each signal line. A step signal of a second voltage level different from the level is supplied, and the second power supply voltage is applied as a characteristic value setting voltage to the control electrodes of the drive transistors of all the pixels. Voltage obtain or inputs a voltage exceeding the voltage range supplied from the signal driver.

(3) In (1) or (2), the step signal generation circuit includes the voltage level of either the first voltage level or the second voltage level of the step signal, and the first voltage of the step signal. The level and the step width of the second voltage level can be changed.
(4) In (1) or (2), the drive transistor is a p-type field effect transistor, the cathode electrode of the self-luminous element is connected to the second power supply voltage, and the step signal is The first voltage level is High level, the second voltage level is Low level, and the characteristic value setting voltage input to the control electrodes of the drive transistors of all the pixels is lower than the second power supply voltage. The voltage or a voltage having a lower potential than the lowest potential voltage in the voltage range supplied from the signal driver.
(5) In (1) or (2), the drive transistor is an n-type field effect transistor, an anode electrode of the self-luminous element is connected to the second power supply voltage, and the step signal is The first voltage level is the Low level, the second voltage level is the High level, and the characteristic value setting voltage input to the control electrodes of the drive transistors of all the pixels is higher than the second power supply voltage. The voltage or a voltage having a higher potential than the highest voltage in the voltage range supplied from the signal driver.

(6) A plurality of pixels each having a self-luminous element, a plurality of signal lines for inputting an image signal to each pixel, and a drive circuit for supplying the image signal to each signal line, A drive transistor that drives the self-luminous element based on the image signal, and a capacitive element connected between a corresponding signal line of the plurality of signal lines and a control electrode of the drive transistor, The drive transistor is a p-type field effect transistor, the first electrode of the drive transistor is connected to a first power supply voltage, and the cathode electrode of the self-luminous element is connected to a second power supply voltage. The device includes a set period and a write period in which the image signal is written to each pixel in succession to the set period within one frame period, and includes a power supply circuit and a plurality of voltage input lines. And before Each pixel has a reference switch element connected between a corresponding voltage input line of the plurality of voltage input lines and one end of the self-luminous element, and the reference of all the pixels is set during the setting period. By turning on the switch element and supplying a voltage having a lower potential than the second power supply voltage from the power supply circuit to the voltage input lines, a characteristic value setting voltage is applied to the control electrodes of the drive transistors of all the pixels. A voltage having a lower potential than the second power supply voltage is input.

(7) A plurality of pixels each having a self-luminous element, a plurality of signal lines for inputting an image signal to each pixel, and a drive circuit for supplying the image signal to each signal line, A drive transistor that drives the self-luminous element based on the image signal, and a capacitive element connected between a corresponding signal line of the plurality of signal lines and a control electrode of the drive transistor, The drive transistor is an n-type field effect transistor, the first electrode of the drive transistor is connected to a first power supply voltage, and the anode electrode of the self-luminous element is connected to a second power supply voltage. The device includes a set period and a write period in which the image signal is written to each pixel in succession to the set period within one frame period, and includes a power supply circuit and a plurality of voltage input lines. And before Each pixel has a reference switch element connected between a corresponding voltage input line of the plurality of voltage input lines and one end of the self-luminous element, and the reference of all the pixels is set during the setting period. By turning on the switch element and supplying a voltage having a higher potential than the second power supply voltage from the power supply circuit to the voltage input lines, a characteristic value setting voltage is applied to the control electrodes of the drive transistors of all the pixels. A voltage having a higher potential than the second power supply voltage is input.
(8) In (6) or (7), the signal line also serves as the voltage input line, and the reference switch element of each pixel is connected to the corresponding signal line in the plurality of signal lines. It is connected between one end of the light emitting element.

The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.
According to the image display device of the present invention, uniform display without display abnormality due to the hysteresis characteristic of the thin film transistor is possible.

Hereinafter, embodiments applied to the organic EL display device of the present invention will be described in detail with reference to the drawings.
In all the drawings for explaining the embodiments, parts having the same functions are given the same reference numerals, and repeated explanation thereof is omitted.
[Example 1]
FIG. 1 is a diagram showing an overall configuration of an organic EL display device according to Embodiment 1 of the present invention. As shown in FIG. 1, a plurality of pixels 1 are provided in a matrix in the display area of the organic EL display panel.
A signal line 12, a reset line 7, a lighting switch line 21, and a power supply line 6 are input to the pixel 1, respectively.
The reset line 7 is connected to the gate driver 8. The lighting switch line 21 is connected to the OR circuit 42. A scanning output line 40 and a lighting control line 41 output from the gate drive unit 8 are input to the OR circuit 42.
Since the configuration of the gate driver 8 is a generally well-known shift register circuit, a detailed description thereof is omitted here.
The signal line 12 is connected to the signal driver 9 via a signal line selection switch element 11 formed of a thin film transistor. An image signal is supplied to the signal driver 9 from the outside via a signal input line 10.
Between the signal driving unit 9 and the organic EL display panel, there are a step signal input line 15, a triangular wave input line 16, a step signal selection switch control line 17, a triangular wave selection switch control line 18, and a signal line selection switch control line 19. It is extended.
These outputs are applied to the signal line 12 extending from the signal driver 9 with a time difference by a signal line selection switch element 11, a triangular wave selection switch element 13, and a step signal selection switch element 14 formed of thin film transistors.

In practice, a large number of pixels 1 are arranged in the display area of the organic EL display panel. However, in order to simplify the drawing, only four pixels are shown in FIG. As will be described later, other common ground lines are also wired to the pixel 1, but these descriptions are omitted.
Each pixel 1 is provided with an organic electroluminescence element (hereinafter referred to as an organic EL element) 2 as a light emitting element, and the cathode electrode of the organic EL element 1 is connected to a common ground line.
The anode electrode is connected to the power supply line 6 through a lighting control switch element 20 composed of an n-type thin film transistor and a p-type thin film transistor (hereinafter referred to as a drive TFT) 4.
The gate electrode of the drive TFT 4 is connected to the signal line 12 via the storage capacitor 3, and a reset switch element 5 formed of a thin film transistor is provided between the drain electrode and the gate electrode of the drive TFT 4.
Note that the gate electrode of the reset switch element 5 is connected to the reset line 7. The gate electrode of the lighting control switch element 20 is connected to the lighting switch line 21.
Each circuit such as the pixel 1, the gate driving unit 8, and the signal driving unit 9 is configured by using a low-temperature polycrystalline silicon thin film transistor having a generally known low-temperature polycrystalline silicon layer as a semiconductor layer. Is formed on a glass substrate.
In addition, the manufacturing method of the low-temperature polycrystalline silicon thin film transistor or the organic EL element 1 is not greatly different from that generally reported, and the description thereof is omitted here.

FIG. 2 is a diagram illustrating a timing chart of the organic EL display device according to the present embodiment.
As shown in the lower side of FIG. 2, in this embodiment, there is a writing period, a light emitting period, and a setting period in one frame period, and an image signal is written to each pixel 1 in the writing period. During the light emission period, all pixels are turned on for display. The image viewing signal is written for each display line, that is, for each reset line 7.
Hereinafter, the operation in each period will be described.
[Writing period]
In the “writing period”, the signal line selection switch element 11 is turned on by the signal line selection switch control line 19. Further, the gate driving unit 8 sequentially scans the plurality of pixels 1 in each row for each display line, and in synchronization therewith, an analog image signal is sent from the signal driving unit 9 via the signal line selection switch element 11 to the signal line. 12 is written.
Hereinafter, an operation in the “writing period” of the pixel 1 of an arbitrary display line selected by the gate driving unit 8 will be described.
During the writing period, a signal voltage is applied to one end of the storage capacitor 3 of the pixel 1 selected for writing through the signal line 12 from time T1 to time T4.
Next, at time T2, the reset switch element 5 and the lighting control switch element 20 are turned on, whereby the driving TFT 4 becomes a diode connection in which the gate electrode and the drain electrode are connected.

Next, when the lighting control switch element 20 is turned off at time T3, the drive TFT 4 and the organic EL element 2 are forcibly turned off. At this time, the gate electrode and the drain electrode of the drive TFT 4 are the reset switch elements. 5, the voltage of the gate electrode of the driving TFT 4, which is also one end of the storage capacitor 3, is a voltage (Vdd−Vth) lower than the voltage (Vdd) of the power supply line 6 by the threshold voltage (Vth). It is automatically reset.
At this time, an analog image signal of Vs is input from the signal line 12 to the other end of the storage capacitor 3.
Next, when the reset switch element 5 is turned off at time T4, the potential difference between both ends of the storage capacitor 3 is stored in the storage capacitor 3 as it is. That is, when a voltage equal to the analog image signal of Vs written in the “writing period” is input to the signal line side of the storage capacitor 3, the voltage V (g) of the gate electrode of the drive TFT 4 is The voltage is forcibly set to a voltage (Vdd−Vth) lower than the voltage of the line 6 by a threshold voltage (Vth).
At this time, if the voltage value input to the signal line side of the storage capacitor 3 is higher than the analog image signal of Vs, the driving TFT 4 is in an OFF state, and the voltage value input to the signal line side of the storage capacitor 3 is Vs. If it is lower than the analog image signal, the driving TFT 4 is turned on. However, since the lighting control switch element 20 of the pixel is always in an off state during the period of scanning the pixels in another row, the organic EL element 1 is lit regardless of the level of the analog image signal of the signal line 12. Never do.
The writing of the analog image signal to the pixel 1 is sequentially performed for each row in this way, and the “writing period” of one frame ends when the writing to all the pixels is completed.

[Flash duration]
In the “light emission period”, the gate drive unit 8 stops and the lighting control line 41 becomes High (hereinafter, “H level”), so that the gate of the lighting control switch element 20 is connected via the OR circuit 42 and the lighting switch line 21. Since the H level voltage is input to the electrodes, the lighting control switch elements 20 of all the pixels are turned on simultaneously.
At this time, the triangular wave selection switch element 13 is turned on by the triangular wave selection switch control line 18, and the triangular wave voltage shown in FIG. 2 is input to the signal line 12 from the triangular wave input line 16.
Here, in the “light emission period”, since the lighting control switch element 20 is always on, the organic EL element 2 of each pixel 1 is applied to the Vs analog image signal and the signal line 12 written in advance. It is driven by the driving TFT 4 according to the voltage relationship with the triangular wave voltage.
At this time, if the mutual conductance (gm) of the driving TFT 4 is sufficiently large, it can be considered that the organic EL element 1 is digitally driven to turn on / off. That is, the organic EL element 1 is continuously lit at a substantially constant luminance only during a period (for example, the period of Ts in FIG. 25) that depends on the analog image signal value of Vs written in advance. Visually, it is recognized as multi-tone light emission.

For example, even if the characteristics of the driving TFT 4 vary, there is basically no influence on this. Here, it is desirable that the amplitude of the triangular wave voltage shown in FIG. 2 substantially matches the signal amplitude of the analog image signal.
In this embodiment, the right and left target triangular wave voltage is set so that the time axis center of light emission does not depend on the light emission gradation, but instead of this triangular wave voltage, an asymmetric triangular wave voltage or non-corresponding to gamma characteristic modulation is used. It is also possible to use a linear triangular wave voltage or a plurality of triangular wave voltages, thereby obtaining different visual characteristics.
In addition, according to the present embodiment, the gradation display can be obtained by controlling the light emission period of the organic EL element 1 with no temporal variation by the value of the analog image signal written in the storage capacitor 3 of each pixel. The display characteristic variation between pixels can be sufficiently reduced.
In addition, each thin film transistor uses a single-channel thin film transistor with a simple configuration in this embodiment, but these thin film transistors may have a CMOS configuration, for example.
The peripheral drive circuit including the gate drive unit 8 and the signal drive unit 9 is composed of a low-temperature polycrystalline silicon (polysilicon) thin film transistor circuit. The peripheral drive circuit or a part thereof is a single crystal LSI (Large LSI). (Scale Integrated circuit) may be configured and mounted. In that case, the drive TFT 4, the reset switch element 5, the lighting control switch element 20, and the like may be configured on a glass substrate using amorphous silicon thin film transistors that use amorphous silicon as a semiconductor layer.

[Setting period]
This embodiment is characterized in that, before the writing period, the characteristic values of the driving TFTs 4 of all the pixels are aligned with the characteristic C1 shown in FIG.
In the “set period” of one frame, the gate driver 8 stops. At time T5, since the lighting control line 41 becomes H level, an H level voltage is input to the gate electrode of the lighting control switch element 20 via the OR circuit 42 and the lighting switch line 21, so that all pixels The lighting control switch elements 20 are simultaneously turned on. At the same time, the reset switch elements 5 of all the pixels are turned on by the reset line 7. As a result, the gate voltage (Vg) of the driving TFT 4 converges to Vm.
At this time, the step signal selection switch control line 17 turns on the step signal selection switch element 14, and the voltage Vsteph is applied to the signal line 12 from the step signal generator 29 via the step signal input line 15. . For example, the voltage of Vsteph is the highest potential voltage among the voltages that can be applied from the signal driver 9 or the voltage of the power supply line 6.
Thereafter, the reset switch elements 5 and the lighting control switch elements 20 of all the pixels are turned off, and the difference voltage between Vm and Vsteph is stored in the storage capacitors 3 of all the pixels.
Next, at time T <b> 6, a voltage of Vstepl is applied to the signal line 12 from the step signal generator 29 via the step signal input line 15. For example, the voltage of Vstepl is the lowest potential voltage among the voltages that can be applied from the signal driver 9, or the voltage of the common ground line.
Since the storage capacitor 3 holds the difference voltage between Vm and Vsteph, the gate voltage (Vg) of the driving TFT 4 becomes Vm− (Vsteph−Vstepl). This voltage is equal to or lower than the lowest voltage VL among the gradation voltages applied to the pixels for display.
As described above, in this embodiment, the drive TFTs 4 of all the pixels are aligned with the characteristic C1 in FIG. 14B and can be used with characteristics close to the characteristic A after light emission. A uniform display without any problem is possible.
In this embodiment, the driving TFT 4 and the organic EL element 2 are connected via the lighting control switch element 20, but the same effect can be obtained without the lighting control switch element 20. Even if the lighting control switch element 20 is connected between the power supply line 6 and the source of the driving TFT 4, the same effect can be obtained.

[Example 2]
FIG. 3 is a diagram showing an overall configuration of an organic EL display device according to Example 2 of the present invention.
The present embodiment is different from the first embodiment in that the reference switch element 22 is turned on during the set period and a voltage of VL is applied from the reference voltage line 23 to the gate electrodes of the drive TFTs 4 of all the pixels. The remaining points are the same as in the above-described implementation, and thus detailed description thereof is omitted.
FIG. 4 is a diagram showing a timing chart of the organic EL display device of the present embodiment. In this embodiment, the operations of “writing period” and “light emission period” are the same as those of the first embodiment, and this embodiment is different from the first embodiment in the operation of “setting period”. .
In this embodiment, the reset switch element 5 and the lighting control switch element 20 of all the pixels are turned off by the reset line 7 and the lighting switch line 21 at time T7 of the light emission period setting period.
At the same time, the reference switch elements 22 of all the pixels are turned on by the reference line 25, and the voltage VL is applied to the gate electrodes of the driving TFTs 4 of all the pixels. At this time, the step signal selection switch control line 17 turns on the step signal selection switch element 14, and the voltage Vsteph is applied to the signal line 12 from the step signal generator 29 via the step signal input line 15. . For example, the voltage of Vsteph is the highest potential voltage among the voltages that can be applied from the signal driver 9 or the voltage of the power supply line 6.

Thereafter, by turning off the reference switch element 22, the difference voltage between VL and Vsteph is stored in the storage capacitors 3 of all the pixels.
Next, at time T <b> 8, a voltage of Vstepl is applied to the signal line 12 from the step signal generation unit 29 via the step signal input line 15. For example, the voltage of Vstepl is the lowest potential voltage among the voltages that can be applied from the signal driver 9, or the voltage of the common ground line.
At this time, since the storage capacitor 3 holds the difference voltage between VL and Vsteph, the gate voltage (Vg) of the driving TFT 4 becomes VL− (Vsteph−Vstepl).
This voltage is a voltage equal to or lower than the lowest voltage value VL among the gradation voltages applied to the pixels for display, and is a voltage lower than Vm− (Vsteph−Vstepl) in the first embodiment. Can do.
As described above, in this embodiment, after the light emission, the drive TFTs 4 of all the pixels can be aligned with the characteristic C1 of FIG. 14B and can be used with characteristics close to the characteristic A. Therefore, the display caused by the hysteresis of the drive TFT 4 It is possible to perform uniform display without abnormality.

[Example 3]
FIG. 5 is a diagram showing an overall configuration of an organic EL display device according to Example 3 of the present invention.
The difference between the organic EL display device 3 of the present embodiment and the organic EL display device of the first embodiment is that the voltage of the gate electrode of the drive TFT 4 during the reset operation by lowering the voltage is reduced in addition to the countermeasure against hysteresis of the drive TFT 4 It is a measure for lack of convergence.
When the power supply voltage on the power supply line 6 is lowered due to the low voltage, or when the writing period per pixel is shortened for high definition, it is driven during the reset operation of the writing period due to insufficient writing. The convergence voltage of the gate electrode of the TFT 4 may not be a constant voltage (here, Vdd−Vth), and as a result, an afterimage is generated.
The present embodiment also solves this problem.
5 is different from FIG. 1 in that the other end of the organic EL element 2 is connected to the signal line 12 via a precharge switch element 26 controlled by a precharge line 27.
FIG. 6 is a timing chart for explaining the operation of the organic EL display device of this embodiment.
2 is different from the timing chart of FIG. 2 in the writing period in the precharge period (Tch period shown in FIG. 6), the precharge switch element 26, the lighting control switch element 20, the reset switch element 5, and the signal line selection. The switch element 11 is turned on, and the precharge voltage is preliminarily applied to the gate electrode of the drive TFT 4 from the signal drive unit 9 through the signal line 12 → precharge switch element 26 → lighting control switch element 20 → reset switch element 5. It is a point to charge.
Thereby, the convergence voltage at the time of the reset operation in the writing period is made constant, and the afterimage problem described in Patent Document 1 can be solved.
As described above, in this embodiment, the driving TFTs 4 of all the pixels can be aligned with the characteristic C1 in FIG. 14B after the light emission, and can be used with characteristics close to the characteristic A. Since the shortage can be solved, there is no display abnormality due to the hysteresis characteristic of the driving TFT 4 and uniform display without an afterimage is possible.

[Example 4]
FIG. 7 is a diagram showing an overall configuration of an organic EL display device according to Example 4 of the present invention.
The difference between the organic EL display of the present embodiment and the organic EL display device of the first embodiment is that the switching means (SW) for supplying a plurality of power supply voltages to the power supply line 6 for switching the luminance mode. Further, the level variable step signal generator 31 can vary the voltage value of the step voltage, or the step voltage of the H level or the low level (hereinafter referred to as L level) of the step voltage. .
FIG. 8 is a timing chart for explaining the operation of the organic EL display device of this embodiment. The difference from the timing chart of FIG. 2 is that the voltage of Vstepl is switched according to the value of the power supply voltage of the power supply line 6.
In order to use the driving TFT 4 with the same characteristics as the power supply voltage of Vdd1 when the power supply voltage of the power supply line 6 is switched from Vdd1 to Vdd2 lower than Vdd1, the voltage of Vstep1 is set to a lower voltage. Alternatively, it is necessary to make the voltage application time of Vstep1 longer. However, if the application time of the voltage of Vstep1 is lengthened, the light emission period is shortened, so that the display luminance is lowered.
Therefore, in this embodiment, the voltage of Vstep1 is switched according to the voltage value of the power supply voltage. For example, when the power supply voltage is Vdd1, the voltage of Vstep11 is used as the voltage of Vstep1, and when the power supply voltage is Vdd2, the voltage of Vstep12 lower than the voltage of Vstep11 is used as the voltage of Vstep1.
Accordingly, the drive TFTs 4 of all the pixels can be aligned with the characteristic C1 of FIG. 14B and used with characteristics close to the characteristic A while maintaining the light emission period in the same period. Uniform display without display abnormality is possible.
In the fourth embodiment, the case where the power supply voltage of the power supply line 6 and the voltage value of the step voltage can be switched in the first embodiment described above, but in the second embodiment or the third embodiment described above. By making it possible to switch between the power supply voltage of the power supply line 6 and the voltage value of the step voltage, the same effect as in the fourth embodiment can be obtained.

[Example 5]
FIG. 9 is a circuit diagram showing an equivalent circuit of one pixel of the organic EL display device according to Example 5 of the present invention.
The difference between the organic EL display device of the present embodiment and the organic EL display device of the first embodiment is that the organic EL element 2 is directly connected to the power line 6 and the driving TFT 4 is disposed on the reference potential side. It is a point. Accordingly, in this embodiment, the reset switch element 5 is also connected to the cathode side of the organic EL element 2.
In this embodiment, the driving TFT 4 is composed of an n-type thin film transistor. Therefore, the thin film transistor in one pixel can be formed only by the n-type process.
The basic operation is the same as that of the first embodiment except that the organic EL element 2 is installed on the power supply line 6 side and the driving TFT 4 is installed on the reference potential side to move the related elements. .
FIG. 10 is a timing chart for explaining the operation of the organic EL display device of this embodiment.
The timing chart of FIG. 10 is basically the same as the timing chart of FIG. However, although the time required for the reset operation is related to the characteristics of the driving TFT 4, the driving TFT 4 is a p-type thin film transistor in the first embodiment, whereas the present embodiment is an n-type thin film transistor. 1 and Example 5 are different.
Another difference between the timing chart of FIG. 10 and the timing chart of FIG. 2 is that the triangular wave in the light emission period is convex upward.
In this embodiment, since the driving TFT 4 is an n-type thin film transistor, the driving TFT 4 is turned on when the gate voltage becomes higher than the source electrode. Further, during the set period, when the reset switch element 5 and the lighting control switch element 20 are on, a voltage of Vstepl is applied to the signal line 12.
Next, after the reset switch element 5 and the lighting control switch element 20 are turned off, a voltage of Vsteph higher than Vstepl is applied.
Thereby, all the driving TFTs 4 can be aligned with the characteristic C1 of FIG. 14B and used with characteristics close to the characteristic A after light emission, so that uniform display without display abnormality due to hysteresis of the driving TFT 4 is possible. .

[Example 6]
FIG. 11 is a diagram showing an overall configuration of an organic EL display device according to Example 6 of the present invention.
The organic EL display device of the present embodiment is different from the organic EL display device of Embodiment 1 described above in that the gate electrode of the driving TFT 4 is connected to the signal line 12 via the reference switch element 22 controlled by the reference line 25. The signal line 12 is connected to the external negative power source 30 via the step signal selection switch element 14 and the external negative voltage input line 28.
FIG. 12 is a timing chart for explaining the operation of the organic EL display device of this embodiment.
The difference from the first embodiment described above is that the reference switch element 22 is turned on in the set period after the light emission period, and the external negative voltage input line 28 → step signal selection switch from the external negative power supply 30 to the gate electrode of the driving TFT 4 The negative voltage is supplied through the path of the element 14 → the signal line 12 → the reference switch element 22.
Accordingly, in this embodiment, the drive TFTs 4 of all the pixels can be aligned with the characteristic C1 of FIG. 14B and used with characteristics close to the characteristic A after the light emission, so that the display abnormality caused by the hysteresis characteristics of the drive TFT 4 can be obtained. No uniform display is possible.
In the sixth embodiment, the gate electrode of the drive TFT 4 is connected to the signal line 12 via the reference switch element 22, but the gate electrode of the drive TFT 4 is different from the signal line 12 via the reference switch element 22. Even when another voltage input line is connected to the external negative power supply 30, the same effect can be obtained.

In the sixth embodiment, the driving TFT 4 is a p-type thin film transistor. However, even when the driving TFT 4 is an n-type thin film transistor, the external negative power supply 30 is set to a voltage higher than the power supply voltage. The same effect can be obtained.
Further, in the sixth embodiment, the power supply line 6 is provided with switching means (SW) for supplying a plurality of power supply voltages, and when the driving TFT 4 is a p-type thin film transistor, the power supply voltage is changed from the voltage of Vdd1. When switching to a voltage of Vdd2 lower than Vdd1, the same effect as in the fourth embodiment can be obtained by switching the external power source from Vr1 to a voltage of Vr2 having a lower potential.
When the driving TFT 4 is an n-type thin film transistor, the same effect as that of the fourth embodiment can be obtained by switching the external power source from Vr1 to a higher voltage Vr3.
In each of the above-described embodiments, the step signal generator 29, the level variable step signal generator 31, and the external negative power source 30 are formed of a low-temperature polycrystalline silicon thin film transistor circuit and formed on a glass substrate. The signal generator 29, the level variable step signal generator 31, and the external negative power supply 30 may be formed in the signal driver 9.
Further, the step signal generation unit 29, the level variable step signal generation unit 31, and the external negative power source 30 may be input from the outside such as the main computer side.
As mentioned above, the invention made by the present inventor has been specifically described based on the above embodiments. However, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Of course.

It is a figure which shows the whole structure of the organic electroluminescent display apparatus of Example 1 of this invention. It is a figure which shows the timing chart of the organic electroluminescent display apparatus of Example 1 of this invention. It is a figure which shows the whole structure of the organic electroluminescence display of Example 2 of this invention. It is a figure which shows the timing chart of the organic electroluminescent display apparatus of Example 2 of this invention. It is a figure which shows the whole structure of the organic electroluminescent display apparatus of Example 3 of this invention. It is a timing chart for demonstrating operation | movement of the organic electroluminescent display apparatus of Example 3 of this invention. It is a figure which shows the whole structure of the organic electroluminescent display apparatus of Example 4 of this invention. It is a timing chart for demonstrating operation | movement of the organic electroluminescent display apparatus of Example 4 of this invention. It is a circuit diagram which shows the equivalent circuit of 1 pixel of the organic electroluminescence display of Example 5 of this invention. It is a timing chart for demonstrating operation | movement of the organic electroluminescent display apparatus of Example 5 of this invention. It is a figure which shows the whole structure of the organic electroluminescent display apparatus of Example 6 of this invention. It is a timing chart for demonstrating operation | movement of the organic electroluminescent display apparatus of Example 6 of this invention. It is a figure which shows the hysteresis characteristic of a thin-film transistor. It is a figure which shows the relationship between the gate voltage and drain current of a thin-film transistor with hysteresis. It is a figure which shows the characteristic of the drive thin-film transistor at the time of the conventional display abnormality.

Explanation of symbols

1 pixel 2 organic electroluminescence element (organic EL element)
3 Memory capacity 4 p-type thin film transistor (drive TFT)
DESCRIPTION OF SYMBOLS 5 Reset switch element 6 Power supply line 7 Reset line 8 Gate drive part 9 Signal drive part 10 Signal input line 11 Signal line selection switch element 12 Signal line 13 Triangular wave selection switch element 14 Step signal selection switch element 15 Step signal input line 16 Triangular wave input Line 17 Step signal selection switch control line 18 Triangular wave selection switch control line 19 Signal line selection switch control line 20 Lighting control switch element 21 Lighting switch line 22 Reference switch element 23 Reference voltage line 25 Reference line 26 Precharge switch element 27 Precharge line 28 External Negative Voltage Input Line 29 Step Signal Generation Unit 30 External Negative Power Supply 31 Level Variable Step Signal Generation Unit 32 Precharge Signal Selection Line 40 Scanning Output Line 41 Lighting Control Line 42 OR Circuit SW Switching Means G gate electrode GI gate insulating film CAP carrier

Claims (20)

A plurality of pixels each having a self-luminous element;
A plurality of signal lines for inputting image signals to the pixels;
A drive circuit for supplying the image signal to the signal lines;
A step signal generation circuit for supplying a step signal to each signal line;
Each of the pixels includes a driving transistor that drives the self-luminous element based on the image signal;
A capacitive element connected between a corresponding signal line of the plurality of signal lines and a control electrode of the driving transistor;
A reset switch element connected between a control electrode and a second electrode of the drive transistor;
A first electrode of the driving transistor is connected to a first power supply voltage;
The other end of the self-luminous element is an image display device connected to a second power supply voltage,
Within one frame period, it has a setting period, and a writing period for writing the image signal to each pixel in succession to the setting period,
In the first half of the set period, the reset switch elements of all the pixels are turned on, the control electrodes of the drive transistors of all the pixels are converged to a predetermined voltage, and each signal from the step signal generation circuit Supplying a first voltage level step signal to the line;
In the latter half of the setting period, the reset switch elements of all the pixels are turned off, and the first voltage level is applied to each signal line from the step signal generation circuit within the latter half of the setting period. An image display device that supplies step signals having different second voltage levels. Each pixel has a lighting control switch element connected between the second electrode of the driving transistor and one end of the self-light-emitting element,
In the first half of the set period, the reset switch element and the lighting control switch element of all the pixels are turned on, the control electrodes of the drive transistors of all the pixels are converged to a predetermined voltage, and the step signal Supplying a step signal of the first voltage level from the generation circuit to each of the signal lines;
The reset switch elements and the lighting control switch elements of all the pixels are turned off during the latter half of the set period , and the signal lines are supplied from the step signal generation circuit to the signal lines within the latter half of the set period. The image display device according to claim 1, wherein a step signal of a second voltage level is supplied . A second electrode of the driving transistor of each pixel is connected to one end of the self-luminous element;
The first power supply voltage is supplied to the first electrode of the drive transistor of each pixel through a lighting control switch element;
In the first half of the set period, the reset switch elements and the lighting control switch elements of all the pixels are turned on, the gate electrodes of the drive transistors of all the pixels are converged to a predetermined voltage, and the step signal Supplying a step signal of the first voltage level from the generation circuit to each of the signal lines;
The reset switch elements and the lighting control switch elements of all the pixels are turned off during the latter half of the set period , and the signal lines are supplied from the step signal generation circuit to the signal lines within the latter half of the set period. The image display device according to claim 1, wherein a step signal of a second voltage level is supplied . Each pixel has a precharge switch element connected between a corresponding signal line of the plurality of signal lines and one end of the self-light-emitting element,
The writing period includes a precharge period for sequentially inputting a precharge voltage to each pixel and an image signal writing period for sequentially inputting an image signal to each pixel for each display line unit,
In the precharge period, the precharge switch element and the reset switch element of each pixel are turned on, the precharge voltage is supplied from the drive circuit to the signal lines, and the drive transistor of each pixel The image display apparatus according to claim 1, wherein the precharge voltage is input to the control electrode. Each pixel has a lighting control switch element connected between the second electrode of the driving transistor and one end of the self-light-emitting element,
In the precharge period, the precharge switch element, the lighting control switch element, and the reset switch element of each pixel are turned on, and the precharge voltage is supplied from the drive circuit to the signal lines. The image display device according to claim 4, wherein the precharge voltage is input to a control electrode of the drive transistor of each pixel. The step signal generation circuit has a voltage level of one of the first voltage level and the second voltage level of the step signal, a step width of the first voltage level and the second voltage level of the step signal. The image display device according to claim 1, wherein the image display device can be changed. The drive transistor is a p-type field effect transistor,
A cathode electrode of the self-luminous element is connected to the second power supply voltage;
In the step signal, the first voltage level is a high level and the second voltage level is a low level.
During the latter half of the setting period, a voltage having a lower potential than the second power supply voltage or the drive circuit is supplied to the control electrodes of the drive transistors of all the pixels as a characteristic value setting voltage. The image display device according to claim 1, wherein a voltage having a lower potential than a voltage having the lowest potential in the voltage range is input . The driving transistor is an n-type field effect transistor,
An anode electrode of the self-luminous element is connected to the second power supply voltage;
In the step signal, the first voltage level is a low level, and the second voltage level is a high level,
In the latter half of the setting period, a voltage having a higher potential than the second power supply voltage or the driving circuit is supplied to the control electrodes of the driving transistors of all the pixels as a characteristic value setting voltage. The image display device according to claim 1, wherein a voltage having a higher potential than a voltage having the highest potential in the voltage range is input . A plurality of pixels each having a self-luminous element;
A plurality of signal lines for inputting image signals to the pixels;
A plurality of reference lines for inputting a reference voltage to each of the pixels;
A drive circuit for supplying the image signal to the signal lines;
A step signal generation circuit for supplying a step signal to each signal line;
Each of the pixels includes a driving transistor that drives the self-luminous element based on the image signal;
A capacitive element connected between a corresponding signal line of the plurality of signal lines and a control electrode of the driving transistor;
And a reference switch element connected between the control electrode of the corresponding reference line and the driving transistor of the plurality of reference lines,
A first electrode of the driving transistor is connected to a first power supply voltage;
The other end of the self-luminous element is an image display device connected to a second power supply voltage,
Within one frame period, it has a setting period, and a writing period for writing the image signal to each pixel in succession to the setting period,
In the first half of the set period, the reference switch elements of all the pixels are turned on, a predetermined voltage is input to the control electrodes of the drive transistors of all the pixels, and each signal from the step signal generation circuit Supplying a first voltage level step signal to the line;
In the latter half of the set period, the reference switch elements of all the pixels are turned off, and the first voltage level is applied to each signal line from the step signal generation circuit within the latter half of the set period. An image display device that supplies step signals having different second voltage levels. The step signal generation circuit has a voltage level of one of the first voltage level and the second voltage level of the step signal, a step width of the first voltage level and the second voltage level of the step signal. The image display device according to claim 9, wherein the image display device can be changed. Each pixel includes a reset switch element connected between a control electrode and a second electrode of the driving transistor;
The image display device according to claim 9, further comprising a lighting control switch element connected between the second electrode of the driving transistor and one end of the self-light-emitting element.   The image display device according to claim 11, wherein the reset switch element and the lighting control switch element are turned off during the set period. The drive transistor is a p-type field effect transistor,
A cathode electrode of the self-luminous element is connected to the second power supply voltage;
In the step signal, the first voltage level is a high level and the second voltage level is a low level.
During the latter half of the setting period, a voltage having a lower potential than the second power supply voltage or the drive circuit is supplied to the control electrodes of the drive transistors of all the pixels as a characteristic value setting voltage. The image display device according to claim 9, wherein a voltage having a lower potential than a voltage having the lowest potential in the voltage range is input . The driving transistor is an n-type field effect transistor,
An anode electrode of the self-luminous element is connected to the second power supply voltage;
In the step signal, the first voltage level is a low level, and the second voltage level is a high level,
In the latter half of the setting period, a voltage having a higher potential than the second power supply voltage or the driving circuit is supplied to the control electrodes of the driving transistors of all the pixels as a characteristic value setting voltage. The image display device according to claim 9, wherein a voltage having a higher potential than a voltage having the highest potential in the voltage range is input . A plurality of pixels each having a self-luminous element;
A plurality of signal lines for inputting image signals to the pixels;
A drive circuit for supplying the image signal to the signal lines,
Each of the pixels includes a driving transistor that drives the self-luminous element based on the image signal;
A capacitive element connected between a corresponding signal line of the plurality of signal lines and a control electrode of the drive transistor;
The drive transistor is a p-type field effect transistor,
A first electrode of the driving transistor is connected to a first power supply voltage;
The cathode electrode of the self-luminous element is an image display device connected to a second power supply voltage,
Within one frame period, it has a setting period, and a writing period for writing the image signal to each pixel in succession to the setting period,
A power circuit;
A plurality of voltage input lines,
Each pixel has a reference switch element connected between a corresponding voltage input line of the plurality of voltage input lines and a control electrode of the driving transistor ,
In the setting period, the reference switch elements of all the pixels are turned on, and a voltage having a lower potential than the second power supply voltage is supplied from the power supply circuit to each of the voltage input lines. An image display device, wherein a voltage having a lower potential than the second power supply voltage is input as a characteristic value setting voltage to a control electrode of a transistor. The signal line also serves as the voltage input line,
The image display device according to claim 15, wherein the reference switch element of each pixel is connected between a corresponding signal line of the plurality of signal lines and a control electrode of the drive transistor. . Each pixel includes a reset switch element connected between a control electrode and a second electrode of the driving transistor;
16. The image display device according to claim 15, further comprising a lighting control switch element connected between the second electrode of the driving transistor and one end of the self-light-emitting element. A plurality of pixels each having a self-luminous element;
A plurality of signal lines for inputting image signals to the pixels;
A drive circuit for supplying the image signal to the signal lines,
Each of the pixels includes a driving transistor that drives the self-luminous element based on the image signal;
A capacitive element connected between a corresponding signal line of the plurality of signal lines and a control electrode of the drive transistor;
The driving transistor is an n-type field effect transistor,
A first electrode of the driving transistor is connected to a first power supply voltage;
The anode electrode of the self-luminous element is an image display device connected to a second power supply voltage,
Within one frame period, it has a setting period, and a writing period for writing the image signal to each pixel in succession to the setting period,
A power circuit;
A plurality of voltage input lines,
Each pixel has a reference switch element connected between a corresponding voltage input line of the plurality of voltage input lines and a control electrode of the driving transistor ,
In the setting period, the reference switch elements of all the pixels are turned on, and a voltage having a higher potential than the second power supply voltage is supplied from the power supply circuit to each of the voltage input lines. An image display device, wherein a voltage having a higher potential than the second power supply voltage is input as a characteristic value setting voltage to a control electrode of a transistor. The signal line also serves as the voltage input line,
19. The image display device according to claim 18, wherein the reference switch element of each pixel is connected between a corresponding signal line of the plurality of signal lines and a control electrode of the drive transistor. . Each pixel includes a reset switch element connected between a control electrode and a second electrode of the driving transistor;
The image display device according to claim 18, further comprising a lighting control switch element connected between the second electrode of the driving transistor and one end of the self-luminous element.

Images