JP2007179037A - El display apparatus and method for driving the el display apparatus - Google Patents

El display apparatus and method for driving the el display apparatus Download PDF

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JP2007179037A
JP2007179037A JP2006325005A JP2006325005A JP2007179037A JP 2007179037 A JP2007179037 A JP 2007179037A JP 2006325005 A JP2006325005 A JP 2006325005A JP 2006325005 A JP2006325005 A JP 2006325005A JP 2007179037 A JP2007179037 A JP 2007179037A
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current
voltage
circuit
signal line
pixel
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Japanese (ja)
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Norio Nakamura
Hiroshi Takahara
則夫 中村
博司 高原
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Toshiba Matsushita Display Technology Co Ltd
東芝松下ディスプレイテクノロジー株式会社
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Abstract

An object of the present invention is to make it difficult to cause insufficient writing in all gradation regions as compared with the prior art, and to reduce display unevenness due to variations in transistor characteristics.
An EL display device in which pixels having EL elements are formed in a matrix, a constant current circuit that generates a predetermined constant current, and a gradation voltage circuit that generates a gradation voltage. The constant current generated by the constant current circuit 10 is supplied to the pixel 16 via the source signal line 18, and the gradation voltage generated by the gradation voltage circuit 20 is supplied to the pixel 16 via the source signal line 18. It is the structure supplied.
[Selection] Figure 1

Description

  The present invention relates to a driving method, a driving circuit, and a display device for a self-luminous display panel (display device) such as an EL display panel (display device) using an organic or inorganic electroluminescence (EL) element. The present invention also relates to a display panel (display device) using these drive circuits.

  In an active matrix image display device using an organic electroluminescence (EL) material or an inorganic EL material as an electro-optic conversion substance, light emission luminance changes according to a current written to a pixel. The EL display panel is a self-luminous type having a light emitting element in each pixel. The EL display panel has advantages such as higher image visibility, higher light emission efficiency, no backlight, and faster response speed than the liquid crystal display panel.

  An active matrix organic EL display panel is disclosed in Patent Document 1. An equivalent circuit of one pixel of this display panel is shown in FIG. The pixel 16 includes an EL element 15 that is a light emitting element, a first transistor (driving transistor) 11 a, a second transistor (switching transistor) 11 b, and a storage capacitor (capacitor) 19. The light emitting element 15 is an organic electroluminescence (EL) element.

  The driver circuit that drives the pixel configuration of FIG. 3 outputs a video signal indicated by the strength of the voltage. The driver circuit is similar in configuration to the driver circuit that drives the liquid crystal display panel. A voltage signal as a video signal is applied to the source signal line 18 from the driver circuit. The applied voltage signal is applied to the pixel 16 and held in the capacitor 19.

  A method for driving the organic EL display device is disclosed in Patent Document 2.

In this specification, the transistor 11a that supplies current to the EL element 15 is referred to as a driving transistor. A transistor that operates as a switch, such as the transistor 11b in FIG. 3, is referred to as a switching transistor.
JP-A-8-234683 JP 2005-266735 A

  The organic EL display panel is configured by using a transistor array made of low-temperature or high-temperature polysilicon. However, display variations occur in organic EL elements when the transistor characteristics of the polysilicon transistor array vary.

  FIG. 3 shows a pixel configuration of a voltage program method. Note that the voltage programming method applies a voltage signal (program voltage) such as a video signal indicated by the magnitude or strength of a voltage to a data signal line, a source signal line, or a pixel, and the voltage signal is applied by a pixel transistor or the like. This refers to a configuration, circuit, or driving method for converting to a current signal and applying it to an EL element.

  In the current programming method, a current signal (program current) such as a video signal indicated by the magnitude or strength of a current is applied to a data signal line, a source signal line, or a pixel, and a current signal applied by a pixel transistor or the like is applied. It refers to a configuration, circuit, or driving method in which the EL element is applied as it is.

  Both the current flowing into the EL element and the current flowing out from the EL element are called application. In addition, driving the EL element may be used synonymously with applying current or supplying current to the EL element. Alternatively, the current programming method is a configuration in which a current signal substantially proportional to an applied current signal or a current signal (program current) obtained by performing a predetermined conversion process on an applied current is applied directly or indirectly to an EL element. A circuit or driving method.

  In the pixel configuration shown in FIG. 3, the video signal indicated by the voltage level is converted into a current signal by the driving transistor 11a. Therefore, if the transistor 11a has a characteristic variation, the current signal to be converted also varies. Normally, the transistor 11a has a characteristic variation of 50% or more. In the configuration of FIG. 3, there is a problem that display unevenness corresponding to characteristic variation occurs. However, the voltage programming method has a high charge / discharge capability of the source signal line and the like in either the low gradation region or the high gradation region, and display unevenness due to insufficient writing hardly occurs.

  Display unevenness due to variations in the characteristics of the transistors can be reduced by adopting a current program configuration. However, the current programming method has a problem that the driving current in the low gradation region is small and the driving cannot be performed satisfactorily due to the parasitic capacitance of the source signal line 18.

  In consideration of the above-described conventional problems, the present invention is less likely to cause insufficient writing in all gradation regions than in the past, and an EL display device and an EL display that can reduce display unevenness due to variations in transistor characteristics as compared with the prior art. It is an object to provide a method for driving an apparatus.

In order to achieve the above object of the present invention,
The first aspect of the present invention is an EL display device in which pixels having EL elements are formed in a matrix,
A constant current circuit for generating a predetermined constant current;
A gradation voltage circuit for generating a gradation voltage;
The constant current generated by the constant current circuit is supplied to the pixel via a source signal line,
In the EL display device, the gradation voltage generated by the gradation voltage circuit is supplied to the pixel through the source signal line.

The second aspect of the present invention is a method for driving an EL display device in which pixels having EL elements are formed in a matrix.
The EL display device
A constant current circuit for generating a predetermined constant current;
A gradation voltage circuit for generating gradation voltages;
The pixel includes a driving transistor that supplies a driving current to the EL element, and a switching transistor that forms a current path between a source signal line and the driving transistor.
The driving method of the EL display device is as follows:
Applying the constant current generated by the constant current circuit to the pixel via the source signal line;
Obtaining a potential of the source signal line in a state where the constant current is applied to the source signal line;
Add the acquired potential and the gradation voltage or subtract the gradation voltage from the acquired potential,
Applying the result of the addition or subtraction to the driving transistor of the pixel via the source signal line;
This is a method for driving an EL display device.

  The third aspect of the present invention is the EL display according to the second aspect of the present invention, wherein a precharge voltage is applied to the source signal line or the pixel before or during the period in which the constant current is applied to the pixel. It is a drive method of an apparatus.

  According to a fourth aspect of the present invention, there is provided the EL display device driving method according to claim 2, wherein the constant current circuit is composed of a plurality of unit transistors.

The fifth aspect of the present invention is an EL display device in which pixels having EL elements are formed in a matrix,
A constant current circuit for generating a predetermined constant current;
A gradation voltage circuit for generating a gradation voltage;
The pixel includes a driving transistor that supplies a driving current to the EL element, a capacitor connected to a gate terminal of the driving transistor, and a first signal path that forms an electrical path between a source signal line and the driving transistor. An EL display device comprising: a switching transistor; and a second switching transistor that applies the gradation voltage to the driving transistor through the capacitor.

The sixth aspect of the present invention is an EL display device in which pixels having EL elements are formed in a matrix,
A constant current circuit for generating a predetermined constant current;
A gradation voltage circuit for generating gradation voltages;
A first source signal line for supplying the constant current to the pixel;
A second source signal line for supplying the gradation voltage to the pixel,
The pixel forms an electrical path between a driving transistor that supplies a driving current to the EL element, a capacitor connected to a gate terminal of the driving transistor, a first source signal line, and the driving transistor. An EL display device having a first switching transistor and a second switching transistor that forms an electrical path with the second source signal line and the capacitor.

The seventh aspect of the present invention is an EL display device in which pixels having EL elements are formed in a matrix.
A constant current circuit for generating a predetermined constant current;
A gradation voltage circuit for generating gradation voltages;
A capacitor,
A source signal line for supplying the constant current to the pixel,
The gradation voltage is an EL display device that is applied to the source signal line via the capacitor.

According to an eighth aspect of the present invention, there is provided a display unit in which pixels having EL elements are formed in a matrix form;
A constant current output circuit for outputting a reset current to the driving transistor of the EL element;
A voltage holding circuit for acquiring a gate terminal potential of the driving transistor in a state where the reset current is applied;
A gradation voltage circuit that outputs a gradation voltage corresponding to a video signal;
A voltage application circuit for adding the gate terminal potential and the gradation voltage or subtracting the gradation voltage from the gate terminal potential and applying a result of the addition or subtraction to the gate terminal of the driving transistor; EL display device.

  Note that the driver circuit and the EL display device of the present invention include a current generation circuit and a voltage generation circuit. The constant current output from the current generation circuit is applied to a driving transistor that drives the EL element (current program). By applying a constant current to the driving transistor, the gate voltage of the driving transistor is current-programmed to flow the applied constant current. This constant current is called a reset current Ia. The reset current Ia may be used as a meaning of a reference current.

  A current output from the source driver circuit 14 or a current written to the driving transistor or the like is called a program current. A current that is set to cause a reference current to flow through the driving transistor 11a and the like is referred to as a reset current Ia. Therefore, when the current output from the source driver circuit 14 is a reset current, the program current becomes the reset current.

  The state where the constant current is applied or changed as described above is called a current reset state. A voltage applied to the gate terminal of the driving transistor or a generated voltage when the driving transistor is flowing a constant current is referred to as a reset voltage Va. In addition, a constant reference voltage may be referred to as a reset voltage Va.

  The voltage generation circuit outputs the gradation voltage Vx or the target gradation voltage Vc corresponding to the video signal input to the EL display device. The gradation voltage and the like are applied to the gate terminal of the driving transistor with reference to the reset voltage Va (voltage program). For example, if the reset voltage Va is 3V, the ± gradation voltage Vx is applied with reference to the reset voltage Va of 3V. If Vx = 0, the driving transistor 11a causes the current-programmed reset current Ia to flow through the EL element 15 as a light emission current. That is, the current that flows through the EL element 15 is determined based on the reset voltage Va.

  In another embodiment of the present invention, the driver circuit and the EL display device measure or hold the gate terminal voltage (reset voltage Va) of the driving transistor with a constant current (reset current Ia) applied or hold for a predetermined period. Circuit.

  The current program (method) is sometimes called current drive (method). The voltage program (method) is sometimes called voltage drive (method).

  In addition, the driver circuit means not only a circuit composed of a semiconductor IC such as silicon but also a circuit formed on a glass substrate using low temperature polysilicon or the like.

  The present invention has an effect that the writing deficiency is less likely to occur in the entire gradation region compared to the conventional case, and the display unevenness due to the characteristic variation of the transistor can be reduced as compared with the conventional case.

  In the present invention, for example, the reset current Ia is applied to the driving transistor 11a of each pixel to generate the reset voltage Va of the driving transistor 11a. The reset voltage Va of the driving transistor 11a of each pixel differs depending on the characteristics of each driving transistor 11a. This is because variation occurs due to the laser annealing state or the like. By applying the target gradation voltage Vc with the reset voltage Va as a reference, it is possible to apply an accurate gradation current to the EL element 15 even if the characteristics of the driving transistors 11a are different. As the absolute value of the gradation voltage increases, the variation in the current flowing through the EL element 15 increases. However, the variation is a size that does not cause a problem in practice.

  The voltage programming method has a drawback that the characteristic compensation of the driving transistor 11a of the pixel 16 is insufficient. However, the present invention implements a current programming method in which a constant current is applied to the transistor of the pixel 16, for example. The gradation voltage Vx is applied with the gate terminal voltage (reset voltage Va) of the driving transistor 11a generated by the execution of the current program as a reference (origin) (voltage program). Therefore, the target gradation voltage Vc applied to the gate terminal of the driving transistor 11a is Va ± Vx. Therefore, even if there is a variation in the characteristics of the driving transistor 11a, a gradation current corresponding to an accurate gradation voltage can be supplied to the EL element 15.

  By setting the reset current Ia to a current value larger than a predetermined value, the problem of insufficient writing in the low gradation region (low current region), which is a weak point of the current programming method, does not occur. For example, by adding or subtracting the gradation voltage Vx with reference to the reset voltage Va, an advantage that there is no shortage of writing in all gradation areas, which is a characteristic of voltage driving, can be exhibited.

  Embodiments of an EL display device and a driving method thereof according to the present invention will be described below.

(First embodiment)
FIG. 1 is an explanatory diagram of a drive circuit of an EL display device according to the present invention. An output terminal 21 of the source driver IC (circuit) 14 is connected to the source signal line 18. A plurality of pixels 16 are connected to each source signal line 18. EL elements 15 are formed on the pixels 16, and the pixels 16 are arranged in a matrix.

  Each output terminal 21 is configured or formed with a constant current output circuit (current gradation circuit) 10 and a voltage gradation circuit 20. The constant current output circuit 10 is preferably one that can output a gradation current such as a program current. However, in the first embodiment, the constant current output circuit 10 does not need to be able to output a gradation current, and may be configured to output a predetermined constant current (program current).

  By configuring so that constant currents having different current amounts can be output, the magnitude of the reset current Ia can be changed or changed in accordance with the gradation voltage Vx. Further, the magnitude of the constant current can be changed or set in accordance with the panel size or the parasitic capacitance of the source signal line 18. Therefore, the advantage that the current program can be implemented satisfactorily is exhibited.

  Switches SW1, SW2, SW3, SW4, and SW5 are formed or arranged for each output. Further, a capacitor 52 and a buffer 53 are formed or arranged. The capacitor 52 may be any as long as it has a function of cutting a direct current (DC) component. Alternatively, any one can be used as long as the potential can be level-shifted.

  The buffer 53 may be any as long as the input a section has high impedance and the output b section has low impedance. For example, a buffer amplifier and an operational amplifier are exemplified. In addition, an emitter follower circuit may be configured with transistor elements.

  The structure of the pixel 16 of the EL display panel (EL display device) of the present invention is such that one pixel 16 is formed by four transistors 11 and EL elements 15 as shown in FIG. At least, a current path through the transistor 11 a that drives the EL element 15 can continue to the source signal line 18.

  In the pixel configuration of FIG. 2, the current flowing through the transistor 11a (driving transistor 11a) that supplies current to the EL element 15 can be extracted to the source signal line by turning on (closing) the transistor 11c. Alternatively, the pixel configuration is such that at least the voltage applied to the gate terminal of the transistor that drives the EL element 15 can be read from the source signal line 18.

  In the pixel configuration of FIG. 2, the gate terminal voltage of the transistor 11a (driving transistor 11a) that supplies current to the EL element 15 is read from the source signal line 18 by turning on (closing) the transistors 11b and 11c. be able to.

  The pixel circuit in FIG. 2 includes four transistors 11 (11a, 11b, 11c, and 11d) in one pixel. The gate terminal of the driving transistor 11a is connected to the source terminal of the transistor 11b. The gate terminals of the transistors 11b and 11c are connected to the gate signal line 17a. The drain terminal of the transistor 11 b is connected to the source terminal of the transistor 11 c and the source terminal of the transistor 11 d, and the drain terminal of the transistor 11 c is connected to the source signal line 18. The gate terminal of the transistor 11d is connected to the gate signal line 17b, and the drain terminal of the transistor 11d is connected to the anode electrode (terminal) of the EL element 15.

  The transistor 11 is a P-channel transistor. A P-channel transistor is preferable because of its high lifetime reliability. In the configuration of FIG. 2, the current Ia flowing from the driving transistor 11 a to the source driver circuit 14 is a current drawn into the source driver circuit 14. In the source driver circuit 14, an N-channel transistor is formed. The N-channel transistor can satisfactorily absorb the sink current Ia, and the N-channel transistor has small characteristic variation. Therefore, the source driver circuit 14 can be reduced in size.

  In the pixel configuration of FIG. 2, the gate terminals of the transistors 11b and 11c are connected to the gate signal line 17a. The transistors 11b and 11c are on (closed) and off (open) controlled by an on / off control signal applied to the gate signal line 17a. The gate terminal of the transistor 11d is connected to the gate signal line 17b. The transistor 11d is on (closed) and off (open) controlled by an on / off control signal applied to the gate signal line 17b.

  The gate driver 12 (in FIG. 20, the gate driver circuits 12a and 12b) controls the gate signal lines 17a and 17b. As shown in FIG. 20, the gate driver circuit 12a may be formed or arranged at the left end of the display region 184, and the gate driver circuit 12b may be formed or arranged at the right end. The gate driver circuit 12a controls the gate signal line 17a, and the gate driver circuit 12b controls the gate signal line 17b. Since the gate driver circuit 12a and the gate driver circuit 12b each have a shift register circuit formed therein, they can be operated independently.

  In the organic EL pixel configuration shown in FIG. 2, the transistor 11b functions as a switching transistor for selecting a pixel. The transistor 11 a functions as a driving transistor for supplying current to the EL element 15.

  The transistor 11b has a multi-gate structure that is more than a dual gate. The transistor 11b constituting the pixel 16 of the display panel of the present invention functions as a source-drain switch of the transistor 11a. Therefore, the transistor 11b is required to have as low a leakage current characteristic as possible. Low leakage current characteristics can be realized by making the gate structure of the transistor 11b a multi-gate structure having a dual gate structure or higher.

  In order to manufacture a panel at low cost, it is preferable that all the transistors 11 constituting the pixel are formed with a P channel and the gate driver circuit 12 is also formed with a P channel. By forming the array with only P-channel transistors in this way, the number of masks becomes five, and cost reduction and high yield can be realized.

  Hereinafter, a description will be given with reference to FIGS. The following description is for understanding the pixel configuration of the current drive method. The present invention has a current-driven pixel configuration (a pixel configuration capable of current programming). The present invention is characterized in that a program current (reset current Ia) is supplied to the driving transistor 11a of the pixel 16, and the gate terminal potential of the driving transistor 11a is measured or held for a certain period in a state where the program current is supplied. To do. Further, the gradation voltage is added to or subtracted from the gate terminal potential, and the added or subtracted voltage is written to the gate terminal of the pixel driving transistor 11a.

  The operation of the pixel of the present invention is controlled by two operations, a first operation and a second operation. 17A to 17B are explanatory diagrams of operations in the pixel configuration of FIG. The first operation is a current program operation (an operation for setting a current to flow through the EL element 15). The first operation is a current reset operation, a voltage read operation for applying a reset current Ia to read a reset potential of the gate terminal of the driving transistor 11a, and a gradation voltage or a target with the reset voltage Va as a reference (center or origin). The operation is roughly divided into gradation voltage application operations for applying gradation voltages. The second operation is an operation in which a current is passed through the EL element 15 and the EL element 15 emits light. FIG. 17A is an explanatory diagram of the first operation. FIG. 17B is an explanatory diagram of the second operation.

  Hereinafter, the EL display panel and the driving method thereof according to the present invention will be described with reference to FIGS. 1 and 17A to 17B.

  The first operation is an operation for storing a current value flowing through the EL element 15. First, a reset current Ia, which is a predetermined constant current, is applied to the source signal line 18 from the constant current output circuit 10 of the source driver IC (circuit) 14. An example of the constant current output circuit 10 is shown in FIG.

  As an example, the constant current output circuit 10 includes an operational amplifier 291, a transistor 286, and a resistor R. An electronic volume 331 is connected to the + side terminal of the operational amplifier 291. The electronic volume 331 operates as a DA conversion circuit that converts digital data into analog data. The output voltage V of the electronic volume 331 is changed by setting data (digital data). The current Ia flowing through the source signal line 18 is a value obtained by dividing the output voltage V of the electronic volume 331 by the resistance R.

  The generation of the reset current Ia is not limited to the constant current output circuit 10, and any one may be used as long as it can generate a reset current Ia having a predetermined or constant range of magnitude. For example, the reset current Ia can be generated even in an emitter follower circuit. Further, the reset current Ia generated by the constant current output circuit 10 is preferably configured to generate a plurality of reset currents Ia. More preferably, it is possible to generate the reset current Ia corresponding to each gradation voltage.

  The reset current Ia includes a state of current 0 (Ia = 0, no current flows). In the pixel configuration of FIG. 2, if the program current Ia = 0, the driving transistor 11 a changes the potential of the gate terminal (the potential of one terminal of the capacitor 19) so that no current flows through the EL element 15 ( Variable). The reset voltage Va at the gate terminal of the driving transistor 11a after the fluctuation indicates the characteristics of the driving transistor 11a. The reset voltage Va when the reset current Ia = 0 is the operation start voltage of the driving transistor 11a.

  When the program current Ia is applied from the source driver IC (circuit) 14 to the source signal line 18, the transistor 11b and the transistor 11c are turned on (closed) as shown in FIG. The transistor 11d is controlled to be in an open state. The transistors 11b, 11c and 11d are controlled by an on / off signal applied to the gate signal lines 17a and 17b.

  As shown in FIG. 4A, the source driver IC (circuit) 14 performs a reset operation before applying the program current (reset current Ia). In the reset operation, the switches SW4 and SW5 illustrated in FIGS. 1 and 4A to 4C are set in an open (off) state. The switches SW2 and SW3 are closed (turned on), and a ground potential or a predetermined fixed voltage is applied to the capacitor 52. The program current may be applied to the source signal line 18 with the switch SW1 being closed.

  The above operation is the reset operation. In the reset operation, a fixed (known) voltage is applied to one terminal c of the capacitor 52. The known voltage includes the ground voltage. The capacitance of the capacitor 52 is preferably 0.05 pF or more and 2 pF or less.

  In the next voltage reading operation, the switch SW1 is closed and the program current (reset current Ia) Ia is applied to the source signal line 18. At this time, the switches SW4 and SW5 are in an open state, and the switch SW2 is in a closed state (see FIG. 4A).

  The driving transistor 11a of the pixel 16 shown in FIGS. 17A to 17B passes the program current Ia and changes the gate terminal potential so that the program current Ia flows. The gate terminal potential is output (read) to the source signal line 18 because the transistors 11b and 11c are in the closed state. The switch SW2 in the source driver IC (circuit) 14 is closed. As a result, the gate terminal potential of the driving transistor 11a through which the program current (reset current) Ia flows is applied (read out) to the a part of the source driver IC (circuit) 14 (see FIG. 1).

  The magnitude of the program current (reset current) Ia is preferably set to be in the range of 1/8 to 1 times the maximum gradation current. In order to shorten the writing time, it may be set to 1 to 10 times the maximum gradation current. The maximum gradation current is the magnitude of the current flowing through the EL element 15 at the maximum gradation or the magnitude of the program current programmed in the pixel 16. For example, in 256 gradations, the maximum gradation current is a current programmed in the EL element 15 in the 255th gradation (the gradation number starts from the 0th gradation).

  When the program current (reset current Ia) is small, it takes a long time to charge and discharge the parasitic capacitance of the source signal line 18. Therefore, the change in the gate potential of the driving transistor 11a does not converge in the first short time of one horizontal scanning period (1H period). Further, when the program current (reset current Ia) is large, the characteristic compensation in the low gradation region where the influence of the characteristic variation of the driving transistor 11a is likely to appear as an image display becomes low.

  With the above operation, the gate terminal potential of the driving transistor 11a is read out to the a part of the capacitor 52. Alternatively, it is held in the a part of the capacitor 52. In the embodiment of FIG. 1, the gate terminal potential of the driving transistor 11 a is read out and held in the a part of the capacitor 52. The present invention is not limited to this. For example, the potential of the part a may be AD (analog-digital) converted and acquired as digital data. The acquired digital data is held in a memory circuit formed or configured inside or outside the source driver IC (circuit) 14. Of course, the data may be held outside or inside the source driver IC (circuit) 14 for a certain period in the state of analog data.

  The next operation is an operation of applying the gradation voltage with the read voltage as a reference (center position or origin position) (see FIG. 4B). In this operation, the switches SW1, SW2, and SW3 are opened, and the switches SW4 and SW5 are controlled to be closed. The a portion of the capacitor 52 holds the gate terminal voltage (reset voltage Va) of the driving transistor 11a of the selected pixel 16 (see FIG. 4A). A voltage held when the reset current Ia is supplied is called a reset voltage Va.

  The gate terminal voltage is a voltage necessary for the driving transistor 11 a to flow the program current (reset current Ia) to the EL element 15. If a ground (GND) voltage is applied to the portion c, the gate terminal voltage of the driving transistor 11 a is held between both electrodes of the capacitor 52.

  When the amplification factor (gain) of the operational amplifier 53 is 1, the voltage at the part a is applied to the source signal line 18 via the switch SW5. The transistors 11b and 11c of the pixel 16 are closed for one selected horizontal scanning period (1H period). In this state, the read gate terminal voltage of the driving transistor 11a is again applied to the gate terminal of the driving transistor 11a of the pixel 16.

  Therefore, the driving transistor 11 a passes a current corresponding to the reset current Ia to the EL element 15. The above state compensates for the characteristic variation of the driving transistor 11a and allows the reset current Ia (programmed current) to flow through the EL element 15 with high accuracy.

  Needless to say, the reset voltage Va is different for each pixel depending on the characteristics of the driving transistor 11a. However, the program current (reset current Ia) is applied to the EL element 15 with high accuracy.

  The voltage gradation circuit 20 outputs a gradation voltage Vx corresponding to each gradation. The gradation voltage Vx is a voltage corresponding to the gradation number of the video signal. It may be considered as a video signal. An image can be displayed by applying the gradation voltage Vx as it is or performing a certain process (proportional process, shift process, addition / subtraction process, etc.) and applying it as a program voltage to the driving transistor 11a.

  The gradation voltage Vx is applied to the c portion of the capacitor 52 through the switch SW4. The potential Va at the portion a of the capacitor 52 is shifted by the gradation voltage Vx output from the voltage gradation circuit 20. Therefore, the potential at the part a is ideally Va + Vx.

  The Va + gradation voltage Vx is output with a low impedance by the operational amplifier 53 having a gain of 1. The Va + gradation voltage Vx is applied to the source signal line 18 via the switch SW5 and the output terminal 21, and is applied to the gate terminal of the driving transistor 11a of the pixel 16. Therefore, the driving transistor 11 a applies a current corresponding to Va + Vx to the EL element 15.

  In FIG. 1, the operational amplifier 53 has a gain of 1, but is not limited thereto. For example, if it is twice, the operational amplifier 53 doubles the voltage applied to the part a and is applied to the source signal line 18. Further, the polarity reversal operation of the applied voltage of the a portion may be performed. The gradation voltage Vx is an arbitrary voltage for each gradation. The gradation voltage Vx is generated or set around the reset voltage Va. The gradation voltage Vx may be set in the plus direction or in the minus direction. Moreover, you may set to +/- direction with a structure.

  Although the operational amplifier 53 is used in FIG. 1, the present invention is not limited to this. Any one having a high input impedance and a low output impedance may be used. For example, FIG. 9 shows a configuration example using an emitter follower circuit 91 formed of a transistor. An emitter follower circuit 91 is constituted by the transistor Q and the resistor R.

  The impedance when the gate of the transistor Q is viewed from the part a is high, and the output impedance of the part b is low. Therefore, the potential of the capacitor 52 can be stably held, and the source signal line 18 can be charged and discharged satisfactorily by the voltage applied via the switch SW5. A gradation voltage can be applied.

  In FIG. 1, the constant current output circuit 10 is arranged or formed in the source driver IC (circuit) 14 corresponding to each source signal line 18, but the present invention is not limited to this. For example, as shown in FIG. 38, a constant current (reset current Ia) generated by one current generation circuit 413 is switched to a plurality of current holding circuits 501 (FIG. 49, FIG. The configuration applied to the description is exemplified. The current holding circuit 501 is connected or arranged to each source signal line 18.

  The current holding circuit 501 applies a reset current Ia to the pixel 16. The current holding circuit 501 has a function of applying the reset current Ia to the pixel 16 and acquiring the reset voltage Va of the driving transistor 11 a of the pixel 16. The reset voltage Va applied to each source signal line 18 or the reset voltage Va acquired or held by each current holding circuit 501 is read out under the control of the switch circuit 381. A target gradation voltage Vc is obtained from the read reset voltage Va and applied to each pixel 16.

  Note that the magnitude of the reset current Ia output from the constant current output circuit 10 or the current generation circuit 413 may be amplified by the current holding circuit 501 or the like. Amplification can be easily realized by an operational amplifier, a differential amplifier circuit, and the like. Amplification means a case where the number is 1 or more, but a case where the number is 1 or less is also included in the present specification.

  The current holding circuit 501 is formed on the array substrate 382 using polysilicon technology such as low-temperature polysilicon. The current generation circuit 413 may also be formed on the array substrate 382. However, when current accuracy is desired, it is preferably formed in the source driver circuit 14 formed of a semiconductor chip.

  The output current (reset current Ia) of the constant current output circuit 10 or the current generation circuit 413 is switched by the switch circuit 381 and applied to the current holding circuit 501 formed or configured in each source signal line 18 or each output terminal 21. Also good. As illustrated in FIG. 50 and the like, the current holding circuit 501 includes a current mirror circuit or a current copier circuit.

  The reset current Ia output from the constant current output circuit 10 or the current generation circuit 413 is not limited to a constant reset current Ia. It may be capable of outputting a plurality of types of gradations, such as 64 gradations or 256 gradations, and currents of different sizes. The reset current Ia may be configured so that its value can be changed for each of the horizontal synchronizing signal (HD) and the vertical synchronizing signal (VD). Further, the value may be changed for each pixel in synchronization with the dot clock. Further, the reset current Ia may be changed in correlation with the panel temperature by using a panel temperature detection circuit as shown in FIG.

  The gradation voltage Vx may be replaced with a gradation number. For example, assume that the reset voltage Va is the 128th gradation of 256 gradations, and Vx = Vc−Va corresponds to a voltage for 64 gradations. When the voltage gradation circuit 20 outputs Vx, Vc becomes 128 + 64 = 192 gradations. If Vx acts in the-direction and Va-Vx corresponds to a voltage corresponding to 64 gradations, the voltage gradation circuit 20 outputs Vx, so that Vb becomes 128-64 = 64 gradations. In FIG. 7, the current corresponding to Vb is Ib. Of course, the gradation voltage Vx may be of any unit and size as long as it is a voltage.

  The current that flows through the EL element 15 with the above gradation voltage Vx is shown in FIG. The solid line in FIG. 7 indicates the VI characteristic of the driving transistor 11a of the pixel 16. In FIG. 7, it is assumed that the current Ia flows through the EL element 15 at the reset voltage Va. That is, ideally, when the reset voltage Va is applied to the gate terminal of the driving transistor 11 a, the reset current Ia flows through the EL element 15. Actually, a current different from the reset current Ia flows through the EL element 15 due to the influence of a punch-through voltage generated between the gate terminal of the driving transistor 11a and the gate signal line 17a. It goes without saying that the present invention can also be applied in this case. In this specification, an ideal state is illustrated and described. Further, the reset voltage Va differs depending on the characteristics of each driving transistor.

  The gradation voltage Vx is a voltage corresponding to each gradation. The gradation voltage is changed on the + side (+ Vx) and the − side (−Vx) around the reset voltage Va. For example, when changed to the + side, the current applied to the EL element 15 is Ic, and when changed to the-side, the current flowing through the EL element 15 is Ib. That is, the voltage gradation circuit 20 adds or subtracts the voltage on the + side or the − side with the reset voltage Va as a reference, and holds it in the a part. Of course, the gradation voltage Vx may be set only in the plus direction (addition) with the reset voltage Va as a reference. Further, the gradation voltage Vx may be set only in the minus direction (subtraction) with the reset voltage Va as a reference. The addition / subtraction is not limited to the addition / subtraction of the analog voltage, and may be realized by adding / subtracting digital data.

  The voltage gradation circuit 20 is not limited to being formed with a semiconductor IC chip. The array substrate 382 may be formed using polysilicon technology. In that case, it is composed of a dot sequential circuit and a line sequential circuit. Alternatively, a sample hold circuit or the like may be used as shown in FIG.

  Needless to say, the voltage output from the voltage gradation circuit 20 may be zero. In this case, the output current of the constant current output circuit 10 is set to 0 (the constant current output circuit 10 is unnecessary). Therefore, according to the present invention, the constant current output circuit 10 can be omitted.

  Alternatively, the reset voltage Va of the driving transistor of each pixel may be measured in advance, and the gradation voltage Vx applied to each pixel may be corrected using the measured reset voltage Va.

  In this case, when the reset voltage Va is measured, only the reset current Ia output from the constant current output circuit 10 or the like is necessary, and the constant current output circuit 10 is unnecessary in the image display state. Therefore, the reset current Ia may be supplied from a circuit separately provided outside the source driver IC 14.

  The reset voltage Va can be indirectly measured optically. This is because if the EL display device is voltage-driven, the characteristic variation of each driving transistor is optically displayed as unevenness. By measuring the optically displayed unevenness, the reset voltage Va of the driving transistor of each pixel or a voltage similar thereto can be easily obtained. Further, the target gradation voltage Vc and the gradation voltage Vx can be corrected.

  An on-voltage is applied to the gate signal line 17a of the corresponding selected pixel 16. By applying an ON voltage to the gate signal line 17a, the driving transistor 11a changes the gate terminal potential so that the current flowing through the EL element 15 becomes zero. A voltage Va at which the current flowing through the EL element 15 becomes 0 is held in the a part of the operational amplifier 53. The voltage gradation circuit 20 outputs a + side voltage, and the + side voltage and the voltage held in the a part are added and output to the b part of the operational amplifier 53 (see FIG. 11).

  As shown in FIG. 11, the current that flows from the constant current output circuit 10 to the source signal line 18 is set to 0, and the source signal line 18 that has been operated so that the current that the driving transistor 11 a flows to the EL element 15 becomes 0 is used. The potential V0 is measured. V0 is a voltage after the reset operation. Even if the reset voltage Va = V0 is applied to the gate terminal of the driving transistor 11a, no current flows through the EL element 15. When the gradation voltage Vx is applied with the reset voltage V0 as a reference, the current Ie flows through the EL element 15.

  The second operation shown in FIGS. 4C and 17B is a second operation for applying a current to the EL element 15. In the second operation in FIG. 2, the driving transistor 11a applies the current Ie to the EL element 15 based on the voltage applied to the gate terminal of the driving transistor 11a. The EL element 15 of each pixel 16 emits light by the applied current Ie.

  The above operation is performed by the gate driver circuit 12a sequentially selecting pixel rows. That is, a pixel row is selected in one horizontal scanning period. First, a reset current Ia is applied to the selected pixel row at the beginning of one horizontal scanning period. In a state where the reset current Ia is applied, the driving transistor 11a reads the reset voltage Va necessary for causing the reset current Ia to flow. Alternatively, the reset voltage Va is held in the a part.

  Next, the gradation voltage Vx is added to or subtracted from the reset voltage Va. The added / subtracted voltage is applied to the gate terminal of the driving transistor 11a. Thus, one horizontal scanning period is completed. In the selected pixel row, current is supplied from the driving transistor to the EL element 15 for a predetermined period after the next one horizontal scanning period, and the EL element 15 emits light.

  In the next one horizontal scanning period, the next adjacent pixel row is selected. A pixel row is selected in one horizontal scanning period, a reset current Ia is applied to the pixel row selected at the beginning of the horizontal scanning period, and Va necessary for the driving transistor 11a to flow the reset current Ia is read.

  Next, the gradation voltage is added to or subtracted from the reset voltage Va and applied to the gate terminal of the driving transistor 11a. Thus, one horizontal scanning period is completed.

  The magnitude of the reset current Ia applied to each pixel 16 may be varied, changed, or adjusted in accordance with the magnitude of the current Ie flowing through the EL element 15 of each pixel 16, the current difference to be rewritten, the lighting cycle, and the like. . Further, it may be varied, changed or adjusted in accordance with the ratio (lighting rate) of the current used in each image display to the maximum current used in the entire display area 184.

  In particular, it is preferable to increase the reset current Ia when the maximum value is 100% and the lighting rate is 25% or less. That is, the magnitude of the reset current Ia is changed (controlled) in accordance with the lighting rate.

  The amplification factor of the operational amplifier 53 may be changed in accordance with the magnitude of the current flowing through the EL element 15 of each pixel 16, the current difference to be rewritten, the lighting cycle, and the like. Further, the period during which the reset current Ia is applied may be varied.

  Further, the amplification factor of the gradation voltage Vx output from the voltage gradation circuit 20 may be changed according to the magnitude of the current flowing through the EL element 15 of each pixel 16, the current difference to be rewritten, the lighting cycle, and the like. Alternatively, the reset voltage Va and the reset voltage V0 may be corrected using a certain amount of voltage, and the corrected Va and V0 may be used as the reference voltage. Further, the switch SW2 and the like may be omitted.

  In the present invention, the reset voltage Va is obtained or acquired. However, the present invention is not limited to this. Any device similar to the reset voltage Va may be used. For example, a voltage proportional to the reset voltage Va and a voltage shifted by a certain level are exemplified. Moreover, the amplified voltage is illustrated. In addition, optically obtained voltage or digital data is exemplified.

  It is not necessary to obtain or acquire the reset voltage Va for all pixels. The reset voltage Va may be extracted from a selected pixel after thinning out at regular intervals. This is because the reset voltages Va of neighboring pixels are relatively matched. The extracted reset voltage Va is used directly as a reset voltage Va of a neighboring pixel or used after processing such as calculation.

  That is, pixel thinning is performed to obtain the reset voltage Va of the selected pixel, and the reset voltage Va of the unselected pixel is obtained using this reset voltage Va. Alternatively, the reset voltage is estimated.

  FIG. 1 may be configured as shown in FIG. FIG. 5 shows a configuration in which a DA (digital-analog) conversion circuit 51 is connected to the switch SW3. The DA conversion circuit 51 applies a voltage to the c section via the switch SW3 based on the 8-bit digital data DATA. Various voltages can be applied to the portion c without being limited to the ground (GND) potential.

  For example, the reset voltage Va read from the gate terminal of the driving transistor 11a can be applied to one electrode c portion of the capacitor 52. Therefore, initialization of the capacitor 52 can be easily performed.

  With the configuration shown in FIG. 5, the voltage applied to the portion a can be shifted by a certain voltage. A punch-through voltage is generated when the gate signal line 17a changes from the on-voltage applied state to the off-voltage applied state. The potential at the gate terminal of the driving transistor 11a is shifted by the punch-through voltage. In the configuration of FIG. 5, the potential shift can be easily corrected. Other configurations are the same as or similar to those in FIG.

  In FIG. 1, the potential of the source signal line 18 is held in an analog manner by the capacitor 52 or the like, but the present invention is not limited to this. For example, you may comprise as FIG.

  In FIG. 6, the potential of the source signal line 18 is analog-digital converted by an analog-digital (AD) conversion circuit 62. The AD converted digital data is added to the output voltage of the voltage gradation circuit 20 by the adding circuit 61. The added voltage is applied to the input a portion of the operational amplifier 53 as in FIG. Other operations and configurations are the same as or similar to those in FIG.

  The adder circuit 61 exhibits the same or similar function as the capacitor 52 and the voltage gradation circuit of FIG. Since the AD conversion circuit 62 has a function of measuring and holding a potential, it has the function of the capacitor 52 in FIG. The adder circuit 61 adds the output data of the AD conversion circuit 62 to the output data of the voltage gradation circuit 20 (may be subtracted or may be added or subtracted), and outputs the result to the a part.

  Therefore, the operation is the same as that of adding the reset voltage Va of the a portion of the capacitor 52 and the output voltage Vx of the voltage gradation circuit to shift the potential of the a portion. The adding circuit 61 may be a subtracting circuit. The addition may be either analog addition or digital addition. The concept of addition includes concepts such as level shift.

  The AD converter circuit 62 applies the measured or held voltage as digital data to the adder circuit 61, but the present invention is not limited to this. For example, the digital data of the AD conversion circuit 62 may be held in a memory circuit (not shown) configured or formed outside or inside the source driver IC (circuit) 14. This digital data is read out as needed and applied or output to the adder circuit 61.

  The potential of the source signal line 18 varies depending on the voltage or current output from the source driver IC (circuit) 14. Basically, the potential of the source signal line 18 is rewritten every horizontal scanning period. According to the present invention, the reset current Ia is applied at the beginning of one horizontal scanning period (1H) to operate the driving transistor 11a, and the gate potential of the driving transistor 11a that is in a steady state after the operation is completed is measured. . By applying the gradation voltage to the driving transistor 11a with the measured voltage as a reference, the characteristic variation of the driving transistor 11a is compensated.

  The reset current Ia is not limited to the predetermined one reset current Ia steadily within one horizontal scanning period (1H period). For example, the reset current Ia may be a large current at the start of application of the reset current Ia, and may be set to a predetermined reset current Ia after a certain period. By operating in this way, parasitic capacitance such as the source signal line 18 can be charged and discharged in a short time. That is, the reset current Ia may be changed in multiple stages in the 1H period. Further, the magnitude of the reset current Ia switched in multiple stages may be changed or changed based on the potential of the source signal line 18.

  In order to change the potential of the gate terminal of the driving transistor 11a and compensate for the specific variation of the driving transistor 11a, first, the reset signal Ia (of course, the operation of the driving transistor 11a is also added) It is necessary to charge and discharge the parasitic capacitance. The charge / discharge time depends on the potential of the source signal line 18 before one horizontal scanning period. For this reason, depending on the potential state of the source signal line 18, there may be a shortage of time for charging and discharging within a predetermined time.

  According to the present invention, in order to solve this problem, the precharge voltage Vp is applied to the source signal line 18 in the first period of one horizontal scanning period (1H). As will be described later, the precharge voltage Vp is formed in the source driver IC (circuit) 14 so that a predetermined voltage can be applied to the source signal line 18. Note that the precharge voltage Vp may be directly applied to the pixel 16. For example, a switching transistor that short-circuits the cathode voltage Vss previously formed in the pixel and the gate terminal of the driving transistor 11a is formed in the pixel, and by turning on this transistor, the cathode voltage is applied to the pixel as the precharge voltage Vp. An application method may be used.

  In FIG. 12, the precharge voltage Vp is applied in the A period of each horizontal scanning period. By applying the precharge voltage Vp, each source signal line is instantaneously charged / discharged to the potential Vp. In the present embodiment, the configuration of the pixel 16 will be described with reference to FIG. The driving transistor 11a of the pixel 16 will be described as a P-channel transistor. Note that even if the driving transistor 11a is an N-channel transistor, those skilled in the art can implement the pixel 16 by slightly changing the following description. The present invention is not limited to the channel polarity of the driving transistor 11a.

  In the case of a P-channel transistor, the current Ie of the driving transistor 11a is smaller (black display or low luminance display) when the gate terminal potential of the driving transistor 11a is closer to the Vdd voltage (anode voltage). When the gate terminal potential of the driving transistor 11a is closer to the GND voltage (ground voltage or cathode voltage), the current Ie of the driving transistor 11a increases (white display or high luminance display).

  The precharge voltage Vp is set near the voltage corresponding to the maximum gradation (white display or high luminance display). The precharge voltage Vp may be a predetermined fixed voltage, but is preferably configured to be variable or adjustable according to the reset voltage Va or the reset voltage V0.

  In FIG. 12, 1H to 3H (1st to 3rd horizontal scanning periods) are each one horizontal scanning period (1H). The first to third H (first to third horizontal scanning periods) are the order in which the pixel rows are selected. Assuming that the pixel row is the nth pixel row, one field (frame) period is composed of an n horizontal scanning period (pixel row) and a blanking period. The precharge voltage Vp is applied in the first A period of each horizontal scanning period.

  Therefore, no matter what the potential of the source signal line 18 before 1H is, it becomes the precharge voltage Vp instantaneously. The reset current Ia is output from the constant current output circuit 10 in the B period after the A period of 1H. The reset current Ia may also be applied during the A period. The reset current Ia flows from the driving transistor 11 a of the pixel 16 into the constant current output circuit 10 via the source signal line 18.

  Due to the reset current Ia, the gate terminal of the driving transistor 11a of the pixel 16 becomes the reset voltage Va. It goes without saying that the reset voltage Va differs depending on the characteristic variation of the driving transistor 11a of each pixel 16. However, the difference between the minimum and maximum reset voltage Va is about 0.5V. The potential difference between the reset voltage Va and the Vp voltage is substantially constant. Regardless of the potential of the source signal line 1H before 1H, the precharge voltage Vp changes to Va when the reset current Ia is applied due to the application of the precharge voltage Vp. Therefore, the convergence time is substantially constant.

  In the C period following the B period, the target gradation voltage Vc as a video signal is applied. Therefore, the target gradation voltage Vc = Va + Vx is applied to the source signal line 18 with the reset voltage Va as a reference. In FIG. 12, the target gradation voltage is V1 in the first H period, the target gradation voltage is V2 in the second H period, and the target gradation voltage is V3 in the third H period. Thereafter, the selection position of the pixel row is shifted to the nth H, and the same operation as described above is performed. As described above, by applying the precharge voltage Vp, the reset current Ia can be easily applied to the driving transistor 11a of the pixel 16, and the convergence time can be shortened. The precharge voltage Vp may be generated by a circuit on the array substrate, or may be generated by a circuit formed in the source driver IC 14.

  FIG. 12 shows an embodiment in which the precharge voltage Vp is constant, but the present invention is not limited to this. For example, the precharge voltage Vp may be changed as shown in FIG.

  In FIG. 13, the first H is the precharge voltage Vp1, the second H is the precharge voltage Vp2, and the third H is an example of the precharge voltage Vp3. Thereafter, the selection position of the pixel row is shifted to the nth H, and the same operation as described above is performed. The precharge voltage Vp is preferably changed in correlation with the gradation voltage or the target gradation voltage Vc. For example, the precharge voltage Vp is set such that the potential difference between the target gradation voltage Vc = Va + Vx and the precharge voltage Vp falls within a predetermined voltage range.

  FIG. 12 shows an embodiment in which the precharge voltage Vp is constant, but the present invention is not limited to this. For example, the reset voltage Va may be changed as shown in FIG. In FIG. 14, the reset voltage is Va1 in the first H period. In the second H period, the reset voltage is Va2, and in the third H, the reset voltage is Va3. Thereafter, the selection position of the pixel row is shifted to the nth H, and the same operation as described above is performed. In the embodiment of FIG. 14, the reset voltage Va is obtained by correcting the reset voltage Va of the driving transistor 11a of each pixel 16.

  In order to change the reset current Ia in gradation or in multiple stages, it is necessary to transmit current data to the source driver IC (circuit) 14. Further, in order to change the gradation voltage Vx for each pixel, it is necessary to transmit voltage data to the source driver IC (circuit) 14. FIG. 15 shows an example. 8-bit reset current data ID (7: 0) and 8-bit gradation voltage data VD (7: 0) are transmitted as a set alternately. The reset current data ID (7: 0) is data for generating the reset current Ia output from the constant current output circuit 10. The voltage data VD (7: 0) is for generating the gradation voltage Vx output from the voltage gradation circuit 20.

  In the above embodiment, the potential of the source signal line 18 is initialized by applying the precharge voltage Vp. After initialization, a reset current Ia is applied to the source signal line 18. The precharge voltage Vp may be applied directly to the pixel 16.

  In the present embodiment, description will be made assuming that the reset current Ia is applied to the transistor and the gate terminal voltage of the driving transistor 11a is measured or held directly or indirectly. However, the present invention is not limited to this. The meaning of the reset current Ia includes the case where the current value is 0 (the reset current Ia does not flow). Further, the measurement of the voltage by applying the reset current Ia is not limited to the measurement of the magnitude of the voltage, but may be the measurement of the change amount of the voltage before and after, the change rate of the voltage, and the difference value of the voltage.

  The voltage measurement includes an operation or configuration in which the measured voltage is converted from analog to digital (AD conversion) and held outside or inside the driver circuit. In addition, an operation of holding the voltage in the memory as digital data is included. Further, not only the measurement but also an operation or configuration for temporarily holding or latching or storing in a holding medium such as a capacitor is included.

  In the embodiment of FIG. 1 and the like, the gate driver circuit 12a sequentially selects one pixel row and applies the reset current Ia to the pixels in each pixel row. However, the present invention is not limited to this. For example, a plurality of pixel rows may be selected and the reset current Ia may be applied as illustrated in FIGS. Further, the reset voltage Va or the reset voltage V0 (see FIG. 11) may be measured simultaneously or in common for a plurality of pixels. This is because the reset voltage Va and the reset voltage V0 are approximated in adjacent pixel rows.

  The embodiment of FIG. 16A has a configuration in which two adjacent pixel rows are simultaneously selected and the reset current Ia is applied from the constant current output circuit 10 in the two pixel rows. When two pixels 16 are selected at the same time, the reset current Ia is doubled as compared with the case of one pixel. When three pixels 16 are selected at the same time, the reset current Ia is set to three times that in the case of one pixel. The reset current Ia does not need to be an integral multiple, and may be any magnitude as long as it is a real multiple. Further, even when a plurality of pixels 16 are selected, the size may be the same as the reset current Ia for selecting one pixel 16.

  The currents output from the driving transistors 11a of the selected two pixel rows are different because the characteristics of the driving transistors 11a are different. However, the difference is slight between adjacent pixel rows. The selection of the pixel rows may be performed by sequentially selecting the first and second pixel rows, the third and fourth pixel rows, the fifth and sixth pixel rows,... The second pixel row, the second and third pixel rows, the third and fourth pixel rows,...

  FIG. 16B shows an embodiment in which a pixel row at a position separated by one pixel row is selected instead of adjacent pixel rows. For example, the first and third pixel rows are selected, then the second and fourth pixel rows are selected, and then the third and fifth pixel rows are selected.

  Also in FIGS. 16A to 16B, other configurations and operations are the same as those in the embodiment described with reference to FIG. As described above, simultaneously selecting a plurality of pixel rows and measuring the reset voltage Va or the like can shorten the operation time of the constant current output circuit 10. Further, the configuration of the constant current output circuit 10 and the like can be simplified.

  The embodiment of FIGS. 16A to 16B is a driving system that simultaneously selects two pixel rows. The present invention is not limited to two pixel rows. Three or more pixels may be selected at the same time. In addition, the selection of the pixel row is not limited to selecting the pixel row by sequentially scanning, and the pixel row may be selected at random. The odd field (frame) may be sequentially selected from the top to the bottom of the screen, and the even field (frame) may be sequentially selected from the bottom to the top of the screen.

  A plurality of pixel rows may be sequentially selected in the 1H period, the reset current Ia may be applied to each pixel row, and the reset voltage Va may be measured. For example, in the first ½H period of 1H, the first pixel row is selected and the reset current Ia is applied, and the second second pixel row is selected in the second ½H period. A method is illustrated.

  The measurement of the reset voltage Va (see FIG. 7) and the reset voltage V0 (see FIG. 11) is performed by sequentially selecting and performing pixel rows. However, the present invention is not limited to this. For example, the pixel rows in the display area may be sequentially selected and scanned during the blanking time of the video signal, and the reset voltages Va and V0 may be measured and stored in the memory. In addition, a plurality of pixel rows are selected simultaneously or sequentially, the reset voltages Va and V0 are measured and held for a certain period, the held reset voltages Va and V0 are sequentially read out, and added to or subtracted from the gradation voltage Vx to obtain a target level. A regulated voltage may be obtained or generated and sequentially applied to each source signal line 18.

  Similar to FIG. 1, FIG. 8 is implemented by the gate driver circuit 12 sequentially selecting pixel columns. That is, a pixel row is selected in one horizontal scanning period. First, the switch SW3 is closed and the switches SW4, SW2, and SW5 are opened. When the switch SW3 is closed, the ground (GND) voltage is applied to one terminal c of the capacitor 52, and the ground voltage is maintained. Further, as described with reference to FIG. 5, an arbitrary predetermined voltage may be applied.

  After a ground voltage is applied to the c portion of the capacitor 52 for resetting, the switches SW2 and SW3 are closed and the switches SW4 and SW5 are opened as shown in FIG. In the a part of the capacitor 52, a voltage at which the driving transistor 11a does not flow current to the EL element 15 (= gate terminal voltage of the driving transistor 11a) is held. The corresponding pixel row is also selected during this period. The gate terminal potential of the driving transistor 11a of each pixel 16 in the pixel row is maintained in an offset state (a state in which no current flows through the EL element 15 even when the transistor 11d is closed).

  With the operation of FIG. 10A, the reset voltage V0 necessary for the driving transistor 11a to be offset is read (held). Accordingly, as shown in FIG. 11, when the reset voltage V0 is applied to the gate terminal of the driving transistor 11a as it is, the driving transistor 11a enters a cut-off state (a state in which the current flowing through the EL element 15 becomes 0).

  Next, as shown in FIG. 10B, the switches SW4 and SW5 are closed, and the switches SW2 and SW3 are opened. The voltage gradation circuit 20 outputs a gradation voltage Vx. The target gradation voltage Vc = V0 + Vx. The corresponding pixel row is also selected during this period.

  The voltage Vx output to the voltage gradation circuit 20 shifts the potential of the a part of the capacitor 52. The reset voltage V0 and the gradation voltage Vx are added by the potential shift of the part a. Thus, one horizontal scanning period is completed. In the selected pixel row, a current is applied to the EL element 15 in the next one horizontal scanning period, and the EL element 15 emits light.

  The above embodiments of the present invention have been described focusing on the measurement of the reset voltages Va and V0 and the addition and subtraction of the gradation voltage Vx to these voltages and applying them to the driving transistor 11a of the pixel 16. The following description will focus on image display of the EL display device of the present invention.

  In the present invention, the potential (indicated by f in FIG. 2) of the gate terminal of the driving transistor 11a is measured (the potential is acquired) while the program current (reset current) Ia is supplied. Alternatively, the potential is held in the capacitor 52 in FIG. Alternatively, data corresponding to the potential is held in a storage unit such as a memory.

  In FIG. 2, the potential f of the gate terminal is the same as the potential of the source signal line 18 (indicated by d) because the transistors 11b and 11c are on. Therefore, when the potential of the source signal line 18 is measured via the terminal 93 of the source driver circuit 14, the potential f of the gate terminal of the transistor 11a is measured.

  The second operation is an operation state in which the transistor 11b and the transistor 11c are closed and the transistor 11d is opened, and an equivalent circuit at that time is shown in FIG. The voltage between the source and gate of the transistor 11a remains held. In this case, since the transistor 11a always operates in the saturation region, the current Ie = Ia is constant. Note that Ie is a current that the driving transistor 11a passes through the EL element 15, and Ie = Ia is an ideal state where the pixel 16 is not affected by the penetration voltage. In the description of the present specification, the implementation under the above ideal state will be described. If the technical idea of the present invention is implemented even in a state other than the ideal state, it is a technical category of the present invention and is an implementation of the present invention.

  The above operation is illustrated on the display screen 184 as shown in FIGS. In FIG. 18A, reference numeral 181 denotes a pixel (row) (write pixel row) that is current-programmed at a certain time on the display screen 184. Alternatively, the pixel row (pixel) is measuring the reset voltage Va and the reset voltage V0. Further, the pixel row (pixel) in which the target gradation voltage Vc is written. The pixel (row) 181 is not lit (non-display pixel (row)). In order to turn off the light, the gate driver circuit 12b may be controlled to open the transistor 11d of the pixel 16.

  Non-lighting (non-display) refers to a state in which no current flows through the EL element 15. Alternatively, it means a state where a small current within a certain level is flowing (display is dark). That is, it is a dark display state. Therefore, the non-illuminated pixel row means a state in which no current flows through the EL elements 15 in the pixel row or a relatively dark display state. A non-display (non-lighting) range of the display area 184 is referred to as a non-display area 182. A display (lighting) range of the display area 184 is referred to as a display (lighting) area 183. The switching transistor 11 d of the pixel 16 in the display region 183 is closed, and a current flows through the EL element 15. However, it is natural that no current flows through the EL element 15 in the black image display. A region where the switching transistor 11d is open is a non-display region 182.

  In the case of the pixel configuration of FIG. 2, as shown in FIG. 17A, a program current (reset current) Ia flows through the source signal line 18 in the first period of 1H (Va or V0 measurement period). The voltage is set (programmed) in the capacitor 19 so that the program current Ia flows through the driving transistor 11a and the current through which the program current Ia flows is held. Alternatively, the voltage is held in the capacitor 19 so that a current for flowing the program current Ia flows to the gate terminal of the driving transistor 11a. At this time, the transistor 11d is in an open state (off state).

  During a period in which current flows through the EL element 15, the transistors 11c and 11b are turned off and the transistor 11d is operated as shown in FIG. That is, the off voltage (Vgh) is applied to the gate signal line 17a, and the transistors 11b and 11c are turned off. On the other hand, an on voltage (Vgl) is applied to the gate signal line 17b, and the transistor 11d is turned on.

  FIGS. 19A to 19C show timing charts of the driving method described in FIGS. 17A to 17B and FIGS. 18A to 18B. 19A to 19C, in the selected pixel row, when the ON voltage (Vgl) is applied to the gate signal line 17a (see FIG. 19A), the gate signal line 17b. An off voltage (Vgh) is applied to (see FIG. 19B). During this period, no current flows through the EL elements 15 in the selected pixel row (non-lighting state). The selection period is one horizontal scanning period (1H).

  Among the pixel rows in which the on-voltage is not applied (not selected) to the gate signal line 17a, the on-voltage (Vgl) is applied to the gate signal line 17b in the lit pixel row. Current flows through the EL elements 15 in this pixel row, and the EL elements 15 emit light.

  Of the pixel rows in which the on-voltage is not applied (not selected) to the gate signal line 17a, the off-voltage (Vgh) is applied to the gate signal line 17b in the non-lighted pixel row. No current flows through the EL elements 15 in this pixel row, and the EL elements 15 are in a non-light emitting state.

  When measuring or acquiring the reset voltage Va, the source signal line 18 is charged / discharged at high speed, or when black insertion (non-display area insertion) is performed in the image display to improve video visibility, the reset is performed. The magnitude of the current Ia is increased N times. By increasing the magnitude of the reset current Ia by N times, the current flowing through the EL element 15 is also increased N times. When the gradation voltage Vx is set to 1 as in the conventional case, the effect that the source signal line 18 can be charged and discharged at high speed by the write effect of the N times reset current Ia is exhibited. In this case, since the reference reset voltage Va is already a voltage that becomes an EL current that is N times, the gradation voltage Vx to be added or subtracted must also be set in consideration of this point. The same applies to the target gradation voltage Vc.

  Note that at least one of the reset voltage Va, the target gradation voltage Vc, the gradation voltage Vx, and the reset current Ia is preferably in a relationship that is proportional or correlated to N times N. Moreover, it is preferable to implement this invention in combination with Examples, such as FIG. 18 (A)-(B), FIG. 21 (A)-(B), FIG. 22 (A)-(B).

  Hereinafter, for ease of explanation, the reset current Ia when measuring the reset voltage Va is also set to N times, and Vx added to Va and V0 also causes the driving transistor 11a to flow N times the current to the EL element 15. Is set to. In addition, the brightness of the screen 184 displayed by the EL display device when the current is 1 times is B, and the brightness of the light emitting unit is displayed with a brightness of B × N when the current is N times.

  The reset current Ia passed through the EL element 15 is N times the current required to obtain the average (predetermined) brightness B of the screen 184. Therefore, the EL element 15 is lit at a luminance (N · B) N times the average (predetermined) luminance B. The lighting period is 1 F / N. 1F is one field (frame). That is, for ease of explanation, it is assumed that there is no blanking period in one field (frame). Practically, since there is a blanking period, it is not exactly N · B. That is, the EL element 15 emits light with N times the luminance (N · B) for a period of 1 / N of 1F. Therefore, the display luminance of the display panel that averages 1F is (N · B) × (1 / N) = B (predetermined luminance).

  N may be any real value as long as it is greater than one. However, if N is too large, the instantaneous current flowing through the EL element 15 is large, and therefore N is preferably 10 or less. Of course, it is needless to say that N = 1 and the display (lighting) region 183 other than the writing pixel row 181 may be used. In this case, the current Ia flowing through the EL element 15 is a current necessary for obtaining the average (predetermined) luminance B of the screen 184. Therefore, the EL element 15 is lit (emitted) with a predetermined luminance B. Further, N may be smaller than 1 in order to realize low luminance display.

  Further, one of the reasons for flowing the N times reset current Ia so that the light emission luminance is N · B is to reduce the influence of the parasitic capacitance of the source signal line 18. By flowing a large current, the charge of the parasitic capacitance can be charged and discharged in a short period.

  A voltage used in the EL display panel of the present invention will be described with reference to FIG. The gate driver circuit 12 includes a buffer circuit 202 and a shift register circuit 201. The buffer circuit 202 uses an off voltage (Vgh) and an on voltage (Vgl) as voltages. On the other hand, the shift register circuit 201 uses a voltage VGDD and a grant (GND) voltage of the shift register, and also uses a VREF voltage for generating an inverted signal of the input signals (CLK, UD, ST). The source driver circuit (IC) 14 uses a voltage Vs and a ground (GND) voltage. By operating the gate driver circuit 12, a pixel row to which the reset current Ia is applied is designated.

  The gate driver circuit 12a includes a shift register circuit 201a and a buffer circuit 202. Therefore, the gate driver circuit 12a controls on / off of the gate signal line 17a. For ease of explanation, the pixel configuration will be described using FIG. 1 as an example.

  18A to 18B show a method in which the display area 183 is one. However, the present invention is not limited to this. For example, as shown in FIGS. 22A to 22B, the display area 183 and the non-display area 182 may be dispersed in a plurality.

  As illustrated in FIGS. 22A to 22B, the intermittent interval (non-display area 182 / display area 183) is not limited to an equal interval. For example, it may be random (as a whole, the display period or the non-display period may be a predetermined value (a constant ratio)). Also, it may be different for RGB. That is, it is only necessary to adjust (set) the R, G, B display period or the non-display period to a predetermined value (a constant ratio) so that the white balance is optimal.

  The non-display area 182 is a pixel 16 area of the non-lighting EL element 15 at a certain time. The display area 183 is an area where the EL element 15 is lit at a certain time. However, the EL element 15 is not lit when the video signal is black. However, even in this case, since it is operating to light the black display, it is a lighting region. The positions of the non-display area 182 and the display area 183 are shifted by one pixel row in synchronization with the horizontal synchronization signal.

  In the embodiment of FIG. 11, the voltage V0 is obtained, and the gradation voltage Vx is added on the basis of the voltage V0 to generate the target gradation voltage Vc. 4A to 4C are systems in which the reset voltage Va is obtained and the target gradation voltage Vc is generated by adding or subtracting the gradation voltage Vx with reference to this voltage. The present invention is not limited to this. For example, when the reset voltage Va is obtained, the reset current Ia to be applied may be a current corresponding to the maximum gradation Iam.

  By applying the reset current Iam corresponding to the maximum gradation to the driving transistor 11a, the reset voltage Vam is generated at the gate terminal of the driving transistor 11a so that the current of the maximum gradation flows. Using this Vam as a reference, the target gradation voltage Vc is generated by subtracting the gradation voltage Vx. The generated voltage Vcm is applied to the gate terminal of the driving transistor 11a.

  The present invention mainly relates to an EL display device having a current-driven pixel configuration. The present invention also relates to an EL display device having a pixel configuration in which the drain terminal or the source terminal of the driving transistor 11a or the transistor 11b that is current mirror-coupled to the driving transistor 11a is connected to the source signal line 18 in a DC manner. . The present invention also relates to an EL display panel having a configuration in which a current flowing through the driving transistor 11a (FIGS. 2, 23, etc.) can be taken out from the source signal line 18 or obtained from the source signal line 18.

  In the driving method of the present invention, the gate terminal potential of the driving transistor 11 is applied after the reset current Ia is applied to the driving transistor 11 or the reset current Ia is supplied from the driving transistor 11 to reach a substantially steady state. Measure (acquire).

  Further, the driving method of the present invention generates a target gradation voltage Vc by performing processing such as addition and subtraction on the voltage corresponding to the gradation voltage using the measured (acquired) potential as a reference (origin or relative position). Let The generated target gradation voltage is applied to the gate terminal of the driving transistor 11 or the like. Further, the driving transistor 11 allows a current corresponding to the target gradation voltage to flow through the EL element 15. Note that flowing current to the EL element 15 includes both cases where a current is supplied to the EL element 15 and a case where the current flows from the EL element 15 into the driving transistor 11.

  Further, the above embodiment is an embodiment in which the current Ie is supplied to the driving transistor 11 with the reset voltage Va, V0, or Vam as a reference. However, the present invention is not limited to this. For example, as described in FIGS. 18A to 18B, FIGS. 21A to 21B, FIGS. 22A to 22B, etc. It goes without saying that the reset current Ia may be set to N times (N is a real number) in the driving method in which a current is passed and no current is passed during another period (1F (N−1) / N). That is, the reset voltage Va corresponding to N times the constant current (reset current Ia) is obtained, and the target gradation voltage Vc is generated based on the reset voltage Va.

  In the driving method of the present invention, intermittent display can be performed for each of red (R), green (G), and blue (B) as shown in FIGS. In FIG. 21A, the areas of the lighting regions 183 are different for R, G, and B. In FIG. 21B, although the areas of the lighting regions 183 are the same for R, G, and B, the total of the areas of the lighting regions is made different by using a plurality of B lighting regions. The white balance of the image display can be adjusted by changing, or changing or adjusting the areas of the R, G, and B lighting regions 183.

  In the above-described embodiment, the area of the lighting region 183 is made different, but conversely, it may be considered that the area of the non-lighting region 182 is made different.

  In the display of FIGS. 18A to 18B, one display area 183 or non-display area 182 moves downward from the top of the screen in a band shape. When the frame rate is low, it is visually recognized that the display area 183 moves. In particular, it becomes easier to recognize when the eyelid is closed or when the face is moved up and down.

  To deal with this problem, the display area 183 may be divided into a plurality of parts as shown in FIGS. If the divided sum is an area of S (N-1) / N, the brightness is equivalent to that shown in FIGS. Note that the divided display areas 183 do not need to be equal (equally divided). Further, the divided non-display areas 182 need not be equal (for the time being).

  The pixel configuration of the present invention will be described by exemplifying the configuration of FIG. 2, but is not limited thereto. For example, other pixel configurations such as FIG. 23 may be used.

  In the pixel configuration of FIG. 23, the transistors 11c and 11d are turned on (closed) during programming. The source driver IC (circuit) 14 outputs a program current (reset current) Ia. A program current (reset current Ia) Ia flows through the transistor 11a constituting the current mirror circuit with the driving transistor 11b, and a voltage corresponding to the program current is held in the capacitor 19. The transistor 11e is turned on / off (closed / opened) by a control signal (on / off signal) applied to the gate signal line 17b, and FIGS. 18 (A) to 18 (B), FIGS. 21 (A) to (B), and FIG. The intermittent control described in (A) to (B) and the like is realized.

  The embodiment of FIG. 23 is not an embodiment in which a program current (reset current) Ia is supplied to the transistor 11b that applies the current Ie to the EL element 15. The embodiment of FIG. 2 is an embodiment in which a program current (reset current) Ia is supplied to the transistor 11a that applies the current Ie to the EL element 15. The technical idea of the present invention is to compensate the characteristics of the driving transistor 11b, in which the reset current Ia or the like is supplied from the source driver IC (circuit) 14 or the like and one current is supplied to the EL element 15 directly or indirectly. The point is to do. Therefore, the configuration of FIG. 23 is also a technical category of the present invention. Note that the transistor 11e may be omitted in the configuration of FIG. This is because the reset current Ia is not divided and does not flow to the EL element 15 at the time of Va measurement or the like.

  In the pixel configuration in FIG. 2 and the like, the current flowing through the EL element 15 by the transistor 11d is controlled by the transistor 11d, but the present invention is not limited to this. For example, as shown in FIG. 26, the current applied to the EL element 15 can be on / off controlled without the transistor 11d.

  In FIG. 26, the gate driver circuit 12b controls the gate signal line 17b, and the potential of the gate signal line 17b is driven by the Vdd voltage and the voltage Vg at which no current flows through the EL element 15 which is a lower voltage. . That is, the Vdd voltage and the Vg voltage are output to the gate signal line 17b. When the Vdd voltage is applied to the gate signal line 17b, current flows through the EL element 15, and when the Vg voltage is applied to the gate signal line 17b, no current flows through the EL element 15. 26 is the same as FIG. 2 in that the reset current Ia is applied to the driving transistor 11a. Therefore, a configuration without the gate driver 12b as shown in FIG. 26 is also a technical category of the present invention.

  As a modification of FIG. 2, the pixel configuration of FIG. 27 is also exemplified. The difference between FIG. 2 and FIG. 27 is that the transistor 11b is separated into transistors 11b1 and 11b2, and the gate signal line 17a is separated into gate signal lines 17a1 and 17a2.

  The transistor 11b1 is controlled by the gate signal line 17a1 together with the transistor 11c. The transistor 11b2 is controlled by the gate signal line 17a2. When the program current (reset current) Ia is applied, the reset voltage Va or the reset voltage V0 is measured, and the gradation voltage Vc is applied to the selected pixel 16, the transistors 11b1, 11b2, and 11c are in the closed state.

  When the pixel selection period is completed (1H period), first, an off voltage is applied to the gate signal line 17a2, and the transistor 11b2 is opened. Next, in a period from 0.5 μsec to 5 μsec, a turn-off voltage is applied to the gate signal line 17a1, and the transistors 11b1 and 11c are turned off. Note that the pixel row selection period (1H period) is the period until the off-voltage is applied to the gate signal line 17a1 or the transistor 11b1 is in the open state.

  Since the transistor 11b2 is in an open (off) state before the transistor 11b1, the influence of the punch-through voltage generated when the on-voltage applied to the gate signal line 17a1 changes to the off-voltage can be reduced. This is because the transistor 11b2 is already in the off (open) state when the off voltage is applied to the gate signal line 17a1. Therefore, the influence of the punch-through voltage does not reach the gate terminal of the transistor 11a.

  In the pixel configuration described with reference to FIG. 2 and the like, the driving transistor 11 a has one configuration for each pixel 16. However, in the present invention, the driving transistor 11a is not limited to one. For example, the pixel configuration of FIG. 24 is illustrated.

  In FIG. 24, the number of transistors constituting the pixel 16 is six, and the program transistor 11an is configured to be connected to the source signal line 18 via the two transistors 11b2 and 11c. 11a1 is an embodiment configured to be connected to the source signal line 18 via two transistors 11b1 and 11c.

  In FIG. 24, the gate terminal of the driving transistor 11a1 and the gate terminal of the programming transistor 11an are made common. The transistor 11b1 operates so as to short-circuit the drain terminal and the gate terminal of the driving transistor 11a1 during current programming. The transistor 11b2 operates so as to short-circuit the drain terminal and the gate terminal of the programming transistor 11an during current programming.

  In FIG. 24, the driving transistor 11a1 and the transistor 11an are illustrated as one each, but the present invention is not limited to this. For example, two or more driving transistors 11a1 may be formed. Two or more transistors 11an may be formed. Needless to say, a plurality of transistors 11a1 and 11an may be formed.

  The transistor 11c is connected to the gate terminal of the driving transistor 11a1, and the transistor 11d is formed or arranged between the driving transistor 11a1 and the EL element 15, and controls the current flowing through the EL element 15. An additional capacitor 19 is formed or arranged between the gate terminal and the anode (Vdd) terminal of the driving transistor 11a1, and the source terminals of the driving transistor 11a1 and the programming transistor 11an are connected to the anode (Vdd) terminal. ing.

  As described above, by configuring the driving transistor 11a1 and the programming transistor 11an to pass through the same number of transistors, the accuracy can be improved. That is, the current flowing through the driving transistor 11a1 flows to the source signal line 18 through the transistors 11b1 and 11c. The current flowing through the programming transistor 11an flows to the source signal line 18 through the transistor 11b2 and the transistor 11c. Therefore, the current of the driving transistor 11a1 and the current of the programming transistor 11an pass through the same number of two transistors and flow to the source signal line 18.

  25A to 25B are explanatory diagrams of the operation of the pixel configuration of FIG. FIG. 25A is a transmission circuit diagram in a current program state or a measurement state of Va. FIG. 25B shows a state in which current is supplied to the EL element 15. Needless to say, intermittent display may be performed by turning on and off the transistor 11d (closed open) in the state of FIG.

  In FIG. 25A, an on-voltage is applied to the gate signal line 17a, and the transistors 11b1, 11b2, and 11c are turned on. The transistor 11a1 supplies the current Ie, the transistor 11an supplies the current Ia-Ie, and the combined reset current Ia becomes the program current (reset current Ia) Ia to the source driver Ic. Accordingly, the source driver IC (circuit) 14 supplies the reset current Ia to the pixel 16.

  With the above operation, the reset voltage Va corresponding to the program current Ia is held in the capacitor 52. During this period, the transistor 11d is kept off (the off voltage is applied to the gate signal line 17b). Thereafter, the target gradation voltage Vc corresponding to the display gradation is written into the pixel 16.

  The case where a current is supplied to the EL element 15 is set to the operation state shown in FIG. An off voltage is applied to the gate signal line 17a, and an on voltage is applied to the gate signal line 17b. In this state, the transistors 11b1, 11b2, and 11c are turned off, and the transistor 11d is turned on. An Ie current is supplied to the EL element 15.

  As described above, the present invention can be applied to a wide variety of pixel configurations such as FIG. 2, FIG. 23, FIG. 24, FIG.

  2, 5, and 6, 10 is a constant current output circuit. Hereinafter, the source driver IC (circuit) 14 will be described focusing on the configuration and operation of the constant current output circuit 10.

  The constant current output circuit 10 is configured as a set of unit transistors 284 as illustrated in FIG. The unit current is the magnitude of one unit of program current output from the unit transistor corresponding to the magnitude of the reference current. The unit transistor is a transistor or a current source that outputs a program current of one unit or a minimum unit. That is, unit transistor = unit current source. A configuration or a part in which a plurality of unit transistors are aggregated to output a program current or a reset current Ia is referred to as a unit transistor group.

  The magnitude of the unit current can be varied by adjusting the magnitude or strength of the reference current Ic output from the reference current circuit. The adjustment of the reference current is performed by an electronic volume 331 built in the source driver IC (circuit) 14 or the like. A reference current circuit for generating a reference current is provided for each of the red (R), green (G), and blue (B) circuits. White balance is achieved by adjusting the magnitude of the reference current of each RGB reference current circuit. Can be taken. Therefore, the magnitudes of the reset current Ia, the reset voltage Va, and the like of the R, G, and B pixels can be set independently. Further, the target gradation voltage Vc and gradation voltage Vx of each of the R, G, and B pixels can be set independently. FIG. 33 shows this embodiment.

  Each output stage of RGB is composed of a set of unit transistors 284, and the magnitude of the output current (unit program current) of the unit transistors can be adjusted by the magnitude of the reference current. If the magnitude of the reference current is adjusted, the magnitude of the program current (reset current) Ia for each gradation can be changed or varied for each RGB. Therefore, in an ideal state where the characteristics of the RGB unit transistors are the same, white balance can be achieved by changing the ratio of the magnitudes of the RGB reference currents.

  In the following embodiments, the unit transistor group 285 and the like are described as being formed or configured in the source driver circuit (IC) 14, but the present invention is not limited to this. For example, the unit transistor group 285 may be formed on the array substrate. The pixel 16, the unit transistor group 285, and the gate driver circuit 12 may be formed on the array substrate, and other portions may be formed on the source driver circuit (IC) 14.

  As shown in FIGS. 28 and 29A to 29B, the source driver circuit (IC) 14 has output stages (transistor groups) 285 corresponding to the number of output terminals formed or arranged. In the transistor group 285 as each output stage, unit transistors 284 corresponding to the variable number of bits of the reset current Ia are formed or arranged. For example, basically, when the control signal (step) of the reset current Ia is 6 bits (D0 to D5), 2 6 −1 = 63 transistors 284 are formed. Since gradation 0 is current 0, no output of any unit transistor is output to the source signal line 18. When the control signal of the reset current Ia is 8 bits (D0 to D7), 2 to the 8th power-1 = 255 transistors 284 are formed.

  Hereinafter, in order to facilitate the description and to facilitate drawing, the constant current output circuit 10 of the source driver circuit (IC) 14 will be described as having 6 bits. 22A to 22B, each unit transistor 284 is arranged for each constant current data (D0 to D5). One unit transistor 284 is arranged for the D0 bit. Two unit transistors 284 are arranged in the D1 bit. Four unit transistors 284 are arranged in the D2 bit, eight unit transistors 284 are arranged in the D3 bit, and sixteen unit transistors 284 are arranged in the D4 bit. Similarly, 32 unit transistors 284 are arranged in the D5 bit.

  Whether or not the output current of the unit transistor 284 of each bit is output to the output terminal 21 is realized by on / off control by the analog switch 281 (281a to 281f). The analog switches 281a to 281f correspond to each bit (6 bits as an example) of a constant current control signal. When the switch 281a corresponding to the D0 bit is closed, one unit current is output (input) from the output terminal 21. A source signal line 18 is connected to the output terminal 21. Similarly, when the switch 281b corresponding to the D1 bit is closed, 2 unit currents are output (input) from the output terminal 21.

  Similarly, when the switch 281c corresponding to the D2 bit is closed, 4 unit currents are output (input) from the output terminal 21. When the switch 281c corresponding to the D3 bit is closed, 8 unit current is output (input) from the output terminal 21. When the switch 281d corresponding to the D4 bit is closed, 16 unit current is output (input) from the output terminal 21. When the switch 281c corresponding to the D5 bit is closed, 32 unit currents are output (input) from the output terminal 21.

  As described above, the switch 281 is digitally closed or opened corresponding to the bit of the control signal of the reset current Ia, and the sum of unit currents (program current) is output from the output terminal 21.

  The unit transistor 284 forms a current mirror circuit with the transistor 286b. Note that in FIGS. 28 and 29A to 29B, one transistor 286b is illustrated for easy understanding. Actually, it is configured (formed) by a plurality of transistors (transistor groups).

  A reference current Ic flows through the transistor 286b, and a current corresponding to the current mirror ratio of the reference current Ic flows through the unit transistor 284. All the 63 unit transistors 284 in FIG. 28 output the same unit current. In order for the unit current to flow, it is necessary to close the corresponding switch 281 and configure a current path.

  The reference current Ic is generated by a constant current generating circuit including an operational amplifier 291a and a resistor R1. The reference current Ic is made constant by stabilizing and increasing the accuracy of the reference voltage Vs. The voltages Vi and Vs that set the reference current Ic are applied across the resistor R1. Therefore, the reference current Ic = (Vs−Vi) / R1. The reference current Ic can be set for each RGB. That is, the transistor group 285 is configured (formed) for each of RGB.

  FIG. 29A shows a circuit configuration for generating the reference current Ic using the Vs voltage. In FIG. 29B, a basic current is generated by using a resistor R1 disposed (inserted) between GND and the negative terminal of the operational amplifier 291a, and is turned back by a current mirror circuit including a transistor 292b and a transistor 286a. In this configuration, the reference current Ic is supplied. In FIG. 29B, it is easier to adjust the magnitude of the reference current Ic. However, since the current mirror circuit composed of the transistor 292b and the transistor 286a is folded back, variations tend to occur.

  In the present invention, as shown in FIG. 30A, one or a plurality of unit transistors 284 are formed or arranged for each bit. For example, the first bit forms one unit transistor, and the second bit forms two unit transistors.

  However, the present invention is not limited to this. For example, it goes without saying that one transistor 284 that outputs a current corresponding to each bit may be formed or arranged in each bit. For example, as the first bit transistor, one transistor that outputs a current twice as large as that of the zeroth bit transistor is formed or arranged. The second-bit transistor forms or forms one transistor that outputs a current four times that of the zero-bit transistor. In addition, two transistors that output a current twice that of the first bit transistor may be formed or arranged for the second bit transistor.

  As shown in FIG. 30A, in the case of 64 gradations (RGB each 6 bits), 63 unit transistors 284 are formed. Therefore, in the case of 256 gradations (8 bits for each of RGB), 255 unit transistors 284 are required.

  FIG. 30A shows a configuration of a transistor group 285 in which unit transistors 284 having the same size are arranged for each bit. For ease of explanation, it is assumed in FIG. 30A that 63 unit transistors 284 are configured and a 6-bit transistor group 285 is configured (formed). Further, FIG. 30B is assumed to be 8 bits.

  In FIG. 30B, the lower 2 bits (indicated by A) are configured with transistors having a size smaller than that of the unit transistor 284. The 0th bit of the minimum bit is formed by 1/4 of the channel width W of the unit transistor 284 (indicated by the unit transistor 284b). The first bit is formed with ½ of the channel width W of the unit transistor 284 (indicated by the unit transistor 284a). The unit transistor 284a may be formed of two unit transistors 284b that are ¼ of the channel width W of the unit transistor 284.

  The gate terminals of the unit transistors 284a, 284b, 284 are connected to the same gate wiring 282. The gate wiring 283 is connected to the gate terminal of the transistor 286b.

  As described above, the lower 2 bits are formed by unit transistors (284a, 284b) having a size smaller than that of the upper unit transistor 284. Therefore, the unit transistors 284a and 284b can output unit currents that are ½ and ¼ that of the unit transistor 284. The area occupied by the unit transistors 284a and 284b is very small. In addition, the number of regular unit transistors 284 is 63 and does not change. Therefore, even when the bit is changed from 6 bits (64 gradations) to 8 bits (256 gradations), the formation area of the transistor group 285 is not significantly different between FIGS. 30A and 30B. That is, the chip size of the source driver IC (circuit) 14 used in the program current method hardly depends on the number of gradations. Conversely, the source driver IC (circuit) 14 used in the program voltage method greatly depends on the number of gradations.

  As shown in FIG. 32, the gate terminals of the unit transistors 284 constituting the transistor group 285 are connected by one gate wiring 283. The output current of the unit transistor 284 is determined by the voltage applied to the gate wiring 283. Therefore, if the unit transistors 284 in the transistor group 285 have the same shape, each unit transistor 284 outputs the same unit current.

  The present invention is not limited to the common gate wiring 283 of the unit transistors 284 constituting the transistor group 285. For example, it may be configured as shown in FIG. Note that the transistor group 251b corresponds to the transistor 286b. The transistor group 285 includes the transistor 286b. In FIG. 31A, a transistor group 251b1 and a unit transistor 284 constituting a current mirror circuit, and a transistor group 251b2 and a unit transistor 284 constituting a current mirror circuit are arranged. The transistor group 285 can output a gradation current corresponding to the gradation voltage. Accordingly, it is possible to generate a reset current Ia that is proportional to or correlated with the target gradation voltage Vc and the gradation voltage Vx. As a matter of course, a reset current Ia having a predetermined value and a multi-stage reset current Ia can be generated. The magnitude of the reset current Ia can be set or adjusted independently for RGB.

  The transistor group 251b1 is connected to the gate wiring 283a. The transistor group 251b2 is connected by a gate wiring 283b. In FIG. 31A, the uppermost unit transistor 284 is LSB (0th bit), and the second unit transistor 284 in the second stage is the fourth unit transistor in the first bit and the third stage. 284 is the second bit. The eight unit transistors 284 in the fourth stage set are the third bit.

  In FIG. 31A, by changing the voltage applied to the gate wiring 283a and the gate wiring 283b, the output current of each unit transistor 284 is changed (changed) even if the size and shape of each unit transistor 284 are the same. can do.

  In FIG. 31A, the unit transistors 284 have the same size and the like, and the gate wirings 283a and 283b have different voltages. However, the present invention is not limited to this. The unit transistors 284 may have the same output current by changing the sizes of the unit transistors 284 and adjusting the voltages of the gate wirings 283a and 283b to be applied.

  The reference current Ic can be changed by changing the electronic volume 331 shown in FIG. FIG. 33 shows an electronic volume 331 and electronic volumes 331R, 331G, and 331B configured for each of RGB. The reference current Ic can be changed in synchronization with the synchronizing signal (HD) in the horizontal scanning period (H) and the synchronizing signal (VD) in the vertical scanning period (V). VD and HD are generated in synchronization with the internal clock of the source driver circuit.

  The source driver circuit (IC) 14 incorporates a precharge circuit that forcibly releases or charges the source signal line 18 (see FIGS. 12, 13, and 14). The voltage (current) output value of the precharge or discharge circuit that forcibly releases or charges the source signal line 18 is preferably configured to be set independently by R, G, and B. This is because the threshold value of the EL element 15 differs between RGB. This is because the reset voltage Va differs between RGB.

  FIG. 34 is a configuration diagram of the precharge unit. Vp is a precharge voltage. The application period of the precharge voltage Vp is preferably determined by the video data D0 to D5. Alternatively, it is preferable to determine the application period of Vp corresponding to the gradation voltage Vx. Further, the magnitude of the precharge voltage Vp is preferably determined by the video data or the gradation voltage Vx.

  The precharge voltage Vp is output in synchronization with HD or VD. The time for outputting the precharge voltage is determined by the set value of the counter 342 with the horizontal synchronization signal HD as a base point. The counter 342 is counted up in synchronization with the clock CLK signal. The precharge voltage output period starts from the beginning of HD. The counter 342 ends the precharge voltage output period when the counted value matches the set value. The output of the counter circuit 342 becomes the a part input of the AND circuit 343. The precharge voltage Vp is configured to be switched on (applied) / off (not applied).

  In the configuration of FIG. 34, the matching circuit 341 determines under which conditions precharging is performed. Video data D0 to D5 are applied to the matching circuit 341. The coincidence circuit stores a precharge voltage range. The coincidence circuit 341 operates in synchronization with the clock CLK. When the enable signal EN is H, the precharge voltage is output. When the enable signal EN is L, the precharge voltage is not output regardless of the value of the video data. The output of the coincidence circuit 341 becomes the b terminal input of the AND circuit 343.

  When the a part input of the AND circuit 343 is H and the b terminal input is H, the switch 281a is closed, the precharge voltage Vp is applied to the internal wiring 282, and when the HI signal is H, the switch 281b is closed and output. A precharge voltage is output from the terminal 21.

  FIG. 35 is a block diagram centering on a precharge circuit (circuit configuration unit for outputting a precharge voltage) 353 of the source driver circuit (IC) 14. The precharge circuit 353 is a circuit that outputs a precharge control signal PC signal (red (RPC), green (GPC), blue (BPC)) by the precharge control circuit.

  The selection (selector) circuit 352 sequentially latches in the latch circuit 351 corresponding to the output stage in synchronization with the main clock. The latch circuit 351 has a two-stage configuration of a latch circuit 351a and a latch circuit 351b. The latch circuit 351b sends data to the precharge circuit 353 in synchronization with the horizontal scanning clock (1H). That is, the selector sequentially latches the image data and PC data for one pixel row, and stores the data in the latch circuit 351b in synchronization with the horizontal scanning clock (1H).

  In FIG. 35, R, G, and B of the latch circuit 351 are RGB image data 6-bit latch circuits, and P is a latch circuit that latches 3 bits of the precharge signals (RPC, GPC, and BPC).

  The precharge circuit 353 turns on the switch 281a and outputs the precharge voltage Vp to the source signal line 18 when the output of the latch circuit 351b is at the H level. The constant current output circuit 10 outputs a program current (reset current Ia) to the source signal line 18 according to the image data.

  Hereinafter, the voltage gradation circuit 20 will be described. The voltage Vx output from the voltage gradation circuit 20 is called a program voltage. The program voltage Vx becomes a target gradation voltage Vc (for example, Vc = Va + Vx) by being added to the reset voltage Va or the reset voltage V0.

  As shown in FIG. 36, a voltage (program voltage) corresponding to 8-bit video DATA is output from the electronic volume 331 in synchronization with the video clock. The program voltage is temporarily held in the Cc capacity and output from the buffer amplifier 291a. The output voltage is sequentially distributed to each output terminal 21 by a sample and hold circuit (illustrated as a switching circuit in this embodiment) 361 (output terminals 21a, 21b, 21c, 21d... 21n, 21a, 21b, 21c,... The distribution is performed in synchronization with the clock CLK.

  The voltage output from the voltage gradation circuit 20 may reflect the characteristic variation of the driving transistor 11a of the EL display panel. The reset voltage Va of each driving transistor 11a or a similar voltage is measured in advance. The measurement is exemplified by a method of electrically reading the reset voltage Va as shown in FIG. A predetermined voltage is applied to the display area of the EL display device, and the light emission state of each lit EL element is optically measured using a scanner or the like. A characteristic variation of each driving transistor 11a is obtained from the measured image data. The gradation voltage Vx is corrected using the obtained data.

(Second Embodiment)
Hereinafter, a second embodiment of the present invention will be described. In the following embodiments, description of the same parts and operations as those of the first embodiment will be omitted. The description will focus on the differences from the first embodiment. The contents described previously apply to the following embodiments. For example, configurations related to driver circuits such as FIGS. 5, 6, 8, and 9 can be applied and can be combined in a timely manner. The precharge method of FIGS. 12, 13, and 14 and the configuration relating to the precharge circuit of FIG. 34 can be applied and can be combined in a timely manner. Moreover, the structure regarding the data transmission method of FIG. 15 can be applied, and it can combine suitably. Further, the gate driver circuit of FIG. 20, FIGS. 18A to 18B, FIGS. 21A to 21B, and 22A to 22B are intermittently displayed, and FIGS. 28 and 29A. To (B), FIGS. 30 (A) to (B), FIGS. 31 (A) to (B), FIG. 32, FIG. 33, FIG. 35, FIG. 36, and FIG. Can be combined. The above items apply not only to the second embodiment but also to other embodiments.

  FIG. 39 is an explanatory diagram of a pixel configuration of an EL display device according to the second embodiment of the present invention. The difference from FIG. 2 is that a capacitor 19b and a switching transistor 11e are added. The capacitor 19b is disposed between the gate terminal of the driving transistor 11a and the drain terminal of the transistor 11e. The capacitor 19b cuts the DC component of the signal. In the EL display device, pixels of three kinds of RGB colors are formed in a matrix. For ease of explanation, FIG. 39 also shows one pixel extracted as in FIG.

  The transistors 11b and 11c operate to apply the current signal applied to the source signal line 18 to the driving transistor 11a (current program). The capacitor 19b and the transistor 11e operate to apply the voltage signal applied to the source signal line 18 to the driving transistor 11a (voltage program).

  The gate driver circuit 12 includes three gates 12a, 12b, and 12c. The gate driver circuit 12a controls the gate signal line 17a. The gate driver circuit 12b controls the gate signal line 17b. The gate driver circuit 12c controls the gate signal line 17c. Each of the gate driver circuits 12a, 12b, and 12c has a shift register circuit therein, and shifts the position of the gate signal line 12 that selects the pixel row in synchronization.

  40 and 41 are explanatory diagrams of a driving method of the EL display device of the present invention shown in FIG. The source driver circuit 14 includes a constant current output circuit and a voltage gradation circuit as in the previous embodiment. As shown in the table of FIG. 42, the operation is roughly classified into a reset period, an address period, and a holding (light emission) period. The reset period is a period during which the reset current Ia is applied to the driving transistor 11a. The writing period is a period during which the target gradation voltage Vc is written to the pixel 16. The holding period is a period during which the EL element 15 emits light.

  The reset period is implemented at the beginning of 1H. After the reset period, an address period is started. Reset period + writing period = 1 horizontal scanning period (a period for selecting one pixel row). In some cases, the writing period may be started immediately after the start of the reset period.

  Similarly to the first embodiment, the second embodiment includes a step of applying a reset current Ia to the pixel 16 and a step of applying a target gradation voltage Vc to the pixel 16. In addition, the target gradation voltage Vc is generated from the reset voltage Va and the gradation voltage Vx.

  Hereinafter, the operation of the EL display device of the present invention will be described with reference to FIG. 42, FIG. 40, and FIG.

  As shown in FIG. 40, in the reset period, the gate driver circuit 12a controls the gate signal line 17a to select one pixel row. The transistors 11c and 11b in the selected pixel row are turned on (closed). The switch SW1 of the source driver circuit 14 is turned on, and the constant current output circuit 413 applies the reset current Ia to the source signal line 18. The reset current Ia flows through the anode voltage Vdd of the selected pixel 16 → the driving transistor 11 a → the transistor 11 c → the source signal line 18. Note that the switch SW2 is in an off state.

  When the reset current Ia flows through the driving transistor 11a, current programming is performed such that the reset current Ia flows through the gate terminal of the driving transistor 11a. The reset voltage Va set so as to flow the reset current Ia is held in the capacitor 19b connected to the gate terminal of the driving transistor 11a (point a) as in the first embodiment. At the same time, since the transistors 11c and 11b are on, the potential at the point a and the potential at the point b of the capacitor 19b are the same. Therefore, no potential difference occurs between both terminals of the capacitor 19b. In the above operation, a turn-off voltage is applied to the gate signal line 17c and the gate signal line 17b, and the transistors 11e and 11d are held in an off (open) state.

  FIG. 41 is an explanatory diagram of the operation during the writing period. The address period is a voltage program period. In the writing period, the gate driver circuit 12c controls the gate signal line 17c to select one pixel row to which the reset current Ia is applied. The transistors 11e in the selected pixel row are turned on (closed). The switch SW2 of the source driver circuit 14 is turned on, and the gradation voltage circuit 411 applies the gradation voltage Vx to the source signal line 18. Note that the switch SW1 is in an off state. Further, the transistors 11b, 11c, and 11d are in an off state.

  The gradation voltage Vx is applied to the b terminal of the capacitor 19b of the selected pixel 16 via the transistor 11e. The gradation voltage Vx is V1. For ease of explanation, it is assumed that the gradation voltage V1 generates a potential difference of V1 with respect to the reset voltage Va.

  When the gradation voltage V1 is applied to the b terminal of the capacitor 19b, the a terminal of the capacitor 19b is shifted by the potential of V1. That is, the potential at the terminal a of the capacitor 19b is the reset voltage Va + the gradation voltage V1 = the target gradation voltage Vc. This target gradation voltage Vc is applied to the gate terminal of the driving transistor 11a.

  In the holding (light emission) period, an on-voltage is applied to the gate signal line 17b, and the transistor 11d is turned on. The on / off control of the transistor 11d is performed so as to correspond to the driving methods of FIGS. 18A to 18B, 21A to 21B, and 22A to 22B. In the holding (light emission) period, the transistors 11e, 11b, and 11c are held in an off state. The driving transistor 11 a performs voltage-current conversion on the target gradation voltage Vc, and applies the converted current to the EL element 15. The EL element 15 emits light corresponding to the applied current.

  As described above, the gate signal line 17a and the gate signal line 17c form a pair and sequentially select pixel rows. The reset current Ia and the gradation voltage Vx are applied to the selected pixel row, and the target gradation voltage Vc is applied to each pixel of the pixel row.

  In the first embodiment of the present invention, the target gradation voltage Vc is generated using the capacitor 52 formed in the source driver or the like. The generated target gradation voltage Vc is output to the source signal line 18 and applied to the driving transistor 11a.

  In the second embodiment of the present invention, the gradation voltage Vx is output to the source signal line 18, the reset voltage Va and the gradation voltage Vx are added (subtracted) by the capacitor 19b of the pixel 16, and the target gradation is obtained. A voltage Vc is generated.

  It goes without saying that the drive systems shown in FIGS. 12 to 14 can be realized if the precharge voltage Vp is applied to the beginning of 1H by the precharge voltage Vp generation circuit shown in FIG. Further, the second embodiment can be combined with the driving method for selecting a plurality of pixel rows in FIGS. Further, as the constant current output circuit, the configuration shown in FIG. 28 or the like can be employed.

  As described above, the second embodiment of the present invention can be combined with other embodiments. Each component and driving method can be adopted. In addition, the pixel configuration described in this specification can also be employed. The above matters are similarly applied to other embodiments of the present invention.

(Third embodiment)
FIG. 43 shows a third embodiment. In FIG. 43, a source driver circuit 14a that generates a reset current Ia and a source driver circuit 14b that generates a gradation voltage Vx are provided. The output terminal of the source driver circuit 14a is connected to the source signal line 18a. The output terminal of the source driver circuit 14b is connected to the source signal line 18b. The source terminal of the transistor 11c is connected to the source signal line 18a, and the source terminal of the transistor 11e is connected to the source signal line 18b. Other configurations are the same as those of the first and second embodiments.

  The table of FIG. 44 shows the operating state of each component of the third embodiment of the present invention. Hereinafter, the third embodiment of the present invention will be described with reference to FIGS. 43 and 44. Note that, similarly to the second embodiment, the gradation voltage Vx is described as V1.

  In the reset period, the gate driver circuit 12a controls the gate signal line 17a to select one pixel row. The transistors 11c and 11b in the selected pixel row are turned on (closed). The source driver circuit 14 applies the reset current Ia to the source signal line 18a. The reset current Ia flows through the anode voltage Vdd of the selected pixel 16 → the driving transistor 11a → the transistor 11c → the source signal line 18a. As described in the above-described embodiment, the current direction of the reset current Ia is selected from either the discharge current direction or the suction current direction according to the configuration of the pixel 16.

  A reset current Ia flows through the driving transistor 11a. Current programming is performed so that the reset current Ia flows through the gate terminal of the driving transistor 11a. Therefore, the reset voltage Va is set so that the reset current Ia flows through the gate terminal of the driving transistor 11a. The reset voltage Va is held at the point a of the capacitor 19b.

  In the writing period, an on-voltage is applied to the gate signal line 17c, and the transistor 11e is turned on. Note that the transistor 11e may be turned on in the reset period and kept on in the writing period. In the writing period, the transistors 11b, 11c, and 11d are kept off.

  During the writing period, the source driver circuit 14b applies the gradation voltage V1 based on the input video signal to the source signal line 18b. By turning on the transistor 11e, the voltage V1 applied to the source signal line 18b is applied to the b terminal of the capacitor 19b. The potential at the b terminal of the capacitor 19b changes from the initial voltage Vb to V1.

  When the voltage at the b terminal changes from the initial voltage Vb to the V1 voltage, the potential at the a terminal of the capacitor 19b changes from the Va voltage to Va + V1 (in the addition direction). Or, it changes to Va-V1 (in the subtraction direction). Therefore, the target gradation voltage Vc = Va ± Vx is applied to the gate terminal of the driving transistor 11a.

  The voltage Vb in the initial state may be the reset voltage Va. This can be realized by electrically shorting the source signal line 18a and the source signal line 18b during the reset period. The short circuit can be easily realized by forming an analog switch between the source signal line 18a and the source signal line 18b. By turning on the analog switch during the reset period, the potential Va of the source signal line 18a is applied to the source signal line 18b.

  The source driver circuit 14a constantly applies the reset current Ia to each source signal line 18a. Therefore, the potential of the source signal line 18a can be stably maintained. However, the reset voltage Va changes in accordance with the characteristics of the driving transistor 11a according to the selection of the pixel row.

  In the holding (light emission) period, an on-voltage is applied to the gate signal line 17b, and the transistor 11d is turned on. The on / off control of the transistor 11d is performed so as to correspond to the driving methods of FIGS. 18A to 18B, 21A to 21B, and 22A to 22B. In the holding (light emission) period, the transistors 11e, 11b, and 11c are held in an off state. The driving transistor 11 a performs voltage-current conversion on the target gradation voltage Vc, and applies the converted current to the EL element 15. The EL element 15 emits light corresponding to the applied current.

  As described above, the gate signal line 17a and the gate signal line 17c form a pair and sequentially select pixel rows. The reset current Ia is applied to the driving transistor in the selected pixel row, and the target gradation voltage Vc is applied to the gate terminal of the driving transistor 11a.

(Fourth embodiment)
FIG. 45 shows a fourth embodiment. The table of FIG. 46 is an explanatory diagram of the operation of FIG. In the embodiment of FIG. 45, each pixel 16 is connected to one source signal line 18 as in the embodiments of FIGS. The major difference is that the capacitor 19b connects the output terminal of the source driver circuit 12a having a constant current output circuit and the output terminal of the source driver circuit 12b having a gradation voltage circuit.

  In the reset period, the gate driver circuit 12a controls the gate signal line 17a to select one pixel row. The transistors 11c and 11b in the selected pixel row are turned on (closed). The source driver circuit 14 a applies a reset current Ia to the source signal line 18. The reset current Ia flows through the anode voltage Vdd of the selected pixel 16 → the driving transistor 11 a → the transistor 11 c → the source signal line 18.

  Current programming is performed so that the reset current Ia flows through the gate terminal of the driving transistor 11a. The reset voltage Va set so as to allow the reset current Ia to flow is held in the gate terminal and the source signal line 18 in the driving transistor 11a as in the first embodiment. The transistor 11d is off during the reset period and the writing period.

  The writing period starts after the reset period. In the writing period, the source driver circuit 14b outputs the gradation voltage Vx. As shown in the table of FIG. 46, it is assumed that the output voltage of the source driver circuit 14b is the Vb voltage in the reset period and that the gradation voltage Vx = V1 is output in the writing period.

  In the writing period, the gradation voltage V1 is output from the gradation voltage circuit 411 of the source driver circuit 14b. The gradation voltage V1 is applied to the source signal line 18 via the capacitor 19b. Therefore, in the source signal line 18, the reset voltage Va + the gradation voltage V1 = the target gradation voltage Vc. This target gradation voltage Vc is applied to the gate terminal of the driving transistor 11a.

  In the holding (light emission) period, an on-voltage is applied to the gate signal line 17b, and the transistor 11d is turned on. In the holding (light emission) period, the transistors 11b and 11c are held off. The driving transistor 11 a performs voltage-current conversion on the target gradation voltage Vc, and applies the converted current to the EL element 15. The EL element 15 emits light corresponding to the applied current.

  As described above, the gate signal line 17a sequentially selects pixel rows. A reset current Ia is applied to the selected pixel row, a reset voltage Va is extracted from the source signal line 18, and a voltage Vc obtained by adding and subtracting the reset voltage Va and the gradation voltage Vx is the gate terminal of the driving transistor 11a. To be applied.

(Fifth embodiment)
FIG. 47 shows a fifth embodiment. The table of FIG. 48 is an explanatory diagram of the operation state of FIG. The difference between the fifth embodiment and the fourth embodiment is that the transistors 11b and 11c can be individually turned on and off by the gate signal line 17a and the gate signal line 17c.

  47, each pixel 16 is connected to one source signal line 18 as in the embodiment of FIG. In the reset period, the gate driver circuit 12a and the gate driver 11c control the gate signal lines 17a and 17c to select one pixel row. The transistors 11c and 11b in the selected pixel row are turned on (closed). The source driver circuit 14 a applies a reset current Ia to the source signal line 18. The reset current Ia flows through the anode voltage Vdd of the selected pixel 16 → the driving transistor 11 a → the transistor 11 c → the source signal line 18.

  Current programming is performed so that the reset current Ia flows through the gate terminal of the driving transistor 11a. The reset voltage Va set to flow the reset current Ia is output to the drive transistor 11a to the gate terminal and the source signal line 18 as in the fourth embodiment. The transistor 11d is off during the reset period and the writing period.

  In the address period, the gate signal line 17a on-voltage is applied, and the on-state of the transistor 11c is maintained. A turn-off voltage is applied to the gate signal line 17c, and the transistor 11b is controlled to be turned off. In the writing period, the gradation voltage V1 is output from the gradation voltage circuit 411 of the source driver circuit 14b. The gradation voltage V1 is applied to the source signal line 18 via the capacitor 19b. Therefore, in the source signal line 18, the reset voltage Va + the gradation voltage V1 = the target gradation voltage Vc. This target gradation voltage Vc is applied to the gate terminal of the driving transistor 11a.

  In the fifth embodiment, unlike the fourth embodiment, since the transistor 11b is turned off during the writing period, the target gradation voltage Vc can be satisfactorily written to the driving transistor 11a.

  In the holding (light emission) period, an on-voltage is applied to the gate signal line 17b, and the transistor 11d is turned on. In the holding (light emission) period, the transistors 11b and 11c are held off. The driving transistor 11 a performs voltage-current conversion on the target gradation voltage Vc, and applies the converted current to the EL element 15. The EL element 15 emits light corresponding to the applied current.

  In the embodiment of the present invention, the reset current Ia applied to the pixel 16 is one type, but the present invention is not limited to this. For example, two reset currents of a first reset current Ia1 that is 10 μA and a second reset current Ia2 that is 20 μA are generated, and these reset currents are applied to the pixels to obtain respective target gradation voltages, etc. You may ask for. The obtained target gradation voltage is averaged to obtain an accurate target gradation voltage.

  In the embodiment of the present invention, the number of reset currents Ia applied to the pixels 16 is one, but the present invention is not limited to this. For example, the reset current Ia of 10 μA may be applied to the pixel 16 four times, and the respective target gradation voltages may be obtained. The obtained target gradation voltage is averaged to obtain an accurate target gradation voltage.

  The following matters are common to the first to fifth embodiments.

  In the first to fifth embodiments, a constant current output circuit is used. The constant current output circuit may be formed in the source driver circuit 14 or may be formed on the array substrate 30. FIG. 49 shows an example in which the constant current output circuit is formed in the source driver circuit 14 manufactured by the semiconductor IC technology. A current holding circuit 501 is formed on the array substrate 31. Two current holding circuits 501 (501a and 501b) are connected to one output terminal of the source driver circuit. The source driver circuit 14 outputs a reset current Ia that is a discharge current direction.

  FIG. 50 is a detailed configuration diagram of two current holding circuits (501a, 501b). The current holding circuit 501 includes a capacitor 19 that holds current, and a driving transistor 11 that outputs or generates a written current (held current). Further, it is composed of switches SA and SB.

  When the reset current Ia of the pixel 16 flows into the current holding circuit 501a, the source driver circuit 14 writes the reset current Ia into the current holding circuit 501b. When the reset current Ib of the pixel 16 flows into the current holding circuit 501b, the source driver circuit 14 writes the reset current Ia into the current holding circuit 501a. In the current holding circuits 501a and 501b, the reset current Ia is written from the source driver circuit 14 alternately.

  When the reset current Ia is written from the source driver circuit 14 to the current holding circuit 501a, the transistor (switch) SAa is turned on. At that time, the transistor (switch) SAb is turned off. When current flows from the pixel 16 into the current holding circuit 501a, the transistor (switch) SAb is turned on. At that time, the transistor (switch) SAa is turned off.

  Similarly, when the reset current Ia is written from the source driver circuit 14 to the current holding circuit 501b, the transistor (switch) SBa is turned on. At that time, the transistor (switch) SBb is turned off. When current flows from the pixel 16 into the current holding circuit 501a, the transistor (switch) SBb is turned on. At that time, the transistor (switch) SBa is turned off. With the above configuration, the configuration of the source driver circuit 14 can be simplified and the number of output terminals can be reduced.

  In order to reduce the output terminals 21 of the source driver circuit 14, it is also effective to configure the pixels 16a and 16b as shown in FIG. One source signal line 18 is connected to one output terminal 21. Two pixel columns are connected to one source signal line. The pixel 16a and the pixel 16b are connected to the same source signal line 18.

  A reset current Ia, a gradation voltage Vx, or a target gradation voltage Vc is applied to the source signal line 18. Moreover, the reset voltage Va is output depending on the configuration of the embodiment of the present invention.

  The reset current Ia is applied to the pixel 16a in the first half of one horizontal scanning period, and the reset current Ia is applied to the pixel 16b in a period other than the period in which the pixel 16b is selected. That is, the pixel 16a and the pixel 16b are selected by time division.

  In the voltage program method, it is preferable to perform temperature compensation for the gradation voltage Vx and the target gradation voltage Vc. This is because the voltage-current (V-I) characteristics of the driving transistor 11a have temperature dependence.

  In the present invention, as shown in FIG. 52, a temperature detection circuit (pixel) 521 having the same or similar configuration as that of the pixel 16 is formed on the array substrate. The temperature detection circuit 521 includes a driving transistor 11 and a holding capacitor 19 that detect a temperature change of the reset voltage Va.

  A plurality of temperature detection circuits 521 are formed on the array substrate. This is because in one temperature detection circuit 521, if this one temperature detection circuit 521 is defective, the panel module becomes a defective product. If a plurality of temperature detection circuits 521 are formed as in the embodiment of FIG. 52, it is sufficient that at least one temperature detection circuit 521 is a non-defective product. One temperature detection circuit 521 is selected from a plurality of temperature detection circuits 521 by a selector circuit 524.

  A constant current circuit 413 is connected to each temperature detection circuit 521. The constant current circuit 413 is formed in the source driver circuit 14. The constant current circuit 413 is the same as the circuit that outputs the reset current Ia. The constant current circuit 413 passes a current having the same magnitude as the reset current Ia to the temperature detection circuit 521. Therefore, the reset voltage Va of the driving transistor 11 of the temperature detection circuit 521 is extracted to the detection wiring 527.

  The selector 524 selects one detection wiring 527 and outputs the reset voltage Va output to the detection wiring 527 to the AD conversion circuit 523. Needless to say, the selector 524 may change the temperature detection circuit 521 selected at the timing of VD or HD. In this case, the output Va of the plurality of temperature detection circuits 521 is averaged.

  The AD conversion circuit 523 converts the reset voltage Va into digital data. The data comparison circuit 525 compares the reset voltage Va of the converted digital data with the data in the external storage circuit (eg, EEPROM) 522. The external storage circuit 522 stores a digital data reset voltage Va at room temperature or a predetermined temperature.

  By comparing the digital data reset voltage Va at room temperature or a predetermined temperature with the reset voltage Va acquired by the temperature detection circuit 521, a voltage fluctuation value corresponding to the temperature of the current panel is obtained. The temperature compensation circuit 526 performs temperature compensation on the gradation voltage Vx and the target gradation voltage Vc using the voltage fluctuation value.

  Hereinafter, an EL display panel or an EL display device of the present invention or a device using the driving method thereof will be described. The following apparatus implements the previously described apparatus or method of the present invention. FIG. 53 is a plan view of a mobile phone as an example of an information terminal device. An antenna 531, a numeric keypad 532, and the like are attached to the housing 533.

  FIG. 54 is a perspective view of the video camera. The video camera includes a photographing (imaging) lens unit 542 and a video or camera body 533, and the photographing lens unit 542 and the viewfinder unit 533 are back to back. In addition, an eyepiece cover is attached to the viewfinder 533. An observer (user) observes the display screen 184 of the display panel 534 from the eyepiece cover portion.

  The EL display panel of the present invention is also used as a display monitor. The display unit 184 can freely adjust the angle at a fulcrum 541. When the display unit 184 is not used, it is stored in the storage unit 543.

  The EL display device and the like in the above embodiment can be applied not only to a video camera but also to an electronic camera, a still camera, or the like as shown in FIG. The display device is used as a monitor 184 attached to the camera body 551. In addition to the shutter 553, a switch 544 is attached to the camera body 551.

  The technical ideas such as the display device, the driving method, the control method, or the method described in the embodiment of the present invention include a video camera, a projector, a stereoscopic (3D) television, a projection television, a field emission display (FED), and an SED (cannon). And displays developed by Toshiba) and PDPs (plasma display panels).

  The present invention can also be applied to a viewfinder, a main monitor and a sub monitor of a mobile phone, a clock display unit, a PHS, a portable information terminal and its monitor, a digital camera, a satellite TV, a satellite mobile TV and a monitor thereof. The present invention can also be applied to an electrophotographic system, a head-mounted display, a direct-view monitor display, a notebook personal computer, a video camera, a digital still camera, and an electronic still camera.

  Note that in this specification, the driving transistor 11a, the switching transistor 11b, and the like are described as thin film transistors, but the present invention is not limited thereto. A MOS-FET, a MOS transistor, or a bipolar transistor may be used.

  The source driver circuit (IC) 14 has not only a simple driver function but also a power supply circuit, a buffer circuit (including a circuit such as a shift register), a level shifter circuit, a data conversion circuit, a latch circuit, a command decoder, an address conversion circuit, and an image memory. (RAM) or the like may be incorporated.

  Although the array 382 substrate is described as a glass substrate, it may be formed of a silicon wafer. The array substrate 382 may be a metal substrate, a ceramic substrate, a plastic sheet (plate), or the like.

  The addition or subtraction described in this specification does not mean calculation by calculation. It means a broad concept such as voltage level shift, level conversion, voltage multiplexing, and amplification. Needless to say, the acquired analog data may be converted into digital data and added or subtracted. Measuring voltage is a broad technical concept that includes acquiring voltage, holding voltage, and voltage sample-holding.

  The present invention is not limited to the above-described embodiments, and various modifications and changes can be made without departing from the scope of the invention when it is practiced. Moreover, each embodiment may be implemented in combination as appropriate as possible.

Configuration diagram of display device of the present invention Configuration diagram of a pixel of a display device of the present invention Configuration diagram of conventional display device (A)-(C): Explanatory drawing of operation | movement of the display apparatus of this invention. Configuration diagram of display device of the present invention Configuration diagram of display device of the present invention Explanatory drawing of the display apparatus of this invention Configuration diagram of display device of the present invention Configuration diagram of display device of the present invention (A)-(B): The block diagram of the display apparatus of this invention Explanatory drawing of the display apparatus of this invention Explanatory drawing of the display apparatus of this invention Explanatory drawing of the display apparatus of this invention Explanatory drawing of the display apparatus of this invention Explanatory drawing of the drive method of the display apparatus of this invention (A)-(B): Explanatory drawing of the drive method of the display apparatus of this invention (A)-(B): Explanatory drawing of the display device of the present invention (A)-(B): Explanatory drawing of the drive method of the display apparatus of this invention (A)-(C): Explanatory drawing of the drive method of the display apparatus of this invention Configuration diagram of display device of the present invention (A)-(B): Explanatory drawing of the drive method of the display apparatus of this invention (A)-(B): The block diagram of the drive method of the display apparatus of this invention Explanatory drawing of the display apparatus of this invention Explanatory drawing of the display apparatus of this invention (A)-(B): Explanatory drawing of the display device of the present invention Explanatory drawing of the display apparatus of this invention Explanatory drawing of the display apparatus of this invention Configuration diagram of display device of the present invention (A)-(B): The block diagram of the display apparatus of this invention (A)-(B): The block diagram of the display apparatus of this invention (A)-(B): The block diagram of the display apparatus of this invention Configuration diagram of display device of the present invention Configuration diagram of display device of the present invention Configuration diagram of display device of the present invention Configuration diagram of display device of the present invention Configuration diagram of display device of the present invention Configuration diagram of display device of the present invention Configuration diagram of display device of the present invention Configuration diagram of display device of the present invention Configuration diagram of display device of the present invention Configuration diagram of display device of the present invention Explanatory drawing which showed operation | movement of the transistor etc. of the display apparatus of this invention. Configuration diagram of display device of the present invention Explanatory drawing which showed operation | movement of the transistor etc. of the display apparatus of this invention. Configuration diagram of display device of the present invention Explanatory drawing which showed operation | movement of the transistor etc. of the display apparatus of this invention. Configuration diagram of display device of the present invention Explanatory drawing which showed operation | movement of the transistor etc. of the display apparatus of this invention. Configuration diagram of display device of the present invention Configuration diagram of display device of the present invention Configuration diagram of display device of the present invention Configuration diagram of display device of the present invention Plan view of a mobile phone using the display device of the present invention The perspective view of the video camera using the display apparatus of this invention The perspective view of the electronic camera using the display apparatus of this invention

Explanation of symbols

10 constant current output circuit 11 transistor (thin film transistor, TFT)
12 Gate driver IC (circuit)
14 Source driver IC (circuit)
15 EL (element, light emitting element)
16 pixel 17 gate signal line 18 source signal line 19 storage capacity (additional capacitor, additional capacity)
20 Voltage gradation circuit 21 Output terminal 55 DA conversion circuit 52 Capacitor (DC component cut circuit)
53 operational amplifier 61 adder circuit 62 AD converter circuit 91 emitter follower circuit 181 write row 182 non-display area (non-lighting area, black display area)
183 Display area (lighting area, image display area)
184 Display area (display screen, display part)
201 Shift register circuit 202 Buffer circuit 281 Switch (ON / OFF means)
282 Internal wiring (output wiring)
283 Gate wiring 284 Unit transistor 291 Operational amplifier 292 Transistor 331 Electronic volume 341 Matching circuit 342 Counter 343 AND circuit 351 Latch circuit 352 Selector circuit 353 Precharge circuit 361 Sample hold circuit (voltage holding means)
381 Switch circuit 411 Gradation voltage circuit 413 Constant current circuit (current generation circuit)
501 Current holding circuit 521 Temperature detection circuit 522 External storage circuit 523 A / D conversion circuit 524 Selector circuit 525 Data comparison circuit 526 Temperature compensation circuit 531 Antenna 532 Key 533 Case 534 Display panel 541 Support point (rotating unit)
542 Photographic lens (photographing means)
543 Storage unit 544 Switch 551 Main body 552 Imaging unit 553 Shutter switch

Claims (8)

  1. An EL display device in which pixels having EL elements are formed in a matrix,
    A constant current circuit for generating a predetermined constant current;
    A gradation voltage circuit for generating a gradation voltage;
    The constant current generated by the constant current circuit is supplied to the pixel via a source signal line,
    The EL display device, wherein the gradation voltage generated by the gradation voltage circuit is supplied to the pixel via the source signal line.
  2. A method for driving an EL display device in which pixels having EL elements are formed in a matrix,
    The EL display device
    A constant current circuit for generating a predetermined constant current;
    A gradation voltage circuit for generating gradation voltages;
    The pixel includes a driving transistor that supplies a driving current to the EL element, and a switching transistor that forms a current path between a source signal line and the driving transistor.
    The driving method of the EL display device is as follows:
    Applying the constant current generated by the constant current circuit to the pixel via the source signal line;
    Obtaining a potential of the source signal line in a state where the constant current is applied to the source signal line;
    The acquired potential and the gradation voltage are added or the gradation voltage is subtracted from the acquired potential, and the result of the addition or subtraction is sent to the driving transistor of the pixel via the source signal line. Applying, and
    A method for driving an EL display device, comprising:
  3.   3. The method for driving an EL display device according to claim 2, wherein a precharge voltage is applied to the source signal line or the pixel before or during the period in which the constant current is applied to the pixel.
  4.   The method of driving an EL display device according to claim 2, wherein the constant current circuit includes a plurality of unit transistors.
  5. An EL display device in which pixels having EL elements are formed in a matrix,
    A constant current circuit for generating a predetermined constant current;
    A gradation voltage circuit for generating a gradation voltage;
    The pixel includes a driving transistor for supplying a driving current to the EL element, a capacitor connected to a gate terminal of the driving transistor, and a first current path that forms a current path between a source signal line and the driving transistor. An EL display device comprising: a switching transistor; and a second switching transistor that applies the gradation voltage to the driving transistor through the capacitor.
  6. An EL display device in which pixels having EL elements are formed in a matrix,
    A constant current circuit for generating a predetermined constant current;
    A gradation voltage circuit for generating gradation voltages;
    A first source signal line for supplying the constant current to the pixel;
    A second source signal line for supplying the gradation voltage to the pixel,
    The pixel forms a current path between the driving transistor for supplying a driving current to the EL element, a capacitor connected to the gate terminal of the driving transistor, and the first source signal line and the driving transistor. And a second switching transistor that forms an electrical path between the second source signal line and the capacitor.
  7. An EL display device in which pixels having EL elements are formed in a matrix,
    A constant current circuit for generating a predetermined constant current;
    A gradation voltage circuit for generating gradation voltages;
    A capacitor,
    A source signal line for supplying the constant current to the pixel,
    The EL display device, wherein the gradation voltage is applied to the source signal line through the capacitor.
  8. A display portion in which pixels having EL elements are formed in a matrix;
    A constant current output circuit for outputting a reset current to the driving transistor of the EL element;
    A voltage holding circuit for acquiring a gate terminal potential of the driving transistor in a state where the reset current is applied;
    A gradation voltage circuit that outputs a gradation voltage corresponding to a video signal;
    A voltage application circuit for adding the gate terminal potential and the gradation voltage or subtracting the gradation voltage from the gate terminal potential and applying a result of the addition or subtraction to the gate terminal of the driving transistor; EL display device.
JP2006325005A 2005-12-01 2006-11-30 El display apparatus and method for driving the el display apparatus Pending JP2007179037A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2005348486 2005-12-01
JP2006325005A JP2007179037A (en) 2005-12-01 2006-11-30 El display apparatus and method for driving the el display apparatus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2006325005A JP2007179037A (en) 2005-12-01 2006-11-30 El display apparatus and method for driving the el display apparatus

Publications (1)

Publication Number Publication Date
JP2007179037A true JP2007179037A (en) 2007-07-12

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Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007248702A (en) * 2006-03-15 2007-09-27 Seiko Epson Corp Light emitting device and driving method therefor, and electronic equipment
JP2009300592A (en) * 2008-06-11 2009-12-24 Hitachi Displays Ltd Image display device
JP2010048863A (en) * 2008-08-19 2010-03-04 Hitachi Displays Ltd Image display
JP2011013293A (en) * 2009-06-30 2011-01-20 Casio Computer Co Ltd Electronic apparatus and method for driving electronic apparatus
JP2013148874A (en) * 2011-12-20 2013-08-01 Canon Inc Display device
JP2014026256A (en) * 2012-07-25 2014-02-06 Samsung Display Co Ltd Apparatus and method for compensating image of display device
US8791882B2 (en) 2008-03-06 2014-07-29 Sharp Kabushiki Kaisha Display device of active matrix type

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007248702A (en) * 2006-03-15 2007-09-27 Seiko Epson Corp Light emitting device and driving method therefor, and electronic equipment
JP4577244B2 (en) * 2006-03-15 2010-11-10 セイコーエプソン株式会社 Light emitting device, its drive method, and electronic device
US8791882B2 (en) 2008-03-06 2014-07-29 Sharp Kabushiki Kaisha Display device of active matrix type
US9224336B2 (en) 2008-03-06 2015-12-29 Sharp Kabushiki Kaisha Display device of active matrix type
US9865198B2 (en) 2008-03-06 2018-01-09 Sharp Kabushiki Kaisha Display device of active matrix type
JP2009300592A (en) * 2008-06-11 2009-12-24 Hitachi Displays Ltd Image display device
JP2010048863A (en) * 2008-08-19 2010-03-04 Hitachi Displays Ltd Image display
JP2011013293A (en) * 2009-06-30 2011-01-20 Casio Computer Co Ltd Electronic apparatus and method for driving electronic apparatus
JP2013148874A (en) * 2011-12-20 2013-08-01 Canon Inc Display device
JP2014026256A (en) * 2012-07-25 2014-02-06 Samsung Display Co Ltd Apparatus and method for compensating image of display device

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