JP5272210B2 - Clock supply device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a device for supplying a clock enabling appropriate maintenance by allowing the condition of trouble of an input clock to be properly determined even when the frequency of the input clock temporally fluctuates due to jitters, wanderings or the like. <P>SOLUTION: The device for supplying a clock is composed by including: a wandering/jitter removal filter 41 installed between an N-system clock reception part 22 and an N-system MTIE measurement part 31; and a wandering removal filter 42 installed between an E-system clock reception part 23 and an E-system MTIE measurement part 32. The device is structured such that the cutoff frequency of a lowpass filter characteristic provided for an oscillator part 26 is coincident with or generally equal to those of lowpass filter characteristics provided for the wandering removal filters 41, 42. <P>COPYRIGHT: (C)2011,JPO&amp;INPIT

Description

  The present invention relates to a clock supply device used in a slave synchronization system in which operation clocks of nodes (stations) and devices in a network coincide with each other, and in particular, when the frequency of an input clock varies with time due to jitter or wander. The present invention also relates to a clock supply device that can accurately determine the state of a clock failure.

  Currently, as a network synchronization method for matching the operation clocks of each node in the network and each device in the node, the Japanese communication network employs a subordinate synchronization method. In the slave synchronization method, as shown in FIG. 5, a node that supplies the highest master clock (Primary Reference Clock) is used as a starting point, and the clock is distributed from the upper node to the lower node via the transmission path (clock path) ( For example, see Patent Document 1).

  The clock distributed to each node is received by the clock supply device 21A installed in the node 11 via the transmission device 12 in the node 11 as shown in FIG.

  The clock supply device 21A generates a clock synchronized with the received clock, distributes the generated clock to each device (the exchange 13 and the transmission device 12) in the node 11, and the clock is further transmitted to a lower node as a transmission path (clock path) 14. Distributed through.

  As shown in FIG. 7, the clock supply device 21 </ b> A includes an N-system clock receiving unit 22, an E-system clock receiving unit 23, an input disconnection monitoring unit 24, an input switching unit 25, an oscillator unit 26, and a distribution unit 27. As shown in FIGS. 5, 6, and 7, the clock dependent element has an N / E (normal system / standby system) redundant configuration, and is usually an N system clock distributed from an N system (normal system) clock path. When the clock supply device 21A detects the N-system clock input disconnection, the clock supply device 21A transmits a switching signal from the input disconnection monitoring unit 24 to the input switching unit 25 to switch the clock supply source to the E-system (standby system). .

  However, when the clock supply device 21A is subordinate to the N system clock input, if the N system clock input is not interrupted and an abnormality such as deterioration of the clock frequency accuracy occurs in the N system clock path, Does not switch. For this reason, the clock supply device 21A is subordinate to a clock whose frequency accuracy has deteriorated. As means for solving such a problem, as shown in FIG. 8, the clock frequency for each of the N-system input clock, the E-system input clock, and the output clock using a signal from a GPS (Global Positioning System) as a reference signal. There is a method of installing an accuracy measuring unit and monitoring MTIE (Maximum Time Interval Error). That is, as shown in FIG. 8, as a clock frequency accuracy measurement unit, an N-system input MTIE measurement unit 31 that measures an N-system input clock, an E-system input MTIE measurement unit 32 that measures an E-system input clock, and an output clock And an output MTIE measuring unit 33 for measuring. In the clock supply device 21A shown in FIG. 8, the input disconnection monitoring unit 24 shown in FIG. 7 is omitted.

Next, the frequency accuracy measurement function in the MTIE measurement units 31, 32, and 33 will be described. MTIE measuring unit 31, 32, 33 compared with 100 second intervals the frequency f of comparison target clock and high accuracy of the reference frequency _{f 0} transmitted from the GPS receiver 30, "Delta] f (n the difference as a frequency deviation × Δt) / f ₀ ”. However, “0 ≦ n ≦ 100, Δt = 100 seconds”. Then, a sliding window (slide interval: 100 sec) of 10,000 seconds is set, and from this deviation “Δf (n × Δt) / f _0” , TIE (Time Interval Error defined by the following equation at time n × Δt) ) Is obtained.

  101 “TIE; TIE (0), TIE (Δt),..., TIE (99 × Δt), TIE (100 × Δt)” are obtained in 10,000 seconds. The 101 TIEs can be obtained for each of the N system input clock, the E system input clock, and the output clock.

  The MTIE measuring units 31, 32, and 33 impose a threshold value of 10 μsec on the difference (MTIE) between the maximum value and the minimum value of the 101 TIEs, and issue an alarm “EMERGENCY” if the threshold value is exceeded. Since the EMERGENCY alarm related to the output clock is an alarm indicating that an influence is exerted on other apparatuses and lower stations in network synchronization, it triggers maintenance work start.

  When the maintenance person confirms the alarm “EMERGENCY” from the output MTIE measurement unit 33, the maintenance person confirms the EMERGENCY emission status in the other MTIE measurement units 31 and 32, and the clock according to the logic of Table 1 shown in FIG. Switch the input dependency. However, “self-running” in Table 1 indicates a state in which the switch in the input switching unit 25 is not connected to any contact of the N system clock input and the E system clock input.

  In Table 1 shown in FIG. 11A, in “State 1”, the output MTIE measuring unit 33 issues an output clock EMERGENCY signal, and the N system MTIE measuring unit 31 issues an N system input clock EMERGENCY signal. The E system MTIE measuring unit 32 shows a state in which the EMERGENCY signal of the E system input clock is issued. In this “state 1”, the input clock is deteriorated in both the N system and the E system, and thus “self-running” is set.

  In “state 2”, the output MTIE measurement unit 33 issues an EMERGENCY signal of an output clock, the N system MTIE measurement unit 31 issues an EMERGENCY signal of an N system input clock, and the E system MTIE measurement unit 32 inputs an E system input. This shows a state in which the EMERGENCY signal of the clock is not issued. In the case of “state 2”, it is determined that the N-system input clock has deteriorated, and “switch to E-system” is performed as a dependent source of the clock input.

  In the “state 3”, the output MTIE measurement unit 33 issues an EMERGENCY signal as an output clock, the N system MTIE measurement unit 31 does not issue an EMERGENCY signal as an N system input clock, and the E system MTIE measurement unit 32 generates an E system. This shows a state in which the EMERGENCY signal of the input clock is issued. In this “state 3”, it is determined that the failure is caused by the failure of the oscillator unit of the clock supply device, and the clock supply device is maintained without switching the dependent source of the clock input.

  In "state 4", the output MTIE measurement unit 33 issues an EMERGENCY signal of an output clock, the N system MTIE measurement unit 31 does not issue an N system input clock EMERGENCY signal, and the E system MTIE measurement unit 32 generates an E system. This shows a state where the EMERGENCY signal of the input clock is not issued. In this “state 4”, it is determined that the oscillator unit of the clock supply device is out of order, and the clock supply device is maintained without switching the dependent source of the clock input.

Japanese Patent No. 3370258

By the way, Table 1 shown in FIG. 11A is based on the premise that the deterioration of the frequency accuracy occurring at the clock input is static, that is, does not change with time. However, in actuality, the clock distributed by the clock path includes temporal frequency fluctuations (for example, fluctuations in signal frequency due to jitter, wander, etc.) due to fluctuations in temperature, characteristics of transmission devices that pass through, etc. The clock frequency is not originally stable over time. In order to convert this into a stable one, the oscillator unit 26 in the clock supply device 21 has a characteristic that functions as a low-pass filter with respect to fluctuations in signal frequency due to jitter, wander, and the like. That is, it has a function of a low-pass filter that cuts a frequency fluctuation that fluctuates at a predetermined speed or higher, and the cut-off frequency of this low-pass filter is ν _C.

For example, a cutoff frequency “ν _C = 810 μHz” is set, and a frequency deviation at a time t = 0 with respect to a normal clock frequency f ₀ in an N-system input clock of a clock supply device of a certain station A,
Consider a case where a variation of [Δf / f ₀ = 1.001 × 10 ⁻⁹ + 2.0 × 10 ⁻⁷ × 2πν × cos (2πνt), ν = 650 μHz] is given.

  FIG. 9 shows the calculation results of MTIE (unit: nsec) in the N-system input MTIE measurement unit 31 and the output MTIE measurement unit 33 from time t = 0 [sec] to t = 20,000 [sec]. FIG. 10 is an enlarged view of a portion from time t = 8,000 [sec] to t = 18,000 [sec] in FIG. From this result, the EMERGENCY issue status will be described.

  As for the EMERGENCY alarm, since the sliding window described above is at 100 second intervals, the MTIE of the N system input is issued at 10,800 seconds, turned off at 11,600 seconds, recurred at 12,400 seconds, and reissued at 13,100 seconds. After the light is turned off again, this “issue → turn off” is repeated. The output MTIE is issued in 11,000 seconds, turned off in 11,800 seconds, reappeared in 12,500 seconds, turned off again in 13,300 seconds, and this “issue → turn off” is repeated.

  That is, when the maintenance person confirms EMERGENCY, the state defined in Table 1 shown in FIG. 11A depends on the confirmation time as shown in Table 2 shown in FIG. Will do. This complicates maintenance and means that systematic maintenance is not possible. For example, according to Table 2, even if the maintenance person confirms that the state is “state 2” at the time of 11,595 seconds and tries to switch the clock dependent source, the state becomes “state 4” a few seconds later. In this case, the switching is stopped and the oscillator unit of the clock supply device is repaired, but becomes “-: normal” during the work. Accordingly, the maintenance person stops repairing the oscillator unit, but after 700 seconds, the state becomes “state 2” again and preparation for switching the clock dependent source is required.

  In the situation where “state 2” and “state 4” occur repeatedly, for example, “previous stage protection: 3 stages”, that is, if the same event is repeated three times in succession, the event is “state to be resolved”. It is possible to recognize that.

  In this case, by repeatedly generating “state 2” and “state 4”, the maintenance person can recognize that one of the states is “a state to be solved”. However, it cannot be determined whether the state is “state 2” or “state 4”. This means that appropriate maintenance itself is not possible with the prior art against frequency degradation that varies with time. As described above, the maintenance operation start trigger (trigger) is the EMERGENCY alarm of the output clock. As described above, the time change of the emission / extinction, that is, the repetition of “state 2” and “−: normal” This is not a problem because it faithfully represents the influence of other devices and the network synchronization on the lower stations due to the frequency fluctuation applied to. The factor complicating the maintenance is that “state 4” exists as a transition state of the transition from “state 2” to “−: normal”.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a frequency of an input clock in a clock supply device used in a slave synchronization system for matching operation clocks of nodes and devices in a network. It is an object of the present invention to provide a clock supply device that can accurately determine the state of failure of an input clock even when the time fluctuates due to jitter, wander, etc., and enables appropriate maintenance.

The present invention has been made to solve the above-described problems, and the clock supply apparatus of the present invention is used in a slave synchronization system that matches the operation clocks of the respective apparatuses, and is based on an input clock input from the preceding stage. A clock supply device that outputs an output clock that is an input clock input to the next stage, a clock receiving unit that receives the input clock from the network side via a transmission path, and the transmission path based on the input clock An oscillator unit having a low-pass filter characteristic for generating the output clock to be output and suppressing frequency fluctuations of the output clock;
An output frequency at which a first error between the frequency of the output clock and a preset frequency is measured, and when the first error exceeds a predetermined threshold range, information on frequency degradation is issued as a first alarm and precision measuring unit, and the frequency of the input clock, with measures a second error between the preset frequency, if the error exceeds a predetermined threshold range, the second alarm information frequency degradation A clock frequency accuracy measurement unit that emits, and a frequency fluctuation removal filter that is installed between the clock reception unit and the clock frequency accuracy measurement unit and suppresses frequency fluctuations of the input clock, and has the oscillator unit The cut-off frequency of the low-pass filter characteristic coincides with the cut-off frequency of the frequency fluctuation removal filter.

Further, in the clock supply device of the present invention, the braking coefficient and the natural angular frequency in the low-pass filter characteristic of the oscillator unit coincide with the braking coefficient and the natural angular frequency of the frequency fluctuation removal filter. And

In the clock supply device of the present invention, the input clock has two systems, that is, an N-system input clock that is a normal system and an E-system input clock that is a standby system. An N-system clock receiver that receives an input clock and an E-system clock receiver that receives an E-system input clock, and the clock frequency accuracy measurement section includes an N-system input clock and a preset frequency. And an N-system frequency accuracy measurement unit that issues frequency degradation information as a second_N alarm when the second_N error exceeds a predetermined threshold range; and an E-system input clock ; with measuring a second 2_E error between a preset frequency, when the first 2_E error exceeds a predetermined threshold range, E system peripheral to fire a frequency information degraded as a 2_E alarm The number and accuracy measuring section, in the configuration, the frequency rejection filter is a first frequency rejection filter installed between said N system clock receiving unit N based frequency precision measurement unit, the E system And a second frequency fluctuation elimination filter installed between the clock receiving unit and the E-system frequency accuracy measuring unit.

  Further, the clock supply device of the present invention is characterized in that the frequency fluctuation removal filter is configured by a PLL (Phase-locked loop).

The clock supply device of the present invention has a clock frequency accuracy measurement unit that measures the frequency accuracy of the input clock and the output clock, and issues information about the frequency deterioration as an alarm when the frequency accuracy deteriorates below a predetermined threshold. A frequency fluctuation elimination filter that absorbs temporal frequency fluctuation (frequency fluctuation due to jitter or wander) of the input clock is arranged between the clock frequency accuracy measurement section and the clock reception section. And the cut-off frequency of the low-pass filter characteristics in the transmission unit are configured to match.
As a result, the characteristics of the frequency fluctuation removal filter can be easily determined, and even if the frequency of the input clock fluctuates in time due to jitter, wander, etc., this frequency fluctuation removal filter outputs it from the oscillator unit. Can effectively stabilize the output clock. For this reason, it becomes possible to accurately determine the state of the failure of the input clock, and appropriate maintenance becomes possible.

Also, the clock supply device of the present invention is configured such that the braking coefficient of the low-pass filter characteristic possessed by the oscillator unit matches the braking coefficient possessed by the frequency fluctuation removal filter.
As a result, the characteristics of the frequency fluctuation removal filter can be easily determined, and even when the frequency of the input clock fluctuates rapidly in time due to jitter, wander, etc., the output clock can be changed. It can be stabilized effectively. For this reason, it becomes possible to accurately determine the state of the defect, and appropriate maintenance becomes possible.

In the clock supply device of the present invention, the frequency fluctuation removal filter includes a first frequency fluctuation removal filter and a second fluctuation removal filter, and is arranged between the N system clock receiving unit and the N system frequency accuracy measurement unit. The first frequency fluctuation removal filter is installed in the second system, and the second frequency fluctuation removal filter is installed between the E system clock receiving unit and the E system frequency accuracy measurement unit.
As a result, in a clock supply device having an N / E (normal / standby) redundant configuration, even when the frequency of an N-system or E-system input clock fluctuates with time due to jitter, wander, etc., It becomes possible to accurately determine the state of the defect, and appropriate maintenance becomes possible.

In the clock supply device of the present invention, the frequency fluctuation removal filter is configured by a PLL (Phase-locked loop).
Accordingly, a PLL can be used as the frequency fluctuation removal filter, and the frequency fluctuation removal filter can be easily configured using a known technique.

It is a figure which shows the structure of the clock supply apparatus which concerns on embodiment of this invention. It is a figure which shows the structural example of a wander jitter removal filter. It is a figure which shows the difference of the filter characteristic by the setting of parameter ((alpha), (beta)). It is a figure which shows the relationship between the EMERGENCY confirmation time and the state shown in Table 1. It is a figure for demonstrating the network synchronization by a subordinate synchronization system. It is a figure which shows the structural example of the node in the conventional network. It is a figure which shows the structural example of the conventional clock supply apparatus. It is a figure which shows the detailed structure of the conventional clock supply apparatus. It is a figure which shows the example of the fluctuation | variation of MTIE when the frequency deviation which fluctuates in time is applied. It is the figure which expanded and showed the time area (8000 second-18000 second) shown in FIG. It is a figure which shows the relationship of the alert issue status of a MTIE measurement part, and dependent element switching.

Embodiments of the present invention will be described below with reference to the accompanying drawings.
FIG. 1 is a diagram showing a configuration of a clock supply apparatus that uses a plurality of stages connected in cascade in a slave synchronization system according to an embodiment of the present invention. The clock supply device according to the present embodiment is used in a slave synchronization system that matches the operation clocks of the devices, and is used as an output clock that is used as an input clock of the next stage by an input clock input from the previous stage (subordinate source). A clock is generated and output to the next stage through a transmission line.
The clock supply device 21 shown in FIG. 1 differs from the conventional clock supply device 21A shown in FIG. 8 in terms of configuration as a frequency fluctuation removal filter that removes wander and jitter from the clock supply device 21A shown in FIG. The wander / jitter elimination filters 41 and 42 shown in FIG. 1 are newly added, and the other configurations are the same as those of the clock supply device 21A shown in FIG. For this reason, the same code | symbol is attached | subjected to the same component and the overlapping description is abbreviate | omitted.

  In the clock supply device 21 shown in FIG. 1, the wander / jitter removal filter 41 is installed between the N-system clock receiver 22 and the N-system input MTIE measurement section 31. The wander / jitter elimination filter 42 is installed between the E system clock receiving unit 23 and the E system input MTIE measurement unit 32.

  FIG. 2 is a diagram illustrating a configuration example of the wander / jitter removal filters 41 and 42. The wander / jitter removal filter shown in FIG. 2 includes a PLL (Phase-locked loop). This wander / jitter elimination filter includes a frequency divider A51, a phase comparator 52, a digital filter (integrator) 53, a voltage controlled oscillator (VCXO) 54, and a frequency divider B55. .

  FIG. 2 shows an example of a wander / jitter removal filter 41 (or 42) provided for an N-system clock input (or E-system clock input) signal.

  In the wander / jitter elimination filter shown in FIG. 2, the frequency divider A51 converts the N-system clock input (or E-system clock input) signal to the input clock frequency (here, 8 kHz) to the phase comparator 52. The frequency divider B55 makes the output frequency of the voltage controlled oscillator 54 coincide with the input clock frequency to the phase comparator 52.

The phase comparator 52 compares the phase of the N-system clock input (or E-system clock input) signal via the frequency divider A51 and the output signal of the voltage controlled oscillator 54 via the frequency divider B55, and compares the result. The digital value is sent to the digital filter unit 53. The digital filter unit 53 averages the phase comparison result over time, integrates (integration coefficient β), and outputs the integration result to the voltage controlled oscillation unit 54 as a digital value. The voltage controlled oscillating unit 54 outputs the input digital value with a gain (α) corresponding to the frequency one to one. The wander frequency characteristics of the PLL by these α and β, that is, “wander cutoff frequency = α / (2π) Hz”, “natural angular frequency = (α · β) ^1/2 ”, “braking coefficient = (1/2 ) · (Α / β) ^1/2 ”is determined.

  As examples of the present invention, examples of selecting the wander cutoff frequency α and the integration coefficient β described above will be given below.

  In the first embodiment of the present invention, only the wander cut-off frequency α of the wander cut-off frequency α and the integral coefficient β in the wander / jitter removal filter shown in FIG. The value is equal to or substantially equal to the cutoff frequency of the low-pass filter characteristic. That is, the “wander cutoff frequency = α / (2π) Hz” of the wander / jitter removal filter is made to coincide with or substantially equal to the cutoff frequency of the low-pass filter characteristic of the oscillator unit 26 in the clock supply device 21. Select α.

In the second embodiment of the present invention, both the wander cutoff frequency α and the integral coefficient β in the wander / jitter elimination filter shown in FIG. 2 match those of the low-pass filter characteristics of the oscillator unit 26 in the clock supply device 21. Let That is, the “wander cutoff frequency = α / (2π) Hz”, “natural angular frequency = (α · β) ^1/2 ”, “braking coefficient = (1/2) · (α / Β) ^1/2 ”is selected to match the low-pass filter characteristic of the oscillator unit 26 in the clock supply device 21.

  FIG. 3 shows a case where only the wander cutoff frequency α of the wander / jitter removal filter is matched with the filter characteristics of the oscillator unit in the clock supply device (in the case of the first embodiment), and the cutoff frequency α and the integration coefficient β. The difference in characteristics when both are matched (in the case of Example 2) is shown.

FIG. 3 shows the output of the filter generated every 100 seconds when a signal having a frequency deviation “Δf / f ₀ = 1.0 × 10 ⁻⁷ ” is applied to the input frequency f ₀ from time t = 0. It represents the time interval (nsec) with respect to the reference signal (frequency f ₀ ).

As shown in FIG. 3, when only the wander cutoff frequency α is matched or substantially equal (in the case of the first embodiment), when both the cutoff frequency α and the integral coefficient β are matched or substantially equal, that is, the braking coefficient is The transient response when a frequency deviation is input is different from that in the case where they are coincident or substantially equal (in the case of the second embodiment). The difference in transient response increases as the frequency deviation and the steepness of application increase.
Taking this transient response into account, even if the frequency fluctuates rapidly due to jitter, wander, etc., the frequency fluctuation characteristics of the input clock are changed to the frequency fluctuation characteristics of the clock input to the output clock frequency accuracy measurement section. Example 2 is used when it is desired to match.
On the other hand, when the frequency variation due to jitter, wander, etc. does not occur so rapidly in time, the output clock from the transmitter can be stabilized even with the first embodiment, and the frequency variation characteristic of the input clock Can be matched with the frequency variation characteristic of the clock input to the frequency accuracy measurement unit of the output clock. In the case of the first embodiment, only the wander cutoff frequency α needs to be matched or substantially equal, and it is not necessary to match or be substantially equal to the integral coefficient β. It becomes possible to combine the thing of a price, and it can be comprised cheaply in price with respect to Example 2. FIG.

  As described above, with the clock supply device of the present invention, the frequency variation characteristic of the clock when the input clock frequency is measured by the clock frequency accuracy measurement unit is the same as that of the clock input to the clock frequency accuracy measurement function of the output clock frequency. Consistent with frequency fluctuation characteristics. Thereby, for example, the case of Table 2 shown in FIG. 4A becomes as shown in Table 3 shown in FIG.

  As shown in Table 3 in FIG. 4B, since the state 3 which is a transient state due to the difference in the frequency variation characteristic of the input clock is suppressed, “previous stage protection: 3 stages” is provided as described above. Then, at the time of 14,000 seconds, the “switch to the E system clock dependent source” that is the maintenance action for “state 2” can be performed.

  According to the present invention, it is possible to suppress a transient state caused by a difference in frequency variation characteristics of an input clock with respect to an output clock that is a trigger (trigger) for starting a maintenance operation, and it is also suitable for a clock input that varies with time. Maintenance is possible.

  The clock supply device 21 shown in FIG. 1 has a computer system inside. (Here, “computer system” includes an OS and hardware such as peripheral devices.)

  A series of processes related to the above-described process is stored in a computer-readable recording medium in the form of a program, and the above-described process is performed by the computer reading and executing this program.

  That is, each processing in the clock supply device 21 is realized by a central processing unit such as a CPU reading the above program into a main storage device such as a ROM or a RAM and executing information processing and arithmetic processing. Is. (Of course, each processing unit in the clock supply device 21 may be realized by dedicated hardware.)

  Here, the computer-readable recording medium means a magnetic disk, a magneto-optical disk, a CD-ROM, a DVD-ROM, a semiconductor memory, or the like. Alternatively, the computer program may be distributed to the computer via a communication line, and the computer that has received the distribution may execute the program.

  Further, it is assumed that an input device, a display device, and the like (none of them are displayed) are connected to the clock supply device 21 as peripheral devices. Here, the input device refers to an input device such as a keyboard and a mouse. The display device refers to a CRT (Cathode Ray Tube), a liquid crystal display device, or the like.

  The embodiment of the present invention has been described above. In the clock supply device 21 shown in FIG. 1, the clock receiving unit described above includes an N-system clock receiving unit 22 that receives an N-system input clock, and an E-system input. This corresponds to the E-system clock receiver 23 that receives the clock. The clock frequency accuracy measurement unit described above includes an N-system MTIE measurement unit 31 that measures the output frequency accuracy of the N-system input clock, and an E-system MTIE measurement unit 32 that measures the output frequency accuracy of the E-system input clock. This corresponds to the output MTIE measurement unit 33 that measures the output frequency accuracy of the output clock. The frequency fluctuation elimination filter described above corresponds to the wander / jitter elimination filters 41 and 42, the first frequency fluctuation elimination filter is the wander / jitter elimination filter 41, and the second frequency fluctuation elimination filter is the wander / jitter elimination. Each of the filters 42 corresponds.

  The clock supply device 21 shown in FIG. 1 is based on a clock receiver (N-system clock receiver 22 and E-system clock receiver 23) that receives an input clock from the network side via a transmission line, and an input clock. An oscillator unit 26 that generates an output clock to be output to the transmission line, a clock that measures the frequency accuracy of the input clock and the output clock, and issues information about the frequency degradation as an alarm when the frequency accuracy deteriorates below a predetermined threshold Frequency accuracy measurement unit (N system MTIE measurement unit 31, E system MTIE measurement unit 32, output MTIE measurement unit 33), clock reception unit (N system clock reception unit 22 and E system clock reception unit 23), and clock frequency accuracy measurement (N-type MTIE measurement unit 31 and E-type MTIE measurement unit 32), and is a low-pass filter for frequency fluctuations of the input clock. A frequency rejection filter that functions as a filter (wander jitter removal filter 41, 42), configured with a. Here, the clock frequency accuracy measurement unit (N system MTIE measurement unit 31, E system MTIE measurement unit 32, output MTIE measurement unit 33) calculates the difference between the frequency of the input clock or the output clock and a preset reference frequency. If it is detected as an error and this error exceeds a preset threshold range, it is determined that the clock frequency has deteriorated.

  In the clock supply device 21 of the present invention, the input clock has two systems of an N-system input clock that is a normal system and an E-system input clock that is a standby system, and the clock receiver has an N-system input clock. An N-system clock receiver 22 that receives a clock and an E-system clock receiver 23 that receives an E-system input clock. The clock frequency accuracy measurement section is an N-system MTIE measurement section for an N-system input clock. 31, an E-system MTIE measurement unit 32 for an E-system input clock, and an output MTIE measurement unit 33 for an output clock. The frequency fluctuation elimination filter includes an N-system clock reception unit 22 and an N-system MTIE measurement unit 31. And a wander / jitter removal filter 41 installed between the E system clock receiver 23 and the E system MTIE measurement unit 32. A filter 42, in constructed.

  With the above configuration, in the clock supply device using the slave synchronization method that matches the operation clock of each node and each device in the network, even if the input clock fluctuates in time due to jitter, wander, etc. Therefore, it is possible to accurately determine the state, and appropriate maintenance becomes possible.

  Although the embodiments of the present invention have been described above, the clock supply device of the present invention is not limited to the above-described illustrated examples, and various modifications can be made without departing from the scope of the present invention. Of course.

DESCRIPTION OF SYMBOLS 11 Node 12 Transmission apparatus 13 Exchange | exchange 21, 21A Clock supply apparatus 22 N system clock receiving part 23 E system clock receiving part 24 Input disconnection monitoring part 25 Input switching part 26 Oscillator part 27 Distribution part 30 GPS receiver 31 N system input MTIE measurement Unit 32 E system input MTIE measurement unit 33 Output MTIE measurement unit 41, 42 Wander / jitter elimination filter 51 Frequency division unit A
52 Phase Comparator 53 Digital Filter 54 Voltage Control Oscillator 55 Divider B

Claims (4)

A clock supply device that is used in a subordinate synchronization method for matching the operation clocks of each device and outputs an output clock that is an input clock input to the next stage based on an input clock input from the previous stage.
A clock receiver for receiving the input clock from the network side via a transmission line;
An oscillator unit having a low-pass filter characteristic that generates the output clock to be output to the transmission line based on the input clock and suppresses frequency fluctuation of the output clock;
An output frequency at which a first error between the frequency of the output clock and a preset frequency is measured, and when the first error exceeds a predetermined threshold range, information on frequency degradation is issued as a first alarm An accuracy measurement unit;
The frequency of the input clock, with measures a second error between the preset frequency, if the error exceeds a predetermined threshold range, the clock frequency accuracy to fire a frequency information degraded as a second alarm A measurement unit;
A frequency fluctuation removing filter that is installed between the clock receiving section and the clock frequency accuracy measuring section and suppresses frequency fluctuation of the input clock;
With
The clock supply device according to claim 1, wherein a cut-off frequency of the low-pass filter characteristic of the oscillator unit and a cut-off frequency of the frequency fluctuation removal filter coincide with each other. And the damping coefficient and the intrinsic angular frequency of the low-pass filter characteristics in which the oscillator unit has a damping factor and natural angular frequency having the said frequency rejection filter is matched,
The clock supply apparatus according to claim 1. The input clock has two systems of an N system input clock which is a normal system and an E system input clock which is a standby system.
The clock receiver
An N-system clock receiver for receiving an N-system input clock;
An E-system clock receiver for receiving an E-system input clock;
Consists of
The clock frequency accuracy measurement unit
N-system frequency that measures the second_N error between the N-system input clock and a preset frequency, and issues frequency degradation information as a second_N alarm when the second_N error exceeds a predetermined threshold range An accuracy measurement unit;
E system frequency that measures the second_E error between the E system input clock and a preset frequency, and issues information on frequency degradation as a second_E alarm when the second_E error exceeds a predetermined threshold range An accuracy measurement unit ;
In is configured,
The frequency fluctuation elimination filter is
A first frequency fluctuation elimination filter installed between the N system clock receiving unit and the N system frequency accuracy measurement unit;
A second frequency fluctuation elimination filter installed between the E system clock receiving unit and the E system frequency accuracy measurement unit;
The clock supply device according to claim 1, wherein the clock supply device is configured as follows. The frequency fluctuation elimination filter is configured by a PLL (Phase-locked loop).
The clock supply device according to claim 1, wherein the clock supply device is provided.

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