JP2000341257A - Frequency deviation detector, transmitter and frequency deviation detection method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To check a frequency deviation through the use of a frequency deviation circuit by using an oscillator in a detector for a reference clock source even when the detector receives no reference clock from the outside of the detector. SOLUTION: This detector is provided with frequency deviation detection circuits 6A-6E that detect frequency deviation of a reference clock, an oscillator 10 that generates the reference clock, and a monitor section 9 that selects the reference clock when judging the reference clock received from the outside of the detector to be normal and selecting the reference clock generated from the oscillator 10 when judging that the reference clock received from the outside of the detector is not normal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency deviation detecting device, a transmission device, and a frequency deviation detecting method, and more particularly to a frequency deviation suitable for detecting a frequency deviation even when a reference clock is not input into the device from outside the device. The present invention relates to a detection device, a transmission device, and a frequency deviation detection method.

[0002]

2. Description of the Related Art A conventional frequency deviation detecting circuit is disclosed in, for example, Japanese Patent Application Laid-Open No. 8-331109 (Japanese Patent No. 28561).
No. 08). This publication is intended to flexibly change the detection condition of the frequency deviation, and includes a counter that counts for a predetermined period according to a currently used reference clock, and upper K bits (counter) of the count value of the counter. K is an integer of 2 or more), the deviation determination means for detecting whether the repetition frequency of the reference clock deviates from the original frequency by detecting the identity of each bit, and the counter enters a free-run state. And a means for stopping the counting operation of the counter when the count value reaches a predetermined value. That is, in the prior art described in the publication, a clock input from the outside of the device to the inside of the device is used as a reference clock for frequency deviation detection.

As a conventional example of monitoring a frequency using a clock input from the outside of the apparatus to the inside of the apparatus and an internal reference clock, for example, a technique described in Japanese Patent Application Laid-Open No. H8-8889 has been proposed. The publication is intended to accurately determine the state of each external clock and to perform stable clock switching control, and a counting means for measuring a predetermined last pulse width of the external clock using an internal reference clock; Clock frequency monitoring means for judging whether the external clock frequency is normal or abnormal based on the count value of the counting means and outputting alarm information for frequency monitoring according to the judgment result, and an external clock based on the contents of the alarm information for frequency monitoring. And a clock state monitoring control means for outputting a command for selecting an external clock supplied according to the priority of a clock to be used as a synchronization reference, and a clock selection switching means for selecting and switching the external clock according to the command. An external synchronization device characterized by the following is disclosed.

[0004]

However, the above-described prior art has the following problems.

That is, an apparatus having a configuration in which a clock input from the outside of the apparatus to the inside of the apparatus is used as a reference clock for frequency deviation detection as in the conventional example disclosed in Japanese Patent Application Laid-Open No. 8-331109 (Japanese Patent No. 2856108). In the case where the reference clock is not input into the device from outside the device,
There is a problem that frequency deviation cannot be determined.

An object of the present invention is to determine a frequency deviation using a frequency deviation circuit by using an oscillator mounted in the device as a reference clock source even when a reference clock is not input into the device from outside the device. It is an object of the present invention to provide a frequency deviation detection device, a transmission device, and a frequency deviation detection method that can perform the operation.

[0007]

According to the present invention, there is provided a frequency deviation detecting apparatus for detecting whether or not a repetition frequency of a reference clock deviates from an original frequency. Frequency deviation detecting means for detecting a frequency deviation of the reference clock generated by the oscillating means or a reference clock inputted from outside of the apparatus; and control means for selecting a reference clock used for the frequency deviation detection. And

Further, the present invention provides a transmission apparatus for network synchronization, comprising: an oscillating means for generating a reference clock for operation of the apparatus; and an oscillator for generating the reference clock generated by the oscillating means or a reference clock inputted from outside the apparatus. Frequency deviation detecting means for performing frequency deviation detection, and selecting the reference clock when the reference clock input from the outside of the device is determined to be normal, and determining that the reference clock input from the outside of the device is not normal. And control means for selecting the reference clock generated by the oscillation means.

A frequency deviation detecting apparatus according to the present invention, which will be described with reference to FIG. 1, is a frequency deviation detecting apparatus for detecting whether a repetition frequency of a reference clock deviates from an original frequency. Oscillating means (10 in FIG. 1) for internally generating a reference clock, and frequency deviation detecting means (6A in FIG. 1) for detecting a frequency deviation of the reference clock generated by the oscillating means or a reference clock inputted from outside the device. 6E) and control means (9 in FIG. 1) for selecting a reference clock used for the frequency deviation detection.

The transmission device of the present invention, which will be described with reference to FIG.
Oscillating means (10 in FIG. 6) for generating a reference clock for device operation, and frequency deviation detecting means (FIG. 6) for detecting a frequency deviation of the reference clock generated by the oscillating means or a reference clock inputted from outside the device. 6) and when the reference clock input from the outside of the device is determined to be normal, the reference clock is selected, and when it is determined that the reference clock input from the outside of the device is not normal, the reference clock is generated by the oscillation means. Control means (9 in FIG. 6) for selecting the reference clock to be used.

[Operation] The frequency deviation detecting apparatus of the present invention comprises:
Control is performed so as to select a reference clock generated by an oscillating means inside the device or a reference clock input from outside of the device as a reference clock for frequency deviation detection. For this reason, even when a reference clock is not input from the outside of the device to the inside of the device, the frequency deviation can be detected by selecting the reference clock generated by the oscillation unit mounted inside the device as the reference clock. .

Further, the transmission device of the present invention selects the reference clock when it determines that the reference clock input from outside the device is normal, and determines that the reference clock input from outside the device is not normal. Controls to select a reference clock generated by an oscillating means mounted on the device. For this reason, it becomes unnecessary to mount an oscillator dedicated to frequency deviation detection on the device.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS [First Embodiment] Next, an embodiment of the present invention will be described in detail with reference to the drawings.

(1) Description of Configuration FIG. 1 is a block diagram showing an example of the configuration of an improved frequency deviation detection device according to the first embodiment of the present invention. In FIG. 1, the improved frequency deviation detecting device according to the first embodiment of the present invention includes a plurality of frequency deviation detecting circuits 6A to 6E, a monitoring unit 9, an internal oscillator 10, and a reference clock SEL (selector) 120. . In the figure, 101-1 to 101-3 are synchronization clock signals, 102-1 to 102-2 are synchronization clocks,
102-3 indicates a clock signal.

Here, the internal oscillator 10 is arranged in a base station of a mobile communication device, a relay station of an optical fiber network, a base station for satellite communication, or the like, and is provided with independent equipment using, for example, a cesium atom oscillator or a rubidium atom oscillator. A clock oscillator is preferable. When an external clock is present, the crystal oscillator is used to synchronize the external clock with a PLL circuit or the like, and when no external clock is input, the clock is operated in a free-run state to prevent frequency deviation. To detect.

In the first embodiment of the present invention, the clock signal 102-3 from the oscillator 10 mounted in the improved frequency deviation detecting device is used as a reference clock selection circuit SEL1.
20 so that it can be selected as a reference clock for frequency deviation detection. Each clock signal is input to frequency deviation detection circuits 6A to 6E provided in the improved frequency deviation detection device, and the frequency deviation detection circuits 6A to 6E are configured to detect the frequency deviation. .

The detection result 117 is reported to the monitoring unit 9 in the improved frequency deviation detecting device. A control signal 8 is sent from the monitoring unit 9 and the reference clock selection circuit SE
It is configured to operate L120. By this control, a reference clock is selected, and each of the detection circuits 6A to 6E
Is input to The control signal 8 is also used as a detection prohibition signal so that the frequency deviation detection of the currently selected one of the reference clock signals 102-1 and 102-2 is not performed. The operation of the reference clock selection circuit SEL120, that is, the part improved by the present invention will be described later with reference to the flowchart of FIG.

FIG. 2 is a block diagram showing a connection state between the improved frequency deviation detecting device according to the first embodiment of the present invention shown in FIG. 1 and another device. The improved frequency departure detection device 1 is connected to the other devices 21, 22, and 23 via signal lines to which the synchronization clock signals 101-1, 101-2, and 101-3 are supplied from the other devices 21, 22 and 23. 23 respectively. In addition, the improved frequency deviation detection device 1 receives high-precision synchronization clocks 102-1 and 102-2, respectively. The high-precision synchronization clocks, that is, the reference clocks 102-1 and 102-2 are supplied to the clock supply device 2 using a cesium atomic oscillator or a rubidium oscillator, for example.
4 and 25 respectively.

Although the above-described conventional example is effective for the improved frequency deviation detecting device 1, frequency deviation detection cannot be performed by a device to which a high-precision synchronization clock signal is not supplied (for example, an adjacent device). On the other hand, it can be detected by the improved frequency departure detection device in the first embodiment of the present invention. The other device is, for example, a transmission device that configures network synchronization, and is an SDH (Synchronous Digital Hierarchy).
archy) device is applicable, and is more effective in the case of the dependent synchronization method of synchronizing with other devices than the independent synchronization method of independently synchronizing in each country.

Here, FIG. 3 shows an example of the frequency deviation detecting circuit used in the first embodiment of the present invention, and FIG. 4 is a timing chart of a main part of the frequency deviation detecting circuit.

The frequency departure detection circuit 6 outputs the clock signal 1
A frequency dividing circuit 103 that divides the frequency of the clock signal 01 to output a detection time clock pulse 118, and an edge detecting circuit 104 that detects the rising edge of the output clock pulse 118 with the reference clock signal 102 and sends it out as a load signal 119. A down counter 106 in which a load value 105 is loaded in response to the input of the load signal 119 and counts down according to the reference clock 102, and a case where the deviation of the repetition frequency is large using the upper 12 bits of the output count value. A detection circuit 112 for detecting, a comparison circuit 107 for detecting a case where the repetition frequency is low using the lower 10 bits of the output count value, and a free-run state of the down counter 106 using the upper 12 bits of the output count value. Counter free run detection circuit 11
1 and an OR circuit 116 to which alarms from these circuits are input.

(2) Description of Operation Next, the operation of the first embodiment of the present invention will be described with reference to FIGS.
This will be described in detail with reference to FIGS.

In FIG. 3, a synchronization clock signal 101
Is divided by the frequency dividing circuit 103 to generate a detection time clock pulse signal 118. The generated detection time clock pulse signal 118 is input to the edge detection circuit 114, and the edge is detected by the reference clock 102. By this detection, one pulse synchronized with the reference clock is transmitted as a load signal 119 to the down counter 106.

In the down counter 106, the load signal 1
Upon receiving 19, the countdown of a load value predetermined based on the frequency of the reference clock signal 102 is started. This load value is determined by the repetition frequency value of the reference clock 102, and is 21 bits in this example. However, the load value is a value obtained by subtracting “1” from the count value for the frequency in consideration of the detection error.

For example, when the original value corresponding to the repetition frequency value of the reference clock 102 is “FFFF” (H), “FFFE” (H) obtained by subtracting “1” is used as the load value. The down counter 106 counts down from the load value according to the reference clock 102,
The countdown is continued until the next load signal 119 is input. Then, when the count value ends with “0000” (H), it can be determined that the frequency is a normal frequency with no frequency deviation.

Here, the determination of the frequency deviation detection in the first embodiment of the present invention is divided into two. One is when the frequency deviation is large, and the other is when the frequency deviation is small.

Referring again to FIG. 3, the determination when the frequency deviation is large is performed using the upper 12 bits 110 of the 21 bits which are the output count value. That is, when the frequency deviation is large, the value of the upper 12 bits 110 does not become all “1” or all “0”, and this is detected by the large frequency deviation detection circuit 111. In particular,
The exclusive OR of the upper 12 bits is used to detect the identity of each of the 12 bits. As a result, the top 1
If the two-bit value is not all “1” or all “0”, an alarm (alarm) 114 is sent. This detection is detected at the time of the rising edge of the load signal 119. In this example, 12 bits are used.

When the frequency deviation is small, the lower 10 bits out of the 21 bits which are the output of the count value are determined.
9 is performed. The lower 10 in the comparison circuit 108
The bit is compared with the set detection value 108 to detect the magnitude relationship between the two. The lower 10 bits are the set value 108
If it is larger, an alarm (alarm) 115 is sent from the comparison circuit 107. In this example, 12 bits are used. However, the present invention is not limited to this value.

Here, when the reference clock signal 102 is 1.5
It is assumed to be 44 [MHz]. Then, the detectable range of the lower 10 bits is 1 ÷ (1.54
4) Since (1,000,000) = 0.647 ppm, 0.647 × 1024 = 663p per 10 bits
pm. In this example, a frequency deviation larger than this value is assumed to be a case where the frequency deviation is large. Conversely, a frequency deviation smaller than this value is defined as a case where the frequency deviation is small. ppm means parts per million.

By the way, the frequency of the synchronization clock signal 101 may become extremely low or even completely disappear. In such a case, the change point of the clock signal disappears, and one cycle of the clock pulse signal 118 for detection determination becomes about several tens of seconds.
6 could count down forever.
In order to cope with such a case, in this example, a counter free-run detection circuit 111 for detecting the free-run state of the down counter 106 is provided. When the count reaches a certain counter value, an alarm (alarm) 113 is sent out and the counting operation of the down counter 106 is stopped.

The alarm 1 of the detection circuit 111 described above
13. Alarm 114 of detection circuit 112 and comparison circuit 1
The fourteen alarms 115 are input to the OR circuit 116, collected, and sent out as the detection result 117. in short,
In the present detection circuit 6, if the synchronization clock signal 102 does not deviate, the number of clock pulses within the detection time is equal to the frequency of the reference clock 102. Therefore, the count value ends with “0000”, and it can be seen that the synchronous clock has not deviated. Further, the detection value 108 can be arbitrarily changed from the outside, and when it is desired to detect a frequency deviation strictly, that is, when a slight frequency deviation is set as an alarm, the value of the detection value 108 may be reduced. Conversely, if it is not necessary to be strict, the detected value 108
May be increased.

Next, the operation of the main part of FIG. 3 will be described with reference to FIG. FIG. 4 shows a synchronization clock signal 101, a reference clock signal 102, a clock pulse signal 108, and a load signal 119. The synchronizing clock signal 101 is frequency-divided by the frequency dividing circuit 103 to become a clock pulse signal 108 having one cycle of 1 [sec]. This signal is input to the edge detecting circuit 104, and a load signal 119 synchronized with the reference clock 102 is generated. Then, the down-counter 106 is loaded using the load signal 119 as described above.

Next, the characteristic operation of the first embodiment of the present invention will be described. Here, a method of selecting a reference clock used for frequency deviation detection will be described using the reference clock flowchart of FIG.

The monitoring unit 9 of the improved frequency deviation detecting apparatus shown in FIG. 1 determines whether or not the high-accuracy synchronization clock signal 1 system 102-1 input from the outside of the apparatus to the inside of the apparatus is normal. A determination is made (step S51). If it is determined to be normal, it is selected as the reference clock and the reference clock SE
L120 is controlled (step S52). If it is determined that there is an abnormality (including a state where no input has been made), it is determined whether or not the high-accuracy synchronization clock signal 2 system 102-2 is normal (step S53). If it is determined to be normal, it is selected as a reference clock and the reference clock SEL1
20 is controlled (step S54). When both the synchronization clock signal 1 system and the synchronization clock signal 2 system are abnormal, the clock signal 102-3 output from the oscillator 10 in the device is selected as a reference clock (step S55).

The monitoring unit 9 of the improved frequency deviation detecting device performs the processing of this flowchart at a constant cycle, and the reference clock of the synchronization clock signal 1 or 2 which has been abnormal has returned to normal. In this case, a high-accuracy synchronization clock signal 1 system or a synchronization clock signal 2 system is selected. Generally, since the synchronization clock signals 102-1 to 102-2 from the outside of the device are several times higher in accuracy than the clock signal 102-3 of the oscillator 10 mounted in the device, a frequency with higher accuracy is obtained. In order to perform the deviation detection, the oscillator 10 is set in the flow state to perform such processing.

According to the first embodiment of the present invention, even when a reference clock is not input from the outside of the device, a reference clock generated by an oscillator mounted inside the device is selected as the reference clock. Thus, there is an effect that a frequency deviation can be detected.

In this embodiment, the above-mentioned Japanese Patent Application Laid-Open No. 8-331109 (Japanese Patent No. 2856108)
The difference from the technology described in the above is that a sophisticated atomic oscillator is provided inside the device and a selection circuit for a sophisticated clock signal from the outside and the internal clock oscillator 10 is provided. Since the output can be detected based on the output of the clock oscillator 10, the reliability of communication can be kept high by installing this frequency deviation detection circuit in an upper exchange or a base station that needs to guarantee 24-hour operation.

[Second Embodiment] Next, a second embodiment of the present invention will be described in detail with reference to the drawings.

(1) Description of Configuration FIG. 6 is a block diagram showing an example of the configuration of a synchronization section in a transmission apparatus constituting network synchronization according to the second embodiment of the present invention. In FIG. 6, the synchronization unit of the transmission device according to the second embodiment of the present invention includes:
Frequency deviation detection circuit 6, monitoring unit 9, synchronization clock SE
An L (selector) 30, a PLL (Phase Locked Loop) unit 32, and a reference clock SEL (selector) 102 are provided. In the figure, reference numerals 101-1 to 101-3 denote synchronization clock signals, and reference numerals 102-1 to 102-2 denote high-precision synchronization clock signals. In FIG. 6, the same components as those in FIG. 1 are denoted by the same reference numerals.

In the second embodiment of the present invention, the selected synchronization clock signal is detected to have a frequency deviation, and when the abnormality is detected, switching of the synchronization clock signal is executed.

(2) Description of Operation Next, the operation of the second embodiment of the present invention will be described in detail with reference to FIG.

The clock signal 3 selected by the synchronization clock SEL 30 under the control of the monitoring unit 9 of the synchronization unit of the transmission device
1 is distributed as an internal operation clock signal through the PLL unit 32. The clock signal 31 is monitored by the frequency deviation detection circuit 6, and the detection result 117 is notified to the monitoring unit 9. When the monitoring unit 9 determines that an abnormality has occurred based on the notified detection result 117, the monitoring unit 9 controls the synchronization clock SEL 30 with the control signal 34, selects another synchronization clock signal, and sets it as the device operation clock signal.

The reference clock selection circuit SEL102 includes:
High-precision synchronization clock signals 102-1 to 102-2 input from the outside of the device to the inside of the device and a clock signal 102-3 from the oscillator 10 inside the PLL unit 32 are input. The monitoring unit 9 uses the control signal 8 to output the reference clock SEL.
102 to control the reference clock signal 1 for frequency deviation detection.
Select 20. As described above, the selection order of the reference clock SEL 102 is such that the high-precision synchronization clock signals 102-1 to 102-2 from the outside are preferentially selected, and both of them have a failure (including a state that has not been input in advance). In this case, the clock signal 102-3 from the oscillator 10 is selected. The PLL unit 32 has a built-in internal reference clock oscillator 10. When a reference clock signal is used from outside the device, the PLL unit 32 synchronizes the reference clock external to the device with a PLL circuit to obtain a synchronous clock in the device. When there is no reference clock from the outside of the device, the oscillation frequency and stability of the clock oscillator 10 are used as references.

According to the second embodiment of the present invention, the oscillator for operating the device mounted on the transmission device for synchronizing the communication network is provided with the third oscillator.
Since the reference clock is selected, there is an advantage that it is not necessary to mount an oscillator dedicated to frequency deviation detection in the device. When used for switching the synchronization clock signal as in the second embodiment of the present invention, the synchronization clock SE is used.
By detecting the clock signal 31 selected in L30, the frequency deviation detection circuit can be made one, and there is no need to prepare a plurality of frequency deviation detection circuits, so that the circuit scale can be reduced.

The detection circuits 6AA,... Of the frequency departure detection circuit of FIG. 1 described in the first embodiment. . 6E is FIG.
The output of each of the detection circuits in FIG. 1 can be output as one of the clock signals 31 by a clock selection circuit for operation in the apparatus.

[0046]

As described above, according to the frequency deviation detecting apparatus of the present invention, the reference clock generated by the oscillating means inside the apparatus or the reference clock inputted from outside of the apparatus is selected as the reference clock for detecting the frequency deviation. Therefore, even if a reference clock is not input from outside the device to the inside of the device, by selecting a reference clock generated by the oscillating means mounted inside the device as the reference clock, the frequency deviation is controlled. Has the effect of being able to detect

According to the transmission apparatus of the present invention, when it is determined that the reference clock input from the outside of the apparatus is normal, the reference clock is selected, and it is determined that the reference clock input from the outside of the apparatus is not normal. In this case, since control is performed so as to select a reference clock generated by the oscillating means mounted on the device, there is an effect that it is not necessary to mount an oscillator dedicated to frequency deviation detection on the device.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration example of an improved frequency deviation detection device according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a connection state between the improved frequency deviation detection device according to the first embodiment of the present invention and another device.

FIG. 3 is JP-A-8-3 cited in the first embodiment of the present invention.
FIG. 1 is a block diagram illustrating a configuration of a frequency deviation detection circuit disclosed in Japanese Patent No. 31109 (Japanese Patent No. 2856108).

FIG. 4 is JP-A-8-3 cited in the first embodiment of the present invention.
31 is a timing chart of a main part of a frequency deviation detection circuit disclosed in Japanese Patent No. 31109 (Patent No. 2856108).

FIG. 5 is a flowchart showing a reference clock selection process in the improved frequency deviation detection device according to the first embodiment of the present invention.

FIG. 6 is a block diagram illustrating a configuration example of a synchronization unit in a transmission device configuring network synchronization according to a second embodiment of the present invention.

[Explanation of symbols]

 6A to 6E Frequency deviation detection circuit 9 Monitoring unit 10 Oscillator 30 Synchronization clock SEL 32 PLL unit 102, 120 Reference clock SEL

Claims (6)

[Claims] 1. A frequency deviation detecting device for detecting whether or not a repetition frequency of a reference clock deviates from an original frequency, comprising: an oscillating means for generating a reference clock inside the apparatus; A frequency deviation detecting device, comprising: frequency deviation detecting means for detecting a frequency deviation of a clock or a reference clock input from outside the apparatus; and control means for selecting a reference clock used for the frequency deviation detection. 2. The reference clock input from outside the device is a plurality of high-precision reference clocks supplied from a clock supply device, and the control means gives priority to the reference clock input from outside the device. The frequency deviation detection apparatus according to claim 1, wherein the frequency deviation is selected by selecting the frequency deviation. 3. The control means selects the reference clock when the reference clock input from outside the device is normal, and selects the reference clock when the reference clock input from outside the device is not normal. The frequency deviation detecting device according to claim 1, wherein the reference clock generated by the oscillating means is selected. 4. The frequency deviation detecting means determines whether the frequency deviation is large based on the presence / absence of the identity of a predetermined upper bit in an output count value of a counting means for performing a countdown according to the reference clock inputted from outside the device. 2. The frequency deviation according to claim 1, wherein whether the frequency deviation is small is determined based on a comparison between a predetermined lower-order bit of the output count value of the counting means and a set value. Detection device. 5. A transmission apparatus for network synchronization, comprising: an oscillating means for generating a reference clock for operating the apparatus, and detecting a frequency deviation of the reference clock generated by the oscillating means or a reference clock inputted from outside the apparatus. Frequency deviation detecting means for performing, and selecting the reference clock when it is determined that the reference clock input from outside the device is normal, and selecting the oscillation means when determining that the reference clock input from outside the device is not normal. And control means for selecting the reference clock generated in the step (c). 6. A frequency deviation detecting method for detecting whether or not a repetition frequency of a reference clock deviates from an original frequency, wherein the reference clock is selected when it is determined that a reference clock input from outside the device is normal. A frequency deviation detecting method, wherein when it is determined that the reference clock input from outside the device is not normal, a reference clock generated by an oscillating means inside the device is selected.