JP5259055B2 - Signal transmission circuit - Google Patents

Description

  The present invention relates to a signal transmission circuit, and more particularly to a signal transmission circuit for accurately transmitting a digital signal in a signal transmission path including a delay circuit.

  FIG. 1 is a block diagram of a semiconductor test apparatus disclosed in Japanese Patent Laid-Open No. 11-304888. The semiconductor test apparatus shown in FIG. 1 is an apparatus for supplying various test signals to a semiconductor device (DUT) to be tested. FIG. 1 shows a configuration for supplying a test signal to one pin of the DUT. The conventional semiconductor test apparatus has a plurality of block configurations shown in FIG. 1 corresponding to a plurality of pins of the DUT.

  The block configuration shown in FIG. 1 has a pattern generator PG. The pattern generator PG is a unit for generating a test signal pattern, and includes a normal output terminal that outputs a normal signal and an inverted output terminal that outputs an inverted signal. From the normal output terminal, a digital signal pulsed at a predetermined rate is serially output. Further, the inverted output terminal outputs an inverted signal of the signal output from the normal output terminal.

  A set pulse generator is connected to the normal output terminal of the pattern generator PG. The set pulse generation unit includes a TGD that generates a pulse signal in response to an up-edge of a normal rotation signal supplied from the PG, and variable delay means for giving a desired delay to the pulse signal. For this reason, the set pulse generator 10 outputs a set pulse SP10 with a desired delay with respect to the up edge of the normal rotation signal.

  A reset pulse generator is connected to the inverted output terminal of the pattern generator PG. Similar to the set pulse generation unit, the reset pulse generation unit includes a TGD and variable delay means. Since the reset pulse generator is supplied with the inverted signal from PG, the reset pulse generator outputs a reset pulse RP11 with a desired delay with respect to the up edge of the inverted signal (and therefore with respect to the down edge of the normal signal). To do.

  An SR latch 70 is disposed after the set pulse generator and the reset pulse generator. A set pulse SP10 is supplied to the set terminal S of the SR latch 70. On the other hand, a reset pulse RP11 is supplied to the reset terminal R of the SR latch 70. The SR latch is a device that sets the output terminal Q to the following state according to the states of the S terminal and the R terminal.

S terminal R terminal Q terminal
LL maintenance
HLH
LHL
HH prohibited

  In the above rules, “maintain” means that the previous output Q is maintained. Further, “prohibited” means that since the output Q becomes unstable, it is prohibited to set both the input to the S terminal and the R terminal to H.

  FIG. 2 is a timing chart for explaining the operation of the semiconductor test apparatus shown in FIG. More specifically, the column “SP10” in FIG. 2 indicates the generation timing of the set pulse SP10. “SP11” indicates the generation timing of the reset pulse RP11. The column “W1” indicates a test waveform output from the terminal Q of the SR latch 70.

  The set pulse SP10 is generated in response to the up edge of the normal rotation signal generated from the PG. According to the above rule, upon receipt of the set pulse SP10, the SR latch 70 sets the output of the terminal Q to H. The reset pulse RP11 is generated in response to the down edge of the normal rotation signal generated from the PG. The SR latch 70 receives this reset pulse RP11 and sets the output of the terminal Q to L. As a result, the test waveform W1 is the same digital signal as the normal rotation signal emitted from the PG.

  In the configuration shown in FIG. 1, the test waveform W1 generated by the SR latch 70 is supplied to the pins of the DUT through the driver. Therefore, according to the semiconductor test apparatus shown in FIG. 1, the pattern (forward rotation signal) generated by the pattern generator PG can be supplied to the DUT pin after a desired delay.

JP-A-11-304888

  In the semiconductor test apparatus described above, the SR latch 70 changes the state of the terminal Q in response to the generation of the set pulse SP10 and the reset pulse RP11. That is, the SR latch 70 sets the terminal Q to H when the rising edge of the S terminal is detected, and sets the terminal Q to L when the rising edge of the R terminal is detected.

  The set pulse SP10 rises when a test signal (normal rotation signal) generated by PG rises. Since PG generates test signals in various patterns, there are various variations in the way it rises. Specifically, the rising edge of the test signal may occur following the 1-bit L signal, or may rise after the 6-bit L signal.

  FIG. 3 is a diagram for explaining the relationship between how the test signal rises and how the set pulse SP10 rises. Specifically, FIG. 3A shows the waveform of the set pulse SP10 generated by the set pulse generator when the test signal rises following the 1-bit L signal. FIGS. 3B and 3C show the waveforms of the set pulse SP10 generated when the test signal rises following the 2-bit L signal or the 6-bit L signal, respectively. FIG. 3D is an enlarged view of the rising portion of SP10.

  The variable delay means for giving a desired delay to the set pulse SP10 has a configuration in which buffer amplifiers are connected in multiple stages in series. When the test signal generated by the PG is a 6-bit continuous L signal, the L signal is continuously supplied to the variable delay means during a period corresponding to 6 bits. In this case, the inputs of all the buffer amplifiers constituting the variable delay means converge to a sufficiently low value.

  When the test signal rises in the above situation, a pulse is generated by TGD, and the rise of the pulse is sequentially transmitted to buffer amplifiers connected in multiple stages. At this time, since the input to each of the buffer amplifiers is sufficiently lowered, the rising edge of the pulse is transmitted to the subsequent stage with a relatively long delay. For this reason, a relatively large delay is given to the rising timing of the set pulse SP10 while passing through the variable delay means.

  On the other hand, when the test signal generated by the PG rises after the 1-bit L signal, that is, when the test signal becomes an H signal and then becomes an H signal again with the L signal sandwiched by 1 bit. This causes a situation where the potential is raised again before the input potential of the buffer amplifier is sufficiently lowered. In this case, each buffer amplifier transmits the rising edge of the pulse to the subsequent stage in a short time. As a result, the delay time given to the set pulse SP10 while passing through the variable delay means is relatively short.

  In FIG. 3D, the earliest rising waveform is the waveform of SP10 when the test signal is raised following the 1-bit L signal. Hereinafter, the rise time in this case is referred to as “reference time”. For the reasons described above, when the test signal is raised after the 2-bit L signal, the rising timing of SP10 is delayed by Y1 from the reference timing. When the test signal is raised after the 6-bit L signal, the rising time of SP10 is delayed by Y2 from the reference time.

  As described above, the rising timing of SP10 varies depending on how many bits L signal is maintained before the test signal is raised. This relationship can be expressed as shown in FIG. 4, where the horizontal axis represents the number of bits in which the test signal is maintained as the L signal and the vertical axis represents the delay time from the reference time. Hereinafter, a phenomenon in which a shift occurs in the rising timing of the SP 10 according to the principle described above is referred to as “jitter”.

  In the conventional semiconductor test apparatus shown in FIG. 1, jitter also occurs in the reset pulse RP11. That is, in this device, the reset pulse RP11 changes from L to H in response to the rising edge of the inverted signal generated by PG. Since the pattern generator PG generates an inverted signal in an arbitrary pattern, the number of bits maintained in the L signal before the inverted signal rises changes to various values. For this reason, as described above, the same jitter as that generated in the set pulse SP10 occurs at the rising timing of the reset pulse RP11.

  The jitter of the set pulse SP10 affects the rising timing of the test waveform W1. The jitter of the reset pulse RP11 affects the falling timing of the test waveform W1. Digital signals are generally processed on the assumption that they are synchronized with a clock signal. If the rise or fall time of the test waveform W1 changes greatly due to the influence of jitter, the above assumptions are lost and the DUT cannot be accurately inspected. In this respect, the above-described conventional semiconductor test apparatus is not necessarily ideal as an apparatus for transmitting a test signal to the DUT.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a signal transmission circuit capable of transmitting a digital signal to a subsequent stage of a delay path without causing jitter. .

In order to achieve the above object, a first invention is a signal transmission circuit,
A narrow pulse generating circuit for generating a narrow pulse having a first pulse width in response to a change in a digital signal supplied to the input side;
A delay circuit disposed downstream of the narrow pulse and causing a delay in the transmission of the narrow pulse;
A signal reproduction circuit that reproduces a digital signal in response to a termination side edge among a start side edge and a termination side edge of a narrow pulse output from the delay circuit;
It is characterized by having.

The second invention is the first invention, wherein
The narrow pulse generation circuit includes an up side narrow pulse generation circuit that receives an up edge of a digital signal supplied to an input side and generates a narrow pulse, and a down side that receives a down edge of the digital signal and generates a narrow pulse. Including a narrow pulse generation circuit,
The delay circuit includes an up-side delay circuit disposed downstream of the up-side narrow pulse generation circuit, and a down-side delay circuit disposed downstream of the down-side narrow pulse generation circuit,
The signal regeneration circuit changes the output signal from the first value to the second value in response to the terminal end edge of the narrow pulse output from the up-side delay circuit, and outputs the narrow signal output from the down-side delay circuit. The output signal is changed from the second value to the first value in response to the trailing edge of the pulse.

In a third aspect based on the second aspect, the signal regeneration circuit comprises:
An up-side second narrow pulse generating circuit that receives a terminal-side edge of a narrow pulse output from the up-side delay circuit and generates a narrow pulse having a second pulse width;
A down-side second narrow pulse generation circuit that receives a narrow-side end edge of the narrow pulse output from the down-side delay circuit and generates a narrow pulse having a second pulse width;
The narrow pulse output from the up-side second narrow pulse generating circuit is received by one of a set terminal and a reset terminal, and the narrow pulse output from the down-side second narrow pulse generating circuit is received by the set terminal and SR latch received at the other side of the reset terminal,
It is characterized by including.

  The fourth invention is characterized in that, in the third invention, the second pulse width is narrower than the first pulse width.

The fifth invention is the first invention, wherein
The narrow pulse generation circuit includes a both-edge narrow pulse generation circuit that generates a narrow pulse for both the up edge and the down edge of the digital signal supplied to the input side,
The signal regeneration circuit includes a down-edge triggered T flip-flop that receives an end side edge of a narrow pulse output from the delay circuit and inverts an output signal between a first value and a second value. Features.

  According to the first aspect, the changing point of the digital signal supplied to the input side can be converted into a narrow pulse and supplied to the delay circuit. Since the state of the input signal before the change point is various, the influence of jitter is likely to affect the start side edge of the narrow pulse. On the other hand, since the narrow pulse always ends after the first pulse width, the end edge thereof is hardly affected by jitter. The signal reproduction circuit according to the present invention reproduces a digital signal in response to the trailing edge of a narrow pulse at the subsequent stage of the delay circuit. Therefore, according to the present invention, a digital signal that is not affected by jitter can be transmitted to the subsequent stage of the delay circuit.

  According to the second invention, the up edge of the digital signal supplied to the input side is converted into a narrow pulse by the up side narrow pulse generation circuit, and the down edge of the digital signal is converted by the down side narrow pulse generation circuit. Converted to narrow pulse. These narrow pulses are transmitted by the up-side delay circuit and the down-side delay circuit, respectively. The signal regeneration circuit receives the narrow pulse termination side edge output from the up side delay circuit and the narrow pulse termination side edge output from the down side delay circuit, and inverts the state of the output signal, A digital signal that is not affected by jitter can be reproduced.

  According to the third aspect, the terminal end edge of the narrow pulse output from the up side delay circuit is converted into a narrow pulse by the up side second narrow pulse generating circuit. Also, the terminal end edge of the narrow pulse output from the down side delay circuit is converted into a narrow pulse by the down side second narrow pulse generation circuit. By supplying these narrow pulses to the set terminal and the reset terminal of the SR latch, a digital signal that is not affected by jitter is generated by the SR latch.

  According to the fourth invention, a narrow pulse having a wide pulse width can be supplied to the delay circuit, and a narrow pulse having a narrow pulse width can be supplied to the SR latch. If a pulse having a large width is supplied to the delay circuit, it is possible to prevent the narrow pulse from disappearing in the process of traveling through the pulse. On the other hand, if the narrow pulse width supplied to the SR latch is narrowed, the allowable interval between the set pulse and the reset pulse can be narrowed. That is, the pulse width of the reproduced digital signal can be narrowed. For this reason, according to the present invention, the degree of freedom of the reproduction signal can be increased.

  According to the fifth invention, the up-edge and the down-edge of the digital signal supplied to the input side can be converted into narrow pulses by the double-edge narrow pulse activation circuit. Further, by inputting these narrow pulses to a down-edge triggered T flip-flop after the delay circuit, a digital signal that is not affected by jitter can be reproduced.

Embodiment 1 FIG.
[Configuration of Embodiment 1]
FIG. 5 is a block diagram of the signal transmission circuit 10 according to the first embodiment of the present invention. The signal transmission circuit 10 can be used, for example, as a circuit for transmitting a test signal generated by the pattern generator PG to a pin of a semiconductor device (DUT) to be tested in a semiconductor device test apparatus.

  The signal transmission circuit 10 includes an input terminal 12 that receives an input signal. A digital signal composed of a combination of an L signal and an H signal is serially supplied to the input terminal 12 at a predetermined rate. The digital signal supplied to the input terminal 12 is supplied in parallel to the set pulse transmission circuit 14 and the reset pulse transmission circuit 16.

  The set pulse transmission circuit 14 includes a narrow pulse generation circuit 18. The narrow pulse generation circuit 18 is a circuit that generates a narrow pulse having a first pulse width in response to an up edge of an input signal. In the present embodiment, the first pulse width is a width corresponding to one bit of the digital signal to be transmitted.

  A delay adjustment circuit 20 is connected to the narrow pulse generation circuit 18. The delay adjustment circuit 20 is composed of multistage buffer amplifiers connected in series. Each buffer amplifier outputs an H signal when the signal from the previous stage exceeds the threshold, and outputs an L signal when the signal from the previous stage falls below the threshold. The delay adjustment circuit 20 gives a desired delay to the input signal in the process in which each buffer amplifier sequentially transmits a signal to the subsequent buffer amplifier.

  A second narrow pulse generation circuit 24 is connected to the delay adjustment circuit 20 via an inverter 22. The inverter 22 is a circuit for inverting the signal output from the delay adjustment circuit 20. The second narrow pulse generation circuit 24 is a circuit that receives a rising edge of a signal supplied from the inverter 22 and generates a narrow pulse having a second pulse width. In the present embodiment, the second pulse width is narrower than the first pulse width described above.

  The reset pulse transmission circuit 16 has the same configuration as the set pulse transmission circuit 14 except that an inverter 26 is provided immediately after the input terminal 12. Specifically, the reset pulse transmission circuit 16 includes a narrow pulse generation circuit 28, a delay adjustment circuit 30, an inverter 32, and a second narrow pulse generation circuit 34 subsequent to the inverter 26. These circuits function in the same manner as the narrow pulse generation circuit 18, the delay adjustment circuit 20, the inverter 22, and the second narrow pulse generation circuit 24 included in the set pulse transmission circuit 14, respectively.

  An SR latch 36 is disposed downstream of the set pulse transmission circuit 14 and the reset pulse transmission circuit 16. More specifically, the output of the second narrow pulse generation circuit 24 provided in the set pulse transmission circuit 14 is supplied to the set terminal of the SR latch 36. The output of the second narrow pulse generation circuit 34 included in the reset pulse transmission circuit 16 is supplied to the reset terminal of the SR latch 36. The output of the SR latch 36 is supplied to the output terminal 38.

  The SR latch 36 sets the output to the H level when only the set terminal becomes the H level, and conversely sets the output to the L level when only the reset terminal becomes the H level. The SR latch 36 maintains the previous output level when both the set terminal and the reset terminal are at the L level. Setting both the set terminal and the reset terminal to the H level is a prohibited matter because it makes the output of the SR latch 36 unstable.

  According to the signal transmission circuit of this embodiment, when the narrow pulse is generated from the second narrow pulse generation circuit 24 of the set pulse transmission circuit 14, the output of the SR latch 36 becomes H level. Thereafter, when a narrow pulse is generated from the second narrow pulse generation circuit 34 of the reset pulse transmission circuit 16, the output of the SR latch 36 is inverted to the L level. Thereafter, in response to the second narrow pulse generation circuits 24 and 34 alternately generating narrow pulses, the output of the SR latch 36 repeats inversion between the H level and the L level.

[Setting of first pulse width and second pulse width]
FIG. 6 is a diagram for explaining the width of the narrow pulse generated by the narrow pulse generation circuit 18, that is, the condition that the first pulse width should satisfy. 6 (A), 6 (B), and 6 (C) show the nth to n + 2 stages in the delay adjustment circuit 20 when the first pulse width is sufficiently secured. The waveform of the pulse sequentially transmitted by the buffer amplifier is shown. On the other hand, FIG. 6D, FIG. 6E, and FIG. 6F are sequentially transmitted by the buffer amplifiers of the nth to n + 2 stages when the first pulse width is too small. It is a figure showing a mode that a pulse width becomes narrow gradually in the process of going.

  The n-th stage buffer amplifier starts raising the output signal, that is, the input signal to the (n + 1) -th stage buffer amplifier when the value of the input signal exceeds the threshold value. The nth stage buffer amplifier starts to drop the input signal to the (n + 1) th stage buffer amplifier when the value of the input signal falls below the threshold value. This operation is performed similarly in the (n + 1) th stage buffer amplifier and also in the (n + 2) th stage buffer amplifier.

  As shown in FIG. 6A, when the narrow pulse sufficiently converges to the H level and the L level, the state of convergence is sequentially transmitted to the buffer amplifiers in all stages. Therefore, in this case, the width of the narrow pulse is maintained in the process of traveling through the delay adjustment circuit 20. On the other hand, as shown in FIG. 6D, when the input signal to the n-th stage starts to fall before it sufficiently converges to the H level, the width of the pulse increases as it advances through the delay adjustment circuit 20. It gradually narrows, and eventually a situation occurs where the pulse disappears.

  For this reason, in order to reliably transmit the narrow pulse to the subsequent stage of the delay adjustment circuit 20, the narrow pulse generation circuit 18 needs to generate a narrow pulse having a width sufficient to converge to the H level and the L level. There is. In this embodiment, the delay adjustment circuit 20 has an operation speed corresponding to the rate of the digital signal to be transmitted. That is, the delay adjustment circuit 20 is configured to appropriately transmit a 1-bit width signal generated at the above rate.

  In the present embodiment, the width of the narrow pulse generated by the narrow pulse generating circuit 18, that is, the first pulse width is set to a width corresponding to one bit of the digital signal to be transmitted as described above. For this reason, according to the configuration of the present embodiment, the narrow pulse generated by the narrow pulse generation circuit 18 is reliably transmitted to the subsequent stage of the delay adjustment circuit 20.

  The situation described above is similarly established in the reset pulse transmission circuit 16. For this reason, according to the configuration of the present embodiment, the narrow pulse generated by the narrow pulse generation circuit 28 is reliably transmitted to the subsequent stage of the delay adjustment circuit 30.

  The narrow pulses generated by the second narrow pulse generating circuits 24 and 34 are directly supplied to the SR latch 36 without passing through a delay circuit or the like. The SR latch 36 can detect the H level if the narrow pulse instantaneously exceeds the threshold value. On the other hand, in order to prevent the H level from being simultaneously supplied to the set terminal and the reset terminal, that is, in order to avoid prohibition for the SR latch 36, the width of the narrow pulse supplied to the set terminal and the reset terminal It is desirable that the narrow pulse to be supplied has a narrow width.

  For this reason, in the present embodiment, the second pulse width is set narrower than the first pulse width. More specifically, the first pulse width corresponds to one bit of the digital signal to be transmitted, whereas the second pulse width allows the SR latch 36 to recognize the H level. It is the minimum width.

[Operation of Embodiment 1]
FIG. 7 is a diagram for explaining the operation of the signal transmission circuit according to the first embodiment of the present invention. In FIG. 7, the “input signal” column shows the waveform of the signal supplied to the input terminal 12 in FIG. 5, and the “output signal” column shows the waveform of the signal appearing at the output terminal 38 in FIG. . In addition, the columns A to H shown in FIG. 7 show the waveforms of signals appearing at points A to H shown in FIG.

  In this embodiment, the narrow pulse generation circuit 18 belonging to the set pulse transmission circuit 14 receives the rising edge of the input signal and generates a narrow pulse corresponding to 1 bit. For this reason, a narrow pulse that rises in synchronization with the rise of the input signal and falls after the time corresponding to 1 bit has elapsed appears at the subsequent stage (point A) of the narrow pulse generation circuit 18.

  An input signal is supplied to the narrow pulse generation circuit 28 belonging to the reset pulse transmission circuit 16 via the inverter 26. For this reason, the reset pulse transmission circuit 16 rises in synchronization with the fall of the input signal at the subsequent stage (point B) of the narrow pulse generation circuit 28 and then falls when the time corresponding to 1 bit elapses. A narrow pulse appears.

  The rise of the narrow pulse appearing at the point A is sequentially transmitted by the multistage buffer amplifier constituting the delay adjustment circuit 20. As a result, at the subsequent stage (point C) of the delay adjustment circuit 20, a rise occurs after a desired delay time from the rise of the input signal.

  By the way, there are various variations in how the input signal rises. Therefore, there are various variations in how the narrow pulse appears at point A. Specifically, the rising edge appearing at the point A may appear following the 1-bit L signal, or may occur following the 6-bit L signal.

  The individual buffer amplifiers constituting the delay adjustment circuit 20 require a longer time to transmit the signal rise to the subsequent stage as the L period maintained before the rise is longer. By accumulating the differences in the transmission times, jitter that cannot be ignored occurs at the rising timing at the subsequent stage (point C) of the delay adjustment circuit 20 (see Y1 in FIG. 7C).

  The delay adjustment circuit 20 also transmits the falling edge of the narrow pulse appearing at the point A. The trailing edge of the narrow pulse always appears following the 1-bit H signal. That is, regarding the falling, unlike the rising, the method of changing the signal level is standardized. For this reason, the delay adjustment circuit 20 always transmits the fall generated at the point A to the point C over a substantially constant delay time. As a result, almost no jitter occurs at the falling timing at the point C (see Y2 in FIG. 7C).

  The above phenomenon occurs similarly in the reset pulse transmission circuit 16. In other words, at the subsequent stage (point B) of the narrow pulse generation circuit 28, a rise occurs in response to the fall of the input signal. Therefore, various variations occur in how the point B rises according to the number of bits at which the input signal maintains the H level. On the other hand, the way of falling at point B is standardized as following the 1-bit H signal. For this reason, in the subsequent stage (point D) of the delay adjustment circuit 30, jitter that cannot be ignored occurs at the rise timing (see Y1 in FIG. 7D), and almost no jitter occurs at the fall timing (see Y2 in FIG. 7D). ).

  At point C and point D, the time lag Y1 occurring at the rise timing of the narrow pulse is the number of bits at the L level maintained before the rise of the input signal or the number of bits at which the input signal is maintained at the H level. This can be expressed as shown in FIG. Further, as shown in FIG. 8, the deviation Y2 that occurs at the timing when the narrow pulse falls at the points C and D is always sufficiently smaller than Y1.

  In FIG. 7, the E column and the F column represent the narrow pulse waveforms inverted by the inverters 22 and 32. By passing through the inverters 22 and 32, it is possible to generate a narrow pulse (hereinafter referred to as “inverted narrow pulse”) that maintains the L level for one bit. The influence of jitter at points C and D is superimposed on the inverted narrow pulse. That is, in the inversion narrow pulse, a jitter that cannot be ignored occurs on the start-side down edge, while almost no jitter occurs on the end-side up edge.

  The inverted narrow pulse generated by the inverter 22 is supplied to the second narrow pulse generation circuit 24. As a result, a narrow pulse having the second pulse width appears in the subsequent stage (point G) of the second narrow pulse generating circuit 24 in synchronization with the end-side edge of the inverted narrow pulse at the point E. There is no jitter at the end edge of the inverted narrow pulse. For this reason, a narrow pulse not affected by jitter appears at point G. By supplying the narrow pulse to the set terminal of the SR latch 36, the output signal is not affected by jitter after the input signal rises, and the delay time on the set side (corresponds to the first pulse width). It rises accurately when the sum of the time and the delay time by the delay adjustment circuit 20) has elapsed.

  The inverted narrow pulse appearing at point F of the reset signal transmission circuit 16 is supplied to the second narrow pulse generation circuit 34. As a result, a narrow pulse having the second pulse width appears in the subsequent stage (point H) of the second narrow pulse generation circuit 34 in synchronization with the terminal side edge of the inverted narrow pulse at the point F. By supplying this narrow pulse to the reset terminal of the SR latch 36, the output signal is not affected by jitter after the input signal falls, and the delay time on the reset side (corresponding to the first pulse width). When the delay time and the delay time by the delay adjustment circuit 30) have elapsed.

[Effect in Embodiment 1]
As described above, according to the signal transmission circuit of this embodiment, the rising edge of the input signal can be reflected in the output signal after the delay time on the set side without being affected by jitter. Similarly, according to this circuit, the falling edge of the input signal can be reflected in the output signal after the delay time on the reset side without being affected by jitter. That is, according to the signal transmission circuit of the present embodiment, a digital signal supplied to the input terminal 12 can be transmitted to the output terminal 38 without being affected by jitter after giving a desired delay time. .

  Furthermore, according to the configuration of the present embodiment, the set-side delay time and the reset-side delay time each include a time corresponding to the first pulse width. For this reason, according to the signal transmission circuit of the present embodiment, a larger delay time can be generated as compared with a circuit that ensures a delay time only by the delay adjustment circuits 20 and 30.

  Further, according to the configuration of the present embodiment, the delay time generated by the delay adjustment circuit 20 on the set signal transmission circuit 14 side and the delay time generated by the delay adjustment circuit 30 on the reset signal transmission circuit 16 side are made different. Thus, the pulse width of the digital signal can be expanded and contracted during the transmission process.

  In particular, in this embodiment, since the second pulse width is sufficiently narrow, the gap between the narrow pulse at the G point and the narrow pulse at the H point is sufficiently set without touching the prohibited items of the SR latch 36. Can be narrowed. In this respect, the configuration of the present embodiment is suitable for ensuring a large degree of freedom regarding the expansion and contraction of the transmission pulse.

[Modification of Embodiment 1]
FIG. 9 shows a configuration example when the signal transmission circuit of this embodiment is multi-channeled. The signal transmission circuit shown in FIG. 9 includes a plurality of delay circuits (delay circuits 1 to 3). Each of the delay circuits 1 to 3 includes delay adjustment circuits 20 and 30, inverters 22 and 32, second narrow pulse generation circuits 24 and 34, an SR latch 36, and an output terminal 38. The delay circuits 1 to 3 are connected to the common narrow pulse generation circuits 18 and 28.

  Different delay times are assigned to the delay adjustment circuits 20 and 30 for each of the delay circuits 1 to 3. For this reason, according to the signal transmission circuit shown in FIG. 9, by supplying a single digital signal to the input terminal 12, a plurality of signals subjected to different delay processes can be transmitted to the output terminal. This circuit is effective when, for example, it is necessary to change the timing and apply the same signal to a plurality of pins of a semiconductor device.

  In the first embodiment described above, the signal transmission circuit 10 intentionally includes the delay adjustment circuits 20 and 30 for causing a desired delay, but the configuration of the present invention is included in this. It is not limited. For example, when a digital signal is transmitted over a long distance, a plurality of amplifiers are arranged in the signal transmission path, and a multistage delay circuit is inevitably formed. The configuration of the present invention may be used for transmitting a digital signal in such a signal transmission path without causing jitter.

  In the first embodiment described above, the narrow pulse generation circuits 18 and 28 and the inverter 26 are the “narrow pulse generation circuit” in the first invention, and the delay adjustment circuits 20 and 30 are the “narrow pulse generation circuit” in the first invention. The inverters 22 and 32, the second narrow pulse generation circuits 24 and 34, and the SR latch 36 correspond to the “delay circuit” and the “signal regeneration circuit” in the first invention, respectively.

  In the first embodiment described above, the narrow pulse generation circuit 18 is the “up side narrow pulse generation circuit” in the second invention, and the inverter 26 and the narrow pulse generation circuit 28 are the “down side in the second invention”. In the “narrow pulse generation circuit”, the delay adjustment circuit 20 is the “up-side delay circuit” in the second invention, the delay adjustment circuit 30 is the “down-side delay circuit” in the second invention, and the L level is the first The H level corresponds to the “first value” in the second invention, and the “second value” in the second invention.

  In the first embodiment described above, the inverter 22 and the second narrow pulse generation circuit 24 are the “up-side second narrow pulse generation circuit” in the third invention, and the inverter 32 and the second narrow pulse generation circuit 34 are the same. “Corresponds to the“ down-side second narrow pulse generation circuit ”in the third invention.

Embodiment 2. FIG.
[Configuration of Embodiment 2]
Next, a second embodiment of the present invention will be described with reference to FIGS. FIG. 10 is a block diagram for explaining the configuration of the signal transmission circuit 40 according to the second embodiment of the present invention. The signal transmission circuit 40 of this embodiment includes a double-edge narrow pulse generation circuit 42 at the subsequent stage of the input terminal 12.

  The both-edge narrow pulse generating circuit 42 is a circuit that generates a narrow pulse in response to each of the change from L to H and the change from H to L of the input signal. In this embodiment, the width of the narrow pulse generated here (first pulse width) is set to be less than half of the width of 1 bit so as to correspond to at least a double rate of the digital signal to be transmitted. ing.

  The narrow pulse generated by the two-edge narrow pulse generation circuit 42 is supplied to the delay adjustment circuit 44. The delay adjustment circuit 44 is designed to correspond to a rate more than double the digital signal to be transmitted so that the narrow pulse having the first pulse width described above can be transmitted without being extinguished. .

  The signal that has passed through the delay adjustment circuit 44 is supplied to a falling edge triggered T flip-flop (T-FF) 46. The T-FF 46 is a circuit that receives the down edge of the signal supplied from the previous stage and inverts the output signal between the L level and the H level. The output of the T-FF 46 is transmitted to the output terminal 38 as an output signal.

[Operation of Embodiment 2]
FIG. 11 is a diagram for explaining the operation of the signal transmission circuit 40 of the present embodiment. 11, the column “input signal” indicates the waveform of the signal supplied to the input terminal 12 in FIG. 10, and the column “output signal” indicates the waveform of the signal appearing at the output terminal 38 in FIG. . Further, the columns A and B shown in FIG. 11 show the waveforms of signals appearing at points A and B shown in FIG. 10, respectively.

  In the present embodiment, when the input signal changes as shown in FIG. 11, a narrow pulse synchronized with the rising edge of the input signal and a falling edge of the input signal are provided at the subsequent stage (point A) of the both-edge narrow pulse generating circuit 42. Synchronized narrow pulses appear sequentially.

  As the narrow pulse travels through the delay adjustment circuit 44, jitter occurs at the rising timing. On the other hand, almost no jitter occurs at the falling timing. For this reason, in the subsequent stage (point B) of the delay adjustment circuit 44, a narrow pulse in which jitter is generated in the start side edge but no jitter is generated in the end side edge is generated. The reason why such a narrow pulse occurs in the subsequent stage of the delay adjustment circuit 44 is the same as in the case of the first embodiment, and a detailed description thereof is omitted here.

  The T-FF 46 in this embodiment receives the down edge generated at the point B and inverts the output. That is, according to the configuration of the present embodiment, the T-FF 46 inverts the output in response to a down edge that is not affected by jitter. For this reason, the waveform generated by the T-FF 46 is not affected by jitter.

  Further, according to the configuration of the present embodiment, the T-FF 46 is alternately input with the down edge corresponding to the rising edge of the input signal and the down edge corresponding to the falling edge of the input signal. As a result, the T-FF 46 eventually reproduces a signal having the same waveform as the input signal. Thus, according to the signal transmission circuit of the present embodiment, the digital signal supplied to the input terminal 12 is transmitted to the output terminal 38 without being affected by jitter, as in the circuit of the first embodiment. be able to.

  In the second embodiment, the two-edge narrow pulse generation circuit 42 is the “narrow pulse generation circuit” in the first invention, and the delay adjustment circuit 44 is the “delay circuit” in the first invention. The falling edge trigger type T-FF 46 corresponds to the “signal reproduction circuit” in the first aspect of the present invention.

It is a block diagram of the conventional semiconductor test apparatus. It is a figure for demonstrating operation | movement of the semiconductor test apparatus shown in FIG. It is a figure for demonstrating the reason a jitter arises in the semiconductor test apparatus shown in FIG. It is a figure which shows the relationship between the time lag which arises in the change point shown in FIG. 3, and the bit number by which the signal was maintained at L level before the change point. 1 is a block diagram of a signal transmission circuit according to a first embodiment of the present invention. It is a figure for demonstrating the conditions which the width | variety of the narrow pulse which the narrow pulse generation circuit 18 produces | generates, ie, the 1st pulse width, should be satisfied. It is a figure for demonstrating operation | movement of the signal transmission circuit of Embodiment 1 of this invention. In the signal transmission circuit according to the first embodiment of the present invention, the difference Y1 that occurs at the rise timing of the point C and the deviation Y2 that occurs at the fall timing of the point D are shown in comparison. It is a figure for demonstrating a structure when the signal transmission circuit of Embodiment 1 of this invention is multi-channeled. It is a block diagram of the signal transmission circuit of Embodiment 2 of the present invention. It is a figure for demonstrating operation | movement of the signal transmission circuit of Embodiment 2 of this invention.

Explanation of symbols

10; 40 Signal transmission circuit 12 Input terminal 14 Set signal transmission circuit 16 Reset signal transmission circuit 18, 28 Narrow pulse generation circuit 20, 30; 44 Delay adjustment circuit 22, 26, 32 Inverter 24, 34 Second narrow pulse generation circuit 36 SR latch 38 Output terminal 42 Both edges narrow pulse generation circuit 46 Falling edge trigger type T-FF

Claims (5)

A narrow pulse generating circuit for generating a narrow pulse having a first pulse width in response to a change in a digital signal supplied to the input side;
A delay circuit disposed downstream of the narrow pulse and causing a delay in the transmission of the narrow pulse;
A signal reproduction circuit that reproduces a digital signal in response to a termination side edge among a start side edge and a termination side edge of a narrow pulse output from the delay circuit;
A signal transmission circuit comprising: The narrow pulse generation circuit includes an up side narrow pulse generation circuit that receives an up edge of a digital signal supplied to an input side and generates a narrow pulse, and a down side that receives a down edge of the digital signal and generates a narrow pulse. Including a narrow pulse generation circuit,
The delay circuit includes an up-side delay circuit disposed downstream of the up-side narrow pulse generation circuit, and a down-side delay circuit disposed downstream of the down-side narrow pulse generation circuit,
The signal regeneration circuit changes the output signal from the first value to the second value in response to the terminal end edge of the narrow pulse output from the up-side delay circuit, and outputs the narrow signal output from the down-side delay circuit. 2. The signal transmission circuit according to claim 1, wherein the output signal is changed from the second value to the first value in response to an end edge of the pulse. The signal regeneration circuit includes:
An up-side second narrow pulse generating circuit that receives a terminal-side edge of a narrow pulse output from the up-side delay circuit and generates a narrow pulse having a second pulse width;
A down-side second narrow pulse generating circuit that receives a terminal-side edge of the narrow pulse output from the down-side delay circuit and generates a narrow pulse having a second pulse width;
The narrow pulse output from the up-side second narrow pulse generating circuit is received by one of a set terminal and a reset terminal, and the narrow pulse output from the down-side second narrow pulse generating circuit is received by the set terminal and SR latch received at the other side of the reset terminal,
The signal transmission circuit according to claim 2, comprising:   4. The signal transmission circuit according to claim 3, wherein the second pulse width is narrower than the first pulse width. The narrow pulse generation circuit includes a both-edge narrow pulse generation circuit that generates a narrow pulse for both the up edge and the down edge of the digital signal supplied to the input side,
The signal regeneration circuit includes a down-edge triggered T flip-flop that receives an end side edge of a narrow pulse output from the delay circuit and inverts an output signal between a first value and a second value. The signal transmission circuit according to claim 1, wherein:

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