JP2009128081A - Window determination circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a window determination circuit which does not cause false measurement by a phase deviation on the basis of the temperature drift of a DUT output for a DUT to be subjected to eye measurement. <P>SOLUTION: The window determination circuit determines the presence or absence of signal distortion in an output signal of a device under test 1 on the basis of a comparison result with a Hi-level threshold and a Low-level threshold in a window section of a window strobe signal. The window determination circuit comprises: an intermediate value comparator 33 to which the output signal of the device under test 1 is input and which compares it to an intermediate level threshold which is located midway between the Hi-level threshold and the Low-level threshold; a window width generation circuit 161 for generating a signal having a predetermined window width on the basis of the output signal of the intermediate value comparator 33; and a delay circuit 514 for generating the window strobe signal with the output signal of the window width generation circuit 161 delayed by a predetermined period of time. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention is for performing eye (signal opening) measurement for the purpose of evaluating the output waveform quality of a measurement device (hereinafter referred to as DUT: Device Under Test) operating at high speed in a semiconductor test apparatus or the like. The present invention relates to a window determination circuit.

  In a device used in a high-speed communication system, since an output signal is high-speed, it is necessary to perform eye measurement to evaluate waveform edge distortion. In the eye diagram that is displayed when a very large number of signal waveforms corresponding to 1 bit are cut out and overlaid, a portion surrounded by two waveforms, a waveform representing 1 and a waveform representing 0, is an “eye opening”. It is said that the larger this is, the easier the determination of 1 or 0 is. In this case, in the tester's judgment system, not only the normal strobe judgment in which the judgment point is captured by the edge but also whether or not the edge exists inside the eye (opening) is determined within a certain period of time. It is necessary to execute window determination for detecting the presence or absence of an edge. In window determination, two edge generation circuits are required to set a window width (front edge and rear edge) that is a determination period.

FIG. 7 is a block diagram showing an example of a window determination circuit constituting a conventional determination system.
In the tester 100, the Hi-side comparator 31 and the Low-side comparator 32 input the output signal DUT_OUT of the device under test DUT1 via the cable 2 and compare them with the Hi level threshold Hi_cmp_level and the Low level threshold Low_cmp_level, respectively. Here, the reason why two systems of Hi / Low are provided is to shorten the measurement time by simultaneous measurement.

The first strobe generation unit 61 and the second strobe generation unit 62 respectively perform window determination on the first strobe signal STB1 and the second strobe signal STB2 synchronized with the reference clock in the tester 100 that generates the timing of the test pattern and the like. To the units 51 and 52. The position of each edge of the strobe signals STB1 and STB2 is fixed at a preprogrammed position.

The Hi / Low window determination units 51 and 52 receive the comparison result H-CMP of the Hi-side comparator 31 and the comparison result L-CMP of the Low-side comparator 32, and in the window section generated from the strobe signals STB1 and STB2. Determine whether a glitch has occurred.

FIG. 8 is a circuit diagram showing details of the Hi-side window determination unit 51.
The window strobe generation circuit 511 includes a flip-flop circuit (hereinafter referred to as FF), and starts with the first strobe signal STB1 with the first strobe signal STB1 as a clock input and the second strobe signal STB2 as a reset input. Then, the signal WSTB12 on the Hi side is generated in the window period that ends with the second strobe signal STB2.

The glitch detector 512 is composed of FF, the data input is set to Hi, the comparison result H-CMP of the Hi side comparator 31 is used as a clock input, and the signal WSTB12 from the window strobe generation circuit 511 is used as an enable input. .

In the FF constituting the latch circuit 513, the output of the glitch detector 512 is a data input, the strobe signal STB2 is a clock input, and the signal WSTB12 is an enable input. The output Hi_w_cmp of the latch circuit 513 is connected to the reset input of the glitch detector 512.

The low-side window determination unit 52 is the same as the window determination unit 51 except that the output L-CMP of the low-side comparator 32 is input instead of H-CMP.

The operation of the apparatus of FIG. 7 will be described below.
The output signal DUT_OUT of the device under test DUT1 is sent to the tester 100 via the cable 2, and is compared with the Hi level threshold value Hi_cmp_level by the Hi side comparator 31 and the Low level threshold value Low_cmp_level by the Low side comparator 32. The first strobe generation unit 61 and the second strobe generation unit 62 output the first strobe signal STB1 and the second strobe signal STB2 to the window determination units 51 and 52, respectively. The comparison result H-CMP of the Hi-side comparator 31 and the comparison result L-CMP of the Low-side comparator 32 are input to the window determination units 51 and 52, respectively, and a glitch is generated in the window section generated by the strobe signals STB1 and STB2. Existence is determined.

In addition, when the specification of DUT1 is 3V amplitude waveform output, for example, the following is set as a specific example of the level comparison threshold.
Hi_cmp_level: 2.5V
Low_cmp_level: 0.8V

FIG. 9 is a time chart illustrating operations of the comparators 31 and 32 and the window determination units 51 and 52 when a glitch is generated in the output signal DUT_OUT of the DUT 1. Corresponding to the glitches A1, A2, and A3 generated in the output signal DUT_OUT (a) of the device under test DUT1, signal inversions B1 and B3 are generated in the signal H-CMP (b) by comparison with the threshold Hi_cmp_level in the comparator 31. In comparison with the low level threshold Low_cmp_level in the comparator 32, the signal inversion B2 occurs in the signal L-CMP (c).

In the Hi-side window determination unit 51 of FIG. 8, the window strobe signal WSTB12 (f) is generated from the strobe generation circuit 511 by the timing edges of the strobe signals STB1 (d) and STB2 (e). When the comparison output H-CMP is input to the glitch detector 512 and enabled by the window strobe signal WSTB12, the output Win_det (g) changes to Hi when the glitches B1 and B3 occur in the comparison output H-CMP. Since the latch circuit 513 is also enabled by the window strobe signal WSTB12, the Hi level of the output Win_det is latched at the timing of the strobe signal STB2 (C1, C3), the output Hi_w_cmp (h) becomes the Hi level, and a glitch is detected. It shows that. The output (g) of the glitch detector 512 is reset by the signal Hi_w_cmp to prepare for the next glitch detection.

Similarly, when the glitch B2 occurs in the comparison output L-CMP (c) in the low-side window determination unit 52, the signal Win_det (i) changes to Hi, and the output Win_det is output at the timing of the strobe signal STB2 (e). The Hi level is latched (D1), and the output Low_w_cmp (j) becomes the Hi level.

When the window strobe signal WSTB12 (f) is enabled and no glitch occurs in the comparison outputs H-CMP (b) and L-CMP (c), the signal Win_det (g) (i) remains low. (C2, D2), the signals Hi_w_cmp (h) and Low_w_cmp (j) are Low.

  Prior art documents related to the window determination circuit include the following.

JP 2001-350646 A

  However, in the case of a high-speed DUT output signal, if the DUT output waveform is slightly blurred, the ratio of the signal transition time (rising or falling) becomes larger than the test rate. Further, the delay time of the DUT output signal varies as the junction temperature of the DUT changes during the test. If this temperature drifted delay time Td is small compared to the test rate, there will be no problem in measurement accuracy, but if it is large, erroneous measurement will be caused.

FIG. 10 is a time chart showing an example in which erroneous measurement occurs in the delay time due to temperature drift in the window determination circuit of FIG. Originally, it was set to observe the glitch E generated in the window section T12 between the strobe signals STB1 (b) and STB2 (c), but because the phase of DUT_OUT (a) shifted during the test, the delay time The rising edge F of the normal waveform of the signal DUT_OUT (d) after the delay of Td enters the window section T12, the signal Win_det (e) changes to Hi, and is recognized as a glitch. Glitch G can no longer be detected.

Since the strobe signals STB1 and STB2 are generated from the reference clock in the tester, the position of each edge is fixed at a preprogrammed position and cannot be changed automatically.

  An object of the present invention is to provide a window determination circuit in which an erroneous measurement due to a phase shift due to a temperature drift of a DUT output or the like does not occur in a DUT that performs eye measurement.

In order to achieve such a problem, the invention according to claim 1 of the present invention is:
In a window determination circuit that determines the presence or absence of signal distortion based on a comparison result of the output signal of the device under measurement with the Hi level threshold and the Low level threshold in the window section of the window strobe signal.
An intermediate value comparator that receives an output signal of the device under test and compares it with an intermediate level threshold value intermediate between the Hi level threshold value and the Low level threshold value;
A window width generating circuit for generating a signal having a predetermined window width based on the output signal of the intermediate value comparator;
And a delay circuit that delays an output signal of the window width generation circuit for a predetermined time to generate the window strobe signal.

The invention according to claim 2
The window determination circuit according to claim 1,
A flip-flop circuit that receives a signal corresponding to the comparison result and is enabled by the window strobe signal;
And a latch circuit that holds a signal output from the flip-flop circuit.

The invention described in claim 3
The window determination circuit according to claim 1 or 2,
The comparison result is obtained from a comparator that compares the output signal of the device under measurement with the Hi level threshold and the Low level threshold in a time division manner.

  As is clear from the above description, according to the present invention, the presence or absence of signal distortion is determined based on the comparison result of the output signal of the device under measurement with the Hi level threshold and the Low level threshold in the window section of the window strobe signal. In the window determination circuit for determining the output, an output signal of the device under test is input, an intermediate value comparator for comparing with an intermediate level threshold value between the Hi level threshold value and the Low level threshold value, and an output signal of the intermediate value comparator A window width generation circuit for generating a signal having a predetermined window width based on the delay time circuit for generating the window strobe signal by delaying an output signal of the window width generation circuit for a predetermined time. Since the signal can automatically follow the DUT output waveform, It can be erroneously determined by the phase shift due to temperature drift or the like to provide a window decision circuit does not occur.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a configuration block diagram showing an example of a window determination circuit according to an embodiment of the present invention. The same parts as those in FIG.

The intermediate value comparator 33 compares the DUT1 output signal DUT_OUT with the intermediate level threshold value Mid_cmp_level, and outputs the signal M-CMP as a comparison result. Here, the intermediate level Mid_cmp_level is an intermediate value between the Hi level threshold Hi_cmp_level and the Low level threshold Low_cmp_level.

The M-WIND generation unit 161 inputs a signal M-CMP and outputs a window width signal M-WIND for generating a determination window to the window determination units 151 and 152.

The strobe generator 162 outputs a strobe signal for latching the determination output at an arbitrary timing to the window determination units 151 and 152.

The window determination units 151 and 152 are based on the signal M-WIND input from the M-WIND creation circuit 161 for the comparison result H-CMP of the Hi side comparator 31 and the comparison result L-CMP of the Low side comparator 32, respectively. To determine whether or not a glitch occurs in the window section.

FIG. 2 is a configuration circuit diagram showing details of the M-WIND generator 161.
In the pulse generation FF 611, the data input is set to Hi, and the signal M-CMP output from the intermediate value comparator 33 is supplied to the clock input.

The delay circuit 612 receives an output signal of the pulse generation FF 611, outputs a signal M-CMP_Delay delayed by a set predetermined time, and inputs the signal M-CMP_Delay to the reset terminal Rst of the pulse generation FF 611. A window width signal M-WIND for generating a determination window is output from the pulse generation FF 611.

FIG. 3 is a configuration circuit diagram showing details of the window determination unit 151. The same parts as those of the window determination unit 51 in FIG.

The delay circuit 514 receives the window width signal M-WIND output from the M-WIND generator 161, generates a window strobe signal M-WSTB delayed by a predetermined time Tstb1, and generates a glitch detector 512 is output to the enable terminal En.

The inverting circuit 515 inverts the output signal M-WSTB from the delay circuit 514. The STB selection circuit 516 selects either the strobe signal STB output from the strobe generator 162 or the output of the inverting circuit 515.

The signal selected by the STB selection circuit 516 is input to the clock terminal of the glitch detector 513 as a strobe signal. Unlike the case of FIG. 8, the window strobe signal is not connected to the enable input of the latch circuit 513.

The window determination unit 152 is the same as the window determination unit 151 described above except that the comparison result L-CMP of the low-side comparator 32 is given to the clock input of the glitch detector 512.

The M-WIND generator 161 constitutes a window width generation circuit that generates a window width signal M-WIND having a predetermined window width T12 based on the output signal of the intermediate value comparator 33.

The delay circuit 514 constitutes a delay circuit that generates the window strobe signal M-WSTB by delaying the output signal of the window width generation circuit 161 by a predetermined time Tstb1.

The operation of the apparatus shown in FIG. 1 will be described below using a time chart.
FIG. 4 is a time chart for illustrating the operation of the intermediate value comparator 33 of FIG. 1 and the M-WIND generator 161 of FIG.

The signal DUT_OUT (a) sent from the device under test DUT1 via the cable 2 is compared with the intermediate level threshold value Mid_cmp_level by the intermediate value comparator 33, and the comparison result M-CMP (b) is compared with the M-WIND generator 161. Is input. At the rising edge of the signal M-CMP, the pulse generation FF 611 becomes “1” (Hi). After this output passes through the delay circuit 612 and is delayed by time T12 (c), the pulse generation FF 611 is reset at the rising edge and the output is set to “0” (Low) (d). As a result, the window width signal M-WIND that is the source of the window strobe is output from the pulse generation FF 611. Here, the window width signal M-WIND has a window width equal to the delay time amount T12.

FIG. 5 is a time chart for illustrating the operation of the window determination unit 151 of FIG. Here, a case where the STB selection circuit selects the strobe signal STB is shown.

Assume that during the test, the delay time of the output signal (a) of the DUT 1 changes by Td due to temperature drift (b). The window width signal M-WIND (c) delayed from this and output from the M-WIND generator 161 is input to the delay circuit 514, and the window strobe signal M delayed by a preset predetermined time Tstb1. -WSTB (d) is generated and input to the enable terminal En of the glitch detector 512.

When this M-WSTB signal is “1” and the signal inversion due to glitch occurs in the comparison result H-CMP on the Hi side, the glitch detector 512 is set and the output Win_det (e) becomes “1”. This output signal Win_det is input to the latch circuit 513 at the next stage and latched at the timing of the strobe signal STB (f), and at the same time, the glitch detector 512 is reset to “0”. The output signal Hi_w_cmp (g) of the latch circuit 513 indicates the determination result of the glitch.

When it is desired to delay the strobe signal more reliably than the position where the glitch is supposed to be generated, the STB selection circuit 516 selects the output signal of the inverting circuit 515 in advance, and the window strobe signal M-WSTB (d) The signal Win_det may be latched at the falling timing.

According to the window determination circuit configured as described above, it is possible to automatically absorb the phase shift due to the temperature drift of the DUT by causing the window strobe signal M-WSTB to follow the delay of the DUT output signal. Therefore, it is possible to realize a window determination circuit that does not cause erroneous measurement due to phase shift due to temperature drift of the DUT output.

Further, not only when a glitch occurs in the waveform but also when the rising edge of the waveform is distorted can be detected. FIG. 6A shows a time chart when the DUT1 signal has a normal waveform, and FIG. 6B shows a time chart when the DUT1 signal has a distorted waveform. In the case of a waveform with a distorted rising edge, the edge position of the H-CMP waveform is considerably backward compared to the edge position of the M-CMP waveform compared to the case of the normal waveform. In this case, since rising distortion exists inside the signal M-WSTB (Hi state), it is detected as a failure. In this way, by setting the delay time appropriately, it is possible to detect the rise distortion.

In the above embodiment, two sets of the comparator and the window determination unit are provided on the Hi side and the Low side, but the hardware cost is reduced to one set by switching the Hi level threshold and the Low level threshold to time division. May be.

Further, when the window determination unit 151 always uses the signal STB as the strobe signal, the inversion circuit 515 and the STB selection circuit 516 can be omitted.

It is a configuration block diagram showing an example of a window determination circuit according to an embodiment of the present invention. 4 is a configuration circuit diagram showing details of an M-WIND generation unit 161. FIG. 3 is a configuration circuit diagram illustrating details of a window determination unit 151. FIG. 3 is a time chart for illustrating operations of the intermediate value comparator 33 of FIG. 1 and the M-WIND generator 161 of FIG. FIG. 4 is a time chart for illustrating the operation of a window determination unit 151 in FIG. 3. FIG. 2 is a time chart showing the operation of the window determination circuit of FIG. 1 when a DUT signal has a normal waveform and a distorted waveform. It is a block diagram showing an example of a conventional window determination circuit. 6 is a circuit diagram showing details of a Hi-side window determination unit 51. FIG. It is a time chart which shows operation | movement of the window determination circuit of FIG. 8 is a time chart showing an example of erroneous measurement caused by temperature drift in the window determination circuit of FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Device under test 31 Hi side comparator 32 Low side comparator 33 Intermediate value comparator 161 Window width generation circuit 514 Delay circuit 512 Flip-flop circuit 513 Latch circuit
Hi_cmp_level Hi level threshold
Low_cmp_level Low level threshold
Mid_ cmp_level Mid level threshold
M-WSTB Window strobe signal T12 Window width

Claims (3)

In a window determination circuit that determines the presence or absence of signal distortion of an output signal of a device under test based on a comparison result between a Hi level threshold and a Low level threshold in a window section of a window strobe signal.
An intermediate value comparator that receives an output signal of the device under test and compares it with an intermediate level threshold value intermediate between the Hi level threshold value and the Low level threshold value;
A window width generating circuit for generating a signal having a predetermined window width based on the output signal of the intermediate value comparator;
And a delay circuit for delaying an output signal of the window width generation circuit for a predetermined time to generate the window strobe signal. A flip-flop circuit that receives a signal corresponding to the comparison result and is enabled by the window strobe signal;
The window determination circuit according to claim 1, further comprising a latch circuit that holds a signal output from the flip-flop circuit. 3. The window determination circuit according to claim 1, wherein the comparison result is obtained from a comparator that compares the output signal of the device under measurement with the Hi level threshold and the Low level threshold in a time division manner.

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