JP5244005B2 - Multiplexer - Google Patents

Description

  In a multiplexer that multiplexes binary data signals input in two series at a predetermined bit rate into one series of data signals and outputs it at a double bit rate, multiple reflection of the transmission path of the clock signal used for multiplexing is performed. It relates to technology to prevent.

  The multiplexer generally inputs a binary data signal of (0, 1) of a plurality of M series to the switch circuit, and sequentially selects the data signal at a speed M times the bit rate of the input data signal. Multiplexed to a series of data signals, the phase margin is lost when the bit rate of the input data signal becomes several tens of Gb / s, and the timing of the selection operation by the switch is changed with respect to the change of the data signal. Cannot be multiplexed.

  As a method for solving this problem, the number M of input sequences is limited to 2, and one phase of the two data signals is delayed by 180 degrees with respect to the other, and the selection operation by the switch with respect to the change of each data signal There is a system that gives a phase margin by matching the timings of.

FIG. 6 shows a basic configuration of the multiplexer 10 of the above method.
As shown in FIG. 7A, the multiplexer 10 converts an input data signal Da composed of bit data da1, da2,... Inputted in the NRZ format into two-stage columns constituting the first shift circuit 11. As shown in FIG. 7 (b), it is input to the first stage of the connected latch circuits 11a and 11b, and is made up of bit data db1, db2,... Input in the NRZ format at the same bit rate as the input data signal Da. The data signal Db is applied to the first stage of the latch circuits 12 a to 12 c connected in a three-stage column constituting the second shift circuit 12.

  As shown in FIG. 7C, the clock supply circuit 15 receives a clock signal CK having a frequency equal to the bit rate of the input data signals Da and Db, and supplies it to the latch circuits 11a, 11b, and 12a to 12c. . Here, although the clock signal supplied from the clock supply circuit 15 is distinguished from CK1 to CK4, they are basically the same and may be simply referred to as the clock signal CK without being distinguished in the following description.

  Here, the latch circuits 11a, 12a, and 12c latch the data signal at one level transition timing (for example, rising) of the input clock signal CK, and the latch circuits 11b and 12b perform the other level transition of the clock signal CK. The data signal is latched at timing (for example, falling).

  Therefore, as shown in FIGS. 7A and 7B, when the data signals Da and Db are input in a synchronized state (in which the data switching timings are equal to each other), the latch circuit 11b of the first shift circuit 11 As shown in FIG. 7D, the first shift data signal Da ′ whose data switching timing coincides with the falling timing of the clock signal CK is output from the latch circuit 12c of the second shift circuit 12. As shown in FIG. 7E, the second shift data signal Db ′ in which the data switching timing coincides with the rising timing of the clock signal CK is output, and both shift data signals Da ′, The switching timing of Db ′ is shifted by a half clock period (180 degrees).

  Two systems of shift data signals Da ′ and Db ′ whose switching timings are shifted by 180 degrees are input to the 2-to-1 selection switch 13.

  As shown in FIG. 7F, the selection switch 13 selectively outputs the first shift data signal Da ′ when the clock signal CK is at a high level, and performs the second shift when the clock signal CK is at a low level. The data signal Db 'is selectively output. As a result, the signal Dx obtained by multiplexing the input data signals Da and Db is output at a bit rate that is twice the input bit rate.

  Note that, as described above, a multiplexer configured to switch the switching timing of two systems of input data signals through different number of stages of latches by a half cycle of the clock and select with a switch is disclosed in Non-Patent Document 1, for example. It is disclosed.

Published by Behzad Razavi, “Design of Integrated Circuits of Optical Communication”, pp.333-340, McGRAW-Hill 2003

  As described above, in the multiplexer configured so that the switching timing of the two systems of input data signals is shifted by a half cycle of the clock via latches having different numbers of stages, the wiring length of the line supplying the clock signal CK is selected. Inevitably becomes longer, and multiple reflections occur due to the influence, which becomes unstable during high-speed operation.

This will be described with reference to an actual circuit.
FIG. 8 shows a more specific circuit of the clock supply circuit 15 in the case where the multiplexer having the above configuration is actually made into an IC, that is, each latch circuit and selection switch is a differential type (inverted two-phase type) data signal. The case where it is configured to handle a clock signal is shown.

  The clock supply circuit 15 receives a clock signal CK that is externally single-ended input by a differential output type buffer 16, and inputs a clock signal that is phase-inverted from the buffer 16 to transistors 17 a and 17 b of the emitter follower circuit 17. The clock signals CK0 and CK0 ′ output from the emitters are supplied to the latch circuits 11a, 11b and 12a to 12c.

  Each of the latch circuits 11a, 11b, 12a to 12c and the selection switch 13 is a differential input / differential output type so-called Gilbert cell circuit (specifically) configured by using three pairs of emitter-connected (or source-connected) pair transistors. A typical circuit configuration will be described later). A 50Ω resistor R is connected to the emitters of the transistors 17a and 17b.

  Here, as described above, the circuit length for latching the data signal and shifting it to the subsequent stage increases the wiring length of the line for transmitting the clock signal. Therefore, each line between the emitter follower circuit 17 and the latch circuits 11a and 12a Relay connections between the latch circuits and between the latch circuit 12c and the selection switch 13 are performed using a microstrip line having a predetermined impedance (for example, 120Ω). The microstrip line has a line conductor having a predetermined width formed on one surface side of the substrate and an earth conductor formed on the opposite surface. In the circuit diagram of FIG. 8, the line conductors U1 to U1 constituting each microstrip line are formed. Only U4 and U1 'to U4' are shown.

  If the substrate on which the microstrip line is formed is, for example, InP (indium phosphorus) having a dielectric constant of 12.4 and a thickness of 130 μm, the width of each line conductor in the design is 5 μm, and the line conductors necessary for the circuit configuration The lengths of U1 to U3 and U1 ′ to U3 ′ are approximately 80 μm, and the lengths of the line conductors U4 and U4 ′ connecting between the latch circuit 12c and the selection switch 13 are 25 μm.

  When the change in amplitude with respect to the frequency of the clock signals CK0 to CK4 at each node shown in FIG. 8 is obtained under the above conditions, the result of FIG. 9 is obtained.

  From this figure, it can be seen that the amplitude of the clock signal after the second stage has a peak in the vicinity of about 40 GHz, and the peak is larger as the latter stage. In particular, the amplitudes of the third and fourth stages increase to more than twice the amplitude when the frequency is low (10 GHz), and as a whole, vary in a wide range of 1300 mV to 180 mV. It can be seen that the circuit operation is unstable due to signal reflection.

  This large fluctuation in amplitude is considered to be due to multiple reflections of the clock signal. As described above, in the transmission line of the clock signal from the emitter follower circuit 17 having a load resistance of 50Ω to the selection switch 13 through each latch circuit. It can be seen that it is difficult to obtain uniform characteristics.

  An object of the present invention is to solve this problem and to provide a multiplexer capable of stably operating by suppressing an amplitude fluctuation due to multiple reflections of a clock signal.

In order to achieve the above object, the multiplexer of the present invention comprises:
An NRZ format first input data signal and a clock signal having a frequency corresponding to the bit rate of the first input data signal are received, and the first input data signal is received at one level transition timing of the clock signal. The first latch circuit (11a) to latch, the latch data of the first latch circuit, and the clock signal are received, and the latch data of the first latch circuit is latched at the other level transition timing of the clock signal. A first shift circuit comprising a second latch circuit (11b) and shifted in such a way that the data switching timing coincides with the other level transition timing of the clock signal in the same code string as the first input data signal A first shift circuit (11) for outputting a data signal;
An NRZ format second input data signal synchronized with the first input data signal and the clock signal are received, and the second input data signal is latched at the one level transition timing of the clock signal. A fourth latch that receives the latch data of the third latch circuit, the latch data of the third latch circuit, and the clock signal, and latches the latch data of the third latch circuit at the other level transition timing of the clock signal; A fifth latch circuit (12b) that receives the latch data of the fourth latch circuit and the clock signal and latches the latch data of the fourth latch circuit at the one level transition timing of the clock signal; 12c), the same code string as the second input data signal, and at the one level transition timing of the clock signal. A second shift circuit for outputting a second shift data signal over data change timing has been shifted to match (12),
The first shift data signal output from the first shift circuit, the second shift data signal output from the second shift circuit, and the clock signal are received, and the clock signal receives the other level transition timing. Until the one level transition timing is reached, the first shift data signal is output, and the period until the clock signal reaches the other level transition timing from the one level transition timing is A selection switch (13) for outputting a second shift data signal;
In a multiplexer comprising a clock supply circuit (25) for supplying the clock signal to the latch circuits of the first shift circuit and the second shift circuit and the selection switch,
The clock supply circuit includes:
An emitter follower circuit (17) for receiving an input clock signal;
A first transmission line (26) for transmitting a clock signal output from the emitter follower circuit for a predetermined distance and supplying the clock signal in common to the first latch circuit of the first shift circuit and the third latch circuit of the second shift circuit When,
A second transmission line (27) for transmitting a clock signal received from the first transmission line for a predetermined distance and supplying the clock signal in common to the second latch circuit of the first shift circuit and the fourth latch circuit of the second shift circuit; ,
A third transmission line (28) for transmitting a clock signal received from the second transmission line for a predetermined distance and supplying the clock signal to the fifth latch circuit of the second shift circuit;
A fourth transmission line (29) for transmitting a clock signal received from the third transmission line for a predetermined distance and supplying the clock signal to the selection switch;
Among the first to fourth transmission lines, at least the input of each latch circuit is between the middle part of the line conductor of the second transmission line and the ground and between the middle part of the line conductor of the third transmission line and the ground. The value is almost twice the capacity, and the inductance of half the length of the line conductor is L,
Characteristic impedance (Z) = √ (L / C)
A capacitor of capacity C satisfying the relationship
Further, the fourth transmission line is terminated with a resistor equal to the characteristic impedance.

  Since the configuration is as described above, amplitude fluctuation due to multiple reflection of the clock signal applied to each latch circuit is suppressed, and stable operation can be performed even in a high frequency region.

Overall configuration diagram of an embodiment of the present invention Configuration diagram of clock supply circuit of differential type embodiment The figure which shows the structural example of the latch circuit using a Gilbert cell The figure which shows the structural example of the selection switch using a Gilbert cell Characteristics chart of the embodiment Basic configuration of multiplexer Operational diagram of multiplexer Conventional circuit of clock supply circuit Characteristics of conventional clock supply circuit

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 shows an overall configuration of a multiplexer 20 to which the present invention is applied, and FIG. 2 shows details of a differential clock supply circuit.

  The overall configuration of the multiplexer 20 is constituted by a first shift circuit 11, a second shift circuit 12, a selection switch 13, and a clock supply circuit 25 as shown in FIG. In the description of the overall configuration, the data signal and the clock signal are conceptually shown without distinction between a single end (single phase) and a differential type (inverted two phase type).

  The first shift circuit 11 is configured by cascading a first latch circuit 11a and a second latch circuit 11b.

  The first latch circuit 11a receives the first input data signal Da in the NRZ format and the clock signal CK1 having a frequency corresponding to the bit rate of the first input data signal Da, and one level transition of the clock signal CK1 The first input data signal Da is latched at the timing.

  Note that one level transition timing of the clock signal CK1 is one of the transition timing from the low level to the high level and the opposite transition timing from the high level to the low level when the clock signal is, for example, single-ended. . Further, in the case of the differential type, the levels of the two-phase signals are inverted from each other, so that one of the two phases may be specified in the same manner as in the single-ended case.

  The second latch circuit 11b receives the latch data of the first latch circuit 11a and the clock signal CK2 in phase with the clock signal CK1, and the latch data of the first latch circuit 11a at the other level transition timing of the clock signal CK2. Latch.

  Therefore, the first latch data shifted from the second latch circuit 11b so that the data switching timing coincides with the other level transition timing of the clock signal CK2 in the same code string as the first input data signal Da. The signal Da ′ is output.

  On the other hand, the second shift circuit 12 is configured by cascading a third latch circuit 12a, a fourth latch circuit 12b, and a fifth latch circuit 12c.

  The third latch circuit 12a receives the second input data signal Db in the NRZ format and the clock signal CK1 that are input in synchronization with the first input data signal Da, and one level transition timing of the clock signal CK1. The second input data signal Db is latched.

  The fourth latch circuit 12b receives the latch data of the third latch circuit 12a and the clock signal CK2, and latches the latch data of the third latch circuit 12a at the other level transition timing of the clock signal CK2.

  The fifth latch circuit 12c receives the latch data of the fourth latch circuit 12b and the clock signal CK3 having the same phase as the clock signal CK1, and the latch data of the fourth latch circuit 12b at one level transition timing of the clock signal CK3. Latch.

  For this reason, the second shift data shifted from the fifth latch circuit 12c so that the data switching timing coincides with one level transition timing of the clock signal CK3 in the same code string as the second input data signal Db. The signal Db ′ is output.

  The selection switch 13 receives the first shift data signal Da ′, the second shift data signal Db ′, and the clock signal CK4 having the same phase as that of the clock signal CK1, and the clock signal CK4 is switched to one of the levels from the other level transition timing. The first shift data signal Da ′ is output during the period until the level transition timing, and the second shift data signal is output during the period until the clock signal CK4 reaches the other level transition timing from the one level transition timing. Db ′ is output, and the data signal Dx obtained by multiplexing the input data signals Da and Db is output at a double bit rate.

  Of the configuration of the multiplexer 20, the configuration other than the clock supply circuit 25 is the same as the conventional circuit, and the basic operation is the same as that described in FIG. 7, but in the embodiment of the present invention, The configuration of the clock supply circuit 25 is changed in order to suppress amplitude fluctuation due to multiple reflections of the clock signal. Hereinafter, the clock supply circuit 25 will be described.

  The clock supply circuit 25 is for supplying clock signals CK1 to CK4 to the latch circuits of the first shift circuit 11 and the second shift circuit 12 and the selection switch 13, and together with the input data signals Da and Db. The input clock signal CK is received by the emitter follower circuit 17 including the transistor 17a.

  Here, the case where the clock signal is single-ended will be described. However, as described above, when the multiplexer 2 is a differential type and the clock signal CK is input single-ended, as shown in FIG. This can be dealt with by providing the differential output type buffer 16 in the preceding stage of the emitter follower circuit 17 and providing the emitter follower circuit 17 and transmission lines to be described later in parallel for two lines.

  The clock signal CK0 output from the emitter follower circuit 17 is input to the first transmission line 26.

  The first transmission line 26 transmits the clock signal CK0 received at one end side for a predetermined distance, and from the other end side as the clock signal CK1, the first latch circuit 11a of the first shift circuit 11 and the third shift circuit 12 of the second shift circuit 12. Commonly supplied to the latch circuit 12a.

  The first transmission line 26 is a microstrip line in which a line conductor U1 having a predetermined width is formed on one surface side of an InP substrate having a dielectric constant of 12.4 and a ground conductor is formed on the opposite surface, as described above. In FIG. 1, only the line conductor U1 is shown.

  In addition, the clock signal CK <b> 1 output from the other end of the first transmission line 26 is input to one end side of the second transmission line 27.

  The second transmission line 27 transmits the clock signal CK1 received at one end side for a predetermined distance, and from the other end side as the clock signal CK2, the second latch circuit 11b of the first shift circuit 11 and the fourth of the second shift circuit 12. Commonly supplied to the latch circuit 12b.

  Similarly, the clock signal CK <b> 2 output from the other end of the second transmission line 27 is input to one end side of the third transmission line 28. The third transmission line 28 transmits the clock signal CK2 received at one end side for a predetermined distance, and applies the clock signal CK3 from the other end side to the fifth latch circuit 12c of the second shift circuit 12.

Like the first transmission line 26, the second transmission line 27 and the third transmission line 28 are basically microstrip lines having line conductors U2 and U3, but as described above, multiplexing of clock signals is performed. in order to suppress the unstable motion of the amplitude due to reflection, between the intermediate portion and the ground line conductor U2, U3, is approximately twice the value of the input capacitance C _L of the latch circuits, the half of the line conductor length of Assuming that the inductance is L and the characteristic impedance is Z (for example, 50Ω),
Z = √ (L / C)
Capacitors C having a capacitance C satisfying the above relationship are connected.

  That is, the line conductor is assumed to be an inductance in a lumped constant, and is connected to the ground by the capacitors 27a and 28a having a capacity C necessary for matching the inductance to the characteristic impedance Z (= 50Ω). Therefore, as will be described later, an increase in amplitude due to multiple reflections of the clock signal is suppressed, and the operation becomes stable.

  In practice, as shown in FIG. 1, the line conductor U2 is connected in series with a half-length line conductor Uh2, and a capacitor 27a having a capacitance C is connected to the connection point. Similarly, the line conductor U2 and The line conductor U3 having the same length (not necessarily the same) is connected in series to the line conductor Uh3 having a half length, and a capacitor 28a having a capacitance C is connected to the connection point.

  The clock signal CK3 output from the other end of the third transmission line 28 is input to one end side of the fourth transmission line 29. The fourth transmission line 29 transmits the clock signal CK3 received at one end side for a predetermined distance, and applies the clock signal CK4 from the other end side to the selection switch 13. The fourth transmission line 29 is a microstrip line, and only the line conductor U4 is shown in FIG.

  Furthermore, in this embodiment, as an effective method for further suppressing the amplitude fluctuation due to the multiple reflection of the clock signal, the emitter of the emitter follower circuit 17 is not terminated with a resistor, and the other end of the fourth transmission line 29 is connected. Each terminal is terminated with a resistor R having the same value as the characteristic impedance Z obtained from each transmission line capacitance and the input capacitance of the latch circuit.

  Although the measurement result will be described later, by making the clock supply circuit 25 configured as described above, the amplitude fluctuation due to multiple reflections of the clock signal can be remarkably reduced.

  Further, it is sufficiently predicted that the amplitude fluctuation due to multiple reflections of the clock signal can be further suppressed by adopting the same configuration as that of the transmission lines 27 and 28 for at least one of the other transmission lines 26 and 27. The

  FIG. 2 shows the clock supply circuit 25 shown in FIG. 1 in the case where each latch circuit and the selection switch are of the differential type. As described above, the differential output type of the clock supply circuit 25 is connected to the preceding stage of the emitter follower circuit 17. A buffer 16 is provided, and an emitter follower circuit 17 and transmission lines to be described later are provided in parallel for two lines, and is basically equivalent to the clock supply circuit 25 of FIG.

  Here, as shown in FIG. 3, each of the differential latch circuits 11a, 11b, 12a-12c includes three pairs of emitter-connected pair transistors (not only bipolar type but also unipolar type, that is, FET). It is constituted by a so-called Gilbert cell circuit comprising Q1 to Q6, load resistors R1 and R2, and a constant current source I.

  In this configuration, a data signal is differentially input to the transistors Q1 and Q2, a clock signal is differentially input to the transistors Q5 and Q6, and an output is extracted from the collectors of the transistors Q1 and Q2. The output on the Q1 side is connected to the collector of Q4 and the base of Q3, and the output on the Q2 side is connected to the base of Q4 and the collector of Q3. When one of the transistors Q5 is turned on by the clock signal, the transistors Q1 and Q2 are activated and continuously output data inverted from the input data D (indicated by a bar above X in the figure). When the other transistor Q6 is turned on, the transistors Q3 and Q4 are activated. For example, if the collector of Q1 is L level and the collector of Q2 is H level, the state is held and output. Conversely, even if the collector of Q1 is at the H level and the collector of Q2 is at the L level, the state is similarly held and output.

  Further, as shown in FIG. 4, each differential selection switch 13 is also constituted by a Gilbert cell circuit.

  In this configuration, one shift data signal Da ′ is differentially input to the pair transistors Q1 and Q2, the other shift data signal Db ′ is differentially input to the pair transistors Q3 and Q4, and a clock is supplied to the pair transistors Q5 and Q6. Input the signal differentially.

  When one transistor Q5 is turned on by the clock signal, the transistors Q1 and Q2 become active, data corresponding to the shift data Da 'is differentially output, and when the other transistor Q6 is turned on, the transistor Q3 and Q4 become active, and data corresponding to the shift data Db ′ is differentially output.

  In the case of the clock supply circuit 25 corresponding to the differential type shown in FIG. 2, each transmission line 26 to 29 is configured by a pair of microstrip lines having the same transmission characteristics, and the pair of microstrip lines. (U1, U1 ′), (U2, U2 ′), (U3, U3 ′), and (U4, U4 ′) are respectively shown.

The configuration of each of the transmission lines 26 to 29 including the pair of microstrip lines is the same as that in the case of FIG. 1, and among the four transmission lines 26 to 29, at least the line conductor U2 of the second transmission line 27 ( = Uh2 + Uh2), U2 '(= Uh2' + Uh2 ') and the line conductor U3 (= Uh3 + Uh3) and U3' (= Uh3 '+ Uh3') of the third transmission line 28, as described above, between the intermediate portion and the ground in a nearly twice the value of the input capacitance C _L of the latch circuits, the inductance of the half of the length of the line conductors is L, the characteristic impedance as Z,
Z = √ (L / C)
A capacitor having a capacitance C satisfying the above relationship is connected, and the other end side of the line conductors U4 and U4 ′ of the fourth transmission line 29 is terminated with a resistor R having a resistance value of 50Ω equal to the characteristic impedance of each transmission line. Amplitude fluctuation due to multiple reflections can be suppressed.

  In FIG. 5, the length of the line conductors U1, U1 ′ in FIG. 2 is 80 μm, the length of the line conductors Uh2, Uh2 ′, Uh3, Uh3 ′ is 40 μm, the length of the line conductors U4, U4 ′ is 25 μm, The result of measuring the amplitude of the clock signals CK0 to CK4 at each node when the capacitance C of the capacitors 27a and 28a is 20 fF and the other end of the fourth transmission line 29 is terminated with a resistor R of 50Ω is shown. It is.

  As is apparent from the comparison between the measurement result of FIG. 5 and the measurement result of FIG. 9 of the conventional circuit, the amplitude of the clock signal at each node falls within the range of about 610 to 260 mV in the frequency range of 10 to 60 GHz. It can be seen that the amplitude fluctuation due to multiple reflection hardly appears and the operation is extremely stable.

Note that the above-described effect is that the transmission lines 27 and 28 before and after the second-stage latch circuit of each shift circuit 11 and 12 are respectively connected between the intermediate portions of the line conductors U2, U2 ', U3, and U3' and the ground. is approximately twice the value of the input capacitance C _L of the latch circuit, the inductance of the half of the length of the line conductors is L, the characteristic impedance as Z,
Z = √ (L / C)
The capacitors 27a and 28a having the capacitance C satisfying the above relationship are connected, and the emitter of the emitter follower circuit 17 is not terminated with a resistor, and the other end of the fourth transmission line 29 has a resistance value of 50Ω equal to the impedance of each transmission line. This is an effect obtained by terminating the resistor R.

Therefore, also in the configuration of FIG. 2, in each of the first transmission line 26 and the fourth transmission line 29, each latch circuit is provided between the intermediate portion of the line conductors U1, U1 ′, U4, U4 ′ and the ground. The input capacitance C _L is approximately twice the value of L, the inductance of half the length of the line conductor is L, the characteristic impedance is Z,
Z = √ (L / C)
By connecting a capacitor having a capacitance C satisfying the above relationship, it is predicted that the increase in amplitude due to multiple reflections of the clock signal can be further suppressed, and the operation can be further stabilized.

  DESCRIPTION OF SYMBOLS 11 ... 1st shift circuit, 11a ... 1st latch circuit, 11b ... 2nd latch circuit, 12 ... 2nd shift circuit, 12a ... 3rd latch circuit, 12b ... 4th latch circuit, 12c ... ... 5th latch circuit, 13 ... selection switch, 16 ... buffer, 17 ... emitter follower circuit, 25 ... clock supply circuit, 26 ... first transmission line, 27 ... second transmission line, 27a ... Capacitor 28... Third transmission line 28 a. Capacitor 29. Fourth transmission line U 1 to U 4, Uh 2, Uh 3, U 1 ′ to U 4 ′, Uh 2 ′, Uh 3 ′ …… Line conductor

Claims (1)

An NRZ format first input data signal and a clock signal having a frequency corresponding to the bit rate of the first input data signal are received, and the first input data signal is received at one level transition timing of the clock signal. The first latch circuit (11a) to latch, the latch data of the first latch circuit, and the clock signal are received, and the latch data of the first latch circuit is latched at the other level transition timing of the clock signal. A first shift circuit comprising a second latch circuit (11b) and shifted in such a way that the data switching timing coincides with the other level transition timing of the clock signal in the same code string as the first input data signal A first shift circuit (11) for outputting a data signal;
An NRZ format second input data signal synchronized with the first input data signal and the clock signal are received, and the second input data signal is latched at the one level transition timing of the clock signal. A fourth latch that receives the latch data of the third latch circuit, the latch data of the third latch circuit, and the clock signal, and latches the latch data of the third latch circuit at the other level transition timing of the clock signal; A fifth latch circuit (12b) that receives the latch data of the fourth latch circuit and the clock signal and latches the latch data of the fourth latch circuit at the one level transition timing of the clock signal; 12c), the same code string as the second input data signal, and at the one level transition timing of the clock signal. A second shift circuit for outputting a second shift data signal over data change timing has been shifted to match (12),
The first shift data signal output from the first shift circuit, the second shift data signal output from the second shift circuit, and the clock signal are received, and the clock signal receives the other level transition timing. Until the one level transition timing is reached, the first shift data signal is output, and the period until the clock signal reaches the other level transition timing from the one level transition timing is A selection switch (13) for outputting a second shift data signal;
In a multiplexer comprising a clock supply circuit (25) for supplying the clock signal to the latch circuits of the first shift circuit and the second shift circuit and the selection switch,
The clock supply circuit includes:
An emitter follower circuit (17) for receiving an input clock signal;
A first transmission line (26) for transmitting a clock signal output from the emitter follower circuit for a predetermined distance and supplying the clock signal in common to the first latch circuit of the first shift circuit and the third latch circuit of the second shift circuit When,
A second transmission line (27) for transmitting a clock signal received from the first transmission line for a predetermined distance and supplying the clock signal in common to the second latch circuit of the first shift circuit and the fourth latch circuit of the second shift circuit; ,
A third transmission line (28) for transmitting a clock signal received from the second transmission line for a predetermined distance and supplying the clock signal to the fifth latch circuit of the second shift circuit;
A fourth transmission line (29) for transmitting a clock signal received from the third transmission line for a predetermined distance and supplying the clock signal to the selection switch;
Among the first to fourth transmission lines, at least the input of each latch circuit is between the middle part of the line conductor of the second transmission line and the ground and between the middle part of the line conductor of the third transmission line and the ground. The value is almost twice the capacity, and the inductance of half the length of the line conductor is L,
Characteristic impedance (Z) = √ (L / C)
A capacitor of capacity C satisfying the relationship
Further, the multiplexer is characterized in that the fourth transmission line is terminated with a resistance equal to the characteristic impedance.

Images