JP4402136B2 - Single flux quantum variable delay circuit - Google Patents

Description

  The present invention relates to a single flux quantum circuit, and to a method for changing the propagation delay time of a single flux quantum.

A single flux quantum (hereinafter abbreviated as SFQ) is a minimum unit of a quantized magnetic flux (Φ ₀ = h / 2e = 2.07 × 10 ⁻¹⁵ Weber). This single flux quantum circuit (SFQ circuit) using SFQ as an information carrier is characterized by ultra-high speed operation of several tens of gigahertz (10 ⁹ Hz) and low power consumption characteristics of several microwatts (μW) or less per gate. It is a superconducting circuit. Based on the principle shown in iTriply, Transaction, Applied, Superconductivity (IEEE Trans. On Appl. Supercond.), Vol. 1, No. 1 (1991), p. 3 (Non-patent Document 1) Gates have been developed, and practical circuits combining these have been widely developed.

  Application to the digital field utilizing the high speed characteristic of the SFQ circuit, and application to the mixed signal field utilizing the property of magnetic flux quantization in combination with high speed are expected. In the digital field, network switches for high-end routers, microprocessors are Itripliy, Transactions, Applied, Superconductivity (IEEE Trans. On Appl. Supercond.), Vol. 15, No. 2 (2005), p. 411 (Non-patent Document 2), It is shown in Eye Transply, Transaction, Applied, Superconductivity (IEEE Trans. On Appl. Supercond.), Vol. 15, No. 2 (2005), 400 (Non-patent Document 3). Also, in the mixed signal field, analog / digital converters and Josephson samplers have been developed by Eye Transplicity, Transactions, Applied, Superconductivity (IEEE Trans. On Appl. Supercond.), Vol. 3, No. 1 (1993), 2732 pages. (Non-patent Document 4), Eye Triply, Transaction, Applied, Super Conductivity (IEEE Trans. On Appl. Supercond.), Vol. 15, No. 2 (2005), p. 316 (Non-patent Document 5).

Similar to the semiconductor circuit, the SFQ circuit is configured by combining smaller logic gates. An outline of the transmission of the SFQ signal between the logic gates will be described with reference to a block diagram shown in FIG. 1A and a time chart shown in FIG. 1B. The actual SFQ signal propagates in the circuit as a voltage pulse with a width of several ps. Therefore, in order to express a digital signal with an SFQ voltage pulse (hereinafter referred to as an SFQ pulse), an SFQ pulse as a data signal and an SFQ pulse as a clock signal are supplied to each logic gate. For example, on the input side of the logic gate 102 that receives a data signal, an SFQ pulse generated at a constant cycle is input as a clock signal. When one SFQ pulse is input as a data signal within the period, the logic gate determines that digital data “1” has been received. On the other hand, if no SFQ pulse is input within the clock period, it is determined that digital data “0” has been received. For this reason, in the SFQ circuit, a data signal transmission between the gates 101 and 102 requires a clock signal transmission line 103 and a data signal transmission line 104.
As the transmission line connecting the logic gates, a microstrip line, which is a general transmission line for high-frequency signals, or a Josephson transmission line unique to the SFQ circuit is used. FIG. 2A shows an equivalent circuit of the Josephson transmission line. The Josephson transmission line is configured by connecting a unit circuit 204 including a Josephson junction 201, a bias current source 202, and an inductor 203 in series. The bias current source 202 is configured by connecting a voltage source 205 and a bias resistor 206 in series as shown in FIG. 2B. When the SFQ signal enters from the input terminal 210, the Josephson junction in the transmission line is sequentially switched from left to right, and the SFQ is moved by this switching. With this operating principle, the SFQ signal is propagated from the input terminal to the output terminal 211.

  In general, in order to operate the entire circuit normally, it is necessary to appropriately adjust the timing of signals traveling between the gates as well as the normal operation of the logic gate alone. Particularly in the SFQ circuit, the context (hereinafter referred to as timing) of the input time of the clock signal and the data signal in the logic gate is particularly important. Further, in order to operate the logic gate normally for several picoseconds before and after the clock signal input, the data signal input is prohibited. Therefore, it is necessary to input the data signal within the input period of the clock signal and avoiding the input prohibition time zone. Therefore, in order to operate the SFQ circuit at a higher speed, it is necessary to design a circuit in which the input timings of the clock signal and the data signal are arranged in an appropriate time relationship. In actual circuit design, circuit simulation is used to determine the length of the microstrip line and the number of unit circuits of the Josephson transmission line, that is, the number of Josephson junctions.

Eye Triply, Transaction, Applied, Superconductivity (IEEE Trans. On Appl. Supercond.), Vol. 1 (1991), p. 3 (IEEE Trans. On Appl. Supercond.), Vol. 15, No. 2 (2005), p. 411 Eye Triply, Transaction, Applied, Superconductivity (IEEE Trans. On Appl. Supercond.), Vol. 15, No. 2 (2005), p. 400 Eye Triply, Transaction, Applied, Superconductivity (IEEE Trans. On Appl. Supercond.), Vol. 3, No. 1 (1993), p. 2732 Eye Triply, Transaction, Applied, Superconductivity (IEEE Trans. On Appl. Supercond.), Vol. 15, No. 2 (2005), p. 316

  In an actually manufactured circuit, timing may vary from a design value due to variations in circuit element parameters caused by manufacturing process conditions. In addition, since the delay time of the circuit element in the circuit design is not accurately estimated, each signal may not maintain an appropriate timing. In either case, the SFQ circuit malfunctions and the operating frequency decreases. For this reason, in the prior art, tolerance design in consideration of variations in circuit element parameters, timing adjustment by adjusting the signal propagation time of the Josephson transmission line, or timing adjustment by supplying a multiphase clock signal has been performed.

  Tolerance design is a method of predicting a variation range of signal timing due to variations in circuit parameters using circuit simulation and reflecting it in the circuit design. However, when a circuit is manufactured outside the assumed variation range, an appropriate timing relationship between signals cannot be maintained. Even if there is no variation in circuit parameters, tolerance design does not make sense if the delay time at the time of circuit design cannot be estimated accurately. For this reason, even if tolerance design is used, it may lead to malfunction of a circuit.

  On the other hand, the method of changing the delay time of the Josephson transmission line utilizes the fact that the SFQ propagation speed on the Josephson transmission line is changed by adjusting the bias current applied to the Josephson junction constituting the Josephson transmission line. It is. In the method of adjusting the bias current, the other end of all the bias resistors 206 connected to the corresponding Josephson junction is made common, and one variable voltage source 205 is also connected to a current source (hereinafter abbreviated as a power source). It will be realized.

  In this method, the timing of signals can be adjusted according to the size and variation of the circuit element parameters of an actually manufactured circuit, and normal operation of the circuit can be realized. However, the delay time per Josephson junction is 2 ps or less, and the variable time is about 10%. For this reason, in order to realize a variable delay time of several tens to several hundreds of ps, it is necessary to increase the number of Josephson junctions by lengthening the Josephson transmission line. Further, one variable current source or one variable voltage source is required for each Josephson transmission line whose propagation time is to be changed. Therefore, when adjusting the timings of the N transmission paths individually, N bias power supplies are required. However, unlike the semiconductor circuit, the SFQ circuit does not have a transistor capable of controlling the power supply, and therefore it is very difficult to integrate the SFQ circuit and a plurality of variable power supplies on the same chip. In this case, a plurality of bias power connection terminals are arranged on the chip, and a power supply is received from the outside after connecting a 4.2 K cryogenic environment and a room temperature environment with a cable. However, increasing the number of power connection terminals is not preferable in terms of mounting. This is because heat inflow from the room temperature environment to the SFQ circuit via the cable is likely to occur. As a result, the number of variable bias power supplies for timing adjustment, that is, the number of Josephson transmission lines capable of timing adjustment is limited to several.

  The multi-phase clock supply method is a method of supplying one clock signal for each logic gate. Since the timing when the clock signal is input to each logic gate can be determined individually, even if the timing of the data signal input to the logic gate changes due to process variations, the timing of the clock signal source Appropriate timing can be realized by adjusting the phase. However, for the same reason as the bias current described above, the number of clock signals, that is, the number of gates is limited.

  To solve the above problem, the present invention provides a variable delay circuit in which the variable width of the SFQ signal propagation time on the transmission line is expanded, and a method for increasing the number of variable transmission lines without increasing the delay time control line.

First, the variable delay circuit will be described. FIG. 3 shows a single flux quantum variable delay circuit proposed in the present invention. The circuit includes a branch circuit 301, a plurality of transmission lines having different delay times, that is, Josephson transmission lines and microstrip lines 302 _{1 to} 302 _N , switch circuits 303 _{1 to} 303 _N corresponding to the transmission lines, and a junction circuit 304. The branch circuit outputs a plurality of SFQ pulses from one input SFQ pulse, and the junction circuit combines a plurality of SFQ pulse inputs and outputs them from one terminal.

This circuit constitutes a plurality of detours with different delay times for one signal transmission path. The SFQ pulse input from the input terminal 310 is branched by the branch circuit and input to the switch circuit via each transmission line. One switch circuit, for example 303 ₂ via the coupling circuit SFQ pulse is outputted from the assumed and the switch circuit to be "ON", and reaches the output terminal 311. Therefore, by setting one of the switch circuits to the “ON” state, one of the detours is selected and the delay time of the detour is the delay time of the variable delay circuit.

  Note that the switch circuit used in the present invention is controlled by an SFQ pulse, and generally uses a non-destructive-read out gate. When the SFQ pulse (Set signal) is input to the Set terminal 314, the “ON” state is entered and the SFQ pulse from the input terminal 312 is output to the output terminal 313 as it is. By inputting the SFQ pulse (Reset signal) to the Reset terminal 315, the “ON” state is canceled and the “OFF” state is set, and the SFQ pulse from the input terminal is cut off.

  The minimum change width (resolution) of the variable delay circuit depends on a difference in delay times of a plurality of transmission lines constituting the detour. When a plurality of Josephson transmission lines are used as detours, the minimum change width is determined by the difference in unit circuits between the transmission lines. For example, in a plurality of Josephson transmission lines constituting the detour, when the difference between the unit circuits is two stages, the change width is about 2 to 4 ps depending on the magnitude of the bias current flowing through the junction. In order to increase the minimum change width, the difference in the number of unit circuits between the Josephson transmission lines may be increased. On the other hand, when the minimum change width is made smaller than one unit circuit of the Josephson transmission line, a microstrip line may be used as the transmission line constituting the detour and the length may be adjusted.

The following relational expression holds for the variable range T of the variable delay circuit, the minimum change width ΔT, and the number of bypass circuits, that is, the number N of switch circuits.

N = T / ΔT

Therefore, in order to expand the variable range, the minimum change width and the number of switch circuits may be increased simultaneously. Further, when the variable range is expanded while keeping the minimum change width small, only the number of switch circuits needs to be greatly increased. However, a variable delay circuit can be realized with a smaller number of switch circuits by the method shown in FIG. A variable delay circuit 401 having a small minimum change width and a variable delay circuit 402 having both a minimum change width and a large variable range are connected in series. For this reason, the delay time of this variable delay circuit is represented by the addition of two variable delay circuits. The minimum variable width ΔT2 of the variable delay circuit 402 is set to be the same as or slightly smaller than the variable range T1 of the variable delay circuit 401. The variable delay circuit 402 substantially determines the variable range T of the entire variable delay circuit, and the variable delay circuit 401 determines the minimum change width ΔT, that is, the resolution.

By this method, it is possible to simultaneously improve the resolution and variable range of the variable delay circuit and reduce the number of switch circuits. Assuming that the variable range T1 of the variable delay circuit 401 and the minimum change width ΔT2 of the variable delay circuit 2 are the same value, the number N of switch circuits is

N = T / ΔT2 + T1 / ΔT = T / ΔT2 + ΔT2 / ΔT

It is expressed. For example, consider a case where T is 100 ps, ΔT2 is 10 ps, and ΔT is 1 ps. When one variable delay circuit is configured, the number of necessary switch circuits is 100. On the other hand, when two variable delay circuits are configured in series, 20 switch circuits are sufficient.

  Next, a method for reducing the number of control lines of the variable delay circuit will be described. In the above-described variable delay circuit using the switch circuit, two control signals, that is, a Set signal and a Reset signal are required for each switch circuit. For this reason, a control line twice as many as the number of switch circuits is required in one variable delay circuit. Therefore, the number of control lines to the variable delay circuit is reduced by a serial-parallel conversion circuit using a shift register. FIG. 5 shows a block diagram of a control circuit of the variable delay circuit 300 according to the present invention. The circuit mainly includes an N-bit shift register circuit 501 and two delay circuits 504 and 507. Regardless of the number of switch circuits, there are two control signals, a Shift signal and a Reset signal. The operation of the circuit will be described below.

First, an SFQ pulse (Reset signal) is input from the Reset terminal 510. The SFQ pulse is input to the variable delay circuit 300 through the branch circuit 502. This SFQ pulse is supplied to the Reset terminals of all the switch circuits 303 _{1 to} 303 _N constituting the variable delay circuit, and the switch circuits are set to the “OFF” state. On the other hand, another SFQ pulse output from the branch circuit 502 is further input to the dump terminal of the shift register circuit 501 via the delay circuit 504 and the branch circuit 505. By this dump signal, the information stored in the shift register circuit is moved in parallel output as the Set input of the switch circuit of the variable delay circuit.

  Here, it is assumed that the information held in the shift register circuit is N bits long, one bit is “1”, and all other bits are “0”. Due to the dump operation of the shift register circuit, one of the switch circuits constituting the variable delay circuit is turned “ON”, and the corresponding detour is selected. Further, another SFQ signal output from the branch circuit 505 is the delay circuit 507. Through this signal, “1” is stored in the first bit of the shift register, and finally, the “ON” state is set toward the shift terminal 511. By repeatedly inputting the number of SFQ pulses corresponding to the bit position of the switch circuit to be moved, “1” in the shift register circuit is moved. This information is newly input as the SFQ pulse for the reset signal. Thus, it can be reflected in the variable delay circuit.

Finally, a method for controlling a plurality of variable delay circuits will be described. In the above-described variable delay circuit using the shift register circuit, two control lines for the Reset signal and the Shift signal are required for each variable delay circuit. Therefore, the number of control lines to a plurality of variable delay circuits is reduced by a serial-parallel conversion circuit using a shift register. FIG. 6 shows a control circuit for a plurality of variable delay circuits 500 according to the present invention. Circuit mainly consists of M-bit shift register circuit 601, switching circuits ₆₀₈ 1 to match the number M of the variable delay circuit ～608 _M and two delay circuits 604 and 607. Regardless of the number of variable delay circuits, there are four control signals: the Address signal, the Shift signal, the Reset1 signal, and the Reset2 signal. The operation of the circuit will be described below.

First, an SFQ pulse (Reset 1 signal) is input from the Reset 1 terminal 620. The SFQ pulse passes through branch circuits 610 _{1 to} 610 _M−1 and supplies SFQ pulses as Reset signals to all variable delay circuits 500 _{1 to} 500 _M. At this point, each variable delay circuit dumps the information in the individual shift register to the switch circuit and is ready to process the next new Shift signal. Next, an SFQ pulse (Reset 2 signal) is input from the Reset 2 terminal 622. The SFQ pulse is supplied to the Reset terminals in all the switch circuits 608 _{1 to} 608 _M via the branch circuits 602 and 603 _{1 to} 603 _M−1 . By this operation, all the switch circuits 608 _{1 to} 608 _M are in the “OFF” state.

  On the other hand, another SFQ pulse output from the branch circuit 602 is further input to the dump terminal of the shift register circuit 601 via the delay circuit 604 and the branch circuits 605 and 606. The information stored in the shift register circuit is moved to the switch circuit 608 by parallel output by the dump signal. Here, the information held in the shift register circuit is assumed to be N bits long, one bit is “1”, and all other bits are “0”. Due to the dump operation of the shift register circuit, only one switch circuit corresponding to the bit for which “1” was held is turned “ON”.

  Here, when a pulse train composed of several SFQs is input to the Shift terminal 621 as the Shift signal, the Shift signal is connected to the switch circuit via the switch circuit 608 in the “ON” state. Supplied only to the circuit. Through this series of operations, one of a plurality of variable delay circuits can be selected and a Shift signal can be input. Further, another SFQ pulse output from the branch circuit 605 is supplied to the data input terminal of the shift register circuit via the delay circuit 607. With this signal, “1” is stored in the first bit of the shift register circuit. Finally, the number −1 SFQ pulse corresponding to the bit position of the switch circuit to be turned “ON” is repeatedly input toward the address terminal 623, thereby moving “1” in the shift register circuit. This information can be reflected in the switch circuit by inputting a new Reset2 signal, and a variable delay circuit that supplies the next Shift signal can be selected.

  By using this control method, the timing of a plurality of signals can be adjusted with four control lines without depending on the number of variable delay circuits.

  According to the present invention, the propagation time of the SFQ signal can be arbitrarily adjusted. Therefore, timing mismatch due to circuit parameter variations is prevented, and a reduction in operating frequency is prevented. In addition, the variable delay circuit of the high-speed sampler can be realized by actively using the adjustment of the delay time. Furthermore, the present invention can reduce the control line to the variable delay circuit. For this reason, even if the design circuit becomes large and the number of variable delay circuits increases, the number of control lines does not increase. As a result, it is possible to ensure both normal operation at a higher operating frequency and expansion of the scale of the target circuit.

The present invention will be described below with reference to examples. This embodiment is an example using the present invention, and the present invention is not limited to the embodiment.
<Example 1>
In the single flux quantum variable delay circuit proposed in the present invention, FIG. 7A shows an equivalent circuit when the detour is configured by a Josephson transmission line. In this example, the number of detours, that is, the number of switch circuits is four. As the branch circuit, a splitter (SP) circuit having a structure similar to that of the unit circuit of the Josephson transmission line was used. Further, in this example, the four paths are not branched at a time, but one unit circuit of the Josephson transmission line is added one by one while one SP circuit 701 branches one path at a time. As the switch circuit, a Non-Distributive-ReadOut gate shown in FIG. 7B was used. A 2-input type confluence buffer (CB) circuit was used as the junction circuit. Similar to the case of branching, in this example, the four inputs are not merged at a time, but one unit circuit of the Josephson transmission line is added one by one, and one CB circuit 704 merges one path at a time. Therefore, the difference in the number of Josephson transmission line unit circuits 702 in adjacent detours is 2.

FIG. 8 shows operation waveforms by circuit simulation. The operation of the circuit will be described with reference to FIG. If you enter a SFQ pulse Reset terminal ₃₁₅ 1 to 315 ₄ of all the switch circuits ₃₀₃ 1 to 303 _4, all the switch circuits are turned OFF. In this case, no output appears even if the SFQ pulse is input to the signal input terminal 710. Now, enter the SFQ pulses example, SET terminal 314 ₂ of the switch circuit 303 _2, with a delay of 27 ps, SFQ pulse is output to the signal output terminal 711. Here one end, enter the SFQ pulse Reset terminal ₃₁₅ 1 to 315 _4, after all the switch circuits in the OFF state, by entering the SFQ pulse to the SET terminal of another switch circuit 303 _3, another longer turn It can be seen that SFQ pulses are output with a delay time of 31 ps. Therefore, this circuit can designate a switch circuit that is turned on by selectively inputting an SFQ pulse to the SET terminal, and can adjust the propagation time of the SFQ pulse in increments of 4 ps.
<Example 2>
In the single flux quantum variable delay circuit proposed in the present invention, FIG. 9 shows an equivalent circuit when the detour is configured by a microstrip line. In this example, the number of switch circuits is four. The branch circuit uses a binary tree structure by the SP circuit 901 and is configured such that SFQ pulses are simultaneously input to the _four microstrip lines 902 _{1 to} 902 ₄ . An impedance matching resistor 909 is inserted on the input side of the microstrip line. As the switch circuit 303, a Non-Distributive-ReadOut gate is used as in the first embodiment. Merging circuit using a binary tree structure by the CB circuit 904, SFQ propagation time from the switch circuits ₃₀₃ 1 to 303 ₄ to the output terminal 911 is configured to be the same.

FIG. 10 shows operation waveforms by circuit simulation. The operation of the circuit will be described with reference to FIG. If you enter a SFQ pulse Reset terminal ₃₁₅ 1 to 315 ₄ of all the switch circuits ₃₀₃ 1 to 303 _4, all the switch circuits are turned OFF. In this case, even if the SFQ pulse is input to the signal input terminal 910, the SFQ pulse does not appear from the output terminal 911. Now, enter the SFQ pulses example, SET terminal 314 ₂ of the switch circuit 303 _2, with a delay of 31Ps, SFQ pulse is output to the signal output terminal 911. Here one end, enter the SFQ pulse Reset terminal ₃₁₅ 1 to 315 _4, after all the switch circuits in the OFF state, by entering the SFQ pulse to the SET terminal of another switch circuit 303 _3, another longer turn It can be seen that SFQ pulses are output with a delay time of 32 ps. Therefore, this circuit can specify a switch circuit that is turned on by selectively inputting an SFQ pulse to the SET terminal, and can adjust the propagation time of the SFQ pulse in increments of 1 ps.
<Example 3>
FIG. 11 shows an equivalent circuit in the case where the single flux quantum variable delay circuit proposed in the present invention is configured by connecting two delay circuits having different minimum variable widths in series. In this example, the variable delay circuit 700 configured by the Josephson transmission line shown in the first embodiment is used as a variable delay circuit having a large variable width, and the microstrip line shown in the second embodiment is used as a variable delay circuit having a small variable width. The configured variable delay circuit 900 was used. FIG. 11 shows the equivalent circuit of the two variable circuits shown in FIGS. 7 and 9 replaced with a block diagram. The number of switch circuits of each variable delay circuit was set to 4 as in the first and second embodiments. In a variable delay circuit having a large variable width, the difference in the number of Josephson transmission line unit circuits in adjacent detours is 2, and the delay time can be changed in increments of 4 ps. On the other hand, in the switch circuit of the small delay circuit, the length of the microstrip line is adjusted so that the propagation time of the SFQ pulse is adjusted in four steps in increments of 1 ps.

FIG. 12 shows operation waveforms by circuit simulation. The operation of the circuit will be described with reference to FIG. When SFQ pulses are input to the reset terminals 315 _{1 to} 315 ₈ , all the switch circuits are turned off. In this case, no output appears even if the SFQ pulse is input to the signal input terminal 1110. Here, entering a switching circuit 303 ₂ of the SET terminal 314 ₂ in SFQ pulse of the switch circuit 303 ₂ of the SET terminal 314 ₂ and the variable delay circuit 900 of the variable delay circuit 700, with a delay of about 63Ps, SFQ output terminal 1111 is output. Here once, Reset terminal ₃₁₅ 1 to 315 ₈ enter the SFQ pulse, after the switch to the OFF state, the other switch circuits 303 ₃ of the variable delay circuit 700 SET terminal 314 ₃ and the variable delay circuit further 900 If you enter a SFQ pulse to the SET terminal 314 _third switching circuit 303 _3, now it can be seen that SFQ pulse is output with a different longer delay time 72 ps. FIG. 14 shows two other combinations of switch circuits that are turned on.

This circuit can specify a switch circuit that is turned on by selectively inputting an SFQ pulse to the SET terminal, and can adjust the propagation time of the SFQ pulse within a range of 58 ps to 74 ps and in increments of 1 ps. .
<Example 4>
In the single flux quantum variable delay circuit proposed in the present invention, control circuits corresponding to the four switch circuits of the first embodiment will be described. As shown in FIG. 13A, the circuit includes a 4-bit shift register circuit 1301, two delay circuits 1302, 1303, and a plurality of branch circuits. In this example, a case where the shift register circuit includes D2-FF circuits 1306 _{1 to} 1306 ₄ which are one of latch circuits is shown.

  The D2-FF circuit is a data flip-flop circuit having one data input (Input), two trigger inputs (Control 1 and Control 2), and two outputs (Output 1 and Output 2) as shown in FIG. 1B. When an SFQ pulse is input from the input terminal, the SFQ is held in the circuit. In this state, when an SFQ pulse is input to the Control 1 terminal or the Control 2 terminal, the SFQ pulse is output to the output terminal Output 1 or Output 2 corresponding to the input number, and the SFQ in the circuit disappears. If SFQ is not held in the circuit, no SFQ pulse is output even if a trigger signal is input.

  The branch circuit is an SP circuit composed of one Josephson junction as in the first embodiment. The delay circuit is formed by connecting about five unit circuits of the Josephson transmission line in series. The delay time only needs to be about several tens of ps, and accuracy is not required.

The operation of the circuit will be described along the time chart shown in FIG. First, an SFQ pulse is input from the Reset terminal 1313 for circuit initialization. This SFQ pulse passes through the SP circuit 1304 and is supplied to the Reset terminals of all the switch circuits constituting the variable delay circuit 700, whereby all the switch circuits are in the “OFF” state. On the other hand, another SFQ pulse output from the SP circuit 1304 is further input to the dump terminal 1314 of the shift register circuit 1301 via the delay circuit 1303 and the SP circuit 1305. In the shift register circuit, the dump terminal is connected to the Control 2 terminal of all the D2-FF circuits. Therefore, the SFQ in all the D2-FFs 1306 _{1 to} 1306 ₄ , that is, the internal state held by the shift register circuit is output in parallel to the switch circuit from the Output 2 terminal by the input of the dump signal. Due to the dump operation of the shift register, one of the switch circuits constituting the variable delay circuit is turned “ON” and the corresponding detour is selected. In the first dump signal shown in FIG. 14, the second bit, that is, the D-FF circuit is selected. An SFQ pulse is output from 1306 ₂ and supplied to the Set terminal of the switch circuit of the second bit, whereby only the switch circuit 2 is turned on.

Further, another SFQ pulse output from the SP circuit 1305 is supplied to the data input terminal 1315 of the shift register circuit via the delay circuit 1302. The data input terminal, in the shift register circuit is connected to the D2-FF circuit 1306 ₁ of Input terminals of the first bit. For this reason, SFQ is held in the first bit of the shift register circuit by data input. On the other hand, the Shift terminal 1312 is connected to the Control 1 terminal of all the D2-FF circuits in the shift register circuit. The Output 1 terminal of each D2-FF circuit is connected to the Input terminal of the adjacent D2-FF circuit. For this reason, when the Shift signal is input, the SFQ pulse held in each D2-FF circuit moves to the adjacent D2-FF through the Output1 terminal. As a result, the number of SFQ signals corresponding to the bit position of the switch circuit to be turned on is repeatedly input to the shift terminal, so that the SFQ in the register is moved from the first bit to the target bit. Can be made. This information can be reflected in the variable delay circuit by inputting a new Reset signal. In the time chart shown in FIG. 14, since two SFQ pulses are input to the Shift terminal, only the switch circuit 3 is turned on by the input of the Reset signal.

By using this control circuit, the number of control lines can be reduced to two without depending on the number of switch circuits. When this control circuit is applied to the first embodiment, the eight control lines can be reduced to two.
<Example 5>
In the single flux quantum variable delay circuit proposed in the present invention, a control circuit corresponding to the two variable delay circuits shown in the third embodiment will be described. As shown in FIG. 15, the two variable delay circuits with control circuits 13 _{700 and} 13 ₉₀₀ shown in the fourth embodiment, a 2-bit shift register circuit 1501, two switch circuits 1507 ₁ and 1507 ₂ , branch circuits 1505 and 1504, and It consists of two delay circuits 1502 and 1503 by Josephson transmission lines. The shift register in this example includes a D2-FF circuit 1506 as in the fourth embodiment. The branch circuit is an SP circuit composed of one Josephson junction as in the first embodiment. The delay circuit is formed by connecting about five unit circuits of the Josephson transmission line in series. The delay time only needs to be about several tens of ps, and accuracy is not required.

The operation of the circuit will be described along the time chart shown in FIG. First, by inputting a SFQ pulses to Reset1 terminal 1512, and supplies a Reset signal with two control circuits to the variable delay circuit _{13 700} and _{13 900.} At this point, each variable delay circuit with a control circuit dumps the information in the individual shift register circuit to the switch circuit and prepares to process the next new Shift signal. Next, the Reset2 signal is input. The SFQ pulse input from the Reset2 terminal 1513 is supplied to the Reset terminals of the variable switch circuits 1507 ₁ and 1507 ₂ via the SP circuit 1504, and all the switch circuits are in the “OFF” state.

On the other hand, another SFQ pulse output from the SP circuit 1504 is further input to the dump terminal 1515 of the shift register circuit via the delay circuit 1503 and the SP circuit 1505. As in the fourth embodiment, the internal state held by the shift register circuit is output in parallel to the switch circuit from the Output 2 terminal by the dump signal. This operation, one of switch circuits constituting the variable delay circuit becomes "ON state. In the first dump signal shown in FIG. 16, the first bit SFQ pulses from the first bit, i.e. D-FF circuit 1506 ₁ is output is supplied to the Set terminal of the switch circuit 1507 _1. Thus, only the switch circuit 1 is turned oN.

Here, when a pulse train composed of several SFQs is input to the Shift terminal 1517 as the Shift signal, the Shift signal is connected to the switch circuit via the switch circuit 1 in the “ON” state. It is supplied only to the variable delay circuit (in this case, 13 ₇₀₀ ). Through this series of operations, one of the plurality of variable delay circuits with a control circuit can be selected and the Shift signal can be input. Further, another SFQ pulse output from the SP circuit 1505 is supplied to the data input terminal 1516 of the shift register circuit via the delay circuit 1502. This signal, the first bit, i.e. D-FF circuit 1506 ₁ of the shift register circuit "1" is stored. Finally, the number −1 SFQ pulse corresponding to the bit position of the switch circuit to be turned “ON” is repeatedly input from the address terminal 1514 to move “1” in the register. This information can be reflected in the switch circuit by inputting a new Reset2 signal, and a variable delay circuit with a control circuit that supplies the next Shift signal can be selected.

In the time chart shown in FIG. 16, since the input one SFQ pulse Address terminals, only the switch circuit 2 is now at the input of Reset2 signal becomes ON state, the control circuit with the variable delay circuit _{13 900} to only Shift signal Can be supplied. In this example, three SFQ pulses are input as the Shift signal when the variable delay circuit with control circuit 13 ₇₀₀ is specified, and two SFQ pulses are input as the Shift signal when the variable delay circuit with control circuit 13 ₉₀₀ is specified. Assume the case. Therefore, the switch 4 is selected in the variable delay circuit 700 and the switch 3 is selected in the variable delay circuit 900, and a predetermined delay time is determined.

  By using this control method, it is possible to control the propagation delay time of a plurality of signals with four control lines without depending on the number of variable delay circuits, and to adjust the input timing of each signal.

The block diagram which shows the data transmission between the logic gates in a SFQ circuit. The time chart figure which shows the data transmission between the logic gates in a SFQ circuit. The figure which shows the equivalent circuit of a Josephson transmission line. The figure which shows the equivalent circuit of a bias current source. The block diagram of the single magnetic flux quantum variable delay circuit of this invention. The figure which shows a switch circuit. The serial connection figure of the single magnetic flux quantum variable delay circuit of this invention. The block diagram of the control circuit of the single magnetic flux quantum variable delay circuit of this invention. The block diagram of the circuit which controls two or more of the single magnetic flux quantum variable delay circuits with the control circuit of this invention. The equivalent circuit schematic of the single magnetic flux quantum variable delay circuit in 1st Example of this invention. The equivalent circuit diagram of a switch circuit. The figure which shows the operation | movement waveform by the circuit simulation of the single magnetic flux quantum variable delay circuit shown in 1st Example of this invention. The equivalent circuit schematic of the single magnetic flux quantum variable delay circuit in 2nd Example of this invention. The figure which shows the operation waveform by the circuit simulation of the single magnetic flux quantum variable delay circuit shown in 2nd Example of this invention. The block diagram of the single magnetic flux quantum variable delay circuit in 3rd Example of this invention. FIG. 7B is an explanatory diagram of symbols used in FIG. 7A. The figure which shows the operation | movement waveform by the circuit simulation of the single magnetic flux quantum variable delay circuit shown in 3rd Example of this invention. The block diagram of the control circuit of the single magnetic flux quantum variable delay circuit in 4th Example of this invention. The equivalent circuit diagram of D2-FF circuit. The flowchart figure of the control circuit of the single magnetic flux quantum variable delay circuit in 4th Example of this invention. The block diagram of the control circuit of the single magnetic flux quantum variable delay circuit in 5th Example of this invention. The flowchart figure of the control circuit of the single magnetic flux quantum variable delay circuit in 5th Example of this invention.

Explanation of symbols

101: Transmission side logic gate, 102: Reception side logic gate, 103: Clock signal transmission line, 104: Data signal transmission line, 201: Josephson junction, 202: Bias current source, 203: Inductor, 204: Unit circuit 205: Voltage source, 206: Bias resistor, 300: Variable delay circuit, 301: Branch circuit, 302: Transmission line, 303: Switch circuit, 304: Junction circuit, 310: Input terminal, 311: Output terminal, 312: Input Terminal 313: Output terminal 314: Set terminal 315: Reset terminal 401: Variable delay circuit 402: Variable delay circuit 405: Delay circuit 406: Delay circuit 407: Delay circuit 408: Delay circuit 410 : Input terminal, 411: output terminal, 500: variable delay circuit with control circuit, 501: N-bit shift register Path 502: branch circuit 503: switch circuit 504: delay circuit 505: branch circuit 506: branch circuit 507: delay circuit 601: M-bit shift register circuit 602: branch circuit 603: branch circuit 604: Delay circuit, 605: Branch circuit, 606: Branch circuit, 607: Delay circuit, 608: Switch circuit, 609: Branch circuit, 610: Branch circuit, 620: Reset1 terminal, 621: Shift terminal, 622: Reset2 terminal, 623: Address terminal, 700: variable delay circuit, 701: SP circuit, 702: Josephson transmission line unit circuit, 704: CB circuit, 710: input terminal, 711: output terminal, 900: variable delay circuit, 901: SP circuit 902: Microstrip line 904: CB circuit 905: Josepho 907: Josephson transmission line, 908: Josephson transmission line unit circuit, 909: impedance matching resistor, 910: input terminal, 911: output terminal, 1110: input terminal, 1111: output terminal, 1301: 4-bit Shift register circuit, 1302: delay circuit, 1303: delay circuit, 1304: SP circuit, 1305: SP circuit, 1306: D2-FF circuit, 1310: input terminal, 1311: output terminal, 1312: Shift terminal, 1313: Reset terminal 1314: Shift register circuit dump terminal, 1315: Shift register circuit data input terminal, 1501: 2-bit shift register circuit, 1502: Delay circuit, 1503: Delay circuit, 1504: SP circuit, 1505: SP circuit, 1506: D2- FF circuit, 1507: switch 1510: input terminal, 1511: output terminal, 1512: Reset1 terminal, 1513: Reset2 terminal, 1514: Shift terminal, 1515: shift register circuit dump terminal, 1516: shift register circuit data input terminal.

Claims (5)

It has one input terminal and N (N = 2, 3,...) Output terminals, and a single flux quantum input from the input terminal is replicated into N single flux quanta. One branch circuit that outputs one single flux quantum per output terminal from one output terminal;
One merging circuit having N input terminals and one output terminal, and outputting a single magnetic flux quantum input to any one of the N input terminals to the output terminal;
N transmission lines for propagating a single flux quantum;
N switch circuits having one input terminal and one output terminal and capable of selecting propagation and blocking of a single flux quantum,
One end of the transmission line is connected to one output terminal of the branch circuit, the input terminal of the switch circuit is connected to the other end of the transmission line, and one of the input terminals of the junction circuit is connected to the output terminal of the switch circuit. Are connected,
Among the N switch circuits, one selected switch circuit is controlled to propagate a single flux quantum, and the other N-1 switch circuits are controlled to block a single flux quantum.
A delay time of a single magnetic flux quantum propagating through a path from the input terminal of the branch circuit to the output terminal of the junction circuit via the selected one switch circuit is determined according to the selection of the switch circuit. Different for each said route ,
The branch circuit has one input terminal and two output terminals, and a single flux quantum input from the input terminal is duplicated into two single flux quanta, and one output is output from each of the two output terminals. N first to N-th splitter circuits that output one single flux quantum per terminal are provided,
The input terminal of the first splitter circuit is used as the input terminal of the branch circuit, and one output terminal of the first splitter circuit and the input terminal of the second splitter are connected by a first Josephson transmission line. The configuration in which one output terminal of the second splitter circuit and the input terminal of the third splitter are connected by a second Josephson transmission line is repeated until the N-th splitter circuit. To the other output terminal of the splitter circuit from N to N-1 and one output terminal of the N-th splitter circuit as an output terminal of the branch circuit,
The merging circuit has two input terminals and one output terminal, and outputs a single magnetic flux quantum input to one of the two input terminals to the output terminal. N Nth confluence buffer circuits are provided,
The output terminal of the first confluence buffer circuit is used as the output terminal of the merging circuit, and one input terminal of the first confluence buffer circuit and the output terminal of the second confluence buffer circuit are N + 1th Josephson transmission. A configuration in which one input terminal of the second confluence buffer circuit and an output terminal of the third confluence buffer circuit are connected by an N + 2 Josephson transmission line to the Nth confluence buffer circuit. After repeating, the other input terminal of the first to (N-1) th confluence buffer circuits and one input terminal of the Nth confluence buffer circuit are used as the input terminals of the merge circuit, and the transmission is performed. SFQ variable delay circuit line is characterized by Josephson transmission line der Rukoto. It has one input terminal and N (N = 2, 3,...) Output terminals, and a single flux quantum input from the input terminal is replicated into N single flux quanta. One branch circuit that outputs one single flux quantum per output terminal from one output terminal;
One merging circuit having N input terminals and one output terminal, and outputting a single magnetic flux quantum input to any one of the N input terminals to the output terminal;
N transmission lines for propagating a single flux quantum;
N switch circuits having one input terminal and one output terminal and capable of selecting propagation and blocking of a single flux quantum,
One end of the transmission line is connected to one output terminal of the branch circuit, the input terminal of the switch circuit is connected to the other end of the transmission line, and one of the input terminals of the junction circuit is connected to the output terminal of the switch circuit. Are connected,
Among the N switch circuits, one selected switch circuit is controlled to propagate a single flux quantum, and the other N-1 switch circuits are controlled to block a single flux quantum.
A delay time of a single magnetic flux quantum propagating through a path from the input terminal of the branch circuit to the output terminal of the junction circuit via the selected one switch circuit is determined according to the selection of the switch circuit. Different for each said route,
The branch circuit has one input terminal and two output terminals, and a single flux quantum input from the input terminal is duplicated into two single flux quanta, and one output is output from each of the two output terminals. the first to the splitter circuit of the N -1 N -1 Kosonae outputs one single flux quantum per terminal,
Wherein the input terminals of the first splitter circuit as an input terminal of said branch circuit, said first and second Josephson each input terminal of the second and third splitters two output terminals of the first splitter circuit connected by transmission lines, obtained by repeated the second two output terminals of the splitter circuit of the fourth and the input terminal and the fourth fifth splitter circuit, a structure for connecting the fifth Josephson transmission line the output terminal of the end of the splitter circuit of binary tree structure on which an output terminal of said branch circuit being,
The merging circuit has two input terminals and one output terminal, and outputs a single magnetic flux quantum input to one of the two input terminals to the output terminal. the confluence buffer circuit of the N -1 N -1 Kosonae,
The output terminal of the first confluence buffer circuit is the output terminal of the confluence circuit, and the two input terminals of the first confluence buffer circuit are the output terminals of the second and third confluence buffer circuits and the ( N + 1) th , N + 2 Josephson transmission lines are connected, and two input terminals of the second confluence buffer circuit and output terminals of the fourth and fifth confluence buffer circuits are connected by N + 4th and N + 5 Josephson transmission lines. on the input terminal of the end of the confluence buffer circuit binary tree structure obtained by repeating the structure for connecting the input terminal of the coupling circuit, the transmission line it is a microstrip line single Single flux quantum variable delay circuit. Comprising first and second unit circuits having the single flux quantum variable delay circuit ;
A single magnetic flux that is set by the selection of the switch circuit in the first unit circuit, in which the output terminal of the first unit circuit and the input terminal of the second unit circuit are connected by a first Josephson transmission line. variable range of the propagation time of the quantum claim 1 or 2 single described, wherein the larger step size of the propagation time of a single flux quantum that can be set by selection of the switch circuit in the second unit circuit Single flux quantum variable delay circuit. It has one input terminal and N (N = 2, 3,...) Output terminals, and a single flux quantum input from the input terminal is replicated into N single flux quanta. One branch circuit that outputs one single flux quantum per output terminal from one output terminal;
One merging circuit having N input terminals and one output terminal, and outputting a single magnetic flux quantum input to any one of the N input terminals to the output terminal;
N transmission lines for propagating a single flux quantum;
N switch circuits having one input terminal and one output terminal and capable of selecting propagation and blocking of one single flux quantum ,
One end of the transmission line is connected to one output terminal of the branch circuit, the other end of the transmission line and the input terminal of the switch circuit are connected, and one of the input terminals of the junction circuit is connected to the output terminal of the switch circuit. Are connected,
Among the N switch circuits, one selected switch circuit is controlled to propagate a single flux quantum, and the other N-1 switch circuits are controlled to block a single flux quantum.
A delay time of a single magnetic flux quantum propagating through a path from the input terminal of the branch circuit to the output terminal of the junction circuit via the selected one switch circuit is determined according to the selection of the switch circuit. Different for each said route,
Each of the N switch circuits has a SET terminal and a RESET terminal,
Propagating a single flux quantum by inputting a single flux quantum to the SET terminal,
By inputting a single flux quantum to the RESET terminal, the single flux quantum is blocked.
A second branch circuit having N output terminals connected to a RESET terminal of the N switch circuits;
An N-bit shift register with a first dump function connected to the SET terminals of the N switch circuits and having N data output terminals;
A third branch circuit in which one of two output terminals is connected to the input terminal of the second branch circuit;
A fourth branch circuit in which the other of the two output terminals of the third branch circuit is connected to the input terminal via the first delay circuit;
One of the two output terminals of the branch circuit is connected to the dump terminal of the N-bit shift register, and the other output terminal of the two output terminals of the branch circuit is connected via a second delay circuit. wherein connected to the data input terminal of the shift register, the N-bit shift register of the by sHIFT terminal of N single flux quantum variable with the control circuit you characterized by specifying one propagation state of the switch circuit Delay circuit. M single flux quantum variable delay circuits with a control circuit according to claim 4,
An M-bit shift register with a first dump function;
M switch circuits,
The RESET terminals of the M switch circuits and the M output terminals of the first branch circuit are connected, and the M data output terminals of the M-bit shift register with the dump function and the M switch circuits Are connected to each other, one of the two output terminals of the second branch circuit is connected to the input terminal of the first branch circuit, and the other of the two output terminals of the second branch circuit. Is connected to the input terminal of the third branch circuit via the first delay circuit, and one output terminal of the two output terminals of the branch circuit is connected to the dump terminal of the M-bit shift register, The other output terminal of the two output terminals of the branch circuit is connected to the data input terminal of the M-bit shift register via the second delay circuit, and the M output terminals of the fourth branch circuit M pieces An input terminal of the switch circuit is connected, an output terminal of the M switch circuits is connected to a SHIFT terminal of the single flux quantum variable delay circuit with the M control circuits, and a single unit with the M control circuits is connected. 5. The single-flux-quantum variable with control circuit according to claim 4 , wherein an input terminal of the third branch circuit of the one-flux-quantum variable delay circuit is connected to M output terminals of the fifth branch circuit. Delay circuit.

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